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1

Schematic of INVERTER in only NMOS:

Symbol of INVERTER:

2
INVERTER in only NMOS
AIM: Develop the schematic diagram and layout for an INVERTER in only NMOS. Perform
experiment to verify its functional response with appropriate EDA tool. Also make a comment on
area requirement to develop it as an IC.

APPARATUS:
Cadence schematic editor
 Simulation: Spectra simulator.
 Technology: gpdk045

PROCEDURE:

1. Work space creation: Make a right click on the Desktop and select the option “Create Folder”.
2. Name the folder, for example, we have named it as “inverter”.
3. Open the created folder and you get the window.

INITIALISING csh & SOURCING cshrc.

4. Make a right click and select the option “Open in Terminal”


5. Type the command “csh” to initialize shell and source the cshrc file with the command
“source/home/install/cshrc”.

INVOKING VIRTUOSO:

6. Soon after we source the “cshrc” file, we get a display “Welcome to Cadence Tools Suite”. Now
invoke virtuoso using the command “virtuoso &” or “virtuoso”.
7. We get a virtuoso window.

CREATE A LIBRARY:

8. In virtuoso’s top menu, select “Tools” and select “Library Manager”. The Cadence Library
Manager appears.
9. From the top menu of the Library Manager, select “File -> New -> Library” to create a new
library for a new design.
10. We’ll get a “New Library” form where we can name the library that we create.
11. Select “OK” after the library is named.
12. Select “Technology File..” tab that keeps blinking at the bottom of the screen to map the created
library to a technology node based on the specification.
13. We get a form “Technology File for New Library”. Select the option “Attach to an existing
technology library”.
14. Select the respective Technology Node from the list of libraries. For example, we have selected
“gpdk045”.
15. The created library is now available in the Library Manager under Library.

CREATE A CELL:

16. Before creating a cell, make sure that the created library is selected. Only then the created cell can
be viewed under the respective library.
17. To create a Cell View, select File -> New -> Cell View.
18. Now we get a “New File” and we can name the Cell and check the Library, View and Type of the
respective Cell that is to be created.

3
Test Bench of INVERTER:

4
19. We get the Virtuoso Schematic Editor.

ADD AN INSTANCE:

20. To add an instance to the circuit, select “Create -> Instance”. We can also use the bin key ‘I’ or
the icon
21. We get the “Add Instance” form.
22. Select “Browse” option we get the “Library Manager” to choose the transistors required for the
circuit and the type of view for the respective component from the respective Technology
Library.
23. After selecting the component, we get its properties like Length, Width, Multipliers, etc., Select
“Hide” at the end of the form, we can have a view of the transistor in the Schematic Editor.

ADD PIN:

24. To include pins to the circuit, select “Create -> Pin”. We can also use the bin key ‘P’ or the icon.
25. We name the pins and select its direction.
26. Place the pins by a left click on the mouse and the circuit can be viewed.

ADD WIRE:

27. Connect the pins and the components with the help of wire. Select “Create -> Wire”. We can also
use the bin key ‘W’ or the icon.
28. Once wiring is completed, the circuit can be viewed.

SAVE THE DESIGN:

29. After completing the design, it is mandatory to save the design before we move ahead to
Simulation. We have two options, “Save” and “Check and Save”.
30. Save option saves your design as it is but Check and Save option checks for any discontinuities
like floating net or terminal, provides the details of errors or warnings in the circuit and then
saves the design. The results can be seen in the virtuoso tab.

SYMBOL CREATION:

31. To create a symbol for the circuit, select “Create -> Cellview -> From Cellview”. Check the
Library Name, Cell Name, From View Name, To View Name, etc., and select OK.
32. We get the “Symbol Generation Options” window. We are free to decide upon the pin locations
with options like Left Pins, Right Pins, Top Pins and Bottom Pins.
33. Select OK. The tool opens a “Virtuoso Symbol Editor” window which shows a temporary view
of the symbol based on the pins assigned.
34. The symbol can be customized with the help of drawing tools.
35. To create custom symbol, remove the inner rectangle (green) and then using drawing tools,
custom symbol can be created. To remove the inner rectangle (green), place the mouse pointer
within the rectangle so that the entire rectangle gets highlighted, make a left click so that the
entire rectangle gets selected and click on delete in the keyboard to remove the rectangle so that it
is removed.

5
Waveforms:

6
36. Since Inverter design is taken as an example in this manual, the focus is on creating its symbol.
To create a triangle, use “Create Line” option among the drawing tools and the way triangle is
created is as similar as how wiring is done in the schematic. To create a bubble, use “Create
Circle” option, decide a point, make a left click to expand the circle and again make a left click to
fix its size.
37. After creating the symbol, save the symbol using the “Check & Save” option.

TESTBENCH CIRCUIT FOR SIMULATION:

38. Instead of using transistor level design, testbench circuit can be created using its symbolic
representation. To create a testbench circuit, a new Cellview with a different Cell Name should be
created.
39. To include the created symbol, use the “Add Instance” option and select the respective library
and cell using the browse option and then the symbol should appear in schematic editor with the
mouse pointer.
40. Create an output pin. To include supply voltage and input signal sources, “Add Instance” option
shall be used. Browse to the “analogLib” library, select the Cell as “vdc”, View as “symbol” and
click on “Tab” key in the keyboard to get the device properties.
41. Mention the appropriate “DC voltage” based on the specification or technology node. Similarly,
for an input source, (for example) “vpulse” is considered and parameters like Voltage 1, Voltage
2, Period, Delay time, Rise time, Fall time and Pulse width are mentioned.
42. Similarly, “gnd” terminal shall be included to the circuit and the complete circuit.

FUNCTIONAL SIMULATION:

43. To simulate the design, Launch “ADE L”.


44. We get a window and following options are to be verified:
(1) Simulator – to make sure that Spectre is the simulator selected
(2) Model Libraries & Process Corners – to make sure that “.scs” file of the respective technology
node has been selected.
45. To analyze the circuit, select “Analyses” from the top menu in ADE L and under Analyses, select
“Choose”. The analyses chosen and the arguments that had been set up can be seen under
“Analyses” tab in the ADE L window. Similarly, rest of the analyses can be performed based on
designer’s demands.
46. To setup the simulation, select “Outputs” from the ADE L window and select “Setup” under
Outputs option. We get a “Setting Outputs” window as, select “From Design” which would bring
back the test bench circuit created for the simulation process. Select the input wire and output
wire and in ADE L, they are supposed to be displayed under “Outputs” option.
47. To run the simulation, select “Simulation” from ADE L and select the option “Netlist and Run”.
The design is simulated and waveforms are seen.
48. Input signals and Output signals can be seen separately by selecting “Graph -> Split All Strips”.
49. To save the simulation state, select “Session” under ADE L, select “Save State”, we get a “Saving
State” window. Select “Cell view” and select “OK” to save the state.
50. The simulation state and test bench circuit are viewed.

7
LAYOUT:

8
LAYOUT:

51. Open the schematic through the Library Manager and select “Launch -> Layout XL”.
52. A “Startup Option” window pops up. Select “Create New” under Layout tab, “Automatic” under
Configuration tab and select OK. A “New File” window pops up. No changes are to be made, so
select OK. Virtuoso Layout Suite XL Editing window can be seen.
53. To import the circuit components, select “Connectivity -> Generate -> All From Source”.
54. Select OK in the “Generate Layout” window, and the components of the circuit can be seen.
55. Select “Shift + F” to have a view of all the terminals of the transistors.
56. The blue colored box surrounding the circuit components is the PR (Placement & Routing)
Boundary. PR-Boundary can be shifted using the shortcut “S”. To shift the PR-Boundary, place
the mouse pointer close to the respective boundary so that it gets highlighted, make a left mouse
click to select the boundary, use the mouse or arrow (up, down, left or right) keys to shift the
boundary.
57. To attach “Bulk” terminal to the transistors, select the particular transistor by a left mouse click
58. Make a right mouse click and select “Properties”, select “Parameter -> Body tie Type ->
Integrated (or) Detached -> Left Tap (or) Right Tap” and select OK. Bulk terminal of that
transistor can be seen. Repeat the above steps for rest of the transistors to include the Bulk
terminal.
59. By default, the background available in the Virtuoso Layout Editor is the P-Substrate. So, the
PMOS transistors should be placed within an N-Well. This is mandatory for PMOS transistors in
gpdk090 and gpdk045, but for PMOS transistors in gpdk180, it has an N-Well by default. To
create an N-Well, select the respective layer from the “Layers” tab on the left-hand side of the
Virtuoso Layout Editor.
60. Select “R” to create N-Well in the shape of a rectangle surrounding the PMOS transistor.
61. The PMOS transistor is placed within the N-Well and to complete routing between the
components, we can use “P” which denotes “Path” in the layout and is meant for routing process.
62. When the mouse pointer is taken closer to any of the terminals of the components, the terminal
gets highlighted with a yellow color bold line, make a left click to start the path segment from one
terminal to another.
63. For routing between two different layers, usage of “Via” is mandatory. There are two options to
place a via. Start routing from the layer of interest, make a right-click, select “Via Down To..”
and select the layer of interest (or) select “Create” from the top menu, select “Via”, select the
respective via under “Via Definition”, make a left mouse click to place the via.
64. For the example used here, “VDD” is at the top and “VSS” is at the bottom. Source & Bulk of
PMOS/NMOS can be routed to VDD/VSS respectively as earlier between other pins and
terminals (or) the entire top layer can be used for VDD and bottom layer for VSS using “Pin
Placement” option.

9
10
65. Select “Place -> Pin Placement”, a window pops up. Under “Pin Planner” tab, “Pin Name,
Attributes & Create” options can be seen. Select “VDD” under “Pin Name”, select “Top” under
“Attributes -> Edge”, select “HRail” under “Create” and select “Apply” under “Attributes” to
place VDD at the top layer. Similarly, select “VSS” under “Pin Name”, select “Bottom” under
“Attributes -> Edge”, select “HRail” under “Create” and select “Apply” under “Attributes” to
place VSS at the bottom layer. After routing the terminals of PMOS/NMOS terminals with
VDD/VSS respectively, save the layout.
Result:

11
INVERTER in CMOS:

12
INVERTER in CMOS
AIM: Develop the schematic diagram and layout for an INVERTER in only CMOS. Perform
experiment to verify its functional response with appropriate EDA tool. Also make a comment on
area requirement to develop it as an IC.

APPARATUS:
Cadence schematic editor
 Simulation: Spectre simulator.
 Technology: gpdk045

PROCEDURE:

1. Work space creation: Make a right click on the Desktop and select the option “Create Folder”.
2. Name the folder, for example, we have named it as “inverter”.
3. Open the created folder and you get the window.

INITIALISING csh & SOURCING cshrc.

4. Make a right click and select the option “Open in Terminal”


5. Type the command “csh” to initialize shell and source the cshrc file with the command
“source/home/install/cshrc”.

INVOKING VIRTUOSO:

6. Soon after we source the “cshrc” file, we get a display “Welcome to Cadence Tools Suite”. Now
invoke virtuoso using the command “virtuoso &” or “virtuoso”.
7. We get a virtuoso window.

CREATE A LIBRARY:

8. In virtuoso’s top menu, select “Tools” and select “Library Manager”. The Cadence Library
Manager appears.
9. From the top menu of the Library Manager, select “File -> New -> Library” to create a new
library for a new design.
10. We’ll get a “New Library” form where we can name the library that we create.
11. Select “OK” after the library is named.
12. Select “Technology File..” tab that keeps blinking at the bottom of the screen to map the created
library to a technology node based on the specification.
13. We get a form “Technology File for New Library”. Select the option “Attach to an existing
technology library”.
14. Select the respective Technology Node from the list of libraries. For example, we have selected
“gpdk045”.
15. The created library is now available in the Library Manager under Library.

CREATE A CELL:

16. Before creating a cell, make sure that the created library is selected. Only then the created cell can
be viewed under the respective library.
17. To create a Cell View, select File -> New -> Cell View.
18. Now we get a “New File” and we can name the Cell and check the Library, View and Type of the
respective Cell that is to be created.

13
Symbol of INVERTER:

Test bench of INVERTER:

14
19. We get the Virtuoso Schematic Editor.

ADD AN INSTANCE:

20. To add an instance to the circuit, select “Create -> Instance”. We can also use the bin key ‘I’ or
the icon
21. We get the “Add Instance” form.
22. Select “Browse” option we get the “Library Manager” to choose the transistors required for the
circuit and the type of view for the respective component from the respective Technology
Library.
23. After selecting the component, we get its properties like Length, Width, Multipliers, etc., Select
“Hide” at the end of the form, we can have a view of the transistor in the Schematic Editor.

ADD PIN:

24. To include pins to the circuit, select “Create -> Pin”. We can also use the bin key ‘P’ or the icon.
25. We name the pins and select its direction.
26. Place the pins by a left click on the mouse and the circuit can be viewed.

ADD WIRE:

27. Connect the pins and the components with the help of wire. Select “Create -> Wire”. We can also
use the bin key ‘W’ or the icon.
28. Once wiring is completed, the circuit can be viewed.

SAVE THE DESIGN:

29. After completing the design, it is mandatory to save the design before we move ahead to
Simulation. We have two options, “Save” and “Check and Save”.
30. Save option saves your design as it is but Check and Save option checks for any discontinuities
like floating net or terminal, provides the details of errors or warnings in the circuit and then
saves the design. The results can be seen in the virtuoso tab.

SYMBOL CREATION:

31. To create a symbol for the circuit, select “Create -> Cellview -> From Cellview”. Check the
Library Name, Cell Name, From View Name, To View Name, etc., and select OK.
32. We get the “Symbol Generation Options” window. We are free to decide upon the pin locations
with options like Left Pins, Right Pins, Top Pins and Bottom Pins.
33. Select OK. The tool opens a “Virtuoso Symbol Editor” window which shows a temporary view
of the symbol based on the pins assigned.
34. The symbol can be customized with the help of drawing tools.
35. To create custom symbol, remove the inner rectangle (green) and then using drawing tools,
custom symbol can be created. To remove the inner rectangle (green), place the mouse pointer
within the rectangle so that the entire rectangle gets highlighted, make a left click so that the
entire rectangle gets selected and click on delete in the keyboard to remove the rectangle so that it
is removed.

15
Waveforms:

16
36. Since Inverter design is taken as an example in this manual, the focus is on creating its symbol.
To create a triangle, use “Create Line” option among the drawing tools and the way triangle is
created is as similar as how wiring is done in the schematic. To create a bubble, use “Create
Circle” option, decide a point, make a left click to expand the circle and again make a left click to
fix its size.
37. After creating the symbol, save the symbol using the “Check & Save” option.

TESTBENCH CIRCUIT FOR SIMULATION:

38. Instead of using transistor level design, test bench circuit can be created using its symbolic
representation. To create a test bench circuit, a new Cell view with a different Cell Name should
be created.
39. To include the created symbol, use the “Add Instance” option and select the respective library
and cell using the browse option and then the symbol should appear in schematic editor with the
mouse pointer.
40. Create an output pin. To include supply voltage and input signal sources, “Add Instance” option
shall be used. Browse to the “analogLib” library, select the Cell as “vdc”, View as “symbol” and
click on “Tab” key in the keyboard to get the device properties.
41. Mention the appropriate “DC voltage” based on the specification or technology node. Similarly,
for an input source, (for example) “vpulse” is considered and parameters like Voltage 1, Voltage
2, Period, Delay time, Rise time, Fall time and Pulse width are mentioned.
42. Similarly, “gnd” terminal shall be included to the circuit and the complete circuit.

FUNCTIONAL SIMULATION:

43. To simulate the design, Launch “ADE L”.


44. We get a window and following options are to be verified:
(1) Simulator – to make sure that Spectre is the simulator selected
(2) Model Libraries & Process Corners – to make sure that “.scs” file of the respective technology
node has been selected.
45. To analyze the circuit, select “Analyses” from the top menu in ADE L and under Analyses, select
“Choose”. The analyses chosen and the arguments that had been set up can be seen under
“Analyses” tab in the ADE L window. Similarly, rest of the analyses can be performed based on
designer’s demands.
46. To setup the simulation, select “Outputs” from the ADE L window and select “Setup” under
Outputs option. We get a “Setting Outputs” window as, select “From Design” which would bring
back the test bench circuit created for the simulation process. Select the input wire and output
wire and in ADE L, they are supposed to be displayed under “Outputs” option.
47. To run the simulation, select “Simulation” from ADE L and select the option “Netlist and Run”.
The design is simulated and waveforms are seen.
48. Input signals and Output signals can be seen separately by selecting “Graph -> Split All Strips”.
49. To save the simulation state, select “Session” under ADE L, select “Save State”, we get a “Saving
State” window. Select “Cell view” and select “OK” to save the state.
50. The simulation state and test bench circuit are viewed.

17
LAYOUT:

18
LAYOUT:

51. Open the schematic through the Library Manager and select “Launch -> Layout XL”.
52. A “Startup Option” window pops up. Select “Create New” under Layout tab, “Automatic” under
Configuration tab and select OK. A “New File” window pops up. No changes are to be made, so
select OK. Virtuoso Layout Suite XL Editing window can be seen.
53. To import the circuit components, select “Connectivity -> Generate -> All From Source”.
54. Select OK in the “Generate Layout” window, and the components of the circuit can be seen.
55. Select “Shift + F” to have a view of all the terminals of the transistors.
56. The blue colored box surrounding the circuit components is the PR (Placement & Routing)
Boundary. PR-Boundary can be shifted using the shortcut “S”. To shift the PR-Boundary, place
the mouse pointer close to the respective boundary so that it gets highlighted, make a left mouse
click to select the boundary, use the mouse or arrow (up, down, left or right) keys to shift the
boundary.
57. To attach “Bulk” terminal to the transistors, select the particular transistor by a left mouse click
58. Make a right mouse click and select “Properties”, select “Parameter -> Body tie Type ->
Integrated (or) Detached -> Left Tap (or) Right Tap” and select OK. Bulk terminal of that
transistor can be seen. Repeat the above steps for rest of the transistors to include the Bulk
terminal.
59. By default, the background available in the Virtuoso Layout Editor is the P-Substrate. So, the
PMOS transistors should be placed within an N-Well. This is mandatory for PMOS transistors in
gpdk090 and gpdk045, but for PMOS transistors in gpdk180, it has an N-Well by default. To
create an N-Well, select the respective layer from the “Layers” tab on the left-hand side of the
Virtuoso Layout Editor.
60. Select “R” to create N-Well in the shape of a rectangle surrounding the PMOS transistor.
61. The PMOS transistor is placed within the N-Well and to complete routing between the
components, we can use “P” which denotes “Path” in the layout and is meant for routing process.
62. When the mouse pointer is taken closer to any of the terminals of the components, the terminal
gets highlighted with a yellow color bold line, make a left click to start the path segment from one
terminal to another.
63. For routing between two different layers, usage of “Via” is mandatory. There are two options to
place a via. Start routing from the layer of interest, make a right-click, select “Via Down To..”
and select the layer of interest (or) select “Create” from the top menu, select “Via”, select the
respective via under “Via Definition”, make a left mouse click to place the via.
64. For the example used here, “VDD” is at the top and “VSS” is at the bottom. Source & Bulk of
PMOS/NMOS can be routed to VDD/VSS respectively as earlier between other pins and
terminals (or) the entire top layer can be used for VDD and bottom layer for VSS using “Pin
Placement” option.

19
20
65. Select “Place -> Pin Placement”, a window pops up. Under “Pin Planner” tab, “Pin Name,
Attributes & Create” options can be seen. Select “VDD” under “Pin Name”, select “Top” under
“Attributes -> Edge”, select “HRail” under “Create” and select “Apply” under “Attributes” to
place VDD at the top layer. Similarly, select “VSS” under “Pin Name”, select “Bottom” under
“Attributes -> Edge”, select “HRail” under “Create” and select “Apply” under “Attributes” to
place VSS at the bottom layer. After routing the terminals of PMOS/NMOS terminals with
VDD/VSS respectively, save the layout.
Result:

21
NAND using pseudo NMOS:

22
NAND using pseudo NMOS
AIM: Develop the schematic diagram and layout for an NAND in pseudo nMOS. Perform
experiment to verify its functional response with appropriate EDA tool. Also make a comment on
area requirement to develop it as an IC.

APPARATUS:
Cadence schematic editor
 Simulation: Spectre simulator.
 Technology: gpdk045

PROCEDURE:

1. Work space creation: Make a right click on the Desktop and select the option “Create Folder”.
2. Name the folder, for example, we have named it as “inverter”.
3. Open the created folder and you get the window.

INITIALISING csh & SOURCING cshrc.

4. Make a right click and select the option “Open in Terminal”


5. Type the command “csh” to initialize shell and source the cshrc file with the command
“source/home/install/cshrc”.

INVOKING VIRTUOSO:

6. Soon after we source the “cshrc” file, we get a display “Welcome to Cadence Tools Suite”. Now
invoke virtuoso using the command “virtuoso &” or “virtuoso”.
7. We get a virtuoso window.

CREATE A LIBRARY:

8. In virtuoso’s top menu, select “Tools” and select “Library Manager”. The Cadence Library
Manager appears.
9. From the top menu of the Library Manager, select “File -> New -> Library” to create a new
library for a new design.
10. We’ll get a “New Library” form where we can name the library that we create.
11. Select “OK” after the library is named.
12. Select “Technology File..” tab that keeps blinking at the bottom of the screen to map the created
library to a technology node based on the specification.
13. We get a form “Technology File for New Library”. Select the option “Attach to an existing
technology library”.
14. Select the respective Technology Node from the list of libraries. For example, we have selected
“gpdk045”.
15. The created library is now available in the Library Manager under Library.

CREATE A CELL:

16. Before creating a cell, make sure that the created library is selected. Only then the created cell can
be viewed under the respective library.
17. To create a Cell View, select File -> New -> Cell View.
18. Now we get a “New File” and we can name the Cell and check the Library, View and Type of the
respective Cell that is to be created.

23
SYMBOL:

24
19. We get the Virtuoso Schematic Editor.

ADD AN INSTANCE:

20. To add an instance to the circuit, select “Create -> Instance”. We can also use the bin key ‘I’ or
the icon
21. We get the “Add Instance” form.
22. Select “Browse” option we get the “Library Manager” to choose the transistors required for the
circuit and the type of view for the respective component from the respective Technology
Library.
23. After selecting the component, we get its properties like Length, Width, Multipliers, etc., Select
“Hide” at the end of the form, we can have a view of the transistor in the Schematic Editor.

ADD PIN:

24. To include pins to the circuit, select “Create -> Pin”. We can also use the bin key ‘P’ or the icon.
25. We name the pins and select its direction.
26. Place the pins by a left click on the mouse and the circuit can be viewed.

ADD WIRE:

27. Connect the pins and the components with the help of wire. Select “Create -> Wire”. We can also
use the bin key ‘W’ or the icon.
28. Once wiring is completed, the circuit can be viewed.

SAVE THE DESIGN:

29. After completing the design, it is mandatory to save the design before we move ahead to
Simulation. We have two options, “Save” and “Check and Save”.
30. Save option saves your design as it is but Check and Save option checks for any discontinuities
like floating net or terminal, provides the details of errors or warnings in the circuit and then
saves the design. The results can be seen in the virtuoso tab.

SYMBOL CREATION:

31. To create a symbol for the circuit, select “Create -> Cellview -> From Cellview”. Check the
Library Name, Cell Name, From View Name, To View Name, etc., and select OK.
32. We get the “Symbol Generation Options” window. We are free to decide upon the pin locations
with options like Left Pins, Right Pins, Top Pins and Bottom Pins.
33. Select OK. The tool opens a “Virtuoso Symbol Editor” window which shows a temporary view
of the symbol based on the pins assigned.
34. The symbol can be customized with the help of drawing tools.
35. To create custom symbol, remove the inner rectangle (green) and then using drawing tools,
custom symbol can be created. To remove the inner rectangle (green), place the mouse pointer
within the rectangle so that the entire rectangle gets highlighted, make a left click so that the
entire rectangle gets selected and click on delete in the keyboard to remove the rectangle so that it
is removed.

25
Test bench:

26
36. Since Inverter design is taken as an example in this manual, the focus is on creating its symbol.
To create a triangle, use “Create Line” option among the drawing tools and the way triangle is
created is as similar as how wiring is done in the schematic. To create a bubble, use “Create
Circle” option, decide a point, make a left click to expand the circle and again make a left click to
fix its size.
37. After creating the symbol, save the symbol using the “Check & Save” option.

TESTBENCH CIRCUIT FOR SIMULATION:

38. Instead of using transistor level design, test bench circuit can be created using its symbolic
representation. To create a test bench circuit, a new Cell view with a different Cell Name should
be created.
39. To include the created symbol, use the “Add Instance” option and select the respective library
and cell using the browse option and then the symbol should appear in schematic editor with the
mouse pointer.
40. Create an output pin. To include supply voltage and input signal sources, “Add Instance” option
shall be used. Browse to the “analogLib” library, select the Cell as “vdc”, View as “symbol” and
click on “Tab” key in the keyboard to get the device properties.
41. Mention the appropriate “DC voltage” based on the specification or technology node. Similarly,
for an input source, (for example) “vpulse” is considered and parameters like Voltage 1, Voltage
2, Period, Delay time, Rise time, Fall time and Pulse width are mentioned.
42. Similarly, “gnd” terminal shall be included to the circuit and the complete circuit.

FUNCTIONAL SIMULATION:

43. To simulate the design, Launch “ADE L”.


44. We get a window and following options are to be verified:
(1) Simulator – to make sure that Spectre is the simulator selected
(2) Model Libraries & Process Corners – to make sure that “.scs” file of the respective technology
node has been selected.
45. To analyze the circuit, select “Analyses” from the top menu in ADE L and under Analyses, select
“Choose”. The analyses chosen and the arguments that had been set up can be seen under
“Analyses” tab in the ADE L window. Similarly, rest of the analyses can be performed based on
designer’s demands.
46. To setup the simulation, select “Outputs” from the ADE L window and select “Setup” under
Outputs option. We get a “Setting Outputs” window as, select “From Design” which would bring
back the test bench circuit created for the simulation process. Select the input wire and output
wire and in ADE L, they are supposed to be displayed under “Outputs” option.
47. To run the simulation, select “Simulation” from ADE L and select the option “Netlist and Run”.
The design is simulated and waveforms are seen.
48. Input signals and Output signals can be seen separately by selecting “Graph -> Split All Strips”.
49. To save the simulation state, select “Session” under ADE L, select “Save State”, we get a “Saving
State” window. Select “Cell view” and select “OK” to save the state.
50. The simulation state and test bench circuit are viewed.

27
Waveforms:

28
LAYOUT:

51. Open the schematic through the Library Manager and select “Launch -> Layout XL”.
52. A “Startup Option” window pops up. Select “Create New” under Layout tab, “Automatic” under
Configuration tab and select OK. A “New File” window pops up. No changes are to be made, so
select OK. Virtuoso Layout Suite XL Editing window can be seen.
53. To import the circuit components, select “Connectivity -> Generate -> All From Source”.
54. Select OK in the “Generate Layout” window, and the components of the circuit can be seen.
55. Select “Shift + F” to have a view of all the terminals of the transistors.
56. The blue colored box surrounding the circuit components is the PR (Placement & Routing)
Boundary. PR-Boundary can be shifted using the shortcut “S”. To shift the PR-Boundary, place
the mouse pointer close to the respective boundary so that it gets highlighted, make a left mouse
click to select the boundary, use the mouse or arrow (up, down, left or right) keys to shift the
boundary.
57. To attach “Bulk” terminal to the transistors, select the particular transistor by a left mouse click
58. Make a right mouse click and select “Properties”, select “Parameter -> Body tie Type ->
Integrated (or) Detached -> Left Tap (or) Right Tap” and select OK. Bulk terminal of that
transistor can be seen. Repeat the above steps for rest of the transistors to include the Bulk
terminal.
59. By default, the background available in the Virtuoso Layout Editor is the P-Substrate. So, the
PMOS transistors should be placed within an N-Well. This is mandatory for PMOS transistors in
gpdk090 and gpdk045, but for PMOS transistors in gpdk180, it has an N-Well by default. To
create an N-Well, select the respective layer from the “Layers” tab on the left-hand side of the
Virtuoso Layout Editor.
60. Select “R” to create N-Well in the shape of a rectangle surrounding the PMOS transistor.
61. The PMOS transistor is placed within the N-Well and to complete routing between the
components, we can use “P” which denotes “Path” in the layout and is meant for routing process.
62. When the mouse pointer is taken closer to any of the terminals of the components, the terminal
gets highlighted with a yellow color bold line, make a left click to start the path segment from one
terminal to another.
63. For routing between two different layers, usage of “Via” is mandatory. There are two options to
place a via. Start routing from the layer of interest, make a right-click, select “Via Down To..”
and select the layer of interest (or) select “Create” from the top menu, select “Via”, select the
respective via under “Via Definition”, make a left mouse click to place the via.
64. For the example used here, “VDD” is at the top and “VSS” is at the bottom. Source & Bulk of
PMOS/NMOS can be routed to VDD/VSS respectively as earlier between other pins and
terminals (or) the entire top layer can be used for VDD and bottom layer for VSS using “Pin
Placement” option.

29
LAYOUT:

30
65. Select “Place -> Pin Placement”, a window pops up. Under “Pin Planner” tab, “Pin Name,
Attributes & Create” options can be seen. Select “VDD” under “Pin Name”, select “Top” under
“Attributes -> Edge”, select “HRail” under “Create” and select “Apply” under “Attributes” to
place VDD at the top layer. Similarly, select “VSS” under “Pin Name”, select “Bottom” under
“Attributes -> Edge”, select “HRail” under “Create” and select “Apply” under “Attributes” to
place VSS at the bottom layer. After routing the terminals of PMOS/NMOS terminals with
VDD/VSS respectively, save the layout.
Result:

31
NAND gate in only CMOS:

32
NAND gate in only CMOS
AIM: Develop the schematic diagram and layout for an NAND in only CMOS. Perform experiment
to verify its functional response with appropriate EDA tool. Also make a comment on area
requirement to develop it as an IC.

APPARATUS:
Cadence schematic editor
 Simulation: Spectre simulator.
 Technology: gpdk045

PROCEDURE:

1. Work space creation: Make a right click on the Desktop and select the option “Create Folder”.
2. Name the folder, for example, we have named it as “inverter”.
3. Open the created folder and you get the window.

INITIALISING csh & SOURCING cshrc.

4. Make a right click and select the option “Open in Terminal”


5. Type the command “csh” to initialize shell and source the cshrc file with the command
“source/home/install/cshrc”.

INVOKING VIRTUOSO:

6. Soon after we source the “cshrc” file, we get a display “Welcome to Cadence Tools Suite”.
Now invoke virtuoso using the command “virtuoso &” or “virtuoso”.
7. We get a virtuoso window.

CREATE A LIBRARY:

8. In virtuoso’s top menu, select “Tools” and select “Library Manager”. The Cadence Library
Manager appears.
9. From the top menu of the Library Manager, select “File -> New -> Library” to create a new
library for a new design.
10. We’ll get a “New Library” form where we can name the library that we create.
11. Select “OK” after the library is named.
12. Select “Technology File..” tab that keeps blinking at the bottom of the screen to map the
created library to a technology node based on the specification.
13. We get a form “Technology File for New Library”. Select the option “Attach to an existing
technology library”.
14. Select the respective Technology Node from the list of libraries. For example, we have
selected “gpdk045”.
15. The created library is now available in the Library Manager under Library.

CREATE A CELL:

16. Before creating a cell, make sure that the created library is selected. Only then the created cell
can be viewed under the respective library.
17. To create a Cell View, select File -> New -> Cell View.
18. Now we get a “New File” and we can name the Cell and check the Library, View and Type of
the respective Cell that is to be created.

33
Symbol:

34
19. We get the Virtuoso Schematic Editor.

ADD AN INSTANCE:

20. To add an instance to the circuit, select “Create -> Instance”. We can also use the bin key ‘I’
or the icon
21. We get the “Add Instance” form.
22. Select “Browse” option we get the “Library Manager” to choose the transistors required for
the circuit and the type of view for the respective component from the respective Technology
Library.
23. After selecting the component, we get its properties like Length, Width, Multipliers, etc.,
Select “Hide” at the end of the form, we can have a view of the transistor in the Schematic
Editor.

ADD PIN:

24. To include pins to the circuit, select “Create -> Pin”. We can also use the bin key ‘P’ or the
icon.
25. We name the pins and select its direction.
26. Place the pins by a left click on the mouse and the circuit can be viewed.

ADD WIRE:

27. Connect the pins and the components with the help of wire. Select “Create -> Wire”. We can
also use the bin key ‘W’ or the icon.
28. Once wiring is completed, the circuit can be viewed.

SAVE THE DESIGN:

29. After completing the design, it is mandatory to save the design before we move ahead to
Simulation. We have two options, “Save” and “Check and Save”.
30. Save option saves your design as it is but Check and Save option checks for any
discontinuities like floating net or terminal, provides the details of errors or warnings in the
circuit and then saves the design. The results can be seen in the virtuoso tab.

SYMBOL CREATION:

31. To create a symbol for the circuit, select “Create -> Cellview -> From Cellview”. Check the
Library Name, Cell Name, From View Name, To View Name, etc., and select OK.
32. We get the “Symbol Generation Options” window. We are free to decide upon the pin
locations with options like Left Pins, Right Pins, Top Pins and Bottom Pins.
33. Select OK. The tool opens a “Virtuoso Symbol Editor” window which shows a temporary
view of the symbol based on the pins assigned.
34. The symbol can be customized with the help of drawing tools.
35. To create custom symbol, remove the inner rectangle (green) and then using drawing tools,
custom symbol can be created. To remove the inner rectangle (green), place the mouse pointer
within the rectangle so that the entire rectangle gets highlighted, make a left click so that the
entire rectangle gets selected and click on delete in the keyboard to remove the rectangle so
that it is removed.

35
Testbench:

36
36. Since Inverter design is taken as an example in this manual, the focus is on creating its
symbol. To create a triangle, use “Create Line” option among the drawing tools and the way
triangle is created is as similar as how wiring is done in the schematic. To create a bubble, use
“Create Circle” option, decide a point, make a left click to expand the circle and again make a
left click to fix its size.
37. After creating the symbol, save the symbol using the “Check & Save” option.

TESTBENCH CIRCUIT FOR SIMULATION:

38. Instead of using transistor level design, test bench circuit can be created using its symbolic
representation. To create a test bench circuit, a new Cell view with a different Cell Name
should be created.
39. To include the created symbol, use the “Add Instance” option and select the respective library
and cell using the browse option and then the symbol should appear in schematic editor with
the mouse pointer.
40. Create an output pin. To include supply voltage and input signal sources, “Add Instance”
option shall be used. Browse to the “analogLib” library, select the Cell as “vdc”, View as
“symbol” and click on “Tab” key in the keyboard to get the device properties.
41. Mention the appropriate “DC voltage” based on the specification or technology node.
Similarly, for an input source, (for example) “vpulse” is considered and parameters like
Voltage 1, Voltage 2, Period, Delay time, Rise time, Fall time and Pulse width are mentioned.
42. Similarly, “gnd” terminal shall be included to the circuit and the complete circuit.

FUNCTIONAL SIMULATION:

43. To simulate the design, Launch “ADE L”.


44. We get a window and following options are to be verified:
(1) Simulator – to make sure that Spectre is the simulator selected
(2) Model Libraries & Process Corners – to make sure that “.scs” file of the respective technology
node has been selected.
45. To analyze the circuit, select “Analyses” from the top menu in ADE L and under Analyses,
select “Choose”. The analyses chosen and the arguments that had been set up can be seen
under “Analyses” tab in the ADE L window. Similarly, rest of the analyses can be performed
based on designer’s demands.
46. To setup the simulation, select “Outputs” from the ADE L window and select “Setup” under
Outputs option. We get a “Setting Outputs” window as, select “From Design” which would
bring back the test bench circuit created for the simulation process. Select the input wire and
output wire and in ADE L, they are supposed to be displayed under “Outputs” option.
47. To run the simulation, select “Simulation” from ADE L and select the option “Netlist and
Run”. The design is simulated and waveforms are seen.
48. Input signals and Output signals can be seen separately by selecting “Graph -> Split All
Strips”.
49. To save the simulation state, select “Session” under ADE L, select “Save State”, we get a
“Saving State” window. Select “Cell view” and select “OK” to save the state.
50. The simulation state and test bench circuit are viewed.

37
Waveforms:

38
LAYOUT:

51. Open the schematic through the Library Manager and select “Launch -> Layout XL”.
52. A “Startup Option” window pops up. Select “Create New” under Layout tab, “Automatic”
under Configuration tab and select OK. A “New File” window pops up. No changes are to be
made, so select OK. Virtuoso Layout Suite XL Editing window can be seen.
53. To import the circuit components, select “Connectivity -> Generate -> All From Source”.
54. Select OK in the “Generate Layout” window, and the components of the circuit can be seen.
55. Select “Shift + F” to have a view of all the terminals of the transistors.
56. The blue colored box surrounding the circuit components is the PR (Placement & Routing)
Boundary. PR-Boundary can be shifted using the shortcut “S”. To shift the PR-Boundary,
place the mouse pointer close to the respective boundary so that it gets highlighted, make a
left mouse click to select the boundary, use the mouse or arrow (up, down, left or right) keys
to shift the boundary.
57. To attach “Bulk” terminal to the transistors, select the particular transistor by a left mouse
click
58. Make a right mouse click and select “Properties”, select “Parameter -> Body tie Type ->
Integrated (or) Detached -> Left Tap (or) Right Tap” and select OK. Bulk terminal of that
transistor can be seen. Repeat the above steps for rest of the transistors to include the Bulk
terminal.
59. By default, the background available in the Virtuoso Layout Editor is the P-Substrate. So, the
PMOS transistors should be placed within an N-Well. This is mandatory for PMOS transistors
in gpdk090 and gpdk045, but for PMOS transistors in gpdk180, it has an N-Well by default.
To create an N-Well, select the respective layer from the “Layers” tab on the left-hand side of
the Virtuoso Layout Editor.
60. Select “R” to create N-Well in the shape of a rectangle surrounding the PMOS transistor.
61. The PMOS transistor is placed within the N-Well and to complete routing between the
components, we can use “P” which denotes “Path” in the layout and is meant for routing
process.
62. When the mouse pointer is taken closer to any of the terminals of the components, the
terminal gets highlighted with a yellow color bold line, make a left click to start the path
segment from one terminal to another.
63. For routing between two different layers, usage of “Via” is mandatory. There are two options
to place a via. Start routing from the layer of interest, make a right-click, select “Via Down
To..” and select the layer of interest (or) select “Create” from the top menu, select “Via”,
select the respective via under “Via Definition”, make a left mouse click to place the via.
64. For the example used here, “VDD” is at the top and “VSS” is at the bottom. Source & Bulk of
PMOS/NMOS can be routed to VDD/VSS respectively as earlier between other pins and
terminals (or) the entire top layer can be used for VDD and bottom layer for VSS using “Pin
Placement” option.

39
LAYOUT:

40
65. Select “Place -> Pin Placement”, a window pops up. Under “Pin Planner” tab, “Pin Name,
Attributes & Create” options can be seen. Select “VDD” under “Pin Name”, select “Top”
under “Attributes -> Edge”, select “HRail” under “Create” and select “Apply” under
“Attributes” to place VDD at the top layer. Similarly, select “VSS” under “Pin Name”, select
“Bottom” under “Attributes -> Edge”, select “HRail” under “Create” and select “Apply”
under “Attributes” to place VSS at the bottom layer. After routing the terminals of
PMOS/NMOS terminals with VDD/VSS respectively, save the layout.
Result:

41
NOR using only nMOS

42
NOR using only nMOS
AIM: Develop the schematic diagram and layout for an NOR in only nMOS. Perform experiment to
verify its functional response with appropriate EDA tool. Also make a comment on area requirement
to develop it as an IC.

APPARATUS:
Cadence schematic editor
 Simulation: Spectre simulator.
 Technology: gpdk045

PROCEDURE:

1. Work space creation: Make a right click on the Desktop and select the option “Create Folder”.
2. Name the folder, for example, we have named it as “inverter”.
3. Open the created folder and you get the window.

INITIALISING csh & SOURCING cshrc.

4. Make a right click and select the option “Open in Terminal”


5. Type the command “csh” to initialize shell and source the cshrc file with the command
“source/home/install/cshrc”.

INVOKING VIRTUOSO:

6. Soon after we source the “cshrc” file, we get a display “Welcome to Cadence Tools Suite”.
Now invoke virtuoso using the command “virtuoso &” or “virtuoso”.
7. We get a virtuoso window.

CREATE A LIBRARY:

8. In virtuoso’s top menu, select “Tools” and select “Library Manager”. The Cadence Library
Manager appears.
9. From the top menu of the Library Manager, select “File -> New -> Library” to create a new
library for a new design.
10. We’ll get a “New Library” form where we can name the library that we create.
11. Select “OK” after the library is named.
12. Select “Technology File..” tab that keeps blinking at the bottom of the screen to map the
created library to a technology node based on the specification.
13. We get a form “Technology File for New Library”. Select the option “Attach to an existing
technology library”.
14. Select the respective Technology Node from the list of libraries. For example, we have
selected “gpdk045”.
15. The created library is now available in the Library Manager under Library.

CREATE A CELL:

16. Before creating a cell, make sure that the created library is selected. Only then the created cell
can be viewed under the respective library.
17. To create a Cell View, select File -> New -> Cell View.
18. Now we get a “New File” and we can name the Cell and check the Library, View and Type of
the respective Cell that is to be created.

43
Symbol:

44
19. We get the Virtuoso Schematic Editor.

ADD AN INSTANCE:

20. To add an instance to the circuit, select “Create -> Instance”. We can also use the bin key ‘I’
or the icon
21. We get the “Add Instance” form.
22. Select “Browse” option we get the “Library Manager” to choose the transistors required for
the circuit and the type of view for the respective component from the respective Technology
Library.
23. After selecting the component, we get its properties like Length, Width, Multipliers, etc.,
Select “Hide” at the end of the form, we can have a view of the transistor in the Schematic
Editor.

ADD PIN:

24. To include pins to the circuit, select “Create -> Pin”. We can also use the bin key ‘P’ or the
icon.
25. We name the pins and select its direction.
26. Place the pins by a left click on the mouse and the circuit can be viewed.

ADD WIRE:

27. Connect the pins and the components with the help of wire. Select “Create -> Wire”. We can
also use the bin key ‘W’ or the icon.
28. Once wiring is completed, the circuit can be viewed.

SAVE THE DESIGN:

29. After completing the design, it is mandatory to save the design before we move ahead to
Simulation. We have two options, “Save” and “Check and Save”.
30. Save option saves your design as it is but Check and Save option checks for any
discontinuities like floating net or terminal, provides the details of errors or warnings in the
circuit and then saves the design. The results can be seen in the virtuoso tab.

SYMBOL CREATION:

31. To create a symbol for the circuit, select “Create -> Cellview -> From Cellview”. Check the
Library Name, Cell Name, From View Name, To View Name, etc., and select OK.
32. We get the “Symbol Generation Options” window. We are free to decide upon the pin
locations with options like Left Pins, Right Pins, Top Pins and Bottom Pins.
33. Select OK. The tool opens a “Virtuoso Symbol Editor” window which shows a temporary
view of the symbol based on the pins assigned.
34. The symbol can be customized with the help of drawing tools.
35. To create custom symbol, remove the inner rectangle (green) and then using drawing tools,
custom symbol can be created. To remove the inner rectangle (green), place the mouse pointer
within the rectangle so that the entire rectangle gets highlighted, make a left click so that the
entire rectangle gets selected and click on delete in the keyboard to remove the rectangle so
that it is removed.

45
Testbench:

46
36. Since Inverter design is taken as an example in this manual, the focus is on creating its
symbol. To create a triangle, use “Create Line” option among the drawing tools and the way
triangle is created is as similar as how wiring is done in the schematic. To create a bubble, use
“Create Circle” option, decide a point, make a left click to expand the circle and again make a
left click to fix its size.
37. After creating the symbol, save the symbol using the “Check & Save” option.

TESTBENCH CIRCUIT FOR SIMULATION:

38. Instead of using transistor level design, test bench circuit can be created using its symbolic
representation. To create a test bench circuit, a new Cell view with a different Cell Name
should be created.
39. To include the created symbol, use the “Add Instance” option and select the respective library
and cell using the browse option and then the symbol should appear in schematic editor with
the mouse pointer.
40. Create an output pin. To include supply voltage and input signal sources, “Add Instance”
option shall be used. Browse to the “analogLib” library, select the Cell as “vdc”, View as
“symbol” and click on “Tab” key in the keyboard to get the device properties.
41. Mention the appropriate “DC voltage” based on the specification or technology node.
Similarly, for an input source, (for example) “vpulse” is considered and parameters like
Voltage 1, Voltage 2, Period, Delay time, Rise time, Fall time and Pulse width are mentioned.
42. Similarly, “gnd” terminal shall be included to the circuit and the complete circuit.

FUNCTIONAL SIMULATION:

43. To simulate the design, Launch “ADE L”.


44. We get a window and following options are to be verified:
(1) Simulator – to make sure that Spectre is the simulator selected
(2) Model Libraries & Process Corners – to make sure that “.scs” file of the respective technology
node has been selected.
45. To analyze the circuit, select “Analyses” from the top menu in ADE L and under Analyses,
select “Choose”. The analyses chosen and the arguments that had been set up can be seen
under “Analyses” tab in the ADE L window. Similarly, rest of the analyses can be performed
based on designer’s demands.
46. To setup the simulation, select “Outputs” from the ADE L window and select “Setup” under
Outputs option. We get a “Setting Outputs” window as, select “From Design” which would
bring back the test bench circuit created for the simulation process. Select the input wire and
output wire and in ADE L, they are supposed to be displayed under “Outputs” option.
47. To run the simulation, select “Simulation” from ADE L and select the option “Netlist and
Run”. The design is simulated and waveforms are seen.
48. Input signals and Output signals can be seen separately by selecting “Graph -> Split All
Strips”.
49. To save the simulation state, select “Session” under ADE L, select “Save State”, we get a
“Saving State” window. Select “Cell view” and select “OK” to save the state.
50. The simulation state and test bench circuit are viewed.

47
Waveforms:

48
LAYOUT:

51. Open the schematic through the Library Manager and select “Launch -> Layout XL”.
52. A “Startup Option” window pops up. Select “Create New” under Layout tab, “Automatic”
under Configuration tab and select OK. A “New File” window pops up. No changes are to be
made, so select OK. Virtuoso Layout Suite XL Editing window can be seen.
53. To import the circuit components, select “Connectivity -> Generate -> All From Source”.
54. Select OK in the “Generate Layout” window, and the components of the circuit can be seen.
55. Select “Shift + F” to have a view of all the terminals of the transistors.
56. The blue colored box surrounding the circuit components is the PR (Placement & Routing)
Boundary. PR-Boundary can be shifted using the shortcut “S”. To shift the PR-Boundary,
place the mouse pointer close to the respective boundary so that it gets highlighted, make a
left mouse click to select the boundary, use the mouse or arrow (up, down, left or right) keys
to shift the boundary.
57. To attach “Bulk” terminal to the transistors, select the particular transistor by a left mouse
click
58. Make a right mouse click and select “Properties”, select “Parameter -> Body tie Type ->
Integrated (or) Detached -> Left Tap (or) Right Tap” and select OK. Bulk terminal of that
transistor can be seen. Repeat the above steps for rest of the transistors to include the Bulk
terminal.
59. By default, the background available in the Virtuoso Layout Editor is the P-Substrate. So, the
PMOS transistors should be placed within an N-Well. This is mandatory for PMOS transistors
in gpdk090 and gpdk045, but for PMOS transistors in gpdk180, it has an N-Well by default.
To create an N-Well, select the respective layer from the “Layers” tab on the left-hand side of
the Virtuoso Layout Editor.
60. Select “R” to create N-Well in the shape of a rectangle surrounding the PMOS transistor.
61. The PMOS transistor is placed within the N-Well and to complete routing between the
components, we can use “P” which denotes “Path” in the layout and is meant for routing
process.
62. When the mouse pointer is taken closer to any of the terminals of the components, the
terminal gets highlighted with a yellow color bold line, make a left click to start the path
segment from one terminal to another.
63. For routing between two different layers, usage of “Via” is mandatory. There are two options
to place a via. Start routing from the layer of interest, make a right-click, select “Via Down
To..” and select the layer of interest (or) select “Create” from the top menu, select “Via”,
select the respective via under “Via Definition”, make a left mouse click to place the via.
64. For the example used here, “VDD” is at the top and “VSS” is at the bottom. Source & Bulk of
PMOS/NMOS can be routed to VDD/VSS respectively as earlier between other pins and
terminals (or) the entire top layer can be used for VDD and bottom layer for VSS using “Pin
Placement” option.

49
LAYOUT:

50
65. Select “Place -> Pin Placement”, a window pops up. Under “Pin Planner” tab, “Pin Name,
Attributes & Create” options can be seen. Select “VDD” under “Pin Name”, select “Top”
under “Attributes -> Edge”, select “HRail” under “Create” and select “Apply” under
“Attributes” to place VDD at the top layer. Similarly, select “VSS” under “Pin Name”, select
“Bottom” under “Attributes -> Edge”, select “HRail” under “Create” and select “Apply”
under “Attributes” to place VSS at the bottom layer. After routing the terminals of
PMOS/NMOS terminals with VDD/VSS respectively, save the layout.
Result:

51
NOR using CMOS:

52
NOR using CMOS
AIM: Develop the schematic diagram and layout for an NOR in only CMOS. Perform experiment to
verify its functional response with appropriate EDA tool. Also make a comment on area requirement
to develop it as an IC.

APPARATUS:
Cadence schematic editor
 Simulation: Spectre simulator.
 Technology: gpdk045

PROCEDURE:

1. Work space creation: Make a right click on the Desktop and select the option “Create Folder”.
2. Name the folder, for example, we have named it as “inverter”.
3. Open the created folder and you get the window.

INITIALISING csh & SOURCING cshrc.

4. Make a right click and select the option “Open in Terminal”


5. Type the command “csh” to initialize shell and source the cshrc file with the command
“source/home/install/cshrc”.

INVOKING VIRTUOSO:

6. Soon after we source the “cshrc” file, we get a display “Welcome to Cadence Tools Suite”.
Now invoke virtuoso using the command “virtuoso &” or “virtuoso”.
7. We get a virtuoso window.

CREATE A LIBRARY:

8. In virtuoso’s top menu, select “Tools” and select “Library Manager”. The Cadence Library
Manager appears.
9. From the top menu of the Library Manager, select “File -> New -> Library” to create a new
library for a new design.
10. We’ll get a “New Library” form where we can name the library that we create.
11. Select “OK” after the library is named.
12. Select “Technology File..” tab that keeps blinking at the bottom of the screen to map the
created library to a technology node based on the specification.
13. We get a form “Technology File for New Library”. Select the option “Attach to an existing
technology library”.
14. Select the respective Technology Node from the list of libraries. For example, we have
selected “gpdk045”.
15. The created library is now available in the Library Manager under Library.

CREATE A CELL:

16. Before creating a cell, make sure that the created library is selected. Only then the created cell
can be viewed under the respective library.
17. To create a Cell View, select File -> New -> Cell View.
18. Now we get a “New File” and we can name the Cell and check the Library, View and Type of
the respective Cell that is to be created.

53
Symbol:

54
19. We get the Virtuoso Schematic Editor.

ADD AN INSTANCE:

20. To add an instance to the circuit, select “Create -> Instance”. We can also use the bin key ‘I’
or the icon
21. We get the “Add Instance” form.
22. Select “Browse” option we get the “Library Manager” to choose the transistors required for
the circuit and the type of view for the respective component from the respective Technology
Library.
23. After selecting the component, we get its properties like Length, Width, Multipliers, etc.,
Select “Hide” at the end of the form, we can have a view of the transistor in the Schematic
Editor.

ADD PIN:

24. To include pins to the circuit, select “Create -> Pin”. We can also use the bin key ‘P’ or the
icon.
25. We name the pins and select its direction.
26. Place the pins by a left click on the mouse and the circuit can be viewed.

ADD WIRE:

27. Connect the pins and the components with the help of wire. Select “Create -> Wire”. We can
also use the bin key ‘W’ or the icon.
28. Once wiring is completed, the circuit can be viewed.

SAVE THE DESIGN:

29. After completing the design, it is mandatory to save the design before we move ahead to
Simulation. We have two options, “Save” and “Check and Save”.
30. Save option saves your design as it is but Check and Save option checks for any
discontinuities like floating net or terminal, provides the details of errors or warnings in the
circuit and then saves the design. The results can be seen in the virtuoso tab.

SYMBOL CREATION:

31. To create a symbol for the circuit, select “Create -> Cellview -> From Cellview”. Check the
Library Name, Cell Name, From View Name, To View Name, etc., and select OK.
32. We get the “Symbol Generation Options” window. We are free to decide upon the pin
locations with options like Left Pins, Right Pins, Top Pins and Bottom Pins.
33. Select OK. The tool opens a “Virtuoso Symbol Editor” window which shows a temporary
view of the symbol based on the pins assigned.
34. The symbol can be customized with the help of drawing tools.
35. To create custom symbol, remove the inner rectangle (green) and then using drawing tools,
custom symbol can be created. To remove the inner rectangle (green), place the mouse pointer
within the rectangle so that the entire rectangle gets highlighted, make a left click so that the
entire rectangle gets selected and click on delete in the keyboard to remove the rectangle so
that it is removed.

55
Test bench:

56
36. Since Inverter design is taken as an example in this manual, the focus is on creating its
symbol. To create a triangle, use “Create Line” option among the drawing tools and the way
triangle is created is as similar as how wiring is done in the schematic. To create a bubble, use
“Create Circle” option, decide a point, make a left click to expand the circle and again make a
left click to fix its size.
37. After creating the symbol, save the symbol using the “Check & Save” option.

TESTBENCH CIRCUIT FOR SIMULATION:

38. Instead of using transistor level design, test bench circuit can be created using its symbolic
representation. To create a test bench circuit, a new Cell view with a different Cell Name
should be created.
39. To include the created symbol, use the “Add Instance” option and select the respective library
and cell using the browse option and then the symbol should appear in schematic editor with
the mouse pointer.
40. Create an output pin. To include supply voltage and input signal sources, “Add Instance”
option shall be used. Browse to the “analogLib” library, select the Cell as “vdc”, View as
“symbol” and click on “Tab” key in the keyboard to get the device properties.
41. Mention the appropriate “DC voltage” based on the specification or technology node.
Similarly, for an input source, (for example) “vpulse” is considered and parameters like
Voltage 1, Voltage 2, Period, Delay time, Rise time, Fall time and Pulse width are mentioned.
42. Similarly, “gnd” terminal shall be included to the circuit and the complete circuit.

FUNCTIONAL SIMULATION:

43. To simulate the design, Launch “ADE L”.


44. We get a window and following options are to be verified:
(1) Simulator – to make sure that Spectre is the simulator selected
(2) Model Libraries & Process Corners – to make sure that “.scs” file of the respective technology
node has been selected.
45. To analyze the circuit, select “Analyses” from the top menu in ADE L and under Analyses,
select “Choose”. The analyses chosen and the arguments that had been set up can be seen
under “Analyses” tab in the ADE L window. Similarly, rest of the analyses can be performed
based on designer’s demands.
46. To setup the simulation, select “Outputs” from the ADE L window and select “Setup” under
Outputs option. We get a “Setting Outputs” window as, select “From Design” which would
bring back the test bench circuit created for the simulation process. Select the input wire and
output wire and in ADE L, they are supposed to be displayed under “Outputs” option.
47. To run the simulation, select “Simulation” from ADE L and select the option “Netlist and
Run”. The design is simulated and waveforms are seen.
48. Input signals and Output signals can be seen separately by selecting “Graph -> Split All
Strips”.
49. To save the simulation state, select “Session” under ADE L, select “Save State”, we get a
“Saving State” window. Select “Cell view” and select “OK” to save the state.
50. The simulation state and test bench circuit are viewed.

57
Waveforms:

58
LAYOUT:

51. Open the schematic through the Library Manager and select “Launch -> Layout XL”.
52. A “Startup Option” window pops up. Select “Create New” under Layout tab, “Automatic”
under Configuration tab and select OK. A “New File” window pops up. No changes are to be
made, so select OK. Virtuoso Layout Suite XL Editing window can be seen.
53. To import the circuit components, select “Connectivity -> Generate -> All From Source”.
54. Select OK in the “Generate Layout” window, and the components of the circuit can be seen.
55. Select “Shift + F” to have a view of all the terminals of the transistors.
56. The blue colored box surrounding the circuit components is the PR (Placement & Routing)
Boundary. PR-Boundary can be shifted using the shortcut “S”. To shift the PR-Boundary,
place the mouse pointer close to the respective boundary so that it gets highlighted, make a
left mouse click to select the boundary, use the mouse or arrow (up, down, left or right) keys
to shift the boundary.
57. To attach “Bulk” terminal to the transistors, select the particular transistor by a left mouse
click
58. Make a right mouse click and select “Properties”, select “Parameter -> Body tie Type ->
Integrated (or) Detached -> Left Tap (or) Right Tap” and select OK. Bulk terminal of that
transistor can be seen. Repeat the above steps for rest of the transistors to include the Bulk
terminal.
59. By default, the background available in the Virtuoso Layout Editor is the P-Substrate. So, the
PMOS transistors should be placed within an N-Well. This is mandatory for PMOS transistors
in gpdk090 and gpdk045, but for PMOS transistors in gpdk180, it has an N-Well by default.
To create an N-Well, select the respective layer from the “Layers” tab on the left-hand side of
the Virtuoso Layout Editor.
60. Select “R” to create N-Well in the shape of a rectangle surrounding the PMOS transistor.
61. The PMOS transistor is placed within the N-Well and to complete routing between the
components, we can use “P” which denotes “Path” in the layout and is meant for routing
process.
62. When the mouse pointer is taken closer to any of the terminals of the components, the
terminal gets highlighted with a yellow color bold line, make a left click to start the path
segment from one terminal to another.
63. For routing between two different layers, usage of “Via” is mandatory. There are two options
to place a via. Start routing from the layer of interest, make a right-click, select “Via Down
To..” and select the layer of interest (or) select “Create” from the top menu, select “Via”,
select the respective via under “Via Definition”, make a left mouse click to place the via.
64. For the example used here, “VDD” is at the top and “VSS” is at the bottom. Source & Bulk of
PMOS/NMOS can be routed to VDD/VSS respectively as earlier between other pins and
terminals (or) the entire top layer can be used for VDD and bottom layer for VSS using “Pin
Placement” option.

59
Layout:

60
65. Select “Place -> Pin Placement”, a window pops up. Under “Pin Planner” tab, “Pin Name,
Attributes & Create” options can be seen. Select “VDD” under “Pin Name”, select “Top”
under “Attributes -> Edge”, select “HRail” under “Create” and select “Apply” under
“Attributes” to place VDD at the top layer. Similarly, select “VSS” under “Pin Name”, select
“Bottom” under “Attributes -> Edge”, select “HRail” under “Create” and select “Apply”
under “Attributes” to place VSS at the bottom layer. After routing the terminals of
PMOS/NMOS terminals with VDD/VSS respectively, save the layout.
Result:

61
Schematic Diagram

62
HALFADDER using NAND CMOS
AIM: Develop the schematic diagram and layout for an HALFADDER in only NAND CMOS.
Perform experiment to verify its functional response with appropriate EDA tool. Also make a
comment on area requirement to develop it as an IC.

APPARATUS:
Cadence schematic editor
 Simulation: Spectre simulator.
 Technology: gpdk045

PROCEDURE:

1. Work space creation: Make a right click on the Desktop and select the option “Create Folder”.
2. Name the folder, for example, we have named it as “inverter”.
3. Open the created folder and you get the window.

INITIALISING csh & SOURCING cshrc.

4. Make a right click and select the option “Open in Terminal”


5. Type the command “csh” to initialize shell and source the cshrc file with the command
“source/home/install/cshrc”.

INVOKING VIRTUOSO:

6. Soon after we source the “cshrc” file, we get a display “Welcome to Cadence Tools Suite”.
Now invoke virtuoso using the command “virtuoso &” or “virtuoso”.
7. We get a virtuoso window.

CREATE A LIBRARY:

8. In virtuoso’s top menu, select “Tools” and select “Library Manager”. The Cadence Library
Manager appears.
9. From the top menu of the Library Manager, select “File -> New -> Library” to create a new
library for a new design.
10. We’ll get a “New Library” form where we can name the library that we create.
11. Select “OK” after the library is named.
12. Select “Technology File..” tab that keeps blinking at the bottom of the screen to map the
created library to a technology node based on the specification.
13. We get a form “Technology File for New Library”. Select the option “Attach to an existing
technology library”.
14. Select the respective Technology Node from the list of libraries. For example, we have
selected “gpdk045”.
15. The created library is now available in the Library Manager under Library.

CREATE A CELL:

16. Before creating a cell, make sure that the created library is selected. Only then the created cell
can be viewed under the respective library.
17. To create a Cell View, select File -> New -> Cell View.
18. Now we get a “New File” and we can name the Cell and check the Library, View and Type of
the respective Cell that is to be created.
63
Symbol:

64
19. We get the Virtuoso Schematic Editor.

ADD AN INSTANCE:

20. To add an instance to the circuit, select “Create -> Instance”. We can also use the bin key ‘I’
or the icon
21. We get the “Add Instance” form.
22. Select “Browse” option we get the “Library Manager” to choose the transistors required for
the circuit and the type of view for the respective component from the respective Technology
Library.
23. After selecting the component, we get its properties like Length, Width, Multipliers, etc.,
Select “Hide” at the end of the form, we can have a view of the transistor in the Schematic
Editor.

ADD PIN:

24. To include pins to the circuit, select “Create -> Pin”. We can also use the bin key ‘P’ or the
icon.
25. We name the pins and select its direction.
26. Place the pins by a left click on the mouse and the circuit can be viewed.

ADD WIRE:

27. Connect the pins and the components with the help of wire. Select “Create -> Wire”. We can
also use the bin key ‘W’ or the icon.
28. Once wiring is completed, the circuit can be viewed.

SAVE THE DESIGN:

29. After completing the design, it is mandatory to save the design before we move ahead to
Simulation. We have two options, “Save” and “Check and Save”.
30. Save option saves your design as it is but Check and Save option checks for any
discontinuities like floating net or terminal, provides the details of errors or warnings in the
circuit and then saves the design. The results can be seen in the virtuoso tab.

SYMBOL CREATION:

31. To create a symbol for the circuit, select “Create -> Cellview -> From Cellview”. Check the
Library Name, Cell Name, From View Name, To View Name, etc., and select OK.
32. We get the “Symbol Generation Options” window. We are free to decide upon the pin
locations with options like Left Pins, Right Pins, Top Pins and Bottom Pins.
33. Select OK. The tool opens a “Virtuoso Symbol Editor” window which shows a temporary
view of the symbol based on the pins assigned.
34. The symbol can be customized with the help of drawing tools.
35. To create custom symbol, remove the inner rectangle (green) and then using drawing tools,
custom symbol can be created. To remove the inner rectangle (green), place the mouse pointer
within the rectangle so that the entire rectangle gets highlighted, make a left click so that the
entire rectangle gets selected and click on delete in the keyboard to remove the rectangle so
that it is removed.

65
Test bench:

66
36. Since Inverter design is taken as an example in this manual, the focus is on creating its
symbol. To create a triangle, use “Create Line” option among the drawing tools and the way
triangle is created is as similar as how wiring is done in the schematic. To create a bubble, use
“Create Circle” option, decide a point, make a left click to expand the circle and again make a
left click to fix its size.
37. After creating the symbol, save the symbol using the “Check & Save” option.

TESTBENCH CIRCUIT FOR SIMULATION:

38. Instead of using transistor level design, test bench circuit can be created using its symbolic
representation. To create a test bench circuit, a new Cell view with a different Cell Name
should be created.
39. To include the created symbol, use the “Add Instance” option and select the respective library
and cell using the browse option and then the symbol should appear in schematic editor with
the mouse pointer.
40. Create an output pin. To include supply voltage and input signal sources, “Add Instance”
option shall be used. Browse to the “analogLib” library, select the Cell as “vdc”, View as
“symbol” and click on “Tab” key in the keyboard to get the device properties.
41. Mention the appropriate “DC voltage” based on the specification or technology node.
Similarly, for an input source, (for example) “vpulse” is considered and parameters like
Voltage 1, Voltage 2, Period, Delay time, Rise time, Fall time and Pulse width are mentioned.
42. Similarly, “gnd” terminal shall be included to the circuit and the complete circuit.

FUNCTIONAL SIMULATION:

43. To simulate the design, Launch “ADE L”.


44. We get a window and following options are to be verified:
(1) Simulator – to make sure that Spectre is the simulator selected
(2) Model Libraries & Process Corners – to make sure that “.scs” file of the respective technology
node has been selected.
45. To analyze the circuit, select “Analyses” from the top menu in ADE L and under Analyses,
select “Choose”. The analyses chosen and the arguments that had been set up can be seen
under “Analyses” tab in the ADE L window. Similarly, rest of the analyses can be performed
based on designer’s demands.
46. To setup the simulation, select “Outputs” from the ADE L window and select “Setup” under
Outputs option. We get a “Setting Outputs” window as, select “From Design” which would
bring back the test bench circuit created for the simulation process. Select the input wire and
output wire and in ADE L, they are supposed to be displayed under “Outputs” option.
47. To run the simulation, select “Simulation” from ADE L and select the option “Netlist and
Run”. The design is simulated and waveforms are seen.
48. Input signals and Output signals can be seen separately by selecting “Graph -> Split All
Strips”.
49. To save the simulation state, select “Session” under ADE L, select “Save State”, we get a
“Saving State” window. Select “Cell view” and select “OK” to save the state.
50. The simulation state and test bench circuit are viewed.

67
Waveforms:

68
LAYOUT:

51. Open the schematic through the Library Manager and select “Launch -> Layout XL”.
52. A “Startup Option” window pops up. Select “Create New” under Layout tab, “Automatic”
under Configuration tab and select OK. A “New File” window pops up. No changes are to be
made, so select OK. Virtuoso Layout Suite XL Editing window can be seen.
53. To import the circuit components, select “Connectivity -> Generate -> All From Source”.
54. Select OK in the “Generate Layout” window, and the components of the circuit can be seen.
55. Select “Shift + F” to have a view of all the terminals of the transistors.
56. The blue colored box surrounding the circuit components is the PR (Placement & Routing)
Boundary. PR-Boundary can be shifted using the shortcut “S”. To shift the PR-Boundary,
place the mouse pointer close to the respective boundary so that it gets highlighted, make a
left mouse click to select the boundary, use the mouse or arrow (up, down, left or right) keys
to shift the boundary.
57. To attach “Bulk” terminal to the transistors, select the particular transistor by a left mouse
click
58. Make a right mouse click and select “Properties”, select “Parameter -> Body tie Type ->
Integrated (or) Detached -> Left Tap (or) Right Tap” and select OK. Bulk terminal of that
transistor can be seen. Repeat the above steps for rest of the transistors to include the Bulk
terminal.
59. By default, the background available in the Virtuoso Layout Editor is the P-Substrate. So, the
PMOS transistors should be placed within an N-Well. This is mandatory for PMOS transistors
in gpdk090 and gpdk045, but for PMOS transistors in gpdk180, it has an N-Well by default.
To create an N-Well, select the respective layer from the “Layers” tab on the left-hand side of
the Virtuoso Layout Editor.
60. Select “R” to create N-Well in the shape of a rectangle surrounding the PMOS transistor.
61. The PMOS transistor is placed within the N-Well and to complete routing between the
components, we can use “P” which denotes “Path” in the layout and is meant for routing
process.
62. When the mouse pointer is taken closer to any of the terminals of the components, the
terminal gets highlighted with a yellow color bold line, make a left click to start the path
segment from one terminal to another.
63. For routing between two different layers, usage of “Via” is mandatory. There are two options
to place a via. Start routing from the layer of interest, make a right-click, select “Via Down
To..” and select the layer of interest (or) select “Create” from the top menu, select “Via”,
select the respective via under “Via Definition”, make a left mouse click to place the via.
64. For the example used here, “VDD” is at the top and “VSS” is at the bottom. Source & Bulk of
PMOS/NMOS can be routed to VDD/VSS respectively as earlier between other pins and
terminals (or) the entire top layer can be used for VDD and bottom layer for VSS using “Pin
Placement” option.

69
70
65. Select “Place -> Pin Placement”, a window pops up. Under “Pin Planner” tab, “Pin Name,
Attributes & Create” options can be seen. Select “VDD” under “Pin Name”, select “Top” under
“Attributes -> Edge”, select “HRail” under “Create” and select “Apply” under “Attributes” to
place VDD at the top layer. Similarly, select “VSS” under “Pin Name”, select “Bottom” under
“Attributes -> Edge”, select “HRail” under “Create” and select “Apply” under “Attributes” to
place VSS at the bottom layer. After routing the terminals of PMOS/NMOS terminals with
VDD/VSS respectively, save the layout.
Result:

71
SCHEMATIC DIAGRAM

72
FULL ADDER
AIM: Develop the schematic diagram and layout for aFULL ADDER. Perform experiment to verify
its functional response with appropriate EDA tool. Also make a comment on area requirement to
develop it as an IC.

APPARATUS:
Cadence schematic editor
 Simulation: Spectre simulator.
 Technology: gpdk045

PROCEDURE:

1. Work space creation: Make a right click on the Desktop and select the option “Create Folder”.
2. Name the folder, for example, we have named it as “inverter”.
3. Open the created folder and you get the window.

INITIALISING csh & SOURCING cshrc.

4. Make a right click and select the option “Open in Terminal”


5. Type the command “csh” to initialize shell and source the cshrc file with the command
“source/home/install/cshrc”.

INVOKING VIRTUOSO:

6. Soon after we source the “cshrc” file, we get a display “Welcome to Cadence Tools Suite”.
Now invoke virtuoso using the command “virtuoso &” or “virtuoso”.
7. We get a virtuoso window.

CREATE A LIBRARY:

8. In virtuoso’s top menu, select “Tools” and select “Library Manager”. The Cadence Library
Manager appears.
9. From the top menu of the Library Manager, select “File -> New -> Library” to create a new
library for a new design.
10. We’ll get a “New Library” form where we can name the library that we create.
11. Select “OK” after the library is named.
12. Select “Technology File..” tab that keeps blinking at the bottom of the screen to map the
created library to a technology node based on the specification.
13. We get a form “Technology File for New Library”. Select the option “Attach to an existing
technology library”.
14. Select the respective Technology Node from the list of libraries. For example, we have
selected “gpdk045”.
15. The created library is now available in the Library Manager under Library.

CREATE A CELL:

16. Before creating a cell, make sure that the created library is selected. Only then the created cell
can be viewed under the respective library.
17. To create a Cell View, select File -> New -> Cell View.
18. Now we get a “New File” and we can name the Cell and check the Library, View and Type of
the respective Cell that is to be created.
73
SYMBOL

74
19. We get the Virtuoso Schematic Editor.

ADD AN INSTANCE:

20. To add an instance to the circuit, select “Create -> Instance”. We can also use the bin key ‘I’
or the icon
21. We get the “Add Instance” form.
22. Select “Browse” option we get the “Library Manager” to choose the transistors required for
the circuit and the type of view for the respective component from the respective Technology
Library.
23. After selecting the component, we get its properties like Length, Width, Multipliers, etc.,
Select “Hide” at the end of the form, we can have a view of the transistor in the Schematic
Editor.

ADD PIN:

24. To include pins to the circuit, select “Create -> Pin”. We can also use the bin key ‘P’ or the
icon.
25. We name the pins and select its direction.
26. Place the pins by a left click on the mouse and the circuit can be viewed.

ADD WIRE:

27. Connect the pins and the components with the help of wire. Select “Create -> Wire”. We can
also use the bin key ‘W’ or the icon.
28. Once wiring is completed, the circuit can be viewed.

SAVE THE DESIGN:

29. After completing the design, it is mandatory to save the design before we move ahead to
Simulation. We have two options, “Save” and “Check and Save”.
30. Save option saves your design as it is but Check and Save option checks for any
discontinuities like floating net or terminal, provides the details of errors or warnings in the
circuit and then saves the design. The results can be seen in the virtuoso tab.

SYMBOL CREATION:

31. To create a symbol for the circuit, select “Create -> Cellview -> From Cellview”. Check the
Library Name, Cell Name, From View Name, To View Name, etc., and select OK.
32. We get the “Symbol Generation Options” window. We are free to decide upon the pin
locations with options like Left Pins, Right Pins, Top Pins and Bottom Pins.
33. Select OK. The tool opens a “Virtuoso Symbol Editor” window which shows a temporary
view of the symbol based on the pins assigned.
34. The symbol can be customized with the help of drawing tools.
35. To create custom symbol, remove the inner rectangle (green) and then using drawing tools,
custom symbol can be created. To remove the inner rectangle (green), place the mouse pointer
within the rectangle so that the entire rectangle gets highlighted, make a left click so that the
entire rectangle gets selected and click on delete in the keyboard to remove the rectangle so
that it is removed.

75
Test bench:

76
36. Since Inverter design is taken as an example in this manual, the focus is on creating its
symbol. To create a triangle, use “Create Line” option among the drawing tools and the way
triangle is created is as similar as how wiring is done in the schematic. To create a bubble, use
“Create Circle” option, decide a point, make a left click to expand the circle and again make a
left click to fix its size.
37. After creating the symbol, save the symbol using the “Check & Save” option.

TESTBENCH CIRCUIT FOR SIMULATION:

38. Instead of using transistor level design, test bench circuit can be created using its symbolic
representation. To create a test bench circuit, a new Cell view with a different Cell Name
should be created.
39. To include the created symbol, use the “Add Instance” option and select the respective library
and cell using the browse option and then the symbol should appear in schematic editor with
the mouse pointer.
40. Create an output pin. To include supply voltage and input signal sources, “Add Instance”
option shall be used. Browse to the “analogLib” library, select the Cell as “vdc”, View as
“symbol” and click on “Tab” key in the keyboard to get the device properties.
41. Mention the appropriate “DC voltage” based on the specification or technology node.
Similarly, for an input source, (for example) “vpulse” is considered and parameters like
Voltage 1, Voltage 2, Period, Delay time, Rise time, Fall time and Pulse width are mentioned.
42. Similarly, “gnd” terminal shall be included to the circuit and the complete circuit.

FUNCTIONAL SIMULATION:

43. To simulate the design, Launch “ADE L”.


44. We get a window and following options are to be verified:
(1) Simulator – to make sure that Spectre is the simulator selected
(2) Model Libraries & Process Corners – to make sure that “.scs” file of the respective technology
node has been selected.
45. To analyze the circuit, select “Analyses” from the top menu in ADE L and under Analyses,
select “Choose”. The analyses chosen and the arguments that had been set up can be seen
under “Analyses” tab in the ADE L window. Similarly, rest of the analyses can be performed
based on designer’s demands.
46. To setup the simulation, select “Outputs” from the ADE L window and select “Setup” under
Outputs option. We get a “Setting Outputs” window as, select “From Design” which would
bring back the test bench circuit created for the simulation process. Select the input wire and
output wire and in ADE L, they are supposed to be displayed under “Outputs” option.
47. To run the simulation, select “Simulation” from ADE L and select the option “Netlist and
Run”. The design is simulated and waveforms are seen.
48. Input signals and Output signals can be seen separately by selecting “Graph -> Split All
Strips”.
49. To save the simulation state, select “Session” under ADE L, select “Save State”, we get a
“Saving State” window. Select “Cell view” and select “OK” to save the state.
50. The simulation state and test bench circuit are viewed.

77
Waveforms:

78
LAYOUT:

51. Open the schematic through the Library Manager and select “Launch -> Layout XL”.
52. A “Startup Option” window pops up. Select “Create New” under Layout tab, “Automatic”
under Configuration tab and select OK. A “New File” window pops up. No changes are to be
made, so select OK. Virtuoso Layout Suite XL Editing window can be seen.
53. To import the circuit components, select “Connectivity -> Generate -> All From Source”.
54. Select OK in the “Generate Layout” window, and the components of the circuit can be seen.
55. Select “Shift + F” to have a view of all the terminals of the transistors.
56. The blue colored box surrounding the circuit components is the PR (Placement & Routing)
Boundary. PR-Boundary can be shifted using the shortcut “S”. To shift the PR-Boundary,
place the mouse pointer close to the respective boundary so that it gets highlighted, make a
left mouse click to select the boundary, use the mouse or arrow (up, down, left or right) keys
to shift the boundary.
57. To attach “Bulk” terminal to the transistors, select the particular transistor by a left mouse
click
58. Make a right mouse click and select “Properties”, select “Parameter -> Body tie Type ->
Integrated (or) Detached -> Left Tap (or) Right Tap” and select OK. Bulk terminal of that
transistor can be seen. Repeat the above steps for rest of the transistors to include the Bulk
terminal.
59. By default, the background available in the Virtuoso Layout Editor is the P-Substrate. So, the
PMOS transistors should be placed within an N-Well. This is mandatory for PMOS transistors
in gpdk090 and gpdk045, but for PMOS transistors in gpdk180, it has an N-Well by default.
To create an N-Well, select the respective layer from the “Layers” tab on the left-hand side of
the Virtuoso Layout Editor.
60. Select “R” to create N-Well in the shape of a rectangle surrounding the PMOS transistor.
61. The PMOS transistor is placed within the N-Well and to complete routing between the
components, we can use “P” which denotes “Path” in the layout and is meant for routing
process.
62. When the mouse pointer is taken closer to any of the terminals of the components, the
terminal gets highlighted with a yellow color bold line, make a left click to start the path
segment from one terminal to another.
63. For routing between two different layers, usage of “Via” is mandatory. There are two options
to place a via. Start routing from the layer of interest, make a right-click, select “Via Down
To..” and select the layer of interest (or) select “Create” from the top menu, select “Via”,
select the respective via under “Via Definition”, make a left mouse click to place the via.
64. For the example used here, “VDD” is at the top and “VSS” is at the bottom. Source & Bulk of
PMOS/NMOS can be routed to VDD/VSS respectively as earlier between other pins and
terminals (or) the entire top layer can be used for VDD and bottom layer for VSS using “Pin
Placement” option.

79
80
63.Select “Place -> Pin Placement”, a window pops up. Under “Pin Planner” tab, “Pin Name,
Attributes & Create” options can be seen. Select “VDD” under “Pin Name”, select “Top”
under “Attributes -> Edge”, select “HRail” under “Create” and select “Apply” under
“Attributes” to place VDD at the top layer. Similarly, select “VSS” under “Pin Name”, select
“Bottom” under “Attributes -> Edge”, select “HRail” under “Create” and select “Apply”
under “Attributes” to place VSS at the bottom layer. After routing the terminals of
PMOS/NMOS terminals with VDD/VSS respectively, save the layout.
Result:

81
SCHEMATIC DIAGRAM

82
RING OSCILLATOR
AIM: Develop the schematic diagram and layout for a Ring Oscillator. Perform experiment to verify
its functional response with appropriate EDA tool. Also make a comment on area requirement to
develop it as an IC.

APPARATUS:
Cadence schematic editor
 Simulation: Spectre simulator.
 Technology: gpdk045

PROCEDURE:

1. Work space creation: Make a right click on the Desktop and select the option “Create Folder”.
2. Name the folder, for example, we have named it as “inverter”.
3. Open the created folder and you get the window.

INITIALISING csh & SOURCING cshrc.

4. Make a right click and select the option “Open in Terminal”


5. Type the command “csh” to initialize shell and source the cshrc file with the command
“source/home/install/cshrc”.

INVOKING VIRTUOSO:

6. Soon after we source the “cshrc” file, we get a display “Welcome to Cadence Tools Suite”.
Now invoke virtuoso using the command “virtuoso &” or “virtuoso”.
7. We get a virtuoso window.

CREATE A LIBRARY:

8. In virtuoso’s top menu, select “Tools” and select “Library Manager”. The Cadence Library
Manager appears.
9. From the top menu of the Library Manager, select “File -> New -> Library” to create a new
library for a new design.
10. We’ll get a “New Library” form where we can name the library that we create.
11. Select “OK” after the library is named.
12. Select “Technology File..” tab that keeps blinking at the bottom of the screen to map the
created library to a technology node based on the specification.
13. We get a form “Technology File for New Library”. Select the option “Attach to an existing
technology library”.
14. Select the respective Technology Node from the list of libraries. For example, we have
selected “gpdk045”.
15. The created library is now available in the Library Manager under Library.

CREATE A CELL:

16. Before creating a cell, make sure that the created library is selected. Only then the created cell
can be viewed under the respective library.
17. To create a Cell View, select File -> New -> Cell View.
18. Now we get a “New File” and we can name the Cell and check the Library, View and Type of
the respective Cell that is to be created.
83
84
19. We get the Virtuoso Schematic Editor.

ADD AN INSTANCE:

20. To add an instance to the circuit, select “Create -> Instance”. We can also use the bin key ‘I’
or the icon
21. We get the “Add Instance” form.
22. Select “Browse” option we get the “Library Manager” to choose the transistors required for
the circuit and the type of view for the respective component from the respective Technology
Library.
23. After selecting the component, we get its properties like Length, Width, Multipliers, etc.,
Select “Hide” at the end of the form, we can have a view of the transistor in the Schematic
Editor.

ADD PIN:

24. To include pins to the circuit, select “Create -> Pin”. We can also use the bin key ‘P’ or the
icon.
25. We name the pins and select its direction.
26. Place the pins by a left click on the mouse and the circuit can be viewed.

ADD WIRE:

27. Connect the pins and the components with the help of wire. Select “Create -> Wire”. We can
also use the bin key ‘W’ or the icon.
28. Once wiring is completed, the circuit can be viewed.

SAVE THE DESIGN:

29. After completing the design, it is mandatory to save the design before we move ahead to
Simulation. We have two options, “Save” and “Check and Save”.
30. Save option saves your design as it is but Check and Save option checks for any
discontinuities like floating net or terminal, provides the details of errors or warnings in the
circuit and then saves the design. The results can be seen in the virtuoso tab.

85
86
FUNCTIONAL SIMULATION:

31. To simulate the design, Launch “ADE L”.


32. We get a window and following options are to be verified:
(1) Simulator – to make sure that Spectre is the simulator selected
(2) Model Libraries & Process Corners – to make sure that “.scs” file of the respective technology
node has been selected.
33. To analyze the circuit, select “Analyses” from the top menu in ADE L and under Analyses,
select “Choose”. The analyses chosen and the arguments that had been set up can be seen
under “Analyses” tab in the ADE L window. Similarly, rest of the analyses can be performed
based on designer’s demands.
34. To setup the simulation, select “Outputs” from the ADE L window and select “Setup” under
Outputs option. We get a “Setting Outputs” window as, select “From Design” which would
bring back the test bench circuit created for the simulation process. Select the input wire and
output wire and in ADE L, they are supposed to be displayed under “Outputs” option.
35. To run the simulation, select “Simulation” from ADE L and select the option “Netlist and
Run”. The design is simulated and waveforms are seen.
36. Input signals and Output signals can be seen separately by selecting “Graph -> Split All
Strips”.
37. To save the simulation state, select “Session” under ADE L, select “Save State”, we get a
“Saving State” window. Select “Cell view” and select “OK” to save the state.
38. The simulation state and test bench circuit are viewed.

87
Waveforms:

88
LAYOUT:

39. Open the schematic through the Library Manager and select “Launch -> Layout XL”.
40. A “Startup Option” window pops up. Select “Create New” under Layout tab, “Automatic”
under Configuration tab and select OK. A “New File” window pops up. No changes are to be
made, so select OK. Virtuoso Layout Suite XL Editing window can be seen.
41. To import the circuit components, select “Connectivity -> Generate -> All From Source”.
42. Select OK in the “Generate Layout” window, and the components of the circuit can be seen.
43. Select “Shift + F” to have a view of all the terminals of the transistors.
44. The blue colored box surrounding the circuit components is the PR (Placement & Routing)
Boundary. PR-Boundary can be shifted using the shortcut “S”. To shift the PR-Boundary,
place the mouse pointer close to the respective boundary so that it gets highlighted, make a
left mouse click to select the boundary, use the mouse or arrow (up, down, left or right) keys
to shift the boundary.
45. To attach “Bulk” terminal to the transistors, select the particular transistor by a left mouse
click
46. Make a right mouse click and select “Properties”, select “Parameter -> Body tie Type ->
Integrated (or) Detached -> Left Tap (or) Right Tap” and select OK. Bulk terminal of that
transistor can be seen. Repeat the above steps for rest of the transistors to include the Bulk
terminal.
47. By default, the background available in the Virtuoso Layout Editor is the P-Substrate. So, the
PMOS transistors should be placed within an N-Well. This is mandatory for PMOS transistors
in gpdk090 and gpdk045, but for PMOS transistors in gpdk180, it has an N-Well by default.
To create an N-Well, select the respective layer from the “Layers” tab on the left-hand side of
the Virtuoso Layout Editor.
48. Select “R” to create N-Well in the shape of a rectangle surrounding the PMOS transistor.
49. The PMOS transistor is placed within the N-Well and to complete routing between the
components, we can use “P” which denotes “Path” in the layout and is meant for routing
process.
50. When the mouse pointer is taken closer to any of the terminals of the components, the
terminal gets highlighted with a yellow color bold line, make a left click to start the path
segment from one terminal to another.
51. For routing between two different layers, usage of “Via” is mandatory. There are two options
to place a via. Start routing from the layer of interest, make a right-click, select “Via Down
To..” and select the layer of interest (or) select “Create” from the top menu, select “Via”,
select the respective via under “Via Definition”, make a left mouse click to place the via.
52. For the example used here, “VDD” is at the top and “VSS” is at the bottom. Source & Bulk of
PMOS/NMOS can be routed to VDD/VSS respectively as earlier between other pins and
terminals (or) the entire top layer can be used for VDD and bottom layer for VSS using “Pin
Placement” option.

89
LAYOUT DIAGRAM:

90
53. Select “Place -> Pin Placement”, a window pops up. Under “Pin Planner” tab, “Pin Name,
Attributes & Create” options can be seen. Select “VDD” under “Pin Name”, select “Top”
under “Attributes -> Edge”, select “HRail” under “Create” and select “Apply” under
“Attributes” to place VDD at the top layer. Similarly, select “VSS” under “Pin Name”, select
“Bottom” under “Attributes -> Edge”, select “HRail” under “Create” and select “Apply”
under “Attributes” to place VSS at the bottom layer. After routing the terminals of
PMOS/NMOS terminals with VDD/VSS respectively, save the layout.
Result:

91
SCHEMATIC DIAGRAM

92
RS LATCH
AIM: Develop the schematic diagram and layout for an RS LATCH. Perform experiment to verify its
functional response with appropriate EDA tool. Also make a comment on area requirement to develop
it as an IC.

APPARATUS:
Cadence schematic editor
 Simulation: Spectre simulator.
 Technology: gpdk045

PROCEDURE:

1. Work space creation: Make a right click on the Desktop and select the option “Create Folder”.
2. Name the folder, for example, we have named it as “inverter”.
3. Open the created folder and you get the window.

INITIALISING csh & SOURCING cshrc.

4. Make a right click and select the option “Open in Terminal”


5. Type the command “csh” to initialize shell and source the cshrc file with the command
“source/home/install/cshrc”.

INVOKING VIRTUOSO:

6. Soon after we source the “cshrc” file, we get a display “Welcome to Cadence Tools Suite”.
Now invoke virtuoso using the command “virtuoso &” or “virtuoso”.
7. We get a virtuoso window.

CREATE A LIBRARY:

8. In virtuoso’s top menu, select “Tools” and select “Library Manager”. The Cadence Library
Manager appears.
9. From the top menu of the Library Manager, select “File -> New -> Library” to create a new
library for a new design.
10. We’ll get a “New Library” form where we can name the library that we create.
11. Select “OK” after the library is named.
12. Select “Technology File..” tab that keeps blinking at the bottom of the screen to map the
created library to a technology node based on the specification.
13. We get a form “Technology File for New Library”. Select the option “Attach to an existing
technology library”.
14. Select the respective Technology Node from the list of libraries. For example, we have
selected “gpdk045”.
15. The created library is now available in the Library Manager under Library.

CREATE A CELL:

16. Before creating a cell, make sure that the created library is selected. Only then the created cell
can be viewed under the respective library.
17. To create a Cell View, select File -> New -> Cell View.
18. Now we get a “New File” and we can name the Cell and check the Library, View and Type of
the respective Cell that is to be created.
93
Symbol:

Test bench:

94
19. We get the Virtuoso Schematic Editor.

ADD AN INSTANCE:

20. To add an instance to the circuit, select “Create -> Instance”. We can also use the bin key ‘I’
or the icon
21. We get the “Add Instance” form.
22. Select “Browse” option we get the “Library Manager” to choose the transistors required for
the circuit and the type of view for the respective component from the respective Technology
Library.
23. After selecting the component, we get its properties like Length, Width, Multipliers, etc.,
Select “Hide” at the end of the form, we can have a view of the transistor in the Schematic
Editor.

ADD PIN:

24. To include pins to the circuit, select “Create -> Pin”. We can also use the bin key ‘P’ or the
icon.
25. We name the pins and select its direction.
26. Place the pins by a left click on the mouse and the circuit can be viewed.

ADD WIRE:

27. Connect the pins and the components with the help of wire. Select “Create -> Wire”. We can
also use the bin key ‘W’ or the icon.
28. Once wiring is completed, the circuit can be viewed.

SAVE THE DESIGN:

29. After completing the design, it is mandatory to save the design before we move ahead to
Simulation. We have two options, “Save” and “Check and Save”.
30. Save option saves your design as it is but Check and Save option checks for any
discontinuities like floating net or terminal, provides the details of errors or warnings in the
circuit and then saves the design. The results can be seen in the virtuoso tab.

SYMBOL CREATION:

31. To create a symbol for the circuit, select “Create -> Cellview -> From Cellview”. Check the
Library Name, Cell Name, From View Name, To View Name, etc., and select OK.
32. We get the “Symbol Generation Options” window. We are free to decide upon the pin
locations with options like Left Pins, Right Pins, Top Pins and Bottom Pins.
33. Select OK. The tool opens a “Virtuoso Symbol Editor” window which shows a temporary
view of the symbol based on the pins assigned.
34. The symbol can be customized with the help of drawing tools.
35. To create custom symbol, remove the inner rectangle (green) and then using drawing tools,
custom symbol can be created. To remove the inner rectangle (green), place the mouse pointer
within the rectangle so that the entire rectangle gets highlighted, make a left click so that the
entire rectangle gets selected and click on delete in the keyboard to remove the rectangle so
that it is removed.

95
Waveforms:

96
36. Since Inverter design is taken as an example in this manual, the focus is on creating its
symbol. To create a triangle, use “Create Line” option among the drawing tools and the way
triangle is created is as similar as how wiring is done in the schematic. To create a bubble, use
“Create Circle” option, decide a point, make a left click to expand the circle and again make a
left click to fix its size.
37. After creating the symbol, save the symbol using the “Check & Save” option.

TESTBENCH CIRCUIT FOR SIMULATION:

38. Instead of using transistor level design, test bench circuit can be created using its symbolic
representation. To create a test bench circuit, a new Cell view with a different Cell Name
should be created.
39. To include the created symbol, use the “Add Instance” option and select the respective library
and cell using the browse option and then the symbol should appear in schematic editor with
the mouse pointer.
40. Create an output pin. To include supply voltage and input signal sources, “Add Instance”
option shall be used. Browse to the “analogLib” library, select the Cell as “vdc”, View as
“symbol” and click on “Tab” key in the keyboard to get the device properties.
41. Mention the appropriate “DC voltage” based on the specification or technology node.
Similarly, for an input source, (for example) “vpulse” is considered and parameters like
Voltage 1, Voltage 2, Period, Delay time, Rise time, Fall time and Pulse width are mentioned.
42. Similarly, “gnd” terminal shall be included to the circuit and the complete circuit.

FUNCTIONAL SIMULATION:

43. To simulate the design, Launch “ADE L”.


44. We get a window and following options are to be verified:
(1) Simulator – to make sure that Spectre is the simulator selected
(2) Model Libraries & Process Corners – to make sure that “.scs” file of the respective technology
node has been selected.
45. To analyze the circuit, select “Analyses” from the top menu in ADE L and under Analyses,
select “Choose”. The analyses chosen and the arguments that had been set up can be seen
under “Analyses” tab in the ADE L window. Similarly, rest of the analyses can be performed
based on designer’s demands.
46. To setup the simulation, select “Outputs” from the ADE L window and select “Setup” under
Outputs option. We get a “Setting Outputs” window as, select “From Design” which would
bring back the test bench circuit created for the simulation process. Select the input wire and
output wire and in ADE L, they are supposed to be displayed under “Outputs” option.
47. To run the simulation, select “Simulation” from ADE L and select the option “Netlist and
Run”. The design is simulated and waveforms are seen.
48. Input signals and Output signals can be seen separately by selecting “Graph -> Split All
Strips”.
49. To save the simulation state, select “Session” under ADE L, select “Save State”, we get a
“Saving State” window. Select “Cell view” and select “OK” to save the state.
50. The simulation state and test bench circuit are viewed.

97
LAYOUT DIAGRAM

98
LAYOUT:

51. Open the schematic through the Library Manager and select “Launch -> Layout XL”.
52. A “Startup Option” window pops up. Select “Create New” under Layout tab, “Automatic”
under Configuration tab and select OK. A “New File” window pops up. No changes are to be
made, so select OK. Virtuoso Layout Suite XL Editing window can be seen.
53. To import the circuit components, select “Connectivity -> Generate -> All From Source”.
54. Select OK in the “Generate Layout” window, and the components of the circuit can be seen.
55. Select “Shift + F” to have a view of all the terminals of the transistors.
56. The blue colored box surrounding the circuit components is the PR (Placement & Routing)
Boundary. PR-Boundary can be shifted using the shortcut “S”. To shift the PR-Boundary,
place the mouse pointer close to the respective boundary so that it gets highlighted, make a
left mouse click to select the boundary, use the mouse or arrow (up, down, left or right) keys
to shift the boundary.
57. To attach “Bulk” terminal to the transistors, select the particular transistor by a left mouse
click
58. Make a right mouse click and select “Properties”, select “Parameter -> Body tie Type ->
Integrated (or) Detached -> Left Tap (or) Right Tap” and select OK. Bulk terminal of that
transistor can be seen. Repeat the above steps for rest of the transistors to include the Bulk
terminal.
59. By default, the background available in the Virtuoso Layout Editor is the P-Substrate. So, the
PMOS transistors should be placed within an N-Well. This is mandatory for PMOS transistors
in gpdk090 and gpdk045, but for PMOS transistors in gpdk180, it has an N-Well by default.
To create an N-Well, select the respective layer from the “Layers” tab on the left-hand side of
the Virtuoso Layout Editor.
60. Select “R” to create N-Well in the shape of a rectangle surrounding the PMOS transistor.
61. The PMOS transistor is placed within the N-Well and to complete routing between the
components, we can use “P” which denotes “Path” in the layout and is meant for routing
process.
62. When the mouse pointer is taken closer to any of the terminals of the components, the
terminal gets highlighted with a yellow color bold line, make a left click to start the path
segment from one terminal to another.
63. For routing between two different layers, usage of “Via” is mandatory. There are two options
to place a via. Start routing from the layer of interest, make a right-click, select “Via Down
To..” and select the layer of interest (or) select “Create” from the top menu, select “Via”,
select the respective via under “Via Definition”, make a left mouse click to place the via.
64. For the example used here, “VDD” is at the top and “VSS” is at the bottom. Source & Bulk of
PMOS/NMOS can be routed to VDD/VSS respectively as earlier between other pins and
terminals (or) the entire top layer can be used for VDD and bottom layer for VSS using “Pin
Placement” option.

99
100
65. Select “Place -> Pin Placement”, a window pops up. Under “Pin Planner” tab, “Pin Name,
Attributes & Create” options can be seen. Select “VDD” under “Pin Name”, select “Top” under
“Attributes -> Edge”, select “HRail” under “Create” and select “Apply” under “Attributes” to
place VDD at the top layer. Similarly, select “VSS” under “Pin Name”, select “Bottom” under
“Attributes -> Edge”, select “HRail” under “Create” and select “Apply” under “Attributes” to
place VSS at the bottom layer. After routing the terminals of PMOS/NMOS terminals with
VDD/VSS respectively, save the layout.
Result:

101
SCHEMATIC DIAGRAM

102
STATIC RAM CELL
AIM: Develop the schematic diagram and layout for a STATIC RAM CELL. Perform experiment to
verify its functional response with appropriate EDA tool. Also make a comment on area requirement
to develop it as an IC.

APPARATUS:
Cadence schematic editor
 Simulation: Spectre simulator.
 Technology: gpdk045

PROCEDURE:

1. Work space creation: Make a right click on the Desktop and select the option “Create Folder”.
2. Name the folder, for example, we have named it as “inverter”.
3. Open the created folder and you get the window.

INITIALISING csh & SOURCING cshrc.

4. Make a right click and select the option “Open in Terminal”


5. Type the command “csh” to initialize shell and source the cshrc file with the command
“source/home/install/cshrc”.

INVOKING VIRTUOSO:

6. Soon after we source the “cshrc” file, we get a display “Welcome to Cadence Tools Suite”.
Now invoke virtuoso using the command “virtuoso &” or “virtuoso”.
7. We get a virtuoso window.

CREATE A LIBRARY:

8. In virtuoso’s top menu, select “Tools” and select “Library Manager”. The Cadence Library
Manager appears.
9. From the top menu of the Library Manager, select “File -> New -> Library” to create a new
library for a new design.
10. We’ll get a “New Library” form where we can name the library that we create.
11. Select “OK” after the library is named.
12. Select “Technology File..” tab that keeps blinking at the bottom of the screen to map the
created library to a technology node based on the specification.
13. We get a form “Technology File for New Library”. Select the option “Attach to an existing
technology library”.
14. Select the respective Technology Node from the list of libraries. For example, we have
selected “gpdk045”.
15. The created library is now available in the Library Manager under Library.

CREATE A CELL:

16. Before creating a cell, make sure that the created library is selected. Only then the created cell
can be viewed under the respective library.
17. To create a Cell View, select File -> New -> Cell View.
18. Now we get a “New File” and we can name the Cell and check the Library, View and Type of
the respective Cell that is to be created.
103
104
19. We get the Virtuoso Schematic Editor.

ADD AN INSTANCE:

20. To add an instance to the circuit, select “Create -> Instance”. We can also use the bin key ‘I’
or the icon
21. We get the “Add Instance” form.
22. Select “Browse” option we get the “Library Manager” to choose the transistors required for
the circuit and the type of view for the respective component from the respective Technology
Library.
23. After selecting the component, we get its properties like Length, Width, Multipliers, etc.,
Select “Hide” at the end of the form, we can have a view of the transistor in the Schematic
Editor.

ADD PIN:

24. To include pins to the circuit, select “Create -> Pin”. We can also use the bin key ‘P’ or the
icon.
25. We name the pins and select its direction.
26. Place the pins by a left click on the mouse and the circuit can be viewed.

ADD WIRE:

27. Connect the pins and the components with the help of wire. Select “Create -> Wire”. We can
also use the bin key ‘W’ or the icon.
28. Once wiring is completed, the circuit can be viewed.

SAVE THE DESIGN:

29. After completing the design, it is mandatory to save the design before we move ahead to
Simulation. We have two options, “Save” and “Check and Save”.
30. Save option saves your design as it is but Check and Save option checks for any
discontinuities like floating net or terminal, provides the details of errors or warnings in the
circuit and then saves the design. The results can be seen in the virtuoso tab.

SYMBOL CREATION:

31. To create a symbol for the circuit, select “Create -> Cellview -> From Cellview”. Check the
Library Name, Cell Name, From View Name, To View Name, etc., and select OK.
32. We get the “Symbol Generation Options” window. We are free to decide upon the pin
locations with options like Left Pins, Right Pins, Top Pins and Bottom Pins.
33. Select OK. The tool opens a “Virtuoso Symbol Editor” window which shows a temporary
view of the symbol based on the pins assigned.
34. The symbol can be customized with the help of drawing tools.
35. To create custom symbol, remove the inner rectangle (green) and then using drawing tools,
custom symbol can be created. To remove the inner rectangle (green), place the mouse pointer
within the rectangle so that the entire rectangle gets highlighted, make a left click so that the
entire rectangle gets selected and click on delete in the keyboard to remove the rectangle so
that it is removed.

105
Waveforms:
Read Operation

Write Operation

106
36. Since Inverter design is taken as an example in this manual, the focus is on creating its
symbol. To create a triangle, use “Create Line” option among the drawing tools and the way
triangle is created is as similar as how wiring is done in the schematic. To create a bubble, use
“Create Circle” option, decide a point, make a left click to expand the circle and again make a
left click to fix its size.
37. After creating the symbol, save the symbol using the “Check & Save” option.

TESTBENCH CIRCUIT FOR SIMULATION:

38. Instead of using transistor level design, test bench circuit can be created using its symbolic
representation. To create a test bench circuit, a new Cell view with a different Cell Name
should be created.
39. To include the created symbol, use the “Add Instance” option and select the respective library
and cell using the browse option and then the symbol should appear in schematic editor with
the mouse pointer.
40. Create an output pin. To include supply voltage and input signal sources, “Add Instance”
option shall be used. Browse to the “analogLib” library, select the Cell as “vdc”, View as
“symbol” and click on “Tab” key in the keyboard to get the device properties.
41. Mention the appropriate “DC voltage” based on the specification or technology node.
Similarly, for an input source, (for example) “vpulse” is considered and parameters like
Voltage 1, Voltage 2, Period, Delay time, Rise time, Fall time and Pulse width are mentioned.
42. Similarly, “gnd” terminal shall be included to the circuit and the complete circuit.

FUNCTIONAL SIMULATION:

43. To simulate the design, Launch “ADE L”.


44. We get a window and following options are to be verified:
(1) Simulator – to make sure that Spectre is the simulator selected
(2) Model Libraries & Process Corners – to make sure that “.scs” file of the respective technology
node has been selected.
45. To analyze the circuit, select “Analyses” from the top menu in ADE L and under Analyses,
select “Choose”. The analyses chosen and the arguments that had been set up can be seen
under “Analyses” tab in the ADE L window. Similarly, rest of the analyses can be performed
based on designer’s demands.
46. To setup the simulation, select “Outputs” from the ADE L window and select “Setup” under
Outputs option. We get a “Setting Outputs” window as, select “From Design” which would
bring back the test bench circuit created for the simulation process. Select the input wire and
output wire and in ADE L, they are supposed to be displayed under “Outputs” option.
47. To run the simulation, select “Simulation” from ADE L and select the option “Netlist and
Run”. The design is simulated and waveforms are seen.
48. Input signals and Output signals can be seen separately by selecting “Graph -> Split All
Strips”.
49. To save the simulation state, select “Session” under ADE L, select “Save State”, we get a
“Saving State” window. Select “Cell view” and select “OK” to save the state.
50. The simulation state and test bench circuit are viewed.

107
108
LAYOUT:

51. Open the schematic through the Library Manager and select “Launch -> Layout XL”.
52. A “Startup Option” window pops up. Select “Create New” under Layout tab, “Automatic”
under Configuration tab and select OK. A “New File” window pops up. No changes are to be
made, so select OK. Virtuoso Layout Suite XL Editing window can be seen.
53. To import the circuit components, select “Connectivity -> Generate -> All From Source”.
54. Select OK in the “Generate Layout” window, and the components of the circuit can be seen.
55. Select “Shift + F” to have a view of all the terminals of the transistors.
56. The blue colored box surrounding the circuit components is the PR (Placement & Routing)
Boundary. PR-Boundary can be shifted using the shortcut “S”. To shift the PR-Boundary,
place the mouse pointer close to the respective boundary so that it gets highlighted, make a
left mouse click to select the boundary, use the mouse or arrow (up, down, left or right) keys
to shift the boundary.
57. To attach “Bulk” terminal to the transistors, select the particular transistor by a left mouse
click
58. Make a right mouse click and select “Properties”, select “Parameter -> Body tie Type ->
Integrated (or) Detached -> Left Tap (or) Right Tap” and select OK. Bulk terminal of that
transistor can be seen. Repeat the above steps for rest of the transistors to include the Bulk
terminal.
59. By default, the background available in the Virtuoso Layout Editor is the P-Substrate. So, the
PMOS transistors should be placed within an N-Well. This is mandatory for PMOS transistors
in gpdk090 and gpdk045, but for PMOS transistors in gpdk180, it has an N-Well by default.
To create an N-Well, select the respective layer from the “Layers” tab on the left-hand side of
the Virtuoso Layout Editor.
60. Select “R” to create N-Well in the shape of a rectangle surrounding the PMOS transistor.
61. The PMOS transistor is placed within the N-Well and to complete routing between the
components, we can use “P” which denotes “Path” in the layout and is meant for routing
process.
62. When the mouse pointer is taken closer to any of the terminals of the components, the
terminal gets highlighted with a yellow color bold line, make a left click to start the path
segment from one terminal to another.
63. For routing between two different layers, usage of “Via” is mandatory. There are two options
to place a via. Start routing from the layer of interest, make a right-click, select “Via Down
To..” and select the layer of interest (or) select “Create” from the top menu, select “Via”,
select the respective via under “Via Definition”, make a left mouse click to place the via.
64. For the example used here, “VDD” is at the top and “VSS” is at the bottom. Source & Bulk of
PMOS/NMOS can be routed to VDD/VSS respectively as earlier between other pins and
terminals (or) the entire top layer can be used for VDD and bottom layer for VSS using “Pin
Placement” option.

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65. Select “Place -> Pin Placement”, a window pops up. Under “Pin Planner” tab, “Pin Name,
Attributes & Create” options can be seen. Select “VDD” under “Pin Name”, select “Top” under
“Attributes -> Edge”, select “HRail” under “Create” and select “Apply” under “Attributes” to
place VDD at the top layer. Similarly, select “VSS” under “Pin Name”, select “Bottom” under
“Attributes -> Edge”, select “HRail” under “Create” and select “Apply” under “Attributes” to
place VSS at the bottom layer. After routing the terminals of PMOS/NMOS terminals with
VDD/VSS respectively, save the layout.
Result:

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Design and implementation of 16X1 mux using 4X1 mux
AIM: To design and implement 16x1 mux using 4x1 mux
Apparatus: Personal computer with vivado 2016.4A version software (Artix-7 low voltage)
Theory:
x1 mux using 4x1 muxes
Implementing 16:1 multiplexer with 4:1 multiplexers: A 16x1 mux can be implemented using 5
4x1 muxes. 4 of these multiplexers can be used as first stage to mux 4 inputs each with two least
significant bits of select lines (S0 and S1), resulting in 4 intermediate outputs, which, then can be
muxed again using a 4:1 mux. The implementation of 16x1 mux using 4x1 muxes is shown below in
figure 1:

Figure 1: Implementing 16:1 mux with the help of 4:1 multiplexers

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PROCEDURE:

 The 16x1 mux Design using 4x1 mux is entered through Verilog HDL.
 The design is simulated by applying test vectors-a,b and observe the output c.
 After simulation obtain the RTL, technology schematics and synthesis report.
 It is required to lock the pins and give timing constraints.
 Implement the design by passing the design by various stages by mapping, time analysis and bit
stream. For locking the pins write UCF file before implementation and guide the same through option
set control files. Output can be directly programmed into target device FPGA.
Verilog Code:

HDL Program File for 4:1 MUX [ MUX4X1.v]


module mux4to1_gate(out,in,sel);
input [0:3] in;
input [0:1] sel;
output out;
wire a,b,c,d,n1,n2,a1,a2,a3,a4;
not n(n1,sel[1]);
not nn(n2,sel[0]);
and (a1,in[0],n1,n2);
and (a2,in[1],n2,sel[1]);
and (a3,in[2],sel[0],n1);
and (a4,in[3],sel[0],sel[1]);
or or1(out,a1,a2,a3,a4);
endmodule
HDL Program File for 16:1 MUX [ MUX16X1.v
module mux16to1(out,in,sel);
input [0:15] in;
input [0:3] sel;
output out;
wire [0:3] ma;
mux4to1_gate mux1(ma[0],in[0:3],sel[2:3]);
mux4to1_gate mux2(ma[1],in[4:7],sel[2:3]);
mux4to1_gate mux3(ma[2],in[8:11],sel[2:3]);
mux4to1_gate mux4(ma[3],in[12:15],sel[2:3]);
mux4to1_gate mux5(out,ma,sel[0:1]);
endmodule
HDL Test Bench File for 16:1 MUX [TESTMUX16.v]
module testmux_16;
reg [0:15] in;
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reg [0:3] sel;
wire out;
mux16to1 mux(out,in,sel);
initial
begin
$monitor("in=%b | sel=%b | out=%b",
in,sel,out);
end
initial
begin
in=16'b1000000000000000; sel=4'b0000;
#30 in=16'b0100000000000000; sel=4'b0001;
#30 in=16'b0010000000000000; sel=4'b0010;
#30 in=16'b0001000000000000; sel=4'b0011;
#30 in=16'b0000100000000000; sel=4'b0100;
#30 in=16'b0000010000000000; sel=4'b0101;
#30 in=16'b0000001000000000; sel=4'b0110;
#30 in=16'b0000000100000000; sel=4'b0111;
#30 in=16'b0000000010000000; sel=4'b1000;
#30 in=16'b0000000001000000; sel=4'b1001;
#30 in=16'b0000000000100000; sel=4'b1010;
#30 in=16'b0000000000010000; sel=4'b1011;
#30 in=16'b0000000000001000; sel=4'b1100;
#30 in=16'b0000000000000100; sel=4'b1101;
#30 in=16'b0000000000000010; sel=4'b1110;
#30 in=16'b0000000000000001; sel=4'b1111;
end
endmodule

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RESULT: Hence the 16x1 mux using 4x1 mux id designed using verilog HDL and its functional
response is verified using Artix-7 low voltage

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