4.4.

Thiết kế các thành phần cơ

bản của bộ xử lý nhúng
(datasheet LPC2103)
+ UART
 UART 16550 Register map
• RBR: Receiver Buffer Register DLAB=0 DLAB=1

• THR: Transmitter Holding Reg. addr. RD WR RD WR

• IER: Interrupt Enable Register 0 RBR THR DLL

• IIR: Interrupt Identification Reg. 1 IER DLM

• FCR: FIFO Control Register
2 IIR FCR IIR FCR
• LCR: Line Control Register
• MCR: Modem Control Register 3 LCR (DLAB is here)

• LSR: Line Status Register 4 MCR

• MSR: Modem Status Register
• DLM:DLL: Divisor Latch 5 LSR - LSR -

• DLAB is only relevant for 6 MSR - MSR -

addresses 0 and 1
7 Scratch
• In the LPC2xxx the register
address are word aligned (multiply
address by 4)
 UART 16550 Registers
• RBR and THR. These registers hold the data received
(RBR) and sent to transmitter (THR)
• Even with FIFOs disabled there are 1-byte buffers in front
of shift registers
• With FIFOs enabled RBR and THR are used as RX_FIFO
read and TX_FIFO write registers, respectively
 UART 16550 Registers
• FCR: FIFO control register (write only)
– Bit 0: FIFO enable: Enables both TX and RX FIFOs when 1
– Bit 1: RX FIFO Reset: Flush RX FIFO when written as 1 (bit not
stored)
– Bit 2: TX FIFO Reset: Flush TX FIFO when written as 1 (bit not
stored)
– Bits 3 to 5: Reserved
– Bits [7:6]: RX interrupt trigger level: FCR[7:6] Trigger level
00 1 byte
01 4 bytes
10 8 bytes
11 14 bytes
 UART 16550 Registers
LCR[1:0] Char. Len.
00 5 bits

• LCR: Line Control Register 01 6 bits

– Bits [1:0]: Character Length 10 7 bits

– Bit 2: Number of Stop bits: 11 8 bits

• 0: 1 stop bit, 1: 2 stop bits (1.5 bits for 5-bit characters)
– Bit 3: Parity enable: 0: no parity, 1: parity added
– Bit 4: Even parity: 0: Odd parity 1: Even parity
– Bit 5: Stick parity: 0: normal parity 1: replace parity bit
with (~LCR[4])
– Bit 6: Break control: 0: no break 1: TXD is forced low
(Break state)
– Bit 7: DLAB: Select which register to access for address 0 and 1.
DLAB=1 allows the access to the divisor latch of the Baud rate
generator
 UART 16550 Registers
• LSR: Line Status Register (read only):
– Bit 0: Data Ready:
1: there is data ready for read from RBR, 0: no data
– Bit 1: Overrun Error:
1: The RX FIFO was full and data was lost, 0: no error
– Bit 2: Parity Error:
1: Wrong parity in the received character, 0: no error
– Bit 3: Framing Error:
1: The Stop bit(s) was 0 (wrong data rate?), 0: no error
– Bit 4: Break interrupt:
1: The RXD line was low for more time than the duration of the
character, 0: no break
 UART 16550 Registers
• LSR: Line Status Register (read only):
– Bit 5: THR Empty:
1: THR is empty or TX FIFO is not full. This means: Transmitter can
accept new data
0: THR or TX FIFO are full
– Bit 6: TX Empty:
1: Both the TX FIFO and the shift register are empty
0: At least there is a character in the shift register being transmitted
– Bit 7: Error in RX FIFO:
1: There are errors in the data stored in the RX FIFO
0: Data without errors
 UART 16550 Registers
• Baud Rate Divider (accessed when DLAB=1)
– DLM: Most significant byte of the 16-bit divider
– DLL: Least significant byte of the 16-bit divider
• Baud Rate Calculation:

 0 < MULVAL <= 15

 0 <= DIVADDVAL <= 15
f_baud = f_pclk/(16*U0DLL)
• A divider value of zero has the same effect as divider=1
 UART 16550 Registers
• IER: Interrupt Enable Register
– Bit 0: RX Data Available interrupt enabled when 1
(RX FIFO trigger level reached or RX timeout, if FIFO
enabled)
– Bit 1: Transmitter Holding Register Empty interrupt
enabled when 1
(TX FIFO empty if FIFO enabled)
– Bit 2: Receiver Line Status interrupt enabled when 1
(When an OE, PE, FE error or a Break state are detected)
– Bit 3: Modem Status Change interrupt enabled when 1
(When CTS, DRS, DCD or RI change value with respect to
last MSR read)
– Bits 4-7: Reserved
 UART 16550 Registers
• IIR: Interrupt Identification Register (read only)
– Bit 0: Pending INT:
• 0: Pending interrupt,
• 1: no interrupt
– Bits [2:1]: Interrupt cause
IIR[2:1] Priority Cause ClearingAction
00 Lowest Modem Status MSR read
01 Second THREmpty THRwrite
10 Third RXData Available RBRread
11 Highest RXLine Status LSR read
 UART 16550 Registers
• IIR: Interrupt Identification Register (read only)
– Bit 3: RX timeout:
• Set along RX Data Available when some
characters have been stored in the RX
• FIFO without reaching the programmed trigger
level for more than 4 character times
– Bits 4,5: Always 0
– Bits 6,7: 00 if FIFOs are disabled, 11 if FIFOs are
enabled
 UART 16550 Registers
• MCR: Modem Control Register
– Bit 0: /DTR: Data Terminal Ready 0: DTR High, 1: DTR Low
– Bit 1: /RTS: Request to Send 0: RTS High, 1: RTS Low
– Bit 2: /OUT1 (GPIO) 0: OUT1 High, 1: OUT1 Low
(OUT1 is used in PCs to further enable the UART interrupt through
a tristate gate outside the UART)
– Bit 3: /OUT2 (GPIO, not used) 0: OUT2 High, 1: OUT2 Low
– Bit 4: Loop mode: 0: Normal mode 1: Loop mode
• In loop mode the TXD and RXD signals are connected
together inside the UART. Any character transmitted is sent
to the receiver. Also, DTR,RTS,OUT1 and OUT2 are tied to
DSR,CTS,RI and DCD, respectively.
– Bits 5 to 7: Reserved
 UART 16550 Registers
• MSR: Modem Status Register (read only)
– Bit 0: Delta CTS 1: CTS changed 0: no change
– Bit 1: Delta DSR 1: DSR changed 0: no change
– Bit 2: Delta RI 1: RI changed 0: no change
– Bit 3: Delta DCD 1: DCD changed 0: no change
– Bit 4: /CTS, Clear to Send, 1: CTS Low 0: CTS High
– Bit 5: /DSR, Clear to Send, 1: DSR Low 0: DSR High
– Bit 6: /RI, Clear to Send, 1: RI Low 0: RI High
– Bit 7: /DCD, Clear to Send, 1: DCD Low 0: DCD High
• Delta bits are set when the corresponding input pin
changes its level with respect to that of the last MSR
read.
• Any delta bit set can trigger a Modem Status interrupt
 UART procedure
• Calculate baud rate
• Configure Tx, Rx pins
• Configure uart format: LCR, note that DLAB must be 1
• Configure baud rate: DLL, DLM, MULVAL, DIVADDVAL
• Return DLAB to 0
• FIFO enable
• Polling for receive data
• Send data if needed
 Examples
• Use UART1 to receive char. If a lowercase
char, an UPPERCASE char is replied.
Note that baud rate is 9600.
f_baud = f_pclk/(16*U1DLL)
9600 = 15000000/(16*U1DLL)
U1DLL = 97.66 -> 98
Which U1DLM = 0; DivAddVal=0;
 Real baud rate is 9566