Datasheet: HC32F448 Series

HC32F448 Series
32-bit ARM® Cortex®-M4 Microcontroller
Datasheet
Rev1.0 June 2023
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Features
ARM Cortex-M4 32bit MCU+FPU, 250DMIPS, 256KB Flash, 68KB SRAM, 2MCANs (FD/2.0B), EXMC,
15Timers, 3ADCs, 2DACs, 4CMPs, 6UARTs, 3SPIs, 2I2Cs, QSPI, AES, HASH (SHA256)
◾ ARMv7-M architecture 32bit Cortex-M4 CPU, ◾ Timer

integrated FPU, MPU, DSP supporting SIMD ‒ 2 multifunctional 16bit PWM Timers (Timer6)
instructions, full instruction tracking unit ETM, ‒ 3 16-bit motor PWM Timers (Timer4)
and CoreSight standard debugging unit. The ‒ 1 32bit general-purpose Timers (TimerA)
highest operating frequency is 200MHz, ‒ 4 16bit general-purpose Timers (TimerA)
reaching the computing performance of ‒ Two 16bit basic timers (Timer0)
250DMIPS or 680Coremarks ‒ Real time clock Timer (RTC)
◾ Built-in memory ‒ 2 WDTs, supporting internal dedicated clocks
‒ Flash memory up to 256KB ◾ Up to 67 GPIOs
‒ Maximum 68KB single-cycle access to high-speed ‒ Up to 62 5V-tolerant IOs
SRAM ◾ Maximum 32 communication interfaces
◾ Power, Clock, Reset Management ‒ 6 USART, support ISO7816-3 protocol
‒ System power supply (Vcc): 1.8-3.6V ‒ 3 SPIs
‒ 7 independent clock sources: external main clock ‒ 2 I2C, support SMBus protocol
crystal oscillator (4-25MHz), external secondary ‒ 1 QSPI, support 100Mbps high-speed access (XIP)
crystal oscillator (32.768kHz), internal high-speed ‒ 2 MCANs, supporting CAN2.0B and CAN FD
RC (16/ 20MHz), internal medium-speed RC ◾ External Memory Controller EXMC
(8MHz), internal low-speed RC (32kHz), PLL, ‒ Support for static memory controllers
Internal WDT dedicated RC (10kHz) ◾ Data encryption function
‒ 15 kinds of reset sources including power-on reset ‒ AES/ HASH (SHA256)/ TRNG
(POR), low voltage detection reset (PVD1R/ ◾ Encapsulation form:
PVD2R), port reset (NRST), each reset source has ‒ LQFP80 (12×12mm)
an independent flag bit ‒ LQFP64 (10×10mm)
◾ Low power operation ‒ LQFP48 (7×7mm)
‒ Peripherals can be turned off or on independently ‒ QFN48 (5×5mm)
‒ Three low power consumption modes: Sleep, Stop, ‒ QFN32 (4×4mm)
Power Down mode
◾ Peripheral operation support system
significantly reduces CPU processing load
‒ 12-channel dual-host DMAC
‒ 4 Data Computing Units (DCUs)
‒ Support mutual triggering of peripheral events Support Model
HC32F448FAUI-QFN32TR HC32F448FCUI-QFN32TR
(AOS)
◾ High Performance Simulation HC32F448JAUI-ZFN48TR HC32F448JCUI-ZFN48TR
‒ 3 independent 12bit 2.5MSPS ADCs HC32F448JATI-LQ48 HC32F448JCTI-LQ48

‒ 2 independent 12bit DACs HC32F448KATI-LQFP64 HC32F448KCTI-LQFP64
‒ 4 independent voltage comparators (CMP) HC32F448MATI-LQFP80 HC32F448MCTI-LQFP80
HC32F448SeriesDatasheet_Rev1.0 2/103
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Statement
★ Xiaohua Semiconductor Co., Ltd. (hereinafter referred to as "XHSC") reserves the right to change,
correct, enhance, modify Xiaohua Semiconductor products and / or this document at any time
without prior notice. Users can get the latest information before placing orders. XHSC products are
sold in accordance with the terms and conditions of sale set forth in the Basic Contract for Purchase
and Sales.
★ It is the customer's responsibility to select the appropriate XHSC product for your application and
to design, validate and test your application to ensure that your application meets the appropriate
standards and any safety, security or other requirements. The customer shall be solely responsible
for this.
★ XHSC hereby acknowledges that no intellectual property license has been granted by express or
implied means.
★ The resale of XHSC Products shall be invalidated by any warranty commitment of XHSC to such
Products if its terms are different from those set forth herein.
★ Any graphics or words marked “®” or “™” are trademarks of XHSC. All other products or services
shown on XHSC products are the property of their respective owners.
★ Information in this notification replaces and replaces information in previous versions.
©2023 Xiaohua Semiconductor Co., Ltd. All rights reserved
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Table of Contents
Features........................................................................................................................ 2
Statement ..................................................................................................................... 3
Table of Contents ........................................................................................................... 4
Table Index .................................................................................................................... 7
Figure Index .................................................................................................................. 9
1 Overview ............................................................................................................... 10
1.1 Part Naming Rules ............................................................................................................... 11
1.2 Model Function Comparison Table ....................................................................................... 12
1.3 Functional Block Diagram .................................................................................................... 14
1.4 Feature Brief ........................................................................................................................ 15
1.4.1 CPU .......................................................................................................................... 15
1.4.2 Bus Architecture (BUS) ............................................................................................ 15
1.4.3 Reset Control (RMU)................................................................................................. 16
1.4.4 Clock Control (CMU) ................................................................................................. 16
1.4.5 Power Control (PWC) ................................................................................................ 17
1.4.6 Initialization Configuration (ICG) .............................................................................. 17
1.4.7 Embedded Flash Interface (EFM) ............................................................................. 18
1.4.8 Built-in SRAM (SRAM) ............................................................................................... 18
1.4.9 General IO (GPIO) .................................................................................................... 18
1.4.10 Interrupt Control (INTC)............................................................................................ 19
1.4.11 Automatic Operating System (AOS) ......................................................................... 19
1.4.12 Memory Protection Unit (MPU) ................................................................................. 20
1.4.13 Keyboard Scanning (KEYSCAN) ................................................................................ 20
1.4.14 Internal Clock Calibrator (CTC)................................................................................. 20
1.4.15 DMA Controller (DMA) .............................................................................................. 20
1.4.16 Voltage Comparator (CMP)....................................................................................... 21
1.4.17 Analog-to-Digital Converter (ADC) ........................................................................... 22
1.4.18 Digital to Analog Converter (DAC) ........................................................................... 23
1.4.19 Advanced Control Timer (Timer6) ............................................................................ 23
1.4.20 General Control Timer (Timer4) ............................................................................... 24
1.4.21 Emergency Brake Module (EMB) .............................................................................. 24
1.4.22 General Timer (TimerA) ........................................................................................... 24
1.4.23 General Timer (Timer0)............................................................................................ 24
1.4.24 Real Time Clock (RTC) .............................................................................................. 24
1.4.25 Watchdog Counter (WDT/SWDT) .............................................................................. 25
1.4.26 General Synchronous Asynchronous Transceiver (USART) ....................................... 25
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1.4.27 Integrated Circuit Bus (I2C) ..................................................................................... 26

1.4.28 Serial Peripheral Interface (SPI) ............................................................................... 26
1.4.29 Quad-wire Serial Peripheral Interface (QSPI)............................................................ 28
1.4.30 External Memory Controller (EXMC)......................................................................... 28
1.4.31 Controller Area Network (MCAN) .............................................................................. 28
1.4.32 Cryptographic Coprocessing Module (CPM) ............................................................. 28
1.4.33 Data Computing Unit (CRC) ..................................................................................... 29
1.4.34 CRC Unit (CRC) ......................................................................................................... 29
1.4.35 Debug Controller (DBGC) ......................................................................................... 29
2 Pin Configuration and Functions (Pinouts) ............................................................... 30
2.1 Pin Configuration Diagram .................................................................................................. 30
2.2 Pin Function Table ................................................................................................................ 35
2.3 Pin Function Description ...................................................................................................... 42
2.4 Pin Usage Instructions ......................................................................................................... 45
3 Electrical Characteristics (ECs) ............................................................................... 46
3.1 Parameter Conditions .......................................................................................................... 46
3.1.1 Minimum and Maximum .......................................................................................... 46
3.1.2 Typical Value ............................................................................................................ 46
3.1.3 Typical Curve ........................................................................................................... 46
3.1.4 Load Capacitance .................................................................................................... 46
3.1.5 Pin Input Voltage ...................................................................................................... 46
3.1.6 Power Supply Scheme ............................................................................................. 47
3.1.7 Current Consumption Measurement ........................................................................ 48
3.2 Absolute Maximum Ratings ................................................................................................. 49
3.3 Operating Conditions ........................................................................................................... 50
3.3.1 General Working Conditions .................................................................................... 50
3.3.2 Operating Conditions During Power Up/ Down ......................................................... 50
3.3.3 Reset and Power Control Block Features .................................................................. 51
3.3.4 Supply Current Characteristics ................................................................................ 52
3.3.5 Low Power Mode Wake-Up Timing............................................................................ 60
3.3.6 External Timer Characteristic .................................................................................. 61
3.3.7 Internal Timer Characteristics .................................................................................. 64
3.3.8 PLL Characteristic .................................................................................................... 65
3.3.9 Memory (Flash) Characteristics ............................................................................... 66
3.3.10 Electrical Sensitivity................................................................................................. 67
3.3.11 I/O Port Characteristics ............................................................................................ 68
3.3.12 I2C Interface Characteristics .................................................................................... 71
3.3.13 SPI Interface Characteristics .................................................................................... 72
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3.3.14 QSPI Interface Characteristics ................................................................................. 75

3.3.15 USART Interface Characteristics .............................................................................. 76
3.3.16 JTAG Interface Features ............................................................................................ 77
3.3.17 SWD Interface Characteristics ................................................................................. 79
3.3.18 12-bit ADC Characteristic ........................................................................................ 80
3.3.19 12-bit DAC Characteristic......................................................................................... 84
3.3.20 Comparator Characteristics ..................................................................................... 85
3.3.21 EXMC Characteristic ................................................................................................ 86
3.3.22 EIRQ Filter Characteristics ....................................................................................... 88
3.3.23 RX filter characteristics in USART1 Stop mode ........................................................ 88
4 Package Information .............................................................................................. 89
4.1 Packaging Size ..................................................................................................................... 89
4.2 Schematic Diagram of Pad .................................................................................................. 94
4.3 Silkscreen instructions......................................................................................................... 99
4.4 Packaging Thermal Resistance Coefficient ........................................................................ 100
5 Ordering Information ........................................................................................... 101
Version Revision History ............................................................................................ 103
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Table Index
Table 1-1 Model Function Comparison Table ....................................................................................... 12
Table 2-1 Pin Function Table ................................................................................................................ 35
Table 2-2 Func32~63 table ................................................................................................................. 39
Table 2-3 Port Configuration ............................................................................................................... 40
Table 2-4 Common Functional Specifications ...................................................................................... 41
Table 2-5 Pin Function Description ...................................................................................................... 42
Table 2-6 Pin Usage Description ......................................................................................................... 45
Table 3-1 Voltage Characteristics........................................................................................................ 49
Table 3-2 Current Characteristics ....................................................................................................... 49
Table 3-3 Thermal Characteristics ...................................................................................................... 49
Table 3-4 General Operating Conditions ............................................................................................. 50
Table 3-5 Operating conditions at power-up/power-down ................................................................... 50
Table 3-6 Reset and Power Control Module Characteristics ................................................................ 51
Table 3-7 High Speed Mode Current Consumption 1 .......................................................................... 53
Table 3-8 High Speed Mode Current Consumption2 ........................................................................... 54
Table 3-9 High Speed Mode Current Consumption3 ........................................................................... 55
Table 3-10 Ultra Low Speed Mode Current Consumption1 .................................................................. 56
Table 3-11 Ultra Low Speed Mode Current Consumption2 .................................................................. 57
Table 3-12 Low Power Mode Current Consumption ............................................................................. 58
Table 3-13 Analog Module Current Consumption ................................................................................ 59
Table 3-14 Low power mode wake-up time......................................................................................... 60
Table 3-15 High-Speed External User Clock Characteristics ............................................................... 61
Table 3-16 XTAL 4-25MHz Oscillator Characteristics ........................................................................... 62
Table 3-17 XTAL32 Oscillator Features ................................................................................................ 63
Table 3-18 HRC Oscillator Characteristics ........................................................................................... 64
Table 3-19 MRC Oscillator Characteristics........................................................................................... 64
Table 3-20 LRC Oscillator Characteristics ........................................................................................... 64
Table 3-21 SWDTLRC Oscillator Characteristics .................................................................................. 64
Table 3-22 PLLH Main Performance Indicators .................................................................................... 65
Table 3-23 Flash Features ................................................................................................................... 66
Table 3-24 Flash Program Erase Time ................................................................................................. 66
Table 3-25 Flash Memory Erasability and Data Retention Period ........................................................ 66
Table 3-26 ESD Characteristics ........................................................................................................... 67
Table 3-27 Static Latch-up Features.................................................................................................... 67
Table 3-28 I/O Static Characteristics ................................................................................................... 68
Table 3-29 Output Voltage Characteristics.......................................................................................... 69
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Table 3-30 I/O AC Characteristics........................................................................................................ 70

Table 3-31 I2C Electrical Characteristics ............................................................................................. 71
Table 3-32 SPI Electrical Characteristics ............................................................................................. 72
Table 3-33 QSPI Electrical Characteristics........................................................................................... 75
Table 3-34 USART AC Timing............................................................................................................... 76
Table 3-35 USART Maximum Baud Rates ............................................................................................ 76
Table 3-36 JTAG Interface Features ..................................................................................................... 77
Table 3-37 SWD Interface Features ..................................................................................................... 79
Table 3-38 ADC Characteristics........................................................................................................... 80
Table 3-39 Input Channel Static Accuracy @ fADC=60MHz .................................................................. 81
Table 3-40 Input Channel Static Accuracy @ fADC=8MHz/ 30MHz ....................................................... 81
Table 3-41 Input Channel Dynamic Accuracy @ fADC=60MHz ............................................................. 81
Table 3-42 Input Channel Dynamic Accuracy @ fADC=8MHz/ 30MHz .................................................. 81
Table 3-43 Characteristics when 12bit DAC port output is enabled and the output amplifier is enabled
.............................................................................................................................................................. 84
Table 3-44 Characteristics when 12bit DAC port output is enabled and output amplifier is disabled . 84
Table 3-45 Characteristics when 12bit DAC port output is disabled and output amplifier is disabled 85
Table 3-46 Comparator Characteristics .............................................................................................. 85
Table 3-47 EXMC Characteristics ........................................................................................................ 86
Table 3-48 EIRQ Filter Characteristics ................................................................................................. 88
Table 3-49 RX Filter Characteristics in USART1 STOP Mode ................................................................ 88
Table 4-1 Thermal resistance coefficient table for each package ..................................................... 100
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Figure Index
Figure 1-1 Functional block diagram ................................................................................................... 14
Figure 2-1 Pin Configuration Diagram ................................................................................................. 34
Figure 3-1 Pin loading condition (left) and input voltage measurement (right) .................................. 46
Figure 3-2 Power Scheme ................................................................................................................... 47
Figure 3-3 Current consumption measurement scheme ..................................................................... 48
Figure 3-4 Typical Application Using 8 MHz Crystal ............................................................................ 62
Figure 3-5 Typical application using 32.768kHz crystal oscillator ....................................................... 63
Figure 3-6 Definition of I/O AC Characteristics .................................................................................... 70
Figure 3-7 I2C bus timing definition .................................................................................................... 71
Figure 3-8 SPI timing definition (slave mode, CPHA=0) ...................................................................... 73
Figure 3-9 SPI timing definition (slave mode, CPHA=1) ...................................................................... 73
Figure 3-10 SPI Timing Definition (Host Mode) ................................................................................... 74
Figure 3-11 QSPI Clock Timing ............................................................................................................ 75
Figure 3-12 QSPI Timing Definition ..................................................................................................... 75
Figure 3-13 USART Clock Timing ......................................................................................................... 76
Figure 3-14 USART (CSI) Input and Output Timing .............................................................................. 77
Figure 3-15 JTAG TCK clock ................................................................................................................. 77
Figure 3-16 JTAG Input and Output ..................................................................................................... 78
Figure 3-17 SWD SWCLK Clock ........................................................................................................... 79
Figure 3-18 SWDIO Input and Output ................................................................................................. 79
Figure 3-19 ADC Accuracy Characteristics .......................................................................................... 82
Figure 3-20 Typical Connection Using ADC ......................................................................................... 83
Figure 3-21 Example of Supply and Reference Supply Decoupling ..................................................... 83
Figure 3-22 EXMC Output Signal Timing Diagram............................................................................... 87
Figure 3-23 EXMC Input Signal Timing Diagram ................................................................................. 87
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1 Overview
The HC32F448 series is a high-performance MCU based on ARM® Cortex®-M4 32-bit RISC CPU with
a maximum operating frequency of 200MHz. The Cortex-M4 core integrates a floating-point
arithmetic unit (FPU) and a DSP to implement single-precision floating-point arithmetic operations,
supports all ARM single-precision data processing instructions and data types, and supports the
complete DSP instruction set. The kernel integrates the MPU unit and superimposes the DMAC
dedicated MPU unit at the same time to ensure the safety of system operation.
The HC32F448 series integrates high-speed on-chip memory, including a maximum of 256KB of
Flash and a maximum of 68KB of SRAM. Integrated Flash access acceleration unit to achieve single
cycle program execution of the CPU on Flash. The polled bus matrix supports multiple bus hosts to
access memory and peripherals simultaneously, improving performance. The bus master includes
CPU, DMA. In addition to the bus matrix, it supports data transfer between peripherals, basic
arithmetic operations and mutual triggering of events, which can significantly reduce the
transaction processing load of the CPU.
The HC32F448 series integrates a wealth of peripheral functions, including: 3 independent 12bit
2.5MSPS ADCs; 2 12-bit DACs; 4 high-speed voltage comparators (CMP); 2 multifunctional PWM
Timers (Timer6), supporting 4 1 complementary PWM output; 3 motor PWM Timers (Timer4),
supporting 24 complementary PWM outputs; 4 16bit general-purpose Timers (TimerA) and 1 32bit
general-purpose Timer (TimerA), supporting quadrature encoding input and 40 duty cycles PWM
output can be set; 11 serial communication interfaces (I2C/UART/SPI); 1 QSPI interface; 2 MCAN
controllers; 1 external expansion bus controller, including SMC controller.
The HC32F448 series supports wide voltage range (1.8~3.6V), wide temperature range (-40~105℃)
and various low power consumption modes. Support fast wake-up from low-power mode, the fastest
wake-up from Power Down mode is 25μs.
Typical Application
The HC32F448 series provides 80pin, 64pin, 48pin LQFP packages, 48pin, 32pin QFN packages,
which can be used in high-performance frequency conversion control, intelligent hardware, IoT
connection modules and other fields.
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1.1 Part Naming Rules
HC 32 F 4 4 8 F C U I
Xiaohua Semiconductor
CPU bit width
32: 32bit
Product type
F: Universal
CPU type
4: Cortex-M4
Capability ID
4: mainstream type
Feature Configuration Identifier

8: Configuration 9
Pin number
F: 32Pin
J: 48Pin
K: 64Pin
M: 80Pin
FLASH capacity
A: 128KB
C: 256KB
Package type
U: QFN/ZFN
T: LQFP
Ambient temperature range

I: -40~105℃
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1.2 Model Function Comparison Table

Table 1-1 Model Function Comparison Table
Product Model
Function HC32F448 HC32F448 HC32F448 HC32F448 HC32F448 HC32F448 HC32F448 HC32F448 HC32F448 HC32F448
FAUI FCUI JAUI JCUI JATI JCTI KATI KCTI MATI MCTI
Pin number 32 32 48 48 48 48 64 64 80 80
Number of GPIOs 25 25 38 38 38 38 52 52 67 67
5V Tolerant Number of GPIOs 24 24 36 36 36 36 47 47 62 62
Encapsulation QFN QFN QFN QFN LQFP LQFP LQFP LQFP LQFP LQFP
Temperature range -40~105℃
Supply voltage range 1.8~3.6V
Flash 128KB 256KB 128KB 256KB 128KB 256KB 128KB 256KB 128KB 256KB
Storage OTP 9KB
SRAM 68KB
DMA controller 2unit * 6ch
External port interrupt EIRQ * 13 EIRQ * 16
USART 6ch
SPI 3ch
Communication Interface I2C 2ch
MCAN 2ch
QSPI 1ch
Timer0 2unit
TimerA 5unit
Timers and Counters
Timer4 3unit
Timer6 2unit
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Product Model
Function HC32F448 HC32F448 HC32F448 HC32F448 HC32F448 HC32F448 HC32F448 HC32F448 HC32F448 HC32F448
FAUI FCUI JAUI JCUI JATI JCTI KATI KCTI MATI MCTI
WDT 1ch
SWDT 1ch
RTC 1ch
12bit ADC 3unit, 4ch 3unit, 4ch 3unit, 11ch 3unit, 11ch 3unit, 11ch 3unit, 11ch 3unit, 17ch 3unit, 17ch 3unit, 24ch 3unit, 24ch
Simulation 12bit DAC 1ch 1ch 2ch 2ch 2ch 2ch 2ch 2ch 2ch 2ch
CMP 4ch
Data Computing Unit (CRC) ✓
Encryption and decryption algorithm
✓
processor (AES256)
Secure Hash Algorithm (HASH SHA256) ✓
True random number generator (TRNG) ✓
External Memory Controller (EXMC) not support not support not support not support not support not support ✓ ✓ ✓ ✓
Frequency Monitoring Module (FCM) ✓
Programmable voltage detection function
✓
(PVD)
SWD ✓
Debug controller (DBGC)
JTAG ✓
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1.3 Functional Block Diagram
JTAG/SWD Flash Embedded Flash

IBUS
ARM Cache Up to 256KB
DBUS
Cortex-M4 MPU
SBUS
FPU
SRAMH(32KB)
DMA_1
DMPU
SRAM0(32KB)
DMA_2
Ret SRAM(4KB)
AHB Matrix (200MHz)

AES
(100MHz)
SHA256
AHB4
CRC
INTC HRC
(200MHz)
QSPI KEYSCAN MRC

CMU
(200MHz)
LRC
SMCR SMC
AHB1
AHB5
GPIO XTAL
DCU(4ch)
(200MHz)
XTAL32
KEYSCAN PLL
AHB-APB Bridge
Timer6_1
Timer6_2
Timer4_1
Timer4_2
Timer4_3
APB5 (200MHz)
CMP_1
APB1 (100MHz)
APB4 (50MHz)
APB2 (100MHz)
EFM SPI_3 CMP_2

APB3 (100MHz)
USART_1 MCAN_1 CMP_3

RTC
USART_2 MCAN_2 CMP_4
WKTM
USART_3 Timer0_1 ADC_1 TimerA_1
CTC
SPI_1 Timer0_2 ADC_2 TimerA_2
EMU
SPI_2 TimerA_5 ADC_3 WDT TimerA_3
EMB USART_4 DAC_1(2ch) SWDT TimerA_4
AOS USART_5 TRNG FCM I2C_1
USART_6
I2C_2
Figure 1-1 Functional block diagram
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1.4 Feature Brief
1.4.1 CPU
The HC32F448 series integrates the latest generation of embedded ARM® Cortex®-M4 with FPU
32bit simplified instruction CPU, which realizes fewer pins and lower power consumption while
providing excellent computing performance and rapid interrupt response capability. The memory
capacity integrated on the chip can give full play to the excellent instruction efficiency of Cortex-
M4. The CPU supports DSP instructions, which can realize efficient signal processing operations and
complex algorithms. The single-precision FPU (Floating Point Unit) unit can avoid instruction
saturation and speed up software development.
1.4.2 Bus Architecture (BUS)
The main system is composed of 32-bit multilayer AHB bus matrix, which can interconnect the
following host bus and slave bus.
◾ Host bus
‒ Cortex-M4 core CPU-I bus, CPU-D bus, CPU-S bus
‒ System DMA_1 bus, system DMA_2 bus
◾ Slave bus
‒ Flash ICODE bus
‒ Flash DCODE bus
‒ Flash MCODE bus (the bus that hosts other than the CPU access the Flash)
‒ High-speed SRAMH (SRAMH 32KB) bus
‒ System SRAM (SRAM0 32KB) bus
‒ System SRAM (Ret SRAM 4KB) bus
‒ APB1 Peripheral Bus (EMB/ SPI/ USART/ EFM/ AOS)
‒ APB2 Peripheral Bus (TimerA/ Timer0/ SPI/ USART/ MCAN)
‒ APB3 Peripheral Bus (ADC/ DAC/ TRNG)
‒ APB4 Peripheral Bus (FCM/ WDT/ SWDT/ EMU/ CTC/ RTC/ WKTM)
‒ APB5 Peripheral Bus (TimerA/ Timer4/ Timer6/ CMP/ I2C)
‒ AHB1 Peripheral Bus (DCU/ CMU/ GPIO/ DMA/ INTC/ KEYSCAN/ DMPU)
‒ AHB4 Peripheral Bus (AES/ HASH/ CRC)
‒ AHB5 Peripheral Bus (SMC/ SMCR/ QSPI)
With the help of the bus matrix, high-efficiency concurrent access from the host bus to the slave
bus can be realized.
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1.4.3 Reset Control (RMU)
The chip is configured with 15 reset modes.
◾ Power On Reset (POR)

◾ NRST pin reset (NRST)
◾ Brown-out Reset (BOR)
◾ Programmable Voltage Detect 1 Reset (PVD1R)
◾ Programmable Voltage Detect 2 Reset (PVD2R)
◾ Watchdog Reset (WDTR)
◾ Special watchdog reset (SWDTR)
◾ Power-down wake-up reset (PDRST)
◾ Software Reset (SRST)
◾ MPU error reset (MPUR)
◾ RAM Parity Reset (RAMPR)
◾ RAMECC reset (RAMECCR)
◾ Clock Exception Reset (CKFER)
◾ External high-speed oscillator abnormal shutdown reset (XTALER)
◾ Cortex-M4 Lock-up reset (LKUPR)
1.4.4 Clock Control (CMU)
The clock control unit provides a series of frequency clock functions, including: an external high-
speed oscillator, an external low-speed oscillator, a PLL clock, an internal high-speed oscillator, an
internal medium-speed oscillator, an internal low-speed oscillator, a SWDT dedicated internal low-
speed oscillator, clock prescaler, clock multiplexing and clock gating circuits.
The clock control unit also provides a clock frequency measurement function. The clock frequency
measurement circuit (FCM) uses the measurement reference clock to monitor and measure the
measurement target clock, and interrupts or resets when the clock frequency exceeds the set range.
The AHB, APB and Cortex-M4 clocks are all derived from the system clock. The maximum operating
clock frequency of the system clock can reach 200MHz, and there are 6 optional clock sources:
1) External high-speed oscillator (XTAL)

2) External low-speed oscillator (XTAL32)
3) PLLH clock (PLLH)
4) Internal high-speed oscillator (HRC)
5) Internal Medium Speed Oscillator (MRC)
6) Internal low-speed oscillator (LRC)
For each timer, you can turn it on and off separately when not in use to reduce power consumption.
SWDT has an independent clock source: SWDT dedicated internal low-speed oscillator (SWDTLRC).
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The real-time clock (RTC) uses the external low-speed oscillator, the internal low-speed oscillator or
the XTAL fractional frequency clock as the clock source.
1.4.5 Power Control (PWC)
The power controller is used to control the power supply, switching and detection of multiple power
domains of the chip in multiple operating modes and low power consumption modes. The power
controller is composed of power control logic (PWC) and power voltage detection unit (PVD).
The operating voltage (VCC) of the chip is 1.8V to 3.6V. The voltage regulator (LDO) supplies power
to the VDD domain and the VDDR domain, and the VDDR voltage regulator (RLDO) supplies power
to the VDDR domain in power-down mode. Through the power control logic (PWC), the chip provides
two operating modes of high speed and ultra low speed, and three low power modes of sleep, stop
and power down.
The power voltage detection unit (PVD) provides functions such as power-on reset (POR), power-
down reset (PDR), brown-out reset (BOR), programmable voltage detection 1 (PVD1), and
programmable voltage detection 2 (PVD2). Among them, POR, PDR, and BOR control the reset
action of the chip by detecting the VCC voltage. PVD1 detects the VCC voltage and resets or
interrupts the chip according to the register settings. PVD2 detects VCC voltage or external input
detection voltage, and generates reset or interrupt according to register selection.
When the chip enters the power-down mode, the VDDR area maintains the power supply through
RLDO and keeps the 4KB Ret SRAM data.
The analog blocks are equipped with dedicated supply pins for improved analog performance.
1.4.6 Initialization Configuration (ICG)
After the chip reset is released, the hardware circuit will read the FLASH address 0x0000
0400~0x0000 045F and load the data into the initialization configuration register. Addresses
0x0000 0408~0x0000 040B, 0x0000 0410~0x0000 041F, 0x0000 0438~0x0000 045F are reserved
addresses, please write all 1s to ensure the normal operation of the chip. When the FLASH boot
exchange is invalid, there is a FLASH block 0 sector 0 in this area; when the FLASH boot exchange
is valid, and the OTP of the FLASH block 0 sector 0 is not latched (0x0300 0A80~0x0300 0A83 data
are all 1), there is a FLASH block in this area 0 sector 1; otherwise, there is FLASH block 0 sector 0
in this area. User can modify Initialization Configuration Register (ICG) by programming or erasing
Sector 0. The address 0x0000 0420~0x0000 0437 is the data security protection enable area. The
register reset value is determined by the FLASH address data.
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1.4.7 Embedded Flash Interface (EFM)
The FLASH interface accesses the FLASH through the ICODE, DCODE and MCODE buses, and can
perform programming, erasing and full erasing operations on the FLASH; it accelerates code
execution through the instruction prefetch and cache mechanism.
Main features:
◾ Maximum OTP space of 9KBytes

◾ ICODE bus 16Bytes prefetching
◾ Two independent buffer areas: ICODE bus buffer space 1KBytes; DCODE bus buffer space
128Bytes
◾ Support boot swap function
◾ Support data security protection*1
*1 For specific specifications of Flash security protection, please consult the sales window
1.4.8 Built-in SRAM (SRAM)
This product has 64KB system SRAM (SRAMH/ SRAM0) and 4KB power-down mode retention SRAM
(Ret SRAM).
Each SRAM can be accessed by byte, halfword (16 bits) or full word (32 bits). High-speed SRAM
(SRAMH/ SRAM0) read and write operations can be performed at the fastest speed of the CPU
(200MHz) with 0 waits (ie 1 cycle), or a wait cycle can be inserted. The waiting cycle of each SRAM's
read and write access is set by the SRAM wait control register (SRAM_WTCR).
Ret SRAM can provide 4KB of data retention space in Power Down mode.
SRAM0 and Ret SRAM have ECC check (Error Checking and Correcting), ECC check is a correction
code, that is, it can correct one error and check two errors; SRAMH has a parity check (Even-parity
check) , each byte of data has a parity bit.
1.4.9 General IO (GPIO)
Main Features of GPIO:
◾ Each port group has 16 I/O Pins, which may be less than 16 depending on actual configuration
◾ Support pull-up and pull-down
◾ Support push-pull, open-drain output mode
◾ Supports high, medium and low drive modes
◾ Support CMOS/ Schmitt two input modes to switch freely
◾ Support for external interrupt input
◾ Support I/O pin peripheral function multiplexing, each I/O pin has up to 41 optional multiplexing
functions
◾ Individual I/O pins can be programmed independently
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◾ Each I/O pin can select 2 functions to be valid at the same time (does not support 2 output
functions to be valid at the same time)
1.4.10 Interrupt Control (INTC)
The interrupt controller (INTC) selects an interrupt event as an interrupt request and sends it to
NVIC to wake up WFI; selects an interrupt event as an event input (RXEV) to wake up WFE; selects
an interrupt event to wake up the system from low-power modes (sleep mode and stop mode);
controls external interrupts and software interrupts.
The main specifications of INTC are as follows:
◾ NVIC interrupt request: INTC is equipped with 258 interrupt events, which are sent to NVIC as
interrupt requests (IRQs) after processing, supporting 130 IRQs, and each IRQ corresponds to
one or more interrupt events
For more instructions on exceptions and NVIC programming, please refer to "Arm Cortex-M4
Processor Technical Reference Manual"
◾ Programmable Priority: 16 Programmable Priorities (using 4-bit Interrupt Priority Register)
◾ Non-maskable interrupts: Multiple system interrupt events can be independently selected as
non-maskable interrupts, and each interrupt event is equipped with independent enable
selection, flag, and flag clear registers
◾ Equipped with 16 external pin interrupt events
◾ Equipped with multiple interrupt events, please refer to the interrupt event table in the
interrupt controller chapter of the reference manual for details
◾ Equipped with 32 software interrupt events
◾ Interrupts can wake up the system from sleep mode and stop mode
1.4.11 Automatic Operating System (AOS)
The automatic operation system (Automatic Operation System) is used to realize the linkage
between peripheral hardware circuits without the help of the CPU. Use the events generated by the
peripheral circuit as the AOS source (AOS Source), such as timer comparison matching, timing
overflow, RTC periodic signal, various states of the communication module's sending and receiving
data (idle, receiving data full, sending data end, send data empty), ADC conversion end, etc., to
trigger other peripheral circuit actions. The triggered peripheral circuit action is called AOS target
(AOS Target).
AOS is also equipped with 4 programmable logic operation units (PLU) for logic operation of PORT
and AOS source. Users can select one or more AOS sources to trigger the same AOS target according
to their needs.
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1.4.12 Memory Protection Unit (MPU)
The MPU can provide protection to the memory, and can improve the security of the system by
preventing unauthorized access.
This chip has built-in 1 MPU unit for CPU, 1 MPU unit for CPU main stack pointer, 1 MPU unit for CPU
thread stack pointer, 2 MPU units for DMA and 1 MPU unit for IP.
Among them, the ARM MPU provides the access control of the CPU to the entire 4G address space.
MSPMPU/ PSPMPU respectively provide protection for the CPU's main stack pointer/thread stack
pointer. When the pointer exceeds the set range, the MPU action can be set as non-maskable
interrupt/reset.
SMPU1/ SMPU2 respectively provide system DMA_1/system DMA_2 with read and write access
control to the entire 4G address space. When accessing the prohibited space, the MPU action can
be set to ignore/bus error/non-maskable interrupt/reset.
The IPMPU provides access control to system IP and security-related IP in non-privileged mode.
1.4.13 Keyboard Scanning (KEYSCAN)
This product is equipped with a keyboard control module (KEYSCAN) 1 unit. The KEYSCAN module
supports keyboard array (row and column) scanning, the column is driven by an independent scan
output KEYOUTm (m=0~7), and the row KEYINn (n=0~15) is input as EIRQn (n=0~15) is detected.
This module realizes the key recognition function through the line scan query method.
1.4.14 Internal Clock Calibrator (CTC)
The Clock Trimming Controller (CTC) automatically calibrates the internal high-speed oscillator
(HRC). Because the influence of working environment on HRC frequency may cause deviation, CTC
can automatically adjust HRC frequency by hardware based on external high precision reference
clock to obtain an accurate HRC clock.
The main features of CTC are as follows:
◾ Three external reference clock sources: XTAL, XTAL32, CTCREF

◾ 16-bit calibrated counter for frequency measurement with reload function
◾ 8-bit calibration offset value and 6-bit calibration value for frequency calibration
◾ Error interrupt for calibration failure
1.4.15 DMA Controller (DMA)
DMA is used to transfer data between memory and peripheral function modules, and can realize
data exchange between memories, between memory and peripheral function modules, and
between peripheral function modules without CPU participation.
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◾ DMA bus is independent of CPU bus and transmitted according to AMBA AHB-Lite bus protocol.
◾ With 2 DMA control units, a total of 12 independent channels, which can independently operate
different DMA transfer functions
◾ For each channel, the source of the boot request is configured via a separate trigger source
◾ One block per request
◾ The minimum data block is 1 data, and the maximum is 1024 data
◾ The width of each data can be configured as 8bit, 16bit or 32bit
◾ 1~65535 or unlimited transmissions can be configured
◾ The source address and target address can be independently configured as fixed, self-
incrementing, self-decreasing, looping, or jumping with a specified offset
◾ Three kinds of interrupts can be generated: block transfer complete interrupt, transfer
complete interrupt and transfer error interrupt. Each interrupt can be configured with a mask
or not. Among them, the completion of block transmission and the completion of transmission
can be used as event output, which can be used as the trigger source of other peripheral
modules
◾ Support for linked transmission to enable multiple blocks of data to be transmitted at a time
◾ Support channel reset triggered by external events
◾ You can set the module stop state to reduce power consumption when not in use
◾ The HPROT value in the AHB bus during DMA access can be set by register
1.4.16 Voltage Comparator (CMP)
A voltage comparator (Comparator, hereinafter referred to as CMP) is a peripheral module that

compares two analog voltages and outputs a comparison result. This product is equipped with two
sets of 4 comparison channels: CMP1/ CMP2, CMP3/ CMP4.
CMP has the following main features:
◾ 4 comparison channels can perform voltage comparison independently

◾ The combination of two comparison channels in the same group can realize up to 2 groups of
window comparisons
◾ There are multiple input sources (IO/ DAC) for the positive/ negative terminal voltage of each
comparison channel
◾ The noise filter can filter the output of the comparator, and 7 sampling clocks are optional
◾ Comparator output blank window control using timer PWM
◾ Can generate interrupts, trigger other peripherals, and wake up from STOP mode on the edge
of the comparison result
◾ The comparison result can be monitored by the register, and can also be output to the external
pin VCOUT
◾ Comparison results can be used for emergency braking (EMB) control events
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1.4.17 Analog-to-Digital Converter (ADC)
12-bit ADC is an analog-to-digital converter with successive approximation. This MCU is equipped
with 3 ADC units, unit 1 supports a maximum of 16 channels, unit 2 supports a maximum of 8
channels, and unit 3 supports a maximum of 12 channels, which can convert analog signals from
external pins and inside the chip. The analog input channels can be combined into a sequence
arbitrarily, and a sequence can be converted by single scan or continuous scan. It supports multiple
consecutive conversions on any specified channel and averages the conversion results. The ADC
module is also equipped with an analog watchdog function to monitor the conversion result of any
specified channel and detect whether it exceeds the range set by the user.
The main features of the ADC are as follows:

◾ High performance
‒ Configurable 12-bit, 10-bit and 8-bit resolution
‒ The frequency ratio of ADC digital interface clock PCLK4 and conversion clock PCLK2 (also
known as ADCLK) can be set to 1:1, 2:1, 4:1, 8:1, 1:2, 1:4
PCLK2 can choose the PLL clock that is asynchronous with the system clock HCLK, and the
frequency ratio at this time is PCLK4:PCLK2=1:1
‒ PCLK2 frequency up to 60MHz
‒ Sampling rate: 2.5MSPS (PCLK2=60MHz, 12 bits, sampling 11 cycles, conversion 13 cycles)
‒ The sampling time of each channel is independently programmed
‒ Channel-independent data register
‒ Data register configurable left/right alignment
‒ Consecutive multiple conversion average function
‒ Oversampling function
‒ Simulation watchdog, monitoring conversion results
‒ The ADC module can be set to stop when not in use
◾ Analog input channel
‒ Maximum 24 external analog input channels
‒ 1 internal analog input: internal reference voltage
◾ Conversion start condition
‒ Software Setup Conversion Started
‒ Start of Peripheral Device Synchronization Trigger Conversion
‒ External Pin Triggering Start
◾ Conversion mode
‒ 2 scan sequences A and B, optionally specifying a single or multiple channels
‒ Sequence A single scan
‒ Sequence A continuous scanning
‒ Sequence A multiple data cache mode
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‒ Double sequence scanning, sequence A and B independently select trigger source,

sequence B has higher priority than A
‒ Cooperative mode (for devices with two or three ADCs)
◾ Interrupt and Event Signal Output
‒ Sequence A Scan End Interrupt and Event ADC_EOCA
‒ Sequence B Scan End Interrupt and Event ADC_EOCB
‒ Analogwatchdog 0 compared interrupt and event ADC_CMP0
‒ Simulation watchdog 1 comparing interrupt and event ADC_CMP1
‒ All four of these event outputs can start the DMA
1.4.18 Digital to Analog Converter (DAC)
This MCU is equipped with a digital-to-analog converter unit DAC with 12-bit conversion accuracy.
The DAC unit contains two D/A conversion channels, and the two channels can be converted
independently or synchronously. There are two levels of analog voltage output range can be set.
Each conversion channel is equipped with an output amplifier that can directly drive an external
load without an external op amp.
The main features of the DAC are as follows:
◾ Two D/A conversion channels

◾ 12-bit conversion data can be configured as left-justified or right-justified format
◾ Simultaneous Conversion of Two Conversion Channels
◾ The data of the conversion data computing unit (DCU) can output triangle wave and sawtooth
wave
◾ The output can be used as the negative input of the voltage comparator (CMP)
◾ Outputs are amplified to directly drive external loads
◾ A/D conversion priority mode can reduce interference with ADC conversion
1.4.19 Advanced Control Timer (Timer6)
Advanced Control Timer 6 (Timer6) is a high-performance timer with a 16-bit count width, which
can provide rich and flexible combinations and various interrupts, events, and PWM outputs in
various complex application scenarios. The timer supports two counting waveform modes of
sawtooth wave and triangular wave, and can generate various PWM waveforms (unilaterally aligned
independent PWM, bilaterally symmetrical independent PWM, bilaterally symmetrical
complementary PWM, bilaterally asymmetrical PWM, etc.); software synchronization between units
can be achieved Synchronized with hardware (synchronous start, stop, clear, refresh, etc.); each
reference register supports cache function (single-level cache and double-level cache); supports
pulse width measurement and period measurement; supports 2-phase quadrature encoding
counting and 3 Phase quadrature encoding count; support EMB control. This series of products is
equipped with 2 units of Timer6.
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1.4.20 General Control Timer (Timer4)
General control timer 4 (Timer4) is a timer module for three-phase motor control. It provides three-
phase motor control schemes for various applications. The timer supports two counting waveform
modes of triangle wave and sawtooth wave, and can generate various PWM waveforms; supports
buffer function; supports EMB control. 3 unit of Timer 4 is carried in this product family.
1.4.21 Emergency Brake Module (EMB)
The emergency brake module is a functional module that generates a control event and outputs it
to the timer when certain conditions are met, so as to control the timer to stop or change the output
PWM signal to the external motor. The following factors are used to generate the control event:
◾ Change of input level of external port

◾ Level of PWM output port occurs in phase (same high or same low)
◾ Voltage comparator comparison results
◾ System error occurred
◾ Write register software control
1.4.22 General Timer (TimerA)
General-purpose TimerA is a timer with 16/32-bit count width and 8 PWM outputs. The timer
supports two counting waveform modes of triangular wave and sawtooth wave, and can generate
various PWM waveforms (unilaterally aligned PWM, bilaterally symmetrical PWM); supports counter
synchronous start; comparison reference value register supports cache function; supports
cascaded counting between units; Support 2-phase quadrature code count and 3-phase quadrature
code count. This series of products is equipped with 5 units TimerA (unit 1 is a 32-bit timer, and
units 2~5 are 16-bit timers), which can realize up to 40 channels of PWM output.
1.4.23 General Timer (Timer0)
General-purpose Timer0 is a basic timer that can realize synchronous counting and asynchronous
counting. The timer contains 2 channels (CH-A and CH-B), which can generate comparison match
events and count overflow events during the counting period. This event can trigger an interrupt,
and can also be used as an event output to control other modules. This series of products is
equipped with 2 units of Timer0.
1.4.24 Real Time Clock (RTC)
A real-time clock (RTC) is a counter that stores time information in BCD format. Record the specific
calendar time from 00 to 99. Supports 12/24 hour time format, and can automatically calculate the
number of days 28, 29 (leap year), 30 and 31 according to the month and year.
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1.4.25 Watchdog Counter (WDT/SWDT)
This product has two watchdog counters, one is the counting clock source is a dedicated internal
RC (SWDTLRC: 10KHz) dedicated watchdog counter (SWDT), and the other is a general-purpose
watchdog counter (WDT) whose count clock source is PCLK3. Both the dedicated watchdog and the
general watchdog are 16-bit down counters, which are used to monitor software failures due to
external disturbances or unforeseen logic conditions that deviate from the normal operation of the
application program.
Both watchdogs support window compare function. The window interval can be preset before the
count starts, and when the count value is within the window interval, the counter can be refreshed
and the count restarted.
1.4.26 General Synchronous Asynchronous Transceiver (USART)
This product is equipped with 6 units of Universal Synchronous Asynchronous Transceiver (USART)
module, which can flexibly perform full-duplex data exchange with external devices. The USART
equipped on this product supports universal asynchronous serial communication interface (UART),
clock synchronous communication interface, smart card interface (ISO/IEC7816-3) and LIN
communication interface; supports modem operation (CTS/RTS operation), processor operation.
Cooperate with Timer0 module to support UART receive timeout function. USART_1 supports wake-
up function through RX pin STOP mode.
The specific functions are allocated as follows:
◾ UART: full channel support

◾ Multiprocessor communication: full channel support
◾ Clock synchronous communication: full channel support
◾ RX pin wakes up Stop mode function: USART_1 support
◾ Fractional baud rate: full channel support
◾ LIN: USART_3, USART_6 support
◾ Smart Card: USART_1, USART_2, USART_4, USART_5 supported
◾ UART receive timeout function: USART_1, USART_2, USART_4, USART_5 support
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1.4.27 Integrated Circuit Bus (I2C)
I2C (Integrated Circuit Bus) is used as an interface between the microcontroller and the I2C serial
bus. Provide multi-master mode function, which can control the protocol and arbitration of all I2C
buses. Standard mode and fast mode are supported. SMBus is also supported.
This product is equipped with 2-channel integrated circuit bus I2C.
I2C main features:
◾ I2C bus mode and SMBus bus mode are optional. Host mode and slave mode are optional.
Automatically ensures various prepare times, hold times, and bus idle times relative to the
transfer rate
◾ Standard mode up to 100Kbps, fast mode up to 400Kbps
◾ Automatically generate start condition, restart condition and stop condition, and can detect
bus start condition, restart condition and stop condition
◾ Maximum support for 128 slave addresses. Support 7-bit address format and 10-bit address
format. Can detect broadcast call address, SMBus host address, SMBus device default address,
SMBus alarm address
◾ Answer bits can be automatically determined when sent. Acknowledgment bit can be sent
automatically when receiving
◾ Handshake function
◾ Arbitration function
◾ Timeout function, can detect SCL clock stop for a long time
◾ SCL input and SDA input built-in digital filter, filter capability can be programmed
◾ Communication error, received data is full, sent data is empty, a frame is sent, and the address
match is interrupted
◾ 2-stage transmit FIFO and 2-stage receive FIFO
1.4.28 Serial Peripheral Interface (SPI)
This product is equipped with a serial peripheral interface SPI with 3 channels, supports high-speed
full-duplex serial synchronous transmission, and can easily exchange data with peripheral devices.
Users can set the range of 3/4-wire, host/slave and baud rate as needed.
Main Features of SPI:
◾ Serial communication function

‒ Supporting 4-wire SPI mode and 3-wire clock synchronization mode
‒ Support full-duplex and send-only communication methods
‒ Polarity and phase of adjustable communication clock SCK
◾ Data format
‒ Selectable data shift order: MSB start/LSB start
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‒ Selectable data width: 4/ 5/ 6/ 7/ 8/ 9/ 10/ 11/ 12/ 13/ 14/ 15/ 16/ 20/ 24/ 32 bits
‒ A maximum of 32 bits of data can be transmitted or received ifn four single frame
◾ Baud rate
‒ In host mode, the baud rate can be adjusted through the built-in dedicated baud rate
generator, and the baud rate range is divided by 2 to 256 of PCLK1
‒ The maximum baud rate allowed in slave mode is divided by 6 of PCLK1
◾ Data buffer
‒ Data buffer area with 16 bytes
‒ Supports double buffering
◾ Error monitoring
‒ Mode fault error monitoring
‒ Data overload error monitoring
‒ Data underload error monitoring
‒ Parity error monitoring
◾ Chip selection signal control
‒ Each channel is configured with excluding chip-selected signal line
‒ The relative timing relationship between the chip select signal and the communication
clock can be adjusted
‒ The invalid time of the chip select signal between two consecutive communications can
be adjusted
‒ Polarity adjustable
◾ Transmission Control in Host Mode
‒ Start transmission by writing data to the data register
‒ Communication auto suspend function
◾ Interrupt
‒ Accept data area is full
‒ Sending data area is empty
‒ SPI error (mode/overload/underload/parity)
‒ SPI vacant
‒ Transfer complete (event source only)
◾ Low power control
‒ Configurable module stop
◾ Other functions
‒ SPI initialization function
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1.4.29 Quad-wire Serial Peripheral Interface (QSPI)
The Quad Serial Peripheral Interface (QSPI) is a memory control module designed to communicate
with serial ROMs with an SPI-compatible interface. Its objects mainly include serial flash memory,
serial EEPROM and serial FeRAM.
1.4.30 External Memory Controller (EXMC)
The external memory controller EXMC (External Memory Controller) is an independent module used
to access various off-chip memories and realize data exchange. Through configuration, EXMC can
convert the internal AMBA protocol interface into various types of dedicated off-chip memory
communication protocol interfaces, including SRAM, PSRAM, NOR Flash, etc.
1.4.31 Controller Area Network (MCAN)
This product is equipped with two unit MCAN communication interface modules (MCAN1 and
MCAN2), and is equipped with 2KB RAM for the two MCAN controllers.
Both CAN modules (MCAN1 and MCAN2) comply with ISO 11898-1: 2015 (CAN Protocol Specification
Version 2.0 Part A, B) and CAN FD Protocol Specification Version 1.0 (CAN with Flexible Data-Rate
Specification Version 1.0).
The 2KB message RAM memory can realize the functions of receiving filter (Rx Filter), receiving
FIFO (Rx FIFO), receiving buffer (Rx Buffer), sending event FIFO (Tx Event FIFO), and sending buffer
(Tx Buffer). This message RAM is shared between the MCAN1 and MCAN2 modules.
1.4.32 Cryptographic Coprocessing Module (CPM)
The encryption co-processing module (CPM) includes three sub-modules: AES encryption and
decryption algorithm processor, HASH secure hash algorithm, and TRNG true random number
generator.
The AES encryption and decryption algorithm processor follows the new data encryption standard
officially announced by the National Institute of Standards and Technology (NIST) on October 2,
2000. The block length is fixed at 128 bits, and the key length supports 128/ 192/ 256 bits.
The HASH secure hash algorithm is the SHA-2 version of SHA-256 (Secure Hash Algorithm), which
complies with the national standard "FIPS PUB 180-3" issued by the National Institute of Standards
and Technology, and can generate 256bit message digest output.
TRNG true random number generator is a random number generator based on continuous analog
noise, providing 64bit random numbers.
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1.4.33 Data Computing Unit (CRC)
Data Computing Unit DCU (Data Computing Unit) is a module that simply processes data without
the help of a CPU. Each DCU unit has 3 data registers, which can perform addition and subtraction
of 2 data and size comparison, as well as window comparison function, and can also provide
continuously changing digital quantities to the digital-to-analog conversion module (DAC) through
timer triggers to generate Triangle and sawtooth output. This product is equipped with 4 DCU units.
1.4.34 CRC Unit (CRC)
The CRC algorithm of this module complies with the definition of ISO/ IEC13239, using 32-bit and
16-bit CRC respectively. The generating polynomial of CRC32 is X32+ X26+ X23+ X22+ X16+ X12+
X11+ X10+ X8+ X7+ X5+ X4+ X2+ X+ 1, and the initial value of 32 bits is 0xFFFF FFFF. The generating
polynomial of CRC16 is X16+ X12+ X5+ 1, and the initial value of 16 bits is 0xFFFF.
1.4.35 Debug Controller (DBGC)
The core of this MCU is Cortex-M4, which contains hardware for advanced debugging functions.
With these debugging features, you can stop the kernel when fetching fingers (instruction
breakpoints) or accessing data (data breakpoints). When the kernel is stopped, the internal state
of the kernel and the external state of the system can be queried. After the query is completed, the
kernel and system will be restored and program execution will resume.
Two debugging interfaces are provided:
◾ Serial Debugging Tracking Interface SWD

◾ Parallel debug trace interface JTAG
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2 Pin Configuration and Functions (Pinouts)
2.1 Pin Configuration Diagram

LQFP80
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LQFP64
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LQFP48
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QFN48
Note: The picture above is the top view (Top View) of QFN48.
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QFN32
Note: The picture above is the top view (Top View) of QFN32.
Figure 2-1 Pin Configuration Diagram
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2.2 Pin Function Table

Table 2-1 Pin Function Table
Func Func
Func0 Func1 Func2 Func3 Func4 Func5 Func6 Func7 Func8 Func11 Func12 Func13 Func14 Func15 Func21 Func22
LQFP LQFP QFN/ QFN EIRQ TRACE 9~10 16~20 Func Func
PinName Analog
80 64 LQFP48 32 /WKUP /JTAG TIM4, TIM4, EMB, USART,SPI, KEY, TIM4, EXMC, TIM6, 23~31 Group
GPO other TIMA TIMA - EVNTPT EVENTOUT - PLUIN PLUOUT
VCOUT TIM6 TIMA QSPI USART TIMA TIMA TIMA
TRACE TIMA_3 USART6_R

1 - - - PE2 ADC3_IN0 EIRQ2 TIM4_2_PCT USART3_CK EVENTOUT PLU0_INA PLU0_OUT FG2
CLK _PWM5 TS
TRACE TIM4_2_ADS TIMA_3 USART5_R

2 - - - PE3 ADC3_IN1 EIRQ3 USART4_CK EVENTOUT PLU0_INB PLU1_OUT FG2
D0 M _PWM6 TS
TRACE CTCRE TIM4_2 TIMA_3

3 - - - PE4 ADC3_IN2 EIRQ4 TIM4_1_PCT USART6_CK EVENTOUT PLU0_INC PLU2_OUT FG2
D1 F _OWL _PWM7
TRACE FCMRE TIMA_4 TIMA_3_T USART6_C TIMA_4_T

4 1 1 31 PH2 EIRQ2 TIM4_2_CLK EMB_IN4 USART4_CK EVENTOUT PLU0_IND PLU3_OUT FG2
D2 F _PWM7 RIG TS RIG
TIMA_2_P
TRACE RTC_O TIM4_1 TIMA_4 USART6_R TIM4_1_A EXMC_AD EVNTP31
5 2 2 32 PC13 EIRQ13 VCOUT4 WM2/CLK USART5_CK PLU1_INA PLU0_OUT FG2
D3 UT _OXL _PWM8 TS DSM 16 3
B
CTCRE TIM4_3 TIMA_4 USART5_C TIM4_1_O EXMC_BA EVNTP31
6 3 3 1 PC14 XTAL32_IN EIRQ14 TIM4_1_OVH PLU1_INB PLU1_OUT
F _OXH _PWM5 TS XH A 4
TIM4_3 TIMA_4 USART5_R TIM4_1_C EXMC_CR EVNTP31

7 4 4 2 PC15 XTAL32_OUT EIRQ15 TIM4_1_OWH PLU1_INC PLU2_OUT
_OXL _PWM6 TS LK E 5
TIMA_5_P
8 5 5 3 PH0 XTAL_IN EIRQ0 TIM4_3_OXL PLU1_IND PLU3_OUT
WM3
XTAL_EXT/XTAL TIMA_5_P
9 6 6 4 PH1 EIRQ1 TIM4_3_CLK PLU2_INA PLU0_OUT
_OUT WM4
10 7 7 5 NRST
ADC12_IN1+CM
TIMA_2 EXMC_WA EVNTP30
11 8 - - PC0 P3_INP3+CMP4 EIRQ0 TIM4_3_PCT EVENTOUT PLU2_INB PLU1_OUT FG1
_PWM5 IT 0
_INP3
TIM4_3_ADS TIMA_2 EXMC_CL EVNTP30
12 9 - - PC1 ADC12_IN11 EIRQ1 EVENTOUT PLU2_INC PLU2_OUT FG1
M _PWM6 K 1
TIMA_2 EXMC_BL EVNTP30

13 10 - - PC2 ADC1_IN12 EIRQ2 TIM4_3_OXH EMB_IN3 EVENTOUT PLU2_IND PLU3_OUT FG1
_PWM7 S0 2
ADC1_IN13+CM TIMA_2 EXMC_BL EVNTP30

14 11 - - PC3 EIRQ3 MCO_2 TIM4_3_OXL EVENTOUT PLU3_INA PLU0_OUT FG1
P1_INM2 _PWM8 S1 3
15 - - - VCC
AVSS/
16 12 8 6
VREFL
AVCC/
17 13 9 7
VREFH
TIMA_2 TIMA_1_P
ADC1_IN0 EIRQ0+W TIM4_1 TIMA_2_T USART3_C EXMC_AD EVNTP10
18 14 10 8 PA0 TIM4_2_OUH _PWM1 WM1/CLK SPI1_NSS1 EVENTOUT PLU3_INB PLU1_OUT FG1
+CMP1_INP1 KUP0_0 _OVH RIG TS 17 0
/CLKA A
TIMA_2
ADC1_IN1 TIMA_3_T USART5_C EXMC_AD EVNTP10
19 15 11 - PA1 EIRQ1 TIM4_2_OUL _PWM2 SPI1_NSS2 EVENTOUT PLU3_INC PLU2_OUT FG1
+CMP1_INP2 RIG TS 18 1
/CLKB
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Func Func
PinName Analog
TIMA_5_P
ADC1_IN2 TIMA_2 USART6_C EXMC_AD EVNTP10
20 16 12 - PA2 EIRQ2 TIM4_2_OVH WM1/CLK SPI1_NSS3 EVENTOUT PLU3_IND PLU3_OUT FG1
+CMP1_INP3 _PWM3 TS 19 2
A
ADC1_IN3 TIMA_5_P
TIMA_2 USART3_R EXMC_AD EVNTP10
21 17 13 - PA3 +CMP1_INP4 EIRQ3 TIM4_2_OVL WM2/CLK USART5_CK EVENTOUT PLU0_INA PLU0_OUT FG1
_PWM4 TS 20 3
+CMP2_INP4 B
22 18 - - VSS
23 19 - - VCC
ADC12_IN4
+CMP2_INP1 TIM4_1 TIMA_3_P EXMC_CS EVNTP10
24 20 14 9 PA4 EIRQ4 TIM4_2_OWH USART2_CK KEYOUT0 EVENTOUT PLU0_INB PLU1_OUT FG1
+CMP3_INP4 _OWH WM5 0 4
+DAC_OUT1
ADC12_IN5+CM TIMA_2
TIMA_3_P TIMA_2_T EXMC_DA EVNTP10
25 21 15 - PA5 P2_INP2+DAC_ EIRQ5 TIM4_2_OWL _PWM1 SPI3_NSS1 KEYOUT1 EVENTOUT PLU0_INC PLU2_OUT FG1
WM6 RIG TA7 5
OUT2 /CLKA
TIMA_3_P
ADC123_IN+CM TIM4_2_ADS TIM4_1 EXMC_DA EVNTP10
26 22 16 - PA6 EIRQ6 WM1/CLK EMB_IN2 SPI3_NSS2 KEYOUT2 EVENTOUT PLU0_IND PLU3_OUT FG1
P2_INP3 M _PCT TA0 6
A
TIMA_3_P
ADC123_IN+CM TIM6_1 TIMA_1 EXMC_DA EVNTP10
27 23 17 - PA7 EIRQ7 TIM4_1_OUL WM2/CLK EMB_IN3 SPI3_NSS3 KEYOUT3 EVENTOUT PLU1_INA PLU0_OUT FG1
P1234_INM1 _PWMB _PWM5 TA1 7
B
ADC1_IN14 TIMA_3_P EXMC_DA EVNTP30
28 24 - - PC4 EIRQ4 TIM4_2_OUH USART1_CK EVENTOUT PLU1_INB PLU1_OUT FG1
+CMP2_INM2 WM7 TA8 4
ADC1_IN15 TIMA_3_P EXMC_DA EVNTP30

29 25 - - PC5 EIRQ5 TIM4_2_OUL EVENTOUT PLU1_INC PLU2_OUT FG1
+CMP3_INM2 WM8 TA9 5
ADC123_IN8+C TIM6_2 TIMA_1 TIMA_3_P EXMC_DA EVNTP20

30 26 18 - PB0 EIRQ0 TIM4_1_OVL USART4_CK KEYOUT4 EVENTOUT PLU1_IND PLU3_OUT FG1
MP3_INP1 _PWMB _PWM6 WM3 TA2 0
ADC123_IN9+C
EIRQ1+W CTCRE TIMA_1 TIMA_3_P TIMA_4_P EXMC_DA EVNTP20
31 27 19 10 PB1 MP3_INP2+CMP TIM4_1_OWL QSPI1_NSS KEYOUT5 EVENTOUT PLU2_INA PLU0_OUT FG1
KUP0_1 F _PWM7 WM4 WM4 TA3 1
4_INP2
TIMA_5_P
EIRQ2+W TIM6_T TIMA_1 EVNTP20
32 28 20 11 PB2 PVD2EXINP VCOUT TIM4_1_PCT WM2/CLK EMB_IN1 QSPI1_IO3 EVENTOUT PLU2_INB PLU1_OUT FG1
KUP0_2 RIGB _PWM8 2
B
TIMA_1 EXMC_DA
33 - - - PE12 ADC3_IN3 EIRQ12 TIM4_1_OWL SPI1_NSS1 EVENTOUT PLU2_INC PLU2_OUT FG2
_PWM7 TA10
TIMA_1 EXMC_DA
34 - - - PE13 ADC3_IN4 EIRQ13 TIM4_1_OWH SPI1_NSS2 EVENTOUT PLU2_IND PLU3_OUT FG2
_PWM3 TA11
ADTRG TIMA_1 EXMC_DA

35 - - - PE14 ADC3_IN5 EIRQ14 TIM4_1_CLK SPI1_NSS3 EVENTOUT PLU3_INA PLU0_OUT FG2
1 _PWM4 TA12
ADTRG TIMA_1 TIMA_5_T EXMC_DA

36 - - - PE15 ADC3_IN10 EIRQ15 EMB_IN2 USART4_CK EVENTOUT PLU3_INB PLU1_OUT FG2
3 _PWM8 RIG TA13
ADTRG TIM4_1 TIMA_2 TIMA_5_P TIMA_1_P EXMC_DA EVNTP21

37 29 21 12 PB10 ADC3_IN11 EIRQ10 TIM4_2_OVH QSPI1_IO2 EVENTOUT PLU3_INC PLU2_OUT FG2
2 _OXL _PWM3 WM8 WM3 TA4 0
38 30 22 13 VCAP_1
39 31 23 14 VSS
40 32 24 15 VCC
VCOUT TIM6_T TIMA_1 TIMA_5_T USART5_C EXMC_DA EVNTP21

41 33 25 16 PB12 EIRQ12 TIM4_2_OVL EMB_IN2 QSPI1_IO1 EVENTOUT PLU3_IND PLU3_OUT FG2
1 RIGB _PWM8 RIG TS TA5 2
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Func Func
PinName Analog
TIMA_4_P TIMA_3_P
VCOUT TIM6_1 TIMA_1 USART5_R EVNTP21
42 34 26 17 PB13 EIRQ13 TIM4_1_OUL WM1/CLK WM1/CLK QSPI1_IO0 EVENTOUT PLU0_INA PLU0_OUT FG2
2 _PWMB _PWM5 TS 3
A A
TIMA_4_P TIMA_3_P
VCOUT TIM6_2 TIMA_1 USART6_C EVNTP21
43 35 27 18 PB14 EIRQ14 TIM4_1_OVL WM2/CLK WM2/CLK QSPI1_SCK EVENTOUT PLU0_INB PLU1_OUT FG2
3 _PWMB _PWM6 TS 4
B B
TIMA_1_P TIMA_2_P
RTC_O TIMA_1 USART6_R TIM6_2_P EVNTP21
44 36 28 19 PB15 EIRQ15 TIM4_1_OWL EMB_IN4 USART3_CK WM2/CLK WM2/CLK EVENTOUT PLU0_INC PLU2_OUT FG2
UT _PWM7 TS WMA 5
B B
TIM4_2 TIM4_1_O EVNTP40
45 - - - PD8 EIRQ8 TIM4_3_OUL QSPI1_IO0 KEYOUT7 EVENTOUT PLU0_IND PLU3_OUT FG2
_OWL XH 8
TIM4_2 TIM4_1_O EVNTP40

46 - - - PD9 EIRQ9 TIM4_3_OVL QSPI1_IO1 KEYOUT6 EVENTOUT PLU1_INA PLU0_OUT FG2
_OVL XL 9
TIM4_2_O EVNTP41
47 - - - PD10 EIRQ10 TIM4_3_OWL QSPI1_IO2 KEYOUT5 EVENTOUT PLU1_INB PLU1_OUT FG2
XH 0
TIM4_2_O EVNTP41
48 - - - PD11 EIRQ11 TIM4_3_CLK QSPI1_IO3 KEYOUT4 EVENTOUT PLU1_INC PLU2_OUT FG2
XL 1
TIMA_3
CTCRE TIM4_2_ADS TIM4_1 TIMA_5_P EVNTP30
49 37 - - PC6 EIRQ6 _PWM1 QSPI1_SCK KEYOUT3 EVENTOUT PLU1_IND PLU3_OUT FG2
F M _CLK WM8 6
/CLKA
TIMA_3
TIM4_3 TIMA_5_P EVNTP30
50 38 - - PC7 EIRQ7 TIM4_2_CLK _PWM2 QSPI1_NSS KEYOUT2 EVENTOUT PLU2_INA PLU0_OUT FG2
_OVH WM7 7
/CLKB
TIM4_3 TIMA_3 TIMA_5_P EXMC_DA EVNTP30
51 39 - - PC8 EIRQ8 TIM4_2_OWH USART3_CK KEYOUT1 EVENTOUT PLU2_INB PLU1_OUT FG2
_OVL _PWM3 WM6 TA14 8
TIM4_3 TIMA_3 TIMA_5_P EXMC_DA EVNTP30

52 40 - - PC9 EIRQ9 MCO_2 TIM4_2_OWL KEYOUT0 EVENTOUT PLU2_INC PLU2_OUT FG1
_OUL _PWM4 WM5 TA15 9
TIMA_1 TIMA_2_P
EIRQ8+W TIM6_1 EVNTP10
53 41 29 20 PA8 CMP4_INM2 MCO_1 TIM4_1_OUH _PWM1 WM1/CLK USART1_CK EVENTOUT PLU2_IND PLU3_OUT FG1
KUP2_0 _PWMA 8
/CLKA A
TIMA_1
EIRQ9+W CTCRE TIM6_2 EVNTP10
54 42 30 - PA9 CMP4_INP1 TIM4_1_OVH _PWM2 EVENTOUT PLU3_INA PLU0_OUT FG1
KUP2_1 F _PWMA 9
/CLKB
EIRQ10+ CTCRE TIM4_3 TIMA_1 TIMA_5_T EVNTP11
55 43 31 - PA10 CMP4_INP4 TIM4_1_OWH USART6_CK EVENTOUT PLU3_INB PLU1_OUT FG1
WKUP2_2 F _CLK _PWM3 RIG 0
TIMA_5_P
EIRQ11+ TIM4_1 TIM6_T TIMA_1 USART3_R EVNTP11
56 44 32 21 PA11 TIM4_1_CLK WM1/CLK EMB_IN1 USART5_CK EVENTOUT PLU3_INC PLU2_OUT FG1
WKUP2_3 _OXL RIGA _PWM4 TS 1
A
TIMA_3_P
EIRQ12+ TIM4_1 TIM6_T TIMA_1 TIMA_2_T USART3_C TIM4_2_P EXMC_DA EVNTP11
57 45 33 22 PA12 TIM4_3_OWL USART6_CK WM1/CLK EVENTOUT PLU3_IND PLU3_OUT FG1
WKUP3_0 _ADSM RIGA _TRIG RIG TS CT TA6 2
A
EIRQ13+ JTMS_S TIM4_3_ADS TIMA_2 TIMA_5_T EXMC_DA EVNTP11
58 46 34 23 PA13 SPI2_NSS1 EVENTOUT PLU0_INA PLU0_OUT FG1
WKUP3_1 WDIO M _PWM5 RIG TA7 3
59 47 35 - VSS
60 48 36 24 VCC
EIRQ14+ JTCK_S TIMA_2 TIMA_4_T EXMC_CS EVNTP11

61 49 37 25 PA14 TIM4_3_PCT SPI2_NSS2 EVENTOUT PLU0_INB PLU1_OUT FG1
WKUP3_2 WCLK _PWM6 RIG 0 4
TIMA_2
EIRQ15+ TIMA_2_T EVNTP11
62 50 38 26 PA15 JTDI TIM4_3_OXH _PWM1 SPI2_NSS3 EVENTOUT PLU0_INC PLU2_OUT FG1
WKUP3_3 RIG 5
/CLKA
TIMA_5_P
TIMA_2 TIM4_2_O EVNTP31
63 51 - - PC10 EIRQ10 TIM4_3_OUH WM1/CLK EVENTOUT PLU0_IND PLU3_OUT FG1
_PWM7 XL 0
A
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Func Func
PinName Analog
TIMA_5_P
64 52 - - PC11 EIRQ11 TIM4_3_OVH WM2/CLK EVENTOUT PLU1_INA PLU0_OUT FG1
_PWM8 XH 1
B
TIM4_2 TIMA_4 TIMA_5_P TIM4_1_O EVNTP31
65 53 - - PC12 EIRQ12 TIM4_3_OWH EVENTOUT PLU1_INB PLU1_OUT FG1
_PCT _TRIG WM3 XL 2
TIM4_3 TIMA_5_P EVNTP40

66 - - - PD0 EIRQ0 VCOUT TIM4_2_OUL EVENTOUT PLU1_INC PLU2_OUT FG1
_OUH WM4 0
TIM4_3 TIMA_3 EVNTP40

67 - - - PD1 EIRQ1 TIM4_2_OWH EVENTOUT PLU1_IND PLU3_OUT FG1
_OWH _TRIG 1
TIM4_2 TIMA_2 EVNTP40

68 54 - - PD2 EIRQ2 TIM4_1_OXH EVENTOUT PLU2_INA PLU0_OUT FG1
_OVH _PWM4 2
JTDO_T TIMA_2
EIRQ3+W FCMRE EVNTP20
69 55 39 27 PB3 RACES TIM4_3_CLK _PWM2 EVENTOUT PLU2_INB PLU1_OUT FG2
KUP0_3 F 3
WO /CLKB
TIMA_3
EIRQ4+W EVNTP20
70 56 40 28 PB4 NJTRST TIM4_3_OWL _PWM1 EVENTOUT PLU2_INC PLU2_OUT FG2
KUP1_0 4
/CLKA
TIMA_3 TIMA_1_P
EIRQ5+W ADTRG TIM6_1 TIMA_3_T TIMA_4_T TIM4_1_O EVNTP20
71 57 41 29 PB5 TIM4_3_OWH _PWM2 USART4_CK WM2/CLK EVENTOUT PLU2_IND PLU3_OUT FG2
KUP1_1 3 _PWMA RIG RIG XH 5
/CLKB B
TIMA_4
EIRQ6+W ADTRG TIM4_1_O EVNTP20
72 58 42 - PB6 TIM4_3_OVL _PWM1 EVENTOUT PLU3_INA PLU0_OUT FG2
KUP1_2 2 XL 6
/CLKA
TIMA_4
EIRQ7+W ADTRG TIM4_2_O EXMC_AD EVNTP20
73 59 43 - PB7 TIM4_3_OVH _PWM2 EVENTOUT PLU3_INB PLU1_OUT FG2
KUP1_3 1 XH V 7
/CLKB
EVNTP21
74 60 44 30 PB11/MD PLU3_INC PLU2_OUT
1

75 61 45 - PB8 EIRQ8 TIM4_3_OUL USART5_CK KEYOUT7 EXMC_WE EVENTOUT PLU3_IND PLU3_OUT FG2
_PWM3 XL 8
TIMA_4 TIM4_1_A EVNTP20

76 62 46 - PB9 EIRQ9 TIM4_3_OUH EMB_IN4 SPI2_NSS1 KEYOUT6 EXMC_OE EVENTOUT PLU0_INA PLU0_OUT FG2
_PWM4 DSM 9
TIM4_1_ADS TIMA_4
77 - - - PE0 EIRQ0 MCO_1 SPI2_NSS2 EVENTOUT PLU0_INB PLU1_OUT FG2
M _TRIG
TIM4_2_O
78 - - - PE1 EIRQ1 MCO_2 TIM4_3_CLK SPI2_NSS3 EVENTOUT PLU0_INC PLU2_OUT FG2
UH
79 63 47 - VSS
80 64 48 - VCC
Note:
‒ In the above table, Func32~63 are mainly serial communication functions (including USART, SPI, I2C, and MCAN), which are divided into two groups
of FunctionGroups, referred to as FG1 and FG2. Please refer to Table 2-2 for details.
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Table 2-2 Func32~63 table
FG1 USART1_TX USART1_RX USART1_RTS USART1_CTS USART2_TX USART2_RX USART2_RTS USART2_CTS SPI1_MOSI SPI1_MISO SPI1_NSS0 SPI1_SCK SPI2_MOSI SPI2_MISO SPI2_NSS0 SPI2_SCK
FG2 USART3_TX USART3_RX USART3_RTS USART3_CTS USART4_TX USART4_RX USART4_RTS USART4_CTS SPI3_MOSI SPI3_MISO SPI3_NSS0 SPI3_SCK SPI1_MOSI SPI1_MISO SPI1_NSS0 SPI1_SCK
FG1 I2C1_SDA I2C1_SCL I2C2_SDA I2C2_SCL USART3_TX USART3_RX USART6_TX USART6_RX MCAN1_TX MCAN1_RX - - - - - -
FG2 I2C1_SDA I2C1_SCL MCAN1_TX MCAN1_RX USART5_TX USART5_RX USART6_TX USART6_RX MCAN2_TX MCAN2_RX - - - - - -
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Table 2-3 Port Configuration
Bits
Port Pin Count
Package
Group Total
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PortA o o o o o o o o o o o o o o o o 16
PortB o o o o o o o o o o o o o o o o 16
PortC o o o o o o o o o o o o o o o o 16
LQFP80 67
PortD - - - - o o o o - - - - - o o o 7
PortE o o o o - - - - - - - o o o o o 9
PortH - - - - - - - - - - - - - o o o 3
LQFP64 PortC o o o o o o o o o o o o o o o o 16 52
PortD - - - - - - - - - - - - - o - - 1
PortH - - - - - - - - - - - - - o o o 3
LQFP48 38
PortC o o o - - - - - - - - - - - - - 3
PortH - - - - - - - - - - - - - o o o 3
QFN48 38
PortC o o o - - - - - - - - - - - - - 3
PortH - - - - - - - - - - - - - o o o 3
PortA o o o o o - - o - - - o - - - o 8
PortB o o o o o o - - - - o o o o o - 11
QFN32 25
PortC o o o - - - - - - - - - - - - - 3
PortH - - - - - - - - - - - - - o o o 3
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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Table 2-4 Common Functional Specifications
Pull-up/ Open-Drain
Port Driving Capacity 5V Withstand Voltage
Pull-down Output
PA0~PA6, PA9~PA15 Support Support Low Medium High Support
PortA
PA7, PA8 Support Support Low Medium High not support
PortB PB0~PB15 Support Support Low Medium High Support
PC0~PC2, PC6~PC15 Support Support Low Medium High Support
PortC
PC3~PC5 Support Support Low Medium High not support
PortD PD0~PD2, PD8~11 Support Support Low Medium High Support
PortE PE0~PE5, PE12~15 Support Support Low Medium High Support
PortH PH0~PH2 Support Support Low Medium High Support
Note:
‒ When used as an analog function, the input voltage must not be higher than AVCC/ VREFH.
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2.3 Pin Function Description

Table 2-5 Pin Function Description
Categories Functional name I/O Note

VCC I Power supply
VSS I Source ground
VCAP_1 IO Core voltage
Power
AVCC/VREFH I Analog Power Supply/Analog Reference Voltage
System
AVSS/VREFL I Analog Power Ground/Analog Reference Voltage
NRST I Reset terminal, low effective
MD I Mode terminal
PVD PVD2EXINP I PVD2 external input comparison voltage
XTAL_IN I External master clock oscillator interface
XTAL_EXT/XTAL_OUT O XTAL_EXT external clock input
Clock XTAL32_IN I
External sub clock (32KHz) oscillator interface
XTAL32_OUT O
MCO_x (x=1~2) O Internal clock output
GPIO GPIOxy (x=A~E, H, y=0~15) IO General input/output
EVENTOUT EVENTOUT O Cortex-M4 CPU event output
EIRQx (x=0~15) I Shielded external interrupt
EIRQ
WKUPx_y (x=0~3, y=0~3) I Power Down mode external wake-up input
Event Port EVNTPxy (x=1~4, y=0~15) IO Event port input and output functions
Key KEYOUTx (x=0~7) O KEYSCAN scan output signal
JTCK_SWCLK I
JTMS_SWDIO IO
JTAG/ SWD JTDO_TRACESWO O Online debugging interface
JTDI I
NJTRST I
TRACECLK O Trace debug sync clock output
TRACE
TRACEDx (x=0~3) O Trace debug data output
External reference clock input for clock frequency
FCM FCMREF I
measurement
RTC RTC_OUT O 1Hz clock output
TIM4_<t>_CLK I Counting clock port input
TIM4_<t>_OUH IO PWM port U-phase output
TIM4_<t>_OUL IO PWM port U-phase output
Timer4
TIM4_<t>_OVH IO PWM port V-phase output
(<t>=1~3)
TIM4_<t>_OVL IO PWM port V-phase output
TIM4_<t>_OWH IO PWM port W-phase output
TIM4_<t>_OWL IO PWM port W-phase output
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TIM4_<t>_OXH IO PWM port X-phase output
Timer4 TIM4_<t>_OXL IO PWM port X-phase output

(<t>=1~3) TIM4_<t>_ADSM O Dedicated event output monitoring
TIM4_<t>_PCT O PWM period output monitoring
TIM6_TRIGA I External event trigger A input
Timer6 TIM6_TRIGB I External event trigger B input

(<t>=1~2) TIM6_<t>_PWMA IO External Event Trigger Input or PWM Port Output
TIM6_<t>_PWMB IO External Event Trigger Input or PWM Port Output
TIMA_<t>_TRIG I External event trigger input
External event trigger input or PWM port output or count
TIMA_<t>_PWM1/CLKA IO
TimerA clock port input
(<t>=1~5) External event trigger input or PWM port output or count
TIMA_<t>_PWM2/CLKB IO
clock port input
TIMA_<t>_PWMy (y=3~8) IO External Event Trigger Input or PWM Port Output
EMB EMB_INx (x=1~4) I Port input control signal
USARTx_TX IO Send data
USARTx_RX IO Receiving data
USARTx
USARTx_CK IO Communication clock
(x=1~6)
USARTx_RTS O Request to send a signal
USARTx_CTS I Clear Send Signal
SPIx_MISO IO Primary input/secondary output data transfer pin
SPIx_MOSI IO Primary output/slave input data transfer pin
SPIx
SPIx_SCK IO Transmission clock
(x=1~3)
SPIx_NSS0 IO Select input/output pin from machine
SPIx_NSSy (y=1~3) O Slave select output pin
QSPI_IOx (x=0~3) IO Data line
QSPI QSPI_SCK O clock output
QSPI_NSS O Slave selection
I2Cx I2Cx_SCL IO Clock line
(x=1~2) I2Cx_SDA IO Data line
MCANx MCANx_TX O Send data
(x=1~2) MCANx_RX I Receiving data
VCOUT1 O CMP1 result output
CMP
VCOUT O CMP1~4 result logic or output
CMPx_INPy (x=1~4, y=1~4) I CMPx positive analog input
CMPx_INM2 (x=1~4) I CMPx negative analog input
CMP1234_INM1 I CMP1~4 negative terminal analog input
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ADTRG1 I ADC1 AD conversion external start source
ADC
ADC123_INx (x=6~9) I ADC1/2/3 share external analog input port
ADC ADC12_INx (x=4~5, 10~11) I ADC1/2 share external analog input port
ADC1_INx (x=0~3, 12~15) I ADC1 external analog input port
ADC3_INx (x=0~5, 10, 11) I ADC3 external analog input port
DAC DAC_OUTy (y=1, 2) O DAC analog output
EXMC_CLK IO
EXMC_OE O
EXMC_WE O
EXMC_ALE O
EXMC_BAA O For details, refer to Table 30-4 in Chapter EXMC of the
EXMC
EXMC_ADV O reference manual.
EXMC_CEx (x=0, 4~5) O

EXMC_RB0 I
EXMC_ADDx (x=16~20) IO
EXMC_DATAx (x=0~15) IO
PLUx_INy (x=0~3, y=A~D) I Input of logic operation unit PLU
PLU
PLUx_OUT (x=0~3) O The output of the logical operation unit PLU
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2.4 Pin Usage Instructions

Table 2-6 Pin Usage Description
Pin Name Usage Notes

Power supply, connected to a voltage of 1.8V~3.6V, and a decoupling capacitor
VCC
connected to the VSS pin nearby (refer to [Electrical Characteristics (ECs)])
VSS Source ground, connected to 0V
For the core voltage, connect a capacitor to the VSS pin nearby to stabilize the core
VCAP_1
voltage (refer to [Electrical Characteristics (ECs)])
Analog power supply, supplying power to analog modules, connected to the same
AVCC voltage as VCC (refer to [Electrical Characteristics (ECs)])
When not using the analog module, please short it with VCC
Analog power ground, which supplies power to the analog modules and connects to the
AVSS same voltage as VSS (refer to [Electrical Characteristics (ECs)])
When not using the analog module, please short it with VSS
Analog input. When the reset pin (NRST) is released (from low level to high level), this
PB11/ MD pin must be fixed at low level. It is recommended to connect a resistor (4.7KΩ) to VSS
(pull-down)
NRST Reset pin, low effective. Resistance to VCC when not in use (pull-up)
General pin. When used as an input function, the input voltage of pins that support 5V
tolerance should not exceed 5V and internal pull-up/pull-down is prohibited, and the
Pxy (x=A~E, H, y=0~15) input voltage of pins that do not support 5V tolerance should not exceed VCC. When
used as an analog input, the analog voltage should not exceed VREFH/AVCC
Hang out when not in use or connect to VCC (pull-up)/VSS (pull-down)
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3 Electrical Characteristics (ECs)
3.1 Parameter Conditions

All voltages are referenced to VSS unless otherwise noted.
3.1.1 Minimum and Maximum
Unless otherwise specified, the minimum and maximum values of all devices are guaranteed by
design or performance tests at worst ambient temperature, supply voltage and clock frequency.
3.1.2 Typical Value
Unless otherwise specified, typical data are obtained through design or characteristic test analysis
under the conditions of TA=25°C and VCC=3.3V.
3.1.3 Typical Curve
Unless otherwise specified, all typical curves are not tested for design reference only.
3.1.4 Load Capacitance
The load conditions used to measure the pin parameters are shown in Figure 3-1 (left).
3.1.5 Pin Input Voltage
Figure 3-1 (right) shows how to measure the input voltage at the pins of the device.
MCU pin MCU pin

Vin
Figure 3-1 Pin loading condition (left) and input voltage measurement (right)
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3.1.6 Power Supply Scheme
Input
Level shifter
GPIO IO Core logic
logic circuitry
Output (CPU,
digital
peripherals
, and RAM)
VCAP_1
0.1μF or
0.22μF
VCCx Voltage
regulator
X x 0.1μF+
1 x 4.7μF Flash
VSSx
RTC
Clock module:
RC,
PLL,...
NRST Reset
control
AVCC
0.1μF
+1μF Simulation
ADC
CMP
DAC
AVSS
Figure 3-2 Power Scheme
1. A 4.7µF ceramic capacitor must be connected to one of the VCC pins.

2. AVSS=VSS.
3. Each supply pair (e.g. VCC/VSS, AVCC/AVSS...) must be decoupled with filter ceramic capacitors
as mentioned above. These capacitors must be placed as close as possible to or under the
power pair pins on the underside of the PCB to ensure proper device operation. It is not
recommended to remove the filter capacitor to reduce PCB size or cost, it may cause the device
not to work properly.
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3.1.7 Current Consumption Measurement
ICC
VCC
AVCC
Figure 3-3 Current consumption measurement scheme
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3.2 Absolute Maximum Ratings

Permanent damage to the device may result if loads exceeding the Absolute Maximum Ratings
listed in Table 3-1, Table 3-2, and Table 3-3 are applied to the device. These values are just rated
stresses and do not mean that the device works properly under these conditions. Long-term
operation may affect the reliability.
Table 3-1 Voltage Characteristics
Symbol Item Minimum Value Maximum Value Unit

External main supply voltage
VCC-VSS -0.3 4.0
(including AVCC, VCC) (1) V
VIN Input voltage on pin (2) VSS–0.3 VCC+4.0 (Maximum 5.8V)
VESD(HBM) Electrostatic discharge voltage Please refer to [Electrical Sensitivity] -
1. All main power (VCC, AVCC) and ground (VSS, AVSS) pins must always be connected to an
external power supply, within the limits allowed.
2. The maximum value of VIN must always be followed. For information on the maximum
allowable injected current values, See Table 3-2.
Table 3-2 Current Characteristics
Symbol Item Maximum Value Unit

∑IVCC Total current flowing into all VCCX power lines (source current) (1) 240
∑IVSS Total current flowing (sinking) out of all VSSX ground wires(1) -240
IVCC Maximum current into each VCCX supply line (source current)(1) 100
IVSS Maximum Current Out of Each VSSX Ground Line (Sink)(1) -100
mA
Output current sink for any I/O and control pin 20
IIO
Output current source for any I/O and control pin -20
Total output sink current on all I/O and control pins (2) 120
∑IIO
Total output source current on all I/O and control pins (2) -120
1. All main power (VCC, AVCC) and ground (VSS, AVSS) pins must always be connected to an
external power supply, within the limits allowed.
2. This total output current must be properly distributed in all power domains; this total output
current applies to 64 PINs and above packages, for 48 PINs packages, the maximum total
output current is ±80mA, and for 32 PINs packages, the maximum total output current is
±80mA 40mA.
Table 3-3 Thermal Characteristics
Symbol Item Numerical Value Unit

TSTG Storage temperature range –65~150 °C
TJ Maximum Junction Temperature Range -40~125 °C
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3.3 Operating Conditions
3.3.1 General Working Conditions
Table 3-4 General Operating Conditions
Minimum Typical Maximum

Symbol Parameter Conditions Unit
Value Value Value
High Speed Mode (1)
PWRC2.DVS=0x11 - - 200
Internal AHB clock PWRC3.DDAS=0xF
fHCLK MHz
frequency Super low speed mode
PWRC2.DVS=0x10 - - 8
PWRC3.DDAS=0x0
Standard operating
VCC - 1.8 - 3.6 V
voltage
VAVCC Analog working voltage - 1.8 - 3.6
2V≤VCC≤3.6V
–0.3 - 5.5 V
Input voltage on 5V 2V≤VAVCC≤3.6V
VIN
tolerant pin (2) VCC<2V
–0.3 - 5.2
VAVCC<2V
1. Guarantee of mass production test.
2. To keep the voltage above VCC+0.3V, the internal pull-up/pull-down resistors must be disabled.
3.3.2 Operating Conditions During Power Up/ Down
TA is subject to general working conditions.
Table 3-5 Operating conditions at power-up/power-down
Minimum Maximum
Symbol Parameter Unit
Value Value
VCC rise time rate 20 20000
tVCC µs/V
Reset and Power Control Block Features 20 20000
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3.3.3 Reset and Power Control Block Features
Table 3-6 Reset and Power Control Module Characteristics

Value Value Value
ICG1.BOR_LEV[1:0]=00(1) 1.70 1.90 2.10 V
High speed
mode ICG1.BOR_LEV[1:0]=01 1.80 2.00 2.20 V
Monitoring
VBOR Super low
Voltage of BOR ICG1.BOR_LEV[1:0]=10 1.90 2.10 2.30 V
speed
mode
ICG1.BOR_LEV[1:0]=11(1) 2.10 2.30 2.50 V
PVD1LVL[2:0]=000(1) 1.80 2.00 2.20 V
PVD1LVL[2:0]=001 1.90 2.10 2.30 V
PVD1LVL[2:0]=010 2.10 2.30 2.50 V
High speed
mode PVD1LVL[2:0]=011 2.33 2.55 2.77 V
PVD1 Monitoring
VPVD1 Super low
Voltage (3) PVD1LVL[2:0]=100 2.43 2.65 2.87 V
speed
mode
PVD1LVL[2:0]=101 2.53 2.75 2.97 V
PVD1LVL[2:0]=110 2.63 2.85 3.07 V
PVD1LVL[2:0]=111(1) 2.73 2.95 3.17 V
PVD2LVL[2:0]=000(1) 1.90 2.10 2.30 V
PVD2LVL[2:0]=001 2.10 2.30 2.50 V
PVD2LVL[2:0]=010 2.33 2.55 2.77 V
High speed
mode PVD2LVL[2:0]=011 2.43 2.65 2.87 V
PVD2 Monitoring
VPVD2 Super low
Voltage(3) PVD2LVL[2:0]=100 2.53 2.75 2.97 V
speed
mode
PVD2LVL[2:0]=101 2.63 2.85 3.07 V
PVD2LVL[2:0]=110(1) 2.73 2.95 3.17 V
PVD2LVL[2:0]=111(2) 0.90 1.10 1.30 V
Hysteresis for
Vpvdhyst - - 100 - mV
PVD1/2(4)
Power-on/power- Rising edge VPOR 1.56 1.68 1.80 V
VPOR(1)
off reset threshold Falling edge VPOR 1.52 1.64 1.76 V
VPORhyst POR Hysteresis - - 40 - mV
Inrush current at
regulator power-
IRUSH - - 100 150 mA
up (POR or wake-
up from standby)
NRST reset
TNRST - 10 - - μs
minimum width
PVD1 reset
TIPVD1 - 300 380 460 μs
release time
PVD2 reset
TIPVD2 - 300 380 460 μs
release time
NRST reset
TINRST - 25 35 50 μs
release time
TRIPT Internal reset time - 140 160 200 μs
BOR reset release
TRSTBOR - 440 520 610 μs
time
Power-on reset
TRSTPOR - - 2500 3000 μs
release time
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2. When PVD2LVDL[2:0]=111, the comparison voltage is the external input comparison voltage
of PVD2EXINP pin.
3. The PVD1 monitoring voltage is the monitoring voltage when the VCC voltage drops; when
PVD2LVL[2:0] is set to 111, the PVD2 monitoring voltage is the monitoring voltage when the
PVDEXINP voltage drops, and when PVD2LVD[2:0] is set to a value other than 111, PVD2 The
monitor voltage is a monitor voltage when the VCC voltage drops.
4. The hysteresis of PVD1/2 is the difference between the monitored voltage when VCC is rising
and the monitored voltage when VCC is falling.
PVD1 monitoring voltage when VCC rises = Vpvd1+Vpvdhyst.
PVD2 monitoring voltage when VCC rises = Vpvd2+Vpvdhyst.
3.3.4 Supply Current Characteristics
The current consumption is affected by several parameters and factors, including operating voltage,
ambient temperature, I/O pin load, device software configuration, operating frequency, I/O pin
switch rate, program position in memory and running code.
The method for measuring the current consumption is described in Figure 3-3. The measured values
of current consumption in various modes described in this section are obtained under laboratory
conditions through a set of test codes running on FLASH.
The specific conditions are as follows:
1) All I/O pins are in high-impedance mode (no load).

2) Clock frequency selection high-speed mode fHCLK=200MHz/ 100MHz/ 24MHz and ultra-low-
speed mode fHCLK=8MHz/ 1MHz.
3) The power consumption mode is divided into: normal working mode ICC_RUN, sleep mode
ICC_SLEEP, stop mode ICC_STP, power down mode ICC_PD, Dhrystone working mode
ICC_DHRYSTONE.
4) For peripheral clock ON/OFF, please refer to the description of specific current conditions.
5) In high-speed mode fHCLK=200MHz/ 100MHz, the PLL is on.
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Table 3-7 High Speed Mode Current Consumption 1
Product Specifications
Pattern Parameter Symbol Conditions Ta(°C) Minimum Typical Unit
Max (2)
Value value (1)
while(1), all module
-40 - 23 - mA
clock OFF(3)
ICC_RUN
-40 - 37 - mA
clock ON(3)
ICC_DHRYS CACHE OFF -40 - 24 - mA

TONE CACHE ON -40 - 24 - mA
All module clock
-40 - 14 - mA
OFF(3)
ICC_SLEEP
All module clock
-40 - 28 - mA
ON(3)
25 - 23 - mA
clock OFF(3)
ICC_RUN
25 - 37 - mA
clock ON(3)
ICC_DHRYS CACHE OFF 25 - 24 - mA

TONE CACHE ON 25 - 24 - mA
All module clock
25 - 14 - mA
OFF(3)
ICC_SLEEP
All module clock
High 25 - 28 - mA
fHCLK= ON(3)
speed
200MHz While (1), full-
mode 85 - - 29 mA
module clock OFF
ICC_RUN
While (1), full
85 - - 43 mA
module clock ON
ICC_DHRYS CACHE OFF 85 - - 30 mA

TONE CACHE ON 85 - - 30 mA
Full module clock
85 - - 20 mA
OFF
ICC_SLEEP
Full module clock
85 - - 34 mA
ON
105 - - 33 mA
clock OFF(3)
ICC_RUN
105 - - 48 mA
clock ON(3)
ICC_DHRYS CACHE OFF 105 - - 34 mA

TONE CACHE ON 105 - - 34 mA
All module clock
105 - - 24 mA
OFF(3)
ICC_SLEEP
All module clock
105 - - 39 mA
ON(3)
1. Typical voltage condition VCC=3.3V.
2. Maximum voltage condition VCC=1.8~3.6V.
3. Mass production guarantee.
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Table 3-8 High Speed Mode Current Consumption2
Pattern Parameter Symbol Conditions Ta(°C) Minimum Typical Max Unit
Value value (1) (2)
While (1), full-

-40 - 12 - mA
module clock OFF
ICC_RUN
While (1), full
-40 - 20 - mA
module clock ON
ICC_DHRYSTON CACHE OFF -40 - 13 - mA

E CACHE ON -40 - 13 - mA
Full module clock
-40 - 8 - mA
OFF
ICC_SLEEP
Full module clock
-40 - 15 - mA
ON
While (1), full-
25 - 13 - mA
module clock OFF
ICC_RUN
While (1), full
25 - 20 - mA
module clock ON
ICC_DHRYSTON CACHE OFF 25 - 14 - mA

E CACHE ON 25 - 14 - mA
Full module clock
25 - 8 - mA
OFF
ICC_SLEEP
Full module clock
High 25 - 16 - mA
fHCLK= ON
speed
mode 85 - - 19 mA
module clock OFF
ICC_RUN
While (1), full
85 - - 27 mA
module clock ON
ICC_DHRYSTON CACHE OFF 85 - - 20 mA

E CACHE ON 85 - - 20 mA
Full module clock
85 - - 14 mA
OFF
ICC_SLEEP
Full module clock
85 - - 22 mA
ON
While (1), full-
105 - - 23 mA
module clock OFF
ICC_RUN
While (1), full
105 - - 31 mA
module clock ON
ICC_DHRYSTON CACHE OFF 105 - - 24 mA

E CACHE ON 105 - - 24 mA
Full module clock
105 - - 18 mA
OFF
ICC_SLEEP
Full module clock
105 - - 27 mA
ON
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Table 3-9 High Speed Mode Current Consumption3
Value value (1) (2)
While (1), full-

module clock -40 - 4 - mA
ICC_RUN OFF
While (1), full
-40 - 8 - mA
module clock ON
ICC_DHRYSTON
CACHE OFF -40 - 5 - mA
E
Full module
-40 - 3 - mA
clock OFF
ICC_SLEEP
Full module
-40 - 6 - mA
clock ON
While (1), full-
module clock 25 - 4 - mA
ICC_RUN OFF
While (1), full
25 - 8 - mA
module clock ON
ICC_DHRYSTON
CACHE OFF 25 - 5 - mA
E
Full module
25 - 3 - mA
clock OFF
ICC_SLEEP
Full module
High 25 - 7 - mA
fHCLK= clock ON
speed
mode
module clock 85 - - 10 mA
ICC_RUN OFF
While (1), full
85 - - 14 mA
module clock ON
ICC_DHRYSTON
CACHE OFF 85 - - 12 mA
E
Full module
85 - - 9 mA
clock OFF
ICC_SLEEP
Full module
85 - - 13 mA
clock ON
While (1), full-
module clock 105 - - 15 mA
ICC_RUN OFF
While (1), full
105 - - 19 mA
module clock ON
ICC_DHRYSTON
E
Full module
105 - - 14 mA
clock OFF
ICC_SLEEP
Full module
105 - - 18 mA
clock ON
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Table 3-10 Ultra Low Speed Mode Current Consumption1
Value value (1) (2)
While (1), full-

-40 - 2 - mA
module clock OFF
ICC_RUN
While (1), full
-40 - 4 - mA
module clock ON
ICC_DHRYSTON
CACHE OFF -40 - 2.2 - mA
E
Full module clock
-40 - 1 - mA
OFF
ICC_SLEEP
Full module clock
-40 - 3 - mA
ON
While (1), full-
25 - 2 - mA
module clock OFF
ICC_RUN
While (1), full
25 - 4 - mA
module clock ON
ICC_DHRYSTON
CACHE OFF 25 - 2.3 - mA
E
Full module clock
25 - 1 - mA
OFF
ICC_SLEEP
Full module clock
Ultra low 25 - 3 - mA
fHCLK= ON
speed
Pattern 85 - - 5 mA
module clock OFF
ICC_RUN
While (1), full
85 - - 7 mA
module clock ON
ICC_DHRYSTON
CACHE OFF 85 - - 5.5 mA
E
Full module clock
85 - - 4.6 mA
OFF
ICC_SLEEP
Full module clock
85 - - 6.7 mA
ON
While (1), full-
105 - - 8 mA
module clock OFF
ICC_RUN
While (1), full
105 - - 10 mA
module clock ON
ICC_DHRYSTON
E
Full module clock
105 - - 7.5 mA
OFF
ICC_SLEEP
Full module clock
105 - - 9.5 mA
ON
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Table 3-11 Ultra Low Speed Mode Current Consumption2
Value value (1) (2)
While (1), full-

-40 - 1 - mA
module clock OFF
ICC_RUN
While (1), full
-40 - 2.5 - mA
module clock ON
ICC_DHRYSTON
CACHE OFF -40 - 1 - mA
E
Full module clock
-40 - 0.5 - mA
OFF
ICC_SLEEP
Full module clock
-40 - 2 - mA
ON
While (1), full-
25 - 1 - mA
module clock OFF
ICC_RUN
While (1), full
25 - 2.5 - mA
module clock ON
ICC_DHRYSTON
CACHE OFF 25 - 1 - mA
E
Full module clock
25 - 0.7 - mA
OFF
ICC_SLEEP
Super Full module clock
25 - 2.2 - mA
low fHCLK= ON
speed 1MHz While (1), full-
85 - - 4.5 mA
mode module clock OFF
ICC_RUN
While (1), full
85 - - 6 mA
module clock ON
ICC_DHRYSTON
CACHE OFF 85 - - 4.7 mA
E
Full module clock
85 - - 4.3 mA
OFF
ICC_SLEEP
Full module clock
85 - - 5.9 mA
ON
While (1), full-
105 - - 7.5 mA
module clock OFF
ICC_RUN
While (1), full
105 - - 9 mA
module clock ON
ICC_DHRYSTON
E
Full module clock
105 - - 7 mA
OFF
ICC_SLEEP
Full module clock
105 - - 8.8 mA
ON
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Table 3-12 Low Power Mode Current Consumption
Value value (1) (2)
PWC_PWRC1.STPDAS=0
-40 - 188 - μA
0(3)
PWC_PWRC1.STPDAS=1
-40 - 45 - μA
1(3)
PWC_PWRC1.STPDAS=0
25 - 455 - μA
0(3)
PWC_PWRC1.STPDAS=1
25 - 304 - μA
Stop 1(3)
- ICC_STP
mode PWC_PWRC1.STPDAS=0
85 - - 3.9 mA
0
PWC_PWRC1.STPDAS=1
85 - - 3.6 mA
1
PWC_PWRC1.STPDAS=0
105 - - 6.5 mA
0(3)
PWC_PWRC1.STPDAS=1
105 - - 6.2 mA
1(3)
Power Down Mode 1(3) -40 - 10 - μA
Power Down Mode 2(3) -40 - 4 - μA
Power Down Mode 3(3) -40 - 1.7 - μA
Power Down Mode 4(3) -40 - 1.7 - μA

Power-down mode 2+
-40 - 6 - μA
XTAL32+ RTC
Power-down mode 2+
-40 - 9 - μA
LRC+ RTC(3)
Power Down Mode 1(3) 25 - 11 - μA
Power Down Mode 2(3) 25 - 4.5 - μA

Power-down mode 2+
25 - 7 - μA
XTAL32+ RTC(3)
Power
Power-down mode 2+
Down - ICC_PD 25 - 9 - μA
LRC+ RTC(3)
Mode
Power down mode 1 85 - - 20 μA

Power-down mode 2+
85 - - 20 μA
XTAL32+ RTC
Power down mode 2+
85 - - 20 μA
LRC+ RTC
Power Down Mode 1(3) 105 - - 31 μA

Power-down mode 2+
105 - - 31 μA
XTAL32+ RTC
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Value value (1) (2)
Power-down mode 2+
105 - - 31 μA
LRC+ RTC(3)

Table 3-13 Analog Module Current Consumption
Conditions
Item Parameter Symbol Ta(°C) Minimum Typical Maximum Unit
(VCC=AVCC=3.3V)
Value Value Value
XTAL Oscillation
Mode Large Drive 25 - 1.8 - mA
24MHz
Drive 16 MHz in
25 - 1.0 - mA
Oscillation Mode
Oscillating
mode small drive 10 25 - 0.8 - mA
MHz
Oscillating
mode ultra-small 25 - 0.6 - mA
drive 8 MHz
Module ICC_MOD XTAL 32.768kHz 25 - 1.1 - μA

-
current ULE HRC 25 - 0.3 - mA
PLLH
25 - 3.5 - mA
(VCO=1200MHz)
PLLH (VCO=600MHz) 25 - 1.8 - mA
ADC 25 - 1.3 - mA
Amplifier
25 - 0.8 - mA
allows
DAC
Amplifier
25 - 0.2 - mA
prohibited
CMP 25 - 0.3 - mA
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3.3.5 Low Power Mode Wake-Up Timing
The wake-up time is measured from the wake-up event trigger to the first instruction executed by
the CPU:
◾ For stop or sleep mode: Wakeup event is WFE.

◾ WKUP pins are used to wake up from standby, stop, and sleep modes. All the timings are
measured at ambient temperature and VCC=3.3V.
Table 3-14 Low power mode wake-up time
Typical Maximum
Value Value
Wakeup from
TSTOP System clock is MRC 8 15
stop mode
Wake up from The total capacitance of VCAP_1 is 0.094μF or 0.1μF 25 35
TPD1(1) power-down
mode 1 The total capacitance of VCAP_1 is 0.2μF or 0.22μF 30 40
TPD2(1) power-down
mode 2 The total capacitance of VCAP_1 is 0.2μF or 0.22μF 75 85 μs
TPD3(1) power-down
TPD4(1) power-down
1. The total VCAP_1 capacity of the chip must match the assignment of the PWC_PWRC1.PDTS
bits. When the total capacity of VCAP_1 is 0.2μF or 0.22μF, it is necessary to ensure that the
PWC_PWRC1.PDTS bit is cleared before entering power-down mode. When the total capacity of
VCAP_1 is 0.094μF or 0.1μF, it is necessary to ensure that the PWC_PWRC1.PDTS bit is set
before entering power-down mode.
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3.3.6 External Timer Characteristic
3.3.6.1 High-speed External Subscriber Clock Generated By External Source
In bypass mode, the XTAL oscillator is turned off and the input pins are standard I/Os. The external
clock signal must consider the I/O static characteristics.
Table 3-15 High-Speed External User Clock Characteristics

Value Value Value
fXTAL_EXT User external timer frequency 1 - 25 MHz
XTAL_EXT input pin high level
VIH_XTAL 0.8×VCC - VCC
voltage V
-
VIL_XTAL XTAL_EXT input pin low level voltage VSS - 0.2×VCC
tr(XTAL)
XTAL_EXT rise or fall time - - 5 ns
tf(XTAL)
Duty(XTAL) Duty ratio - 40 - 60 %
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3.3.6.2 High-Speed External Clock from Crystal/Ceramic Resonator
The high-speed external (XTAL) clock can be generated using a 4 to 25MHz crystal/ceramic
resonator. In applications, the resonator and load capacitance must be as close to the oscillator pin
as possible to minimize output distortion and vibration stabilization time. For more information on
the resonator characteristics (frequency, encapsulation, accuracy, etc.), please consult the crystal
resonator manufacturer.
Table 3-16 XTAL 4-25MHz Oscillator Characteristics

Value Value Value
fXTAL_IN Oscillator frequency - 4 - 25 MHz
RF(1) Feedback resistance - - 300 - kΩ
AXTAL(2) XTAL accuracy - -500 - 500 ppm
Gmmax - Wake up 4 - - mA/V
VCC is stable, crystal
- - 2.0 ms
oscillator=8MHz
tSU(XTAL)(3) Start time
VCC is stable, crystal
- - 4.0 ms
oscillator=4MHz
2. This parameter depends on the resonator used in the application system.
3. tSU(XTAL) is the start-up time, that is, the time from when XTAL is enabled by software until a
stable oscillation frequency is obtained. This value is measured based on the standard crystal
resonator and may vary significantly with the crystal resonator manufacturer.
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors between 5pF
and 25pF (typical) designed for high-frequency applications to meet the crystal or resonator
requirements (see figure below). CL1 and CL2 are usually the same size. The load capacitance
specified by the crystal oscillator manufacturer is usually a product family combination of CL1 and
CL2. When specifying CL1 and CL2, the capacitance of the PCB and MCU pins must be taken into
account (the capacitance between the pin and the board can be roughly estimated as 10pF).
Resonators with integrated capacitors
CL1 XTAL_IN FXTAL
Gain of
Resonator RF bias
control
CL2 XTAL_OUT
REXT(1)
Figure 3-4 Typical Application Using 8 MHz Crystal
1. The value of REXT depends on the crystal oscillator characteristics.
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3.3.6.3 Low-speed external clock generated by crystal oscillator/ceramic resonator
Low-speed external clocks can be produced using a oscillator composed of 32.768 kHz crystal
oscillator/ceramic resonator. In applications, the resonator and load capacitance must be as close
to the oscillator pin as possible to minimize output distortion and vibration stabilization time. For
more information on the resonator characteristics (frequency, encapsulation, accuracy, etc.),
please consult the crystal resonator manufacturer.
Table 3-17 XTAL32 Oscillator Features
Specifications
Symbol Parameter Conditions Minimum Typical Maximum Unit
Value Value Value
FXTAL32 Frequency - - 32.768 - kHz
RF(1) Feedback resistance - - 15 - MΩ
IDD_XTAL32 Power consumption XTAL32DRV[2:0]=000 - 0.8 - μA
AXTAL32(2) XTAL32 precision - -500 - 500 ppm
Gmmax Gm - - - 5.6 μA/V
TSUXTAL32 Start time (3) VCC Stabilization - 2 - s
1. Mass production test guarantee.
2. This parameter depends on the resonator used in the application system.
3. TSUXTAL32 is the start-up time, which starts with the software enabling XTAL 32 to measure until
a stable oscillation frequency of 32.768 kHz is obtained. This value is measured based on the
standard crystal resonator and may vary significantly with the crystal resonator manufacturer.
For CL1 and CL2, high quality external ceramic capacitors between 5pF and 18pF (typical) are
recommended (see figure below). CL1 and CL2 are usually the same size. The load capacitance
specified by the crystal oscillator manufacturer is usually a product family combination of CL1 and
CL2. When specifying CL1 and CL2, the capacitance of the PCB and MCU pins must be taken into
account (the pin capacitance can be roughly estimated as 5pF). If CL1 and CL2 are greater than 18pF,
it is recommended to set XTAL32DRV[2:0]=001 (large drive, the typical value of power consumption
increases by 0.2μA).
Resonators with integrated capacitors
CL1 XTAL32_OUT FXTAL32
Gain of
Resonator RF bias
control
CL2 XTAL32_IN
Figure 3-5 Typical application using 32.768kHz crystal oscillator
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3.3.7 Internal Timer Characteristics
3.3.7.1 Internal High Speed (HRC) Oscillator
Table 3-18 HRC Oscillator Characteristics

Value Value Value
Pattern 1 - 16 -
Frequency(1) MHz
Pattern 2 - 20 -
fHRC User Adjustment Scale - - - 0.2 %
TA=-40 to 105℃ -2 - 2 %
Frequency Accuracy(1)
TA=-20 to 105℃ -1.5 - 1.5 %
HRC oscillator oscillation stabilization
tst(HRC)(1) - - - 15 µs
time
3.3.7.2 Internal Medium Speed (MRC) Oscillator
Table 3-19 MRC Oscillator Characteristics

Value Value Value
fMRC(1) Frequency 7.2(1) 8 8.8(1) MHz
tst(MRC)(1) MRC Oscillator Settling Time - - 3 µs
3.3.7.3 Internal Low Speed (LRC) Oscillator
Table 3-20 LRC Oscillator Characteristics

Value Value Value
fLRC(1) Frequency 27.853(1) 32.768 37.683(1) kHz
tst(LRC)(1) LRC Oscillator Settling Time - - 36 µs
3.3.7.4 SWDT Dedicated Internal Low-Speed (SWDTLRC) Oscillator
Table 3-21 SWDTLRC Oscillator Characteristics

Value Value Value
fSWDTLRC(1) Frequency 9(1) 10 11(1) kHz
SWDTLRC oscillator stabilization
tst(SWDTLRC)(1) - - 57.1 µs
time
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3.3.8 PLL Characteristic
Table 3-22 PLLH Main Performance Indicators

Value Value Value
Input clock for PLL phase
fPLL_IN - 4 - 25 MHz
frequency detector (PFD)(1)
The output clock of the PLL
fPLL_OUT - 37.5 - 600 MHz
multiplier
The output of the PLL voltage-
fVCO_OUT - 600 - 1200 MHz
controlled oscillator (VCO)
PLL PFD input clock is
Period jitter 8MHz, system clock is - ±70 -
120MHz, peak-to-peak
JitterPLL ps
PLL PFD input clock is
Jitter between adjacent cycles 8MHz, system clock is - ±100 -
120MHz, peak-to-peak
tLOCK PLL lock time - - 80 120 µs

1. A higher input clock is recommended for good jitter characteristics.
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3.3.9 Memory (Flash) Characteristics
Flash memory was erased when the device was delivered to the customer.
Table 3-23 Flash Features

Value Value Value
Read mode, VCC=1.8 V~3.6V - - 5
Supply Programming mode, VCC=1.8 V~3.6V - - 10

IVCC mA
current Block erase mode, VCC=1.8 V~3.6V - - 10
Full erase mode, VCC=1.8 V~3.6V - - 10
Table 3-24 Flash Program Erase Time

Value Value Value
Word
Single
programming 43+2×Thclk(2) 48+4×Thclk(2) 53+6×Thclk(2) µs
programming mode
time
Tprog(1)
Word
Continuous
programming 12+2×Thclk(2) 14+4×Thclk(2) 16+6×Thclk(2) µs
programming mode
time
Terase(1) Block erase time - 16+2×Thclk(2) 18+4×Thclk(2) 20+6×Thclk(2) ms
Tmas(1) Full erase time - 16+2×Thclk(2) 18+4×Thclk(2) 20+6×Thclk(2) ms
2. Thclk is one cycle of CPU clock.
Table 3-25 Flash Memory Erasability and Data Retention Period
Numerical
Value
Minimum
Value
Programming, number of
Nend TA=85℃ 10 Thousands of times
block erases
Nend Number of whole erases TA=85℃ 10 Thousands of times
Tret Data retention period TA=85℃, after 10 kcycles 10 Year
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3.3.10 Electrical Sensitivity
The chip is tested differently (ESD, LU) using specific measurement methods to determine its
performance in terms of electrical susceptibility.
3.3.10.1 Electrostatic Discharge (ESD)
Electrostatic discharge is applied to the pins of each sample according to each pin combination.
This test complies with the JESD22-A114/ C101 standard.
Table 3-26 ESD Characteristics
Maximum
Value
TA=+25°C, complies with JESD22-A114
VESD(HBM) Electrostatic discharge voltage 4000
standard
V
Electrostatic discharge voltage TA=+25°C, complies with JESD22-C101
VESD(CDM) 1000
(charging equipment model) standard
3.3.10.2 Static Latch-up
To assess static Latch-up performance, two complementary static Latch-up tests are required on
the chip:
◾ Over-voltage applied to each power supply and analog input pin

◾ Apply current injection to other input, output, and configurable I/O pins
These tests comply with the EIA/JESD 78A IC Latch-up standard.
Table 3-27 Static Latch-up Features
Maximum
Value
TA=+105°C, complies with JESD78A
LU Static Latch-up 200 mA
standard
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3.3.11 I/O Port Characteristics
General input/ output characteristics
Table 3-28 I/O Static Characteristics
Minimum Typical
Symbol Parameter Conditions Max. Unit
Value Value
VIL(1) Schmitt input low level 1.8≤VCC≤3.6 - - 0.3VCC V
VIH(1) Schmitt input high level 1.8≤VCC≤3.6 0.7VCC - - V
VHYS Schmitt input hysteresis 1.8≤VCC≤3.6 0.1 0.2 - V
VIL(1) CMOS Input Low Level 1.8≤VCC≤3.6 - - 0.3VCC V
VIH(1) CMOS input high level 1.8≤VCC≤3.6 0.7VCC - - V
CMOS/Schmitt compatible TTL
TTL_VIL(1) 2.7≤VCC≤3.6 - - 0.8 V
Input low level
CMOS/Schmitt compatible TTL
TTL_VIH(1) 2.7≤VCC≤3.6 2.2 - - V
Input high level
2.7≤VCC≤3.6 - - 40 MHz
Schmitt input maximum frequency
1.8≤VCC≤2.7 - - 20 MHz
Fmax(in)
2.7≤VCC≤3.6 - - 80 MHz
CMOS input maximum frequency
1.8≤VCC≤2.7 - - 40 MHz
VSS≤VIN≤VCC - - 1 μA
ILKG(1) I/O input leakage current
VIN=5.5V(2) - - 10 μA
Weak pull-up
VIN=VSS
RPU(1)(2) Equivalent - 10 30 150 KΩ
1.8≤VCC≤3.6
resistance
Weak pull-down
VIN=Vcc
RPD(1)(2) Equivalent - 5 20 50 KΩ
1.8≤VCC≤3.6
resistance
PB11/MD - - 10 - pF
I/O pin
CIO Input pins other
capacitance - - 5 - pF
than the above
2. To keep the voltage above VCC+0.3V, the internal pull-up/ pull-down resistors must be disabled.
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Output current
GPIO (General Purpose Input/ Output) can source or sink current up to ±20mA.
The output voltage

Table 3-29 Output Voltage Characteristics
Driver Minimum Typical Maximum

Settings Value Value Value
Low level
VOL(1)(2) - - 0.6
output
IIO=±1.5mA, 1.8≤VCC<2.7
High level
VOH(1)(3) VCC-0.6 - -
output
Low level
VOL(1)(2) - - 0.6
output
Low drive IIO=±3mA, 2.7≤VCC≤3.6
High level
VOH(1)(3) VCC-0.6 - -
output
Low level
VOL(1)(2) - - 1.3
output
IIO=±6mA, 2.7≤VCC≤3.6
High level
VOH(1)(3) VCC-1.3 - -
output
Low level
VOL(1)(2) - - 0.4
output
IIO=±3mA, 1.8≤VCC<2.7
High level
VOH(1)(3) VCC-0.4 - -
output
Low level
VOL(1)(2) - - 0.4
medium output
IIO=±5mA, 2.7≤VCC≤3.6
drive High level
VOH(1)(3) VCC-0.4 - -
output
V
Low level
VOL(1)(2) - - 1.3
output
IIO=±12mA, 2.7≤VCC≤3.6
High level
VOH(1)(3) VCC-1.3 - -
output
Low level
VOL(1)(2) - - 0.4
output
IIO=±6mA, 1.8≤VCC<2.7
High level
VOH(1)(3) VCC-0.4 - -
output
Low level
VOL(1)(2) - - 0.4
output
IIO=±8mA, 2.7≤VCC≤3.6
High level
VOH(1)(3) VCC-0.4 - -
output
High drive
Low level
VOL(1)(2) - - 1.3
output
IIO=±20mA, 2.7 ≤VCC≤3.6
High level
VOH(1)(3) VCC-1.3 - -
output
Low level
VOL(1)(2) - - 0.88
output
IIO=±20mA, 2.97 ≤VCC≤3.6
High level
VOH(1)(3) VCC-0.88 - -
output
2. The IIO sink current of the device must always take into account the absolute maximum ratings
specified in Table 3-2. The sum of IIO (I/O ports and control pins) must not exceed IVSS.
3. The device's IIO source current must always adhere to the absolute maximum ratings listed in
Table 3-2, and the sum of IIO (I/O ports and control pins) must not exceed IVCC.
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Input/ output AC Characteristics
Table 3-30 I/O AC Characteristics
Driver Minimum Typical Maximum

Symbol Parameter Condition(3) Unit
Settings Value Value Value
CL=30pF, VCC≥2.7V - - 20
Maximum CL=30pF, VCC≥1.8V - - 10

fmax(IO)out MHz
frequency(1) CL=10pF, VCC≥2.7V - - 40
CL=10pF, VCC≥1.8V - - 20
Low drive
CL=30pF, VCC≥2.7V - - 15
Output high to
low level drop CL=30pF, VCC≥1.8V - - 25
tf(IO)out
time and output ns
tr(IO)out CL=10pF, VCC≥2.7V - - 7.5
low to high level
rise time
CL=10pF, VCC≥1.8V - - 15
CL=30pF, VCC≥2.7V - - 45
Maximum CL=30pF, VCC≥1.8V - - 22.5

fmax(IO)out MHz
frequency(1) CL=10pF, VCC≥2.7V - - 90
medium CL=10pF, VCC≥1.8V - - 45

drive CL=30pF, VCC≥2.7V - - 6
Output high to
tf(IO)out
time and output ns
tr(IO)out CL=10pF, VCC≥2.7V - - 4
low to high level
rise time
CL=10pF, VCC≥1.8V - - 6
CL=30pF, VCC≥2.7V - - 100
Maximum
fmax(IO)out CL=30pF, VCC≥1.8V - - 50 MHz
frequency(1)
CL=10pF, VCC≥1.8V - - 100
High
CL=30pF, VCC≥2.7V - - 4
drive Output high to
tf(IO)out
time and output ns
tr(IO)out CL=10pF, VCC≥2.7V - - 2.5
low to high level
rise time
CL=10pF, VCC≥1.8V - - 3.5
1. The maximum frequency is defined in Figure 3-6.
2. The load capacitance CL must take into account the capacitance of the PCB and MCU pins (the
capacitance between the MD pin PB11 and the circuit board can be roughly estimated as 15pF;
the capacitance between other pins and the circuit board can be roughly estimated as 10pF).
The output waveform on

50% 90% 90% 50%
the load capacitor CL
10% 10%
tr(IO)out tf(IO)out
T
Maximum frequency condition: (tr + tf ) ≤ (2/3)T and Duty cycle= 50%±5% (the load capacitance
CL is indicated in the "Condition" column of the "Input/Output AC Characteristics" table)
Figure 3-6 Definition of I/O AC Characteristics
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3.3.12 I2C Interface Characteristics
Table 3-31 I2C Electrical Characteristics
Standard Mode (SM) Fast Mode (FM)

Symbol Parameter Minimum Maximum Minimum Maximum Unit
Value Value Value Value
fSCL SCL frequency 0 100 0 400 kHz
tHD;STA Start condition/restart condition Hold 4.0 - 0.6 - μs
tLOW SCL Low Level 4.7 - 1.3 - μs
tHIGH SCL High Level 4 - 0.6 - μs
tSU;STA Restarting Condition Setup 4.7 - 0.6 - μs
tHD;DAT Data Hold 0 - 0 - μs

30+ 30+
tSU;DAT Data Setup tI2Creference - tI2Creference - ns
clock period(1) clock period(1)
tR Ascending time of SCL/ SDA - 1000 - 300 ns
tF Falling time of SCL/ SDA - 300 - 300 ns
tSU;STO Stop Condition Setup 4 - 0.6 - μs

BUS Idle Time Between Stop Condition
tBUF 4.7 - 1.3 - μs
and Start Condition
Cb Load capacitance - 400 - 400 pF
1. tI2Creference clock period is the I2C reference clock cycle, set by the I2C_CCR.FREQ[2:0] bits.
SDA
tf tSU;DAT tSU;STA tBUF
tSU;STO
tr tHD;STA tSP
SCL
tHD;STA tLOW tHD;DAT tHIGH
START RESTART STOP
Figure 3-7 I2C bus timing definition
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3.3.13 SPI Interface Characteristics
Table 3-32 SPI Electrical Characteristics
Symbol Parameter Conditions Minimum Value Max. Unit

Host mode, 1.8V≤Vcc≤3.6V Tpclk1-1(1) Tpclk1+1(1) ns
tw(SCKH) SCK low level time
Slave mode, 1.8V≤Vcc≤3.6V 3xTpclk1-1(1) 3×Tpclk1+1(1) ns
Host mode (4), 1.8V≤Vcc＜3.6V Tpclk1-1(1) Tpclk1+1(1) ns

tw(SCKL) SCK high level time
Slave mode, 1.8V≤Vcc＜3.6V 3×Tpclk1-1(1) 3×Tpclk1+1(1) ns
tsu(SI) Data input setup time Slave mode, 1.8V≤Vcc≤3.6V 4 - ns
th(SI) Data input hold time Slave mode, 1.8V≤Vcc≤3.6V 3 - ns
Slave mode, 2.7V≤Vcc≤3.6V - 15 ns
tv(SO) Data output effective time
Slave mode, 1.8V≤Vcc＜2.7V - 26 ns
Host mode, 2.7V≤Vcc≤3.6V 5 - ns
tsu(MI) Data input setup time
Host mode, 1.8V≤Vcc＜2.7V 9 - ns
th(MI) Data input hold time Host mode, 1.8V≤Vcc≤3.6V Tpclk1(1) - ns
Slave mode, 1.8V≤Vcc≤3.6V 6×Tpclk1 (1) - ns
tsu(SS) SS establishment time Host mode, 2.7V≤Vcc≤3.6V -5+N×Tsck (1)(2) - ns
Host mode, 1.8V≤Vcc＜2.7V -10+N×Tsck (1)(2) - ns

Slave mode, 1.8V≤Vcc≤3.6V 6×Tpclk1 (1) - ns
th(SS) SS hold time Host mode, 2.7V≤Vcc≤3.6V -5+N×Tsck (1)(3) - ns
Host mode, 1.8V≤Vcc＜2.7V -10+N×Tsck (1)(3) - ns

Host mode, 2.7V≤Vcc≤3.6V - 4 ns
tv(MO) Data output effective time
Host mode, 1.8V≤Vcc≤2.7V - 9 ns
1. Tpclk1 refers to one cycle of the clock PCLK1, and Tsck refers to one cycle of the SPI
communication clock.
2. N=1~8, determined by register SPI_CFG1.MSSI[2:0].
3. N=1~8, determined by register SPI_CFG1.MSSDL[2:0].
4. The values of tw(SCKH) and tw(SCKL) are determined by SPI_CFG2.MBR, and the values listed
in the table are the values of SPI_CFG2.MBR=0.
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tsu(SS) th(SS)
SS input
CPHA=0
tw(SCKH)
CPOL=0
SCK
input tw(SCKL)
CPHA=0
CPOL=1
tv(SO)
MISO output MSB out ... LSB out
tsu(SI)
MOSI input don’t care MSB in ... LSB in don’t care
th(SI)
Figure 3-8 SPI timing definition (slave mode, CPHA=0)
SS0 input tsu(SS) th(SS)
CPHA=1
tw(SCKH)
CPOL=0
SCK
input tw(SCKL)
CPHA=1
CPOL=1
tv(SO)
MISO output MSB out ... LSB out
tsu(SI)
MOSI input don’t care MSB in ... LSB in don’t care
th(SI)
Figure 3-9 SPI timing definition (slave mode, CPHA=1)
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tsu(SS)
th(SS)
SS output
CPHA=1
tw(SCKH)
CPOL=0
SCK
output tw(SCKL)
CPHA=1
CPOL=1
CPHA=1
CPOL=0
SCK
output
CPHA=1
CPOL=1
tsu(MI)
MISO input don’t care MSB in ... LSB in don’t care
th(MI)
tv(MO)
MOSI output MSB out ... LSB out
Figure 3-10 SPI Timing Definition (Host Mode)
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3.3.14 QSPI Interface Characteristics
Table 3-33 QSPI Electrical Characteristics
Minimum
Symbol Parameter Max. Unit
Value
tQscyc SCK clock cycles 2 48 thclk
tQSWH SCK High Level tQscyc×0.4 - ns
tQSWL SCK Low Level tQscyc×0.4 - ns
Data input setup time (2.7V~3.6V) 5 - ns
tSU
Data input setup time (1.8V~2.7V) 5 - ns
Data input hold time (2.7V~3.6V) 11 - ns
tIH
Data input hold time (1.8V~2.7V) 15 - ns
tOD Data output delay - 4 ns
tOH Data output hold time 0 - ns
tQscyc tQSWH
SCK tQSWL
Figure 3-11 QSPI Clock Timing
SSN
SCK
tSU
tOD
IO(input)
MSB DATA LSB
tH tOH
IO(output)
MSB DATA LSB
Figure 3-12 QSPI Timing Definition
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3.3.15 USART Interface Characteristics
Table 3-34 USART AC Timing
Minimum Maximum
Value Value
UART 4 -
tcyc Input clock cycles tPCLK1
Clock synchronization mode 6 -
tCKw Input Clock Width 0.4 0.6 tcyc
tCKr Input Clock Rise Time - 5 ns
tCKf Input Clock Fall Time - 5 ns
Send delay time
Clock synchronization mode - 23 ns
2.7V≤Vcc≤3.6V
tTD
Send delay time
Clock synchronization mode - 30 ns
1.8V≤Vcc<2.7V
Receive data setup time
Clock synchronization mode 17 - ns
2.7V≤Vcc≤3.6V
tRDS
Receive data setup time
Clock synchronization mode 23 - ns
1.8V≤Vcc<2.7V
tRDH Receive data hold time Clock synchronization mode 5 - ns
Table 3-35 USART Maximum Baud Rates
Pattern Highest baud rate

Internal timer PCLK1/8
UART
External timer PCLK1/6
Clock synchronous mode 2.7V≤Vcc≤3.6V 12.0Mbps
Clock synchronous mode 1.8V≤Vcc<2.7V 8.0Mbps
tCKw tCKr tCKf
CKn
n:1~6
tcyc
Figure 3-13 USART Clock Timing
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CKn
tTD
TXn
tRDS tRDH
RXn
n:1~6
Figure 3-14 USART (CSI) Input and Output Timing
3.3.16 JTAG Interface Features
Table 3-36 JTAG Interface Features
Minimum Typical
Value Value
tTCKcyc JTCK clock cycle 50 - - ns
tTCKH JTCK clock high level 15 - - ns
tTCKL JTCK clock low 15 - - ns
tTCKr JTCK clock rise time - - 5 ns
tTCKf JTCK clock fall time - - 5 ns
tTMSs JTMS establishment time 10 - - ns
tTMSh JTMS hold time 10 - - ns
tTDIs JTDI build time 10 - - ns
tTDIh JTDI hold time 10 - - ns
tTDOd JTDO data latency 10 - 25 ns
tTCKcyc
tTCKH
JTCK tTCKf
tTCKr
tTCKL
Figure 3-15 JTAG TCK clock
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JTCK
tTMSS tTMSH
JTMS
tTDIS tTDIH
JTDI
tTDOO
JTDO
Figure 3-16 JTAG Input and Output
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3.3.17 SWD Interface Characteristics
Table 3-37 SWD Interface Features
Minimum Typical
Value Value
tSWCLKcyc SWCLK clock period 50 - - ns
tSWCLKH SWCLK clock high level 15 - - ns
tSWCLKL SWCLK clock low 15 - - ns
tSWCLKr SWCLK clock rise time - - 5 ns
tSWCLKf SWLCK clock fall time - - 5 ns
tSWDIs SWDI establishment time 10 - - ns
tSWDIh SWDI hold time 10 - - ns
tSWDOd SWDO data latency 10 - 25 ns
tSWCLKcyc
tSWCLKH
SWCLK tSWCLKf
tSWCLKr
tSWCLKL
Figure 3-17 SWD SWCLK Clock
SWCLK
tSWDIs tSWDIh
SWDI
tSWDOd
SWDO
Figure 3-18 SWDIO Input and Output
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3.3.18 12-bit ADC Characteristic
Table 3-38 ADC Characteristics

Value Value Value
VAVCC/REFH Power supply - 1.8 - 3.6 V
In high-speed working mode
1 - 60
VAVCC=2.4~3.6V
ADC conversion clock MHz
fADC In low speed mode
frequency 1 - 30
VAVCC=1.8~2.4V
Ultra low speed working mode 1 - 8
Conversion voltage
VAIN - VAVSS - VAVCC/REFH V
range
External input
RAIN Refer to Formula 1 for details - - 50 kΩ
impedance
Sampling switch
RADC - - 3 6 kΩ
resistance
Internal sampling
CADC and retention - - 4 7 PF
capacitance
Trigger conversion
tD fADC=60MHz - - 0.3 µs
delay
0.183 - 4.266 µs
tS Sampling time fADC=60MHz
11 - 255 1/fADC
fADC=60MHz
0.4 - - µs
12-bit resolution
Single-channel total fADC=60MHz
0.37 - - µs
conversion time 10-bit resolution
tCONV
(including sampling fADC=60MHz
0.34 - - µs
time) 8 bit resolution
20 to 268 (sampling time Ts + successively approaching n-bit
1/fADC
resolution + 1)
Sampling rate
fS 12-bit resolution single ADC - - 2.5 Msps
fADC=60MHz
tST Start time - - 1 2 µs
Formula 1: RAIN maximum formula
k
RAIN = N+2
-RADC
fADC × CADC × ln(2 )
The above equation (Equation 1) is used to determine the maximum external impedance that keeps
the error below 1/4LSB. Where N=12 (12-bit resolution), k is the number of sampling periods
defined in the ADC_SSTR register.
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Table 3-39 Input Channel Static Accuracy @ fADC=60MHz
Typical Maximum
Value Value
ET Absolute error ±5.5 ±7 LSB
EO(1) Offset error fADC=60MHz ±4.5 ±7 LSB
Input source impedance<1KΩ
EG(1) Gain error ±4.5 ±7 LSB
VAVCC=2.4~3.6V
ED(1) Differential nonlinear error TA=-40℃~105℃ ±1.5 ±3 LSB
EL(1) Integral nonlinear error ±2.0 ±4 LSB
1. Feature Test Guaranteed.
Table 3-40 Input Channel Static Accuracy @ fADC=8MHz/ 30MHz
Typical Maximum
Value Value
ET Absolute error ±5.5 ±7 LSB
EO(1) Offset error fADC=8/30MHz ±4.5 ±7 LSB
EG(1) Gain error ±4.5 ±7 LSB
VAVCC=1.8V
ED(1) Differential nonlinear error TA=-40℃~105℃ ±1.5 ±3 LSB
EL(1) Integral nonlinear error ±2.0 ±4 LSB
1. Feature Test Guaranteed.
Table 3-41 Input Channel Dynamic Accuracy @ fADC=60MHz
Minimum Maximum
Value Value
ENOB Significant digits 10.5 - Bits
fADC=60MHz
SINAD SNR Input signal frequency = 2kHz 65.0 - dB
SNR SNR VAVCC=2.4~3.6V 65.1 - dB
TA=-40℃~105℃
THD Total Harmonic Distortion - -78.1 dB
Table 3-42 Input Channel Dynamic Accuracy @ fADC=8MHz/ 30MHz
Minimum Maximum
Value Value
ENOB Significant digits 10.5 - Bits
fADC=8/30MHz
SINAD SNR Input signal frequency = 2kHz 65.0 - dB
SNR SNR VAVCC=1.8V 65.1 - dB
TA=-40℃~105℃
THD Total Harmonic Distortion - -78.1 dB
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VAVCC
1LSBIDEAL=
4096 EG
4095
4094 (2)
4093
ET
7 (3)
6 EO (1)
5
4
EL
3
2 ED
1 1LSBIDEAL
1 2 3 456 7 4093 4094 4095 4096
VAVSS VAVCC
Figure 3-19 ADC Accuracy Characteristics
1. Refer to also table above.

2. Examples of actual transmission curves.
3. Ideal transfer curve.
4. End point correlation line.
5. ET = Total Unadjusted Error: The maximum deviation between the actual and ideal transfer
curve.
EO = Offset Error: The deviation between the first actual transition and the first ideal transition.
EG = Gain Error: The deviation between the last ideal transition and the last actual transition.
ED = Differential Nonlinearity Error: The maximum deviation between the actual step and the
ideal value.
EL = Integral Nonlinearity Error: The maximum deviation between any actual transition and the
line associated with the endpoints.
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Sample and hold

ADC converter
RADC(1)
RAIN(1) ADCx_INx 12-bit
Converter
VT
VAIN
0.6V CADC(1)
Caparasitic
IL±1μA
Figure 3-20 Typical Connection Using ADC
1. See Table 3-38 for RAIN, RADC, and CADC values.

2. Cparasitic means PCB capacitance (depending on soldering and PCB routing quality) as well as
pad capacitance (about 5pF). Higher values of Cparasitic result in less accurate conversions.
To solve this problem, fadc should be reduced.
General PCB Design Guidelines
The power supply should be decoupled as shown in the figure below. The 0.1µF capacitor should
be a (good quality) ceramic capacitor. These capacitors should be placed as close to the chip as
possible.
AVCC/VREFH
1μF RAIN(1)
0.1μF
ADCx_INx
AVSS/VREFL
Figure 3-21 Example of Supply and Reference Supply Decoupling
1. See Table 3-38 for RAIN values.
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3.3.19 12-bit DAC Characteristic
Table 3-43 Characteristics when 12bit DAC port output is enabled and the output amplifier is enabled

Value Value Value
VAVCC Analog supply voltage - 1.8 3.3 3.6 V
AO Output voltage range - 0.2 - VAVCC-0.2 -
RL Load Resistance - 5 - - kΩ
CL Load capacitance - - - 50 pF
Differential nonlinearity error
DNL(1) (deviation between two consecutive - - - ±3(1) LSB
codes -1LSB)
Integral nonlinearity error (difference
between the value measured at code I
INL(1) and the value at code I on the line - - - ±5(1) LSB
between code 0 and the last code
4095)
Offset error (difference between
OE measured value at code 2048 and ideal - - - ±15 LSB
value VREF+/2)
GE Gain error - - - ±1 %
Settling Time (Full Scale: Applies to 12-
bit input code transition between
Tst lowest input code and highest input - - 2 3 µs
code until DAC output reaches ±4LSB
of final value)
Table 3-44 Characteristics when 12bit DAC port output is enabled and output amplifier is disabled

Value Value Value
AO Output voltage range - 0 - VAVCC-1LSB V
CL Load capacitance - - - 20 pF
RO Output resistance - - 8.6 12 kΩ

Differential nonlinearity error
DNL (deviation between two consecutive - - - ±2 LSB
codes -1LSB)
TUE Total Unadjustable Error - - - ±24 LSB
Settling time (applicable to 12-bit
input code transition between lowest
Tst input code and highest input code - - 1.5 2.5 µs
until DAC output reaches ±4LSB of
final value, CL=10pF)
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Table 3-45 Characteristics when 12bit DAC port output is disabled and output amplifier is disabled

Value Value Value
AO Output voltage range - 0 - VAVCC-1LSB -

Differential nonlinearity error (deviation
DNL - - - ±2 LSB
between two consecutive codes -1LSB)
TUE Total Unadjustable Error - - - ±5 LSB
Settling time (applicable to 12-bit input
code transition between the lowest input
code and the highest input code until the - - 95.5 117.3 ns
DAC output reaches the final value
±1LSB, Vavcc≥2.7)
Settling time (applicable to 12-bit input
code transition between the lowest input
code and the highest input code until the - - 57.2 70.5 ns
DAC output reaches the final value
Tst ±32LSB, Vavcc≥2.7)
Settling time (applies to 12-bit input code
transition between lowest input code and
- - - 121.6 ns
highest input code until DAC output
reaches final value ±1LSB, Vavcc<2.7)
Settling time (applies to 12-bit input code
transition between lowest input code and
- - - 79.1 ns
highest input code until DAC output
reaches final value ±32LSB, Vavcc<2.7)
3.3.20 Comparator Characteristics
Table 3-46 Comparator Characteristics

Value Value Value
VI Input voltage range - 0 - VAVCC V
Comparator resolution
Tcmp Response time - 30 50 ns
voltage = 100 mV
Input channel switching
Tset - - 100 200 ns
stabilization time
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3.3.21 EXMC Characteristic
Table 3-47 EXMC Characteristics

Value Value Value
Address line output delay time (2.7V~3.6V) - - 12 ns
t_add_d
Address line output delay time (1.8V~2.7V) - - 18 ns
Data line output delay time (2.7V~3.6V) - - 12 ns
t_data_d
Data line output delay time (1.8V~2.7V) - - 18 ns
CE output delay time (2.7V~3.6V) - - 9 ns
t_ce_d
CE output delay time (1.8V~2.7V) - - 12 ns
WE output delay time (2.7V~3.6V) - - 9 ns
t_we_d
WE output delay time (1.8V~2.7V) - - 12 ns
OE output delay time (2.7V~3.6V) - - 9 ns
t_oe_d
OE output delay time (1.8V~2.7V) - - 12 ns
BAA output delay time (2.7V~3.6V) - - 9 ns
t_baa_d
BAA output delay time (1.8V~2.7V) - - 12 ns
ADV output delay time (2.7V~3.6V) - - 9 ns
t_adv_d
ADV output delay time (1.8V~2.7V) - - 12 ns
ALE output delay time (2.7V~3.6V) - - 9 ns
t_ale_d
ALE output delay time (1.8V~2.7V) - - 12 ns
Data line input Setup time (2.7V~3.6V) 24 - - ns
t_data_s
Data line input Setup time (1.8V~2.7V) 28 - - ns
t_data_h Data line input Hold time 0 - - ns
RB input Setup time (2.7V~3.6V) 24 - - ns
t_rb_s
RB input Setup time (1.8V~2.7V) 28 - - ns
t_rb_h RB input Hold time 0 - - ns
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EXMC_CLK …
t_add_d
EXMC_ADD …
t_data_d
EXMC_DATA …
t_ce_d t_ce_d
t_we_d t_we_d
t_oe_d t_oe_d
t_baa_d t_baa_d
EXMC_CE t_adv_d t_adv_d
EXMC_WE
EXMC_OE …
EXMC_BAA
EXMC_ADV
t_ale_d t_ale_d
EXMC_ALE …
Figure 3-22 EXMC Output Signal Timing Diagram
EXMC_CLK
t_data_s t_data_h
EXMC_DATA
t_rb_s t_rb_h
EXMC_RB0
Figure 3-23 EXMC Input Signal Timing Diagram
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3.3.22 EIRQ Filter Characteristics
Table 3-48 EIRQ Filter Characteristics

Value Value Value
INTC_EIRQCR.NOCSEL[1:0] = 00 0.6 - 1.0 μs
EIRQ input INTC_EIRQCR.NOCSEL[1:0] = 01 1.3 - 2.0 μs

WF_EIRQ
filter width INTC_EIRQCR.NOCSEL[1:0] = 10 2.6 - 4.0 μs
INTC_EIRQCR.NOCSEL[1:0] = 11 5.2 - 8.0 μs
3.3.23 RX filter characteristics in USART1 Stop mode
Table 3-49 RX Filter Characteristics in USART1 STOP Mode

Value Value Value
USART1_NFC.USART1_NFS[1:0] = 00 0.6 - 1.0 μs
USART1 USART1_NFC.USART1_NFS[1:0] = 01 1.3 - 2.0 μs
WF_USART1 input filter
width USART1_NFC.USART1_NFS[1:0] = 10 2.6 - 4.0 μs
USART1_NFC.USART1_NFS[1:0] = 11 5.2 - 8.0 μs
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4 Package Information
4.1 Packaging Size

LQFP80 package
12x12 Millimeter
Symbol
Min Nom Max
A -- -- 1.60
A1 0.05 -- 0.15
A2 1.35 1.40 1.45
A3 0.59 0.64 0.69
b 0.18 -- 0.27
b1 0.17 0.20 0.23
c 0.13 -- 0.18
c1 0.12 0.13 0.14
D 13.80 14.00 14.20
D1 11.90 12.00 12.10
E 13.80 14.00 14.20
E1 11.90 12.00 12.10
e 0.4 0.5 0.6
L 0.45 0.6 0.75
L1 1.00REF
θ 0° 3.5° 7°
NOTE:
- Dimensions “D1” and “E1” do not include
mold flash.
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LQFP64 package
A3 A2 A 10x10 Millimeter
Symbol
A1 Min Nom Max
F
A -- -- 1.60
A1 0.05 -- 0.15
A2 1.35 1.40 1.45
A3 0.59 0.64 0.69
b 0.18 -- 0.26
b1 0.17 0.20 0.23
c 0.13 -- 0.17
c1 0.12 0.13 0.14
D 11.80 12.00 12.20

D
D1
D1 9.90 10.00 10.10
E 11.80 12.00 12.20

1
E1 9.90 10.00 10.10
e 0.50BSC
L 0.45 -- 0.75
E1 E
L1 1.00REF
θ 0° -- 7°
NOTE:
b e B B - Dimensions “D1” and “E1” do not include
mold flash.
θ c
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LQFP48 package
7x7 Millimeter
Symbol
Min Nom Max
A -- -- 1.60
A1 0.05 -- 0.15
A2 1.35 1.40 1.45
A3 0.59 0.64 0.69
b 0.18 -- 0.26
b1 0.17 0.20 0.23
c 0.13 -- 0.17
c1 0.12 0.13 0.14
D 8.80 9.00 9.20
D1 6.90 7.00 7.10
E 8.80 9.00 9.20
E1 6.90 7.00 7.10
e 0.50BSC
L 0.40 -- 0.65
L1 1.00REF
θ 0 -- 7°
NOTE:
- Dimensions “D1” and “E1” do not include
mold flash.
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QFN48 package
D
48
5x5 Millimeter
Symbol
1 Min Nom Max
2
PIN 1(Laser Mark)
A 0.50 0.55 0.60
A1 0.00 0.02 0.05
E
A2 0.40REF
b 0.13 0.18 0.23
b1 0.12REF
c 0.10 0.15 0.20
c1 0.145REF
c2 0.140REF
L1
48
D 4.90 5.00 5.10

L
1
2
h D2 3.60 3.70 3.80

h
e 0.35BSC
Ne
E2
Ne 3.85BSC
Nd 3.85BSC
e b1 b
EXPOSED THERMAL Nd E 4.90 5.00 5.10
PAD ZONE
E2 3.60 3.70 3.80
L 0.30 0.35 0.40

c1 L1 0.13 0.18 0.23
h 0.25 0.30 0.35

c2
A2
A1
c
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QFN32 package
4x4 Millimeter
Symbol
PIN 1#
(Lasermark)
Min Nom Max
1
A 0.7 0.75 0.8
2
A1 0 0.02 0.05
b 0.15 0.20 0.3
E
b1 --
c 0.15 0.2 0.25
D 3.90 4.00 4.10
D2 2.6 2.75 2.9
e 0.40BSC
Nd 2.80BSC
A
E 3.90 4.00 4.10
E2 2.6 2.75 2.9

A1
c
Ne 2.80BSC
D2
L 0.2 0.3 0.45
b
32
h 0.25 0.3 0.40
L
1
h
2
h
E2
Ne
e b1
EXPOSED THERMAL
PAD ZONE Nd
BOTTOM VIEW
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4.2 Schematic Diagram of Pad

LQFP80 package (12mm x 12mm)
Note:
‒ Dimensions are in millimeters.

‒ Dimensions are for reference only.
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12.7
10.3
7.8
64 49
1 48
12.7 10.3 7.8
16 33
1.20
17 32
0.30 0.20 0.50
Note:

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9.70
7.30
5.80
48 37
1 36
9.70 7.30 5.80
12 25
1.20
13 24
0.30 0.20 0.50
Note:

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QFN48 package (5mm x 5mm)
6.21
4.35
4.03
48 37
1 36
6.21 4.35 4.03 3.60
3.60
12 25
0.93
13 24
0.17 0.18 0.35
Note:

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4.70
3.40
3.00
32 25
1 24
2.50
4.70 3.40 3.00 2.50
8 17
0.65 0.85
9 16
0.20 0.20 0.40
Note:

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4.3 Silkscreen instructions

The position and information of Pin 1 printed on the front of each package are given below.
LQFP80 package (12mm x 12mm) / LQFP64 package (10mm x 10mm) / LQFP48 package
(7mm x 7mm)
Pin 1
PN (1st~8th bit) PN
PN (9th~12th bit) PN
Date Code+ packaging factory code (7-bit) XXXXXXX
Lot No. (8-bit) Lot No.
Pin 1
PN (5th~12th-bit) PN
Lot No. Lot No. (8-bit)
Date Code (6-bit) Date Code
Pin 1
PN PN (5th~12th-bit)
Lot No. (8-bit) Lot No.
Note:
‒ The blank boxes in the above figure indicate optional marks related to production, which
are not explained in this section.
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4.4 Packaging Thermal Resistance Coefficient

When the packaged chip works at the specified working environment temperature, the junction
temperature Tj (°C) on the chip surface can be calculated according to the following formula:
Tj = TA + (PD x θJA)
◾ TA refers to the working environment temperature when the packaged chip is working, the unit
is ℃;
◾ θJA refers to the thermal resistance coefficient of the package to the working environment, the
unit is ℃/W;
◾ PD is equal to the sum of the internal power consumption (PINT) of the chip and the power
consumption (PI/O) generated by the I/O pin when the chip is working, and the unit is W.
PINT = ICC x VCC
PI/O = ∑(VOL × IOL) +∑((VCC – VOH) × IOH)
When the chip is working at the specified working environment temperature, the junction
temperature Tj of the chip surface cannot exceed the maximum allowable junction temperature TJ
of the chip.
Table 4-1 Thermal resistance coefficient table for each package
Package Type and Size Thermal Resistance Junction-ambient Value (θJA） Unit
LQFP80 12*12*1.4 e=0.5 55+/-10% ℃/W
LQFP64 10*10*1.4 e=0.5 65+/-10% ℃/W
LQFP48 7*7*1.4 e=0.5 75+/-10% ℃/W
QFN32 4*4*0.75 e=0.4 53+/-10% ℃/W
QFN48 5*5*0.55 e=0.35 42+/-10% ℃/W
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5 Ordering Information
Product Model
Function HC32F448 HC32F448 HC32F448 HC32F448 HC32F448 HC32F448 HC32F448 HC32F448
HC32F448 HC32F448
FAUI- FCUI- JAUI- JCUI- KATI- KCTI- MATI- MCTI-
JATI-LQ48 JCTI-LQ48
QFN32TR QFN32TR ZFN48TR ZFN48TR LQFP64 LQFP64 LQFP80 LQFP80
Main frequency (MHz) 200
Kernel M4
Number of GPIOs 25 25 38 38 38 38 52 52 67 67
Power supply voltage range (V) 1.8~3.6
Flash（KB） 128 256 128 256 128 256 128 256 128 256
SRAM（KB） 68
DMA 2unit * 6ch
USART 6ch
SPI 3ch
Communication I2C 2ch

Interface MCAN 2ch
QSPI 1ch
EXMC not support not support not support not support not support not support ✓ ✓ ✓ ✓
Timer0 2unit
TimerA 5unit
Timer4 3unit
Timing and counting Timer6 2unit
WDT 1ch
SWDT 1ch
RTC 1ch
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Product Model
Function HC32F448 HC32F448 HC32F448 HC32F448 HC32F448 HC32F448 HC32F448 HC32F448
HC32F448 HC32F448
FAUI- FCUI- JAUI- JCUI- KATI- KCTI- MATI- MCTI-
JATI-LQ48 JCTI-LQ48
QFN32TR QFN32TR ZFN48TR ZFN48TR LQFP64 LQFP64 LQFP80 LQFP80
12bit ADC 3unit, 4ch 3unit, 4ch 3unit, 11ch 3unit, 11ch 3unit, 11ch 3unit, 11ch 3unit, 17ch 3unit, 17ch 3unit, 24ch 3unit, 24ch
Simulation 12bit DAC 1ch 1ch 2ch 2ch 2ch 2ch 2ch 2ch 2ch 2ch
CMP 4ch
Simulation PVD ✓
TRNG ✓
AES256 ✓
Safety
HASH
✓
（SHA256）
Co-processing DCU ✓
Operating temperature -40~105℃
Encapsulation QFN32 QFN32 QFN48 QFN48 LQFP48 LQFP48 LQFP64 LQFP64 LQFP80 LQFP80
Form: （4*4）（4*4）（5*5）（5*5）（7*7）（7*7）（10*10）（10*10）（12*12）（12*12）
Packaging
（mm） Thickness 0.75 0.75 0.55 0.55 1.6 1.6 1.6 1.6 1.6 1.6
Package style Tape Tape Tape Tape Tray Tray Tray Tray Tray Tray
Before ordering, please contact the sales window for the latest mass production information.
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Version Revision History

Version Revision
Modify the content
Number Date
Rev1.0 2023/06/13 First edition release.

Datasheet: HC32F448 Series

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HC32F448 Series

32-bit ARM® Cortex®-M4 Microcontroller

◾ ARMv7-M architecture 32bit Cortex-M4 CPU, ◾ Timer

‒ 3 independent 12bit 2.5MSPS ADCs HC32F448JATI-LQ48 HC32F448JCTI-LQ48

★ Information in this notification replaces and replaces information in previous versions.

©2023 Xiaohua Semiconductor Co., Ltd. All rights reserved

1.4.27 Integrated Circuit Bus (I2C) ..................................................................................... 26

3.3.14 QSPI Interface Characteristics ................................................................................. 75

Table 3-30 I/O AC Characteristics........................................................................................................ 70

1.1 Part Naming Rules

CPU bit width

Feature Configuration Identifier

Ambient temperature range

1.2 Model Function Comparison Table

1.3 Functional Block Diagram

JTAG/SWD Flash Embedded Flash

AHB Matrix (200MHz)

QSPI KEYSCAN MRC

EFM SPI_3 CMP_2

USART_1 MCAN_1 CMP_3

Figure 1-1 Functional block diagram

1.4 Feature Brief

1.4.2 Bus Architecture (BUS)

1.4.3 Reset Control (RMU)

The chip is configured with 15 reset modes.

◾ Power On Reset (POR)

1.4.4 Clock Control (CMU)

1) External high-speed oscillator (XTAL)

1.4.5 Power Control (PWC)

1.4.6 Initialization Configuration (ICG)

1.4.7 Embedded Flash Interface (EFM)

◾ Maximum OTP space of 9KBytes

1.4.8 Built-in SRAM (SRAM)

1.4.9 General IO (GPIO)

Main Features of GPIO:

1.4.10 Interrupt Control (INTC)

The main specifications of INTC are as follows:

1.4.11 Automatic Operating System (AOS)

1.4.12 Memory Protection Unit (MPU)

1.4.13 Keyboard Scanning (KEYSCAN)

1.4.14 Internal Clock Calibrator (CTC)

The main features of CTC are as follows:

◾ Three external reference clock sources: XTAL, XTAL32, CTCREF

1.4.15 DMA Controller (DMA)

1.4.16 Voltage Comparator (CMP)

A voltage comparator (Comparator, hereinafter referred to as CMP) is a peripheral module that

CMP has the following main features:

◾ 4 comparison channels can perform voltage comparison independently

1.4.17 Analog-to-Digital Converter (ADC)

The main features of the ADC are as follows:

‒ Double sequence scanning, sequence A and B independently select trigger source,

1.4.18 Digital to Analog Converter (DAC)

The main features of the DAC are as follows:

◾ Two D/A conversion channels

1.4.19 Advanced Control Timer (Timer6)

1.4.20 General Control Timer (Timer4)

1.4.21 Emergency Brake Module (EMB)

◾ Change of input level of external port

1.4.22 General Timer (TimerA)