PD - 95150

IRL3103SPbF
l Advanced Process Technology IRL3103LPbF
l Surface Mount (IRL3103S)
HEXFET® Power MOSFET
l Low-profile through-hole (IRL3103L)
l 175°C Operating Temperature D
l Fast Switching VDSS = 30V
l Fully Avalanche Rated
l Lead-Free RDS(on) = 12mΩ
Description G
Advanced HEXFET® Power MOSFETs from International ID = 64A
Rectifier utilize advanced processing techniques to S
achieve extremely low on-resistance per silicon area.
This benefit, combined with the fast switching speed and
ruggedized device design that HEXFET power MOSFETs
are well known for, provides the designer with an
extremely efficient and reliable device for use in a wide
variety of applications.
The D2Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible on-
resistance in any existing surface mount package. The
D2Pak is suitable for high current applications because of its D2Pak TO-262
low internal connection resistance and can dissipate up to IRL3103S IRL3103L
2.0W in a typical surface mount application.
The through-hole version (IRL3103L) is available for low-
profile applications.
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 64
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 45 A
IDM Pulsed Drain Current  220
PD @TC = 25°C Power Dissipation 94 W
Linear Derating Factor 0.63 W/°C
VGS Gate-to-Source Voltage ± 16 V
IAR Avalanche Current 34 A
EAR Repetitive Avalanche Energy 22 mJ
dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns
TJ Operating Junction and -55 to + 175
TSTG Storage Temperature Range °C
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
Mounting torque, 6-32 or M3 srew 10 lbf•in (1.1N•m)

Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 1.6
°C/W
RθJA Junction-to-Ambient (PCB mount)** ––– 40

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IRL3103S/LPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 30 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.028 ––– V/°C Reference to 25°C, ID = 1mA
––– ––– 12 VGS = 10V, ID = 34A „
RDS(on) Static Drain-to-Source On-Resistance mΩ
––– ––– 16 VGS = 4.5V, ID = 28A „
VGS(th) Gate Threshold Voltage 1.0 ––– ––– V VDS = VGS, ID = 250µA
gfs Forward Transconductance 22 ––– ––– S VDS = 25V, ID = 34A„
––– ––– 25 VDS = 30V, VGS = 0V
IDSS Drain-to-Source Leakage Current µA
––– ––– 250 VDS = 24V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 16V
IGSS nA
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -16V
Qg Total Gate Charge ––– ––– 33 ID = 34A
Qgs Gate-to-Source Charge ––– ––– 5.9 nC VDS = 24V
Qgd Gate-to-Drain ("Miller") Charge ––– ––– 17 VGS = 4.5V, See Fig. 6 and 13
td(on) Turn-On Delay Time ––– 8.9 ––– VDD = 15V
tr Rise Time ––– 120 ––– ID = 34A
td(off) Turn-Off Delay Time ––– 14 ––– RG = 1.8Ω
tf Fall Time ––– 9.1 ––– VGS = 4.5V, See Fig. 10 „
Between lead, D
LD Internal Drain Inductance ––– 4.5 –––
6mm (0.25in.)
nH
from package G

LS Internal Source Inductance ––– 7.5 –––

and center of die contact S

Ciss Input Capacitance ––– 1650 ––– VGS = 0V

Coss Output Capacitance ––– 650 ––– VDS = 25V
Crss Reverse Transfer Capacitance ––– 110 ––– pF ƒ = 1.0MHz, See Fig. 5
EAS Single Pulse Avalanche Energy‚ ––– 1320 130† mJ IAS = 34A, L = 0.22mH

Source-Drain Ratings and Characteristics

Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current MOSFET symbol D

––– ––– 64
(Body Diode) showing the
A
ISM Pulsed Source Current integral reverse G

––– ––– 220

(Body Diode) p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.2 V TJ = 25°C, IS = 34A, VGS = 0V „
trr Reverse Recovery Time ––– 57 86 ns TJ = 25°C, IF = 34A
Qrr Reverse Recovery Charge ––– 110 170 nC di/dt = 100A/µs „
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:
 Repetitive rating; pulse width limited by „ Pulse width ≤ 400µs; duty cycle ≤ 2%.
max. junction temperature. (See fig. 11) This is a typical value at device destruction and represents
‚ Starting TJ = 25°C, L = 220µH operation outside rated limits.
RG = 25Ω, IAS = 34A, VGS=10V (See Figure 12) † This is a calculated value limited to TJ = 175°C .
**When mounted on 1" square PCB (FR-4 or G-10 Material). For
ƒ ISD ≤ 34A, di/dt ≤ 120A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C recommended footprint and soldering techniques refer to
application note #AN-994

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 IRL3103S/LPbF

 
1000 1000 VGS
VGS
TOP 15V TOP 15V
10V 10V
4.5V 4.5V
I D , Drain-to-Source Current (A)

3.7V 3.7V

I D , Drain-to-Source Current (A)

3.5V 3.5V
3.3V 3.3V
3.0V 3.0V
BOTTOM 2.7V BOTTOM 2.7V
100 100

2.7V
10 10

2.7V

1

20µs PULSE WIDTH
T = 25 C
J °
1

20µs PULSE WIDTH
T = 175 C
J °

0.1 1 10 100 0.1 1 10 100

VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 2.5

ID = 56A
RDS(on) , Drain-to-Source On Resistance
I D , Drain-to-Source Current (A)


TJ = 25 ° C
2.0

100 
TJ = 175 ° C
(Normalized)

1.5

1.0
10

0.5

1
 V DS = 15V
20µs PULSE WIDTH
0.0

VGS = 10V
2.0 3.0 4.0 5.0 6.0 7.0 8.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS , Gate-to-Source Voltage (V) TJ , Junction Temperature ( °C)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance

Vs. Temperature
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 IRL3103S/LPbF


3000 15
VGS = 0V, f = 1MHz 
ID = 34A
Ciss = Cgs + Cgd , Cds SHORTED
Crss = Cgd

VGS , Gate-to-Source Voltage (V)

2500


Coss = Cds + Cgd 12 VDS = 24V
VDS = 15V
C, Capacitance (pF)

2000 
Ciss
9

1500

Coss
6
1000

3
500
C
rss

0 0
 FOR TEST CIRCUIT
SEE FIGURE 13
1 10 100 0 10 20 30 40
VDS , Drain-to-Source Voltage (V) Q G , Total Gate Charge (nC)

Fig 5. Typical Capacitance Vs. Fig 6. Typical Gate Charge Vs.

Drain-to-Source Voltage Gate-to-Source Voltage

1000 1000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
ISD , Reverse Drain Current (A)

ID , Drain-to-Source Current (A)

100

TJ = 175 ° C 100

10
100µsec

10
1 
TJ = 25 ° C 1msec

Tc = 25°C
Tj = 175°C 10msec

V GS = 0 V
1
Single Pulse
0.1
0.0 0.4 0.8 1.2 1.6 2.0 2.4 1 10 100
VSD ,Source-to-Drain Voltage (V)
VDS , Drain-toSource Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area

Forward Voltage
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 IRL3103S/LPbF

70 RD
VDS
60
VGS
D.U.T.
50 RG
I D , Drain Current (A)

+
-VDD

40
VGS
Pulse Width ≤ 1 µs
30 Duty Factor ≤ 0.1 %

20
Fig 10a. Switching Time Test Circuit
10 VDS
90%
0
25 50 75 100 125 150 175
TC , Case Temperature ( °C)

10%
VGS
Fig 9. Maximum Drain Current Vs.
td(on) tr t d(off) tf
Case Temperature
Fig 10b. Switching Time Waveforms

10
Thermal Response (Z thJC )

1 D = 0.50

0.20


0.10
P DM
0.05
0.1
0.02
0.01  SINGLE PULSE
(THERMAL RESPONSE)
t1
t2

0.01
 Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC

0.00001 0.0001 0.001 0.01 0.1

t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRL3103S/LPbF


240
1 5V
ID

EAS , Single Pulse Avalanche Energy (mJ)

TOP 14A
200 24A
BOTTOM 34A
L D R IV E R
VD S

160
RG D .U .T +
- VD D
IA S A
120
2V0GS
V
tp 0 .0 1 Ω

80
Fig 12a. Unclamped Inductive Test Circuit

40
V (B R )D SS
tp
0
25 50 75 100 125 150 175
Starting TJ , Junction Temperature ( °C)

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current
IAS

Fig 12b. Unclamped Inductive Waveforms

Current Regulator
Same Type as D.U.T.

50KΩ

12V .2µF
QG .3µF

VGS +
V
D.U.T. - DS
QGS QGD
VGS
VG 3mA

IG ID
Charge Current Sampling Resistors

Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit

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 IRL3103S/LPbF
Peak Diode Recovery dv/dt Test Circuit

+ Circuit Layout Considerations

D.U.T* • Low Stray Inductance
• Ground Plane
ƒ
• Low Leakage Inductance
Current Transformer
-

+
‚
„
- +
-


RG • dv/dt controlled by RG +
• ISD controlled by Duty Factor "D" VDD
-
• D.U.T. - Device Under Test
VGS

* Reverse Polarity of D.U.T for P-Channel

Driver Gate Drive

P.W.
Period D=
P.W. Period

[VGS=10V ] ***

D.U.T. ISD Waveform

Reverse
Recovery Body Diode Forward
Current Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
[VDD]
Re-Applied
Voltage Body Diode Forward Drop
Inductor Curent

Ripple ≤ 5% [ ISD ]

*** VGS = 5.0V for Logic Level and 3V Drive Devices

Fig 14. For N-channel HEXFET® power MOSFETs

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IRL3103S/LPbF

D2Pak Package Outline

D2Pak Part Marking Information (Lead-Free)

T H IS IS AN IR F 5 30S WIT H P AR T N U MB E R
L OT COD E 80 24 IN T E R N AT ION AL
AS S E MB L E D ON WW 02 , 2 000 R E CT IF IE R F 5 30 S
IN T H E AS S E MB L Y L IN E "L " L OGO
D AT E COD E
N ote: "P " in as s embly line YE AR 0 = 2 000
pos ition indicates "L ead-F ree" AS S E MB L Y
L OT COD E WE E K 02
L IN E L

OR
P AR T N U MB E R
IN T E R N AT ION AL
R E CT IF IE R F 530S
L OGO
D AT E COD E
P = D E S IGN AT E S L E AD -F R E E
AS S E MB L Y P R OD U CT (OP T ION AL )
L OT COD E Y E AR 0 = 2000
WE E K 02
A = AS S E MB L Y S IT E COD E

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 IRL3103S/LPbF

TO-262 Package Outline

TO-262 Part Marking Information

E XAMP L E : T H IS IS AN IR L 3103L
L OT CODE 1789 P AR T NU MB E R
INT E R NAT IONAL
AS S E MB L E D ON WW 19, 1997
R E CT IF IE R
IN T H E AS S E MB L Y L INE "C" L OGO
Note: "P " in as s embly line DAT E CODE
pos ition indicates "L ead-F ree" YE AR 7 = 1997
AS S E MB L Y
L OT CODE WE E K 19
L INE C

OR
P AR T NU MB E R
INT E R NAT IONAL
R E CT IF IE R
L OGO
DAT E CODE
P = DE S IGNAT E S L E AD-F R E E
AS S E MB L Y P R ODU CT (OP T IONAL )
L OT CODE YE AR 7 = 1997
WE E K 19
A = AS S E MB L Y S IT E CODE

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IRL3103S/LPbF
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)

TR R

1 .6 0 (.0 63 )
1 .5 0 (.0 59 )
1 .6 0 (.0 6 3 )
4.10 (.1 6 1 ) 1 .5 0 (.0 5 9 )
3.90 (.1 5 3 ) 0 .3 6 8 (.0 1 4 5 )
0 .3 4 2 (.0 1 3 5 )

F E E D D IR E C TIO N 1 .8 5 (.0 7 3 ) 1 1 . 6 0 ( .4 5 7 )
1 .6 5 (.0 6 5 ) 1 1 . 4 0 ( .4 4 9 ) 2 4 .3 0 (.9 5 7 )
1 5 .4 2 (. 6 0 9 )
2 3 .9 0 (.9 4 1 )
1 5 .2 2 (. 6 0 1 )
TRL
1 .7 5 (. 0 6 9 )
1 0 . 9 0 ( .4 2 9 ) 1 .2 5 (. 0 4 9 )
1 0 . 7 0 ( .4 2 1 ) 4 .7 2 (.1 3 6 )
1 6 .1 0 ( .6 3 4 ) 4 .5 2 (.1 7 8 )
1 5 .9 0 ( .6 2 6 )

F E E D D IR E C T IO N

1 3. 50 (.5 3 2 ) 2 7 .4 0 (1.0 7 9 )
1 2. 80 (.5 0 4 ) 2 3 .9 0 (.9 4 1 )

330.00 6 0.0 0 (2 . 36 2 )
(14.173) M IN .
M AX.

3 0 .4 0 (1 .1 9 7 )
NO TE S : MAX.
1 . C O M F O R M S T O E IA -4 1 8. 26 .40 (1.03 9) 4
2 . C O N T R O L L IN G D IM E N S IO N : M IL L IM E T E R . 24 .40 (.961 )
3 . D IM E N S IO N M E A S U R E D @ H U B .
3
4 . IN C L U D E S F L A N G E D IS T O R T IO N @ O U T E R E D G E .

Data and specifications subject to change without notice.

This product has been designed and qualified for the industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.04/04
10 www.irf.com
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
IMPORTANT NOTICE
The information given in this document shall in no For further information on the product, technology,
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characteristics (“Beschaffenheitsgarantie”) . contact your nearest Infineon Technologies office
(www.infineon.com).
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regarding the application of the product, Infineon WARNINGS
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applicable legal requirements, norms and Technologies, Infineon Technologies’ products may
standards concerning customer’s products and any not be used in any applications where a failure of
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to evaluate the suitability of the product for the
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respect to such application.