VNL5050N3-E

VNL5050S5-E
OMNIFET III
fully protected low-side driver
Datasheet - production data

Description
2
The VNL5050N3-E and VNL5050S5-E are
monolithic devices made using
3 STMicroelectronics VIPower® Technology,
2
1 intended for driving resistive or inductive loads
SOT-223 SO-8 with one side connected to the battery.
Built-in thermal shutdown protects the chip from
overtemperature and short-circuit. Output current
Features limitation protects the devices in an overload
condition. In case of long duration overload, the
Type Vclamp RDS(on) ID devices limit the dissipated power to a safe level
up to thermal shutdown intervention.Thermal
VNL5050N3-E shutdown, with automatic restart, allows the
41 V 50 mΩ 19 A
VNL5050S5-E devices to recover normal operation as soon as a
fault condition disappears. Fast demagnetization
of inductive loads is achieved at turn-off.
• Automotive qualified
• Drain current: 19 A
• ESD protection
• Overvoltage clamp
• Thermal shutdown
• Current and power limitation
• Very low standby current
• Very low electromagnetic susceptibility
• Compliant with European directive 2002/95/EC
• Open drain status output (VNL5050S5-E only)

Table 1. Devices summary

Order codes
Package
Tube Tape and reel

SOT-223 VNL5050N3-E VNL5050N3TR-E

SO-8 VNL5050S5-E VNL5050S5TR-E

December 2013 DocID15917 Rev 6 1/33

This is information on a product in full production. www.st.com
Contents VNL5050N3-E, VNL5050S5-E

Contents

1 Block diagrams and pins configurations . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4 Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1 SOT-223 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2 SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2 SOT-223 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3 SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4 SOT-223 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.5 SO-8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2/33 DocID15917 Rev 6

VNL5050N3-E, VNL5050S5-E List of tables

List of tables

Table 1. Devices summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Suggested connections for unused and n.c. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Power MOS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Source drain diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. Input section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 9. Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 10. Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 11. Openload detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 12. Supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 13. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 14. Protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 15. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 16. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 17. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 18. SOT-223 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 19. SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 20. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

DocID15917 Rev 6 3/33

3
List of figures VNL5050N3-E, VNL5050S5-E

List of figures

Figure 1. VNL5050N3-E block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. VNL5050S5-E block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. VNL5050N3-E current and voltage conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. VNL5050S5-E current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. Configuration diagrams (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Source diode forward characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Static drain source on-resistance vs. drain current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Static drain source on-resistance vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Static drain source on-resistance vs. drain current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Transfer characteristics (inside view for VIN = 2 V to 3 V) . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13. Normalized on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 14. Normalized input threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 15. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 16. VNL5050N3-E application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 17. VNL5050S5-E application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 18. Maximum demagnetization energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 19. SOT-223 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 20. Rthj-amb vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 19
Figure 21. SOT-223 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 22. Thermal fitting model of a LSD in SOT-223 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 23. SO-8 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 24. Rthj-amb vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 22
Figure 25. SO-8 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 26. Thermal fitting model of a LSD in SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 27. SOT-223 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 28. SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 29. SOT-223 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 30. SO-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 31. SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4/33 DocID15917 Rev 6

VNL5050N3-E, VNL5050S5-E Block diagrams and pins configurations

1 Block diagrams and pins configurations

Figure 1. VNL5050N3-E block diagram

Drain

LOGIC Control & Diagnostic

Current Power
Limitation Clamp

IN DRIVER

OVERTEMPERATURE
PROTECTION

OVERLOAD PROTECTION
(ACTIVE POWER LIMITATION)

GND

Figure 2. VNL5050S5-E block diagram

Drain

SUPPLY SUPPLY Control & Diagnostic

OFF State
LOGIC Open load

Current Power
Limitation Clamp

IN DRIVER

OVERTEMPERATURE
ST
PROTECTION

OVERLOAD PROTECTION
(ACTIVE POWER LIMITATION)

GND

DocID15917 Rev 6 5/33

32
Block diagrams and pins configurations VNL5050N3-E, VNL5050S5-E

Table 2. Pin function

Name Function

Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
INPUT
switch state(1)
DRAIN Power MOS drain
SOURCE Power MOS source and ground reference for the control section
SUPPLY
Supply voltage connected to the signal part (5 V)
VOLTAGE
STATUS Open drain digital diagnostic pin(2)
1. Internally connected to Vsupply in the VNL5050N3-E
2. Valid for VNL5050S5-E only.

Figure 3. VNL5050N3-E current and voltage conventions

*%

7%4
%3"*/
**/
*/165
7*/

4063$&

("1($'5

Figure 4. VNL5050S5-E current and voltage conventions

*%

7%4
%3"*/
**/
*/165
7*/
*45"5
45"564

745"5 *4
4611-:
70-5"(& 4063$&
7TVQQMZ

("1($'5

6/33 DocID15917 Rev 6

VNL5050N3-E, VNL5050S5-E Block diagrams and pins configurations

Figure 5. Configuration diagrams (top view)

%3"*/   /$
 4063$&
4063$&   45"564
%3"*/   %3"*/
4063$&   */165
 */165
%3"*/   4611-:
70-5"(&

405 40
("1($'5

Table 3. Suggested connections for unused and n.c. pins

Connection / pin STATUS N.C. INPUT

Floating X X X
To ground Not allowed X Through 10 kΩ resistor

DocID15917 Rev 6 7/33

32
Absolute maximum rating VNL5050N3-E, VNL5050S5-E

2 Absolute maximum rating

Stressing the device above the rating listed in the Table 4 may cause permanent damage to
the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

2.1 Absolute maximum ratings

Table 4. Absolute maximum ratings
Value
Symbol Parameter Unit
SOT-223 SO-8

VDS Drain-source voltage (VIN = 0 V) Internally clamped V

ID DC drain current Internally limited A
-ID Reverse DC drain current 4 A
IS DC supply current - -1 to 10 mA
IIN DC input current -1 to 10 mA
ISTAT DC status current - -1 to 10 mA

Electrostatic discharge
(R = 1.5 kΩ; C = 100 pF)
VESD1 V
– DRAIN 5000
– SUPPLY, INPUT, STATUS 4000
Electrostatic discharge on output pin only
VESD2 2000 V
(R = 330 Ω, C = 150 pF)
Tj Junction operating temperature -40 to 150 °C
Tstg Storage temperature -55 to 150 °C
Single pulse avalanche energy
EAS 93 mJ
(L = 1.1 mH, TJ = 150 °C, RL = 0, IOUT = IlimL)

2.2 Thermal data

Table 5. Thermal data
Maximum value
Symbol Parameter Unit
SOT-223 SO-8

Rthj-amb Thermal resistance junction-ambient 108.3(1) 87 °C/W

1. When mounted on a standard single-sided FR4 board with 0.5 cm2 of Cu (at least 35 µm thick) connected
to all DRAIN pins

8/33 DocID15917 Rev 6

VNL5050N3-E, VNL5050S5-E Electrical characteristics

3 Electrical characteristics

Values specified in this section are for Vsupply = VIN = 4.5 V to 5.5 V, -40 °C < Tj < 150 °C,
unless otherwise stated.

Table 6. Power MOS section

Symbol Parameter Test conditions Min. Typ. Max. Unit

Vsupply Operating supply voltage - 3.5 5 5.5 V

ID = 2 A; Tj = 25 °C,
50
Vsupply = VIN = 5 V
RON ON-state resistance mΩ
ID = 2 A; Tj = 150 °C,
100
Vsupply = VIN = 5 V
VCLAMP Drain-source clamp voltage VIN = 0 V; ID = 2 A 41 46 52 V
Drain-source clamp
VCLTH VIN = 0 V; ID = 2 mA 36 V
threshold voltage
VIN = 0 V; VDS = 13 V;
0 3
Tj = 25 °C
IDSS OFF-state output current µA
VIN = 0 V; VDS = 13 V;
0 5
Tj = 125 °C

Table 7. Source drain diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

VSD Forward on voltage ID = 2 A; VIN = 0 V - 0.8 - V

Table 8. Input section(1) .

Symbol Parameter Test conditions Min. Typ. Max. Unit

ON-state: Vsupply = VIN = 5 V;

IISS Supply current from input pin 30 65 µA
VDS = 0 V
IS = 1 mA 5.5 7
VICL Input clamp voltage V
IS = -1 mA -0.7
VINTH Input threshold voltage VDS = VIN; ID = 1 mA 1 3.5 V
1. Valid for VNL5050N3-E option (input and supply pins connected together)

Table 9. Status pin(1)

Symbol Parameter Test conditions Min. Typ. Max. Unit

VSTAT Status low output voltage ISTAT = 1 mA 0.5 V

Normal operation;
ILSTAT Status leakage current 10 µA
VSTAT = 5 V
Normal operation;
CSTAT Status pin input capacitance 100 pF
VSTAT = 5 V

DocID15917 Rev 6 9/33

32
Electrical characteristics VNL5050N3-E, VNL5050S5-E

Table 9. Status pin(1) (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

ISTAT = 1 mA 5.5 7
VSTCL Status clamp voltage V
ISTAT = -1 mA -0.7
1. Valid for VNL5050S5-E option

Table 10. Logic input(1)

Symbol Parameter Test conditions Min. Typ. Max. Unit

VIL Low-level input voltage — 0.9 V

IIL Low-level input current VIN = 0.9 V 1 µA
VIH High-level input voltage — 2.1 V
IIH High-level input current VIN = 2.1 V 10 µA
VI(hyst) Input hysteresis voltage — 0.13 V
IIN = 1 mA 5.5 7
VICL Input clamp voltage V
IIN = -1 mA -0.7
1. Valid for VNL5050S5-E option

Table 11. Openload detection(1)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Openload OFF-state voltage

VOl VIN = 0 V 0.6 1.2 1.7 V
detection threshold
Delay between INPUT falling
td(oloff) edge and STATUS falling edge IOUT = 0 A 45 425 1100 µs
in openload condition
1. Valid for VNL5050S5-E option

Table 12. Supply section(1)

Symbol Parameter Test conditions Min. Typ. Max. Unit

OFF-state: Tj = 25 °C;
10 25
VIN = VDRAIN = 0 V;
IS Supply current µA
ON-state: Tj = 25 °C;
25 65
VIN = 5 V; VDS = 0 V
ISCL = 1 mA 5.5 7
VSCL Supply clamp voltage V
ISCL = -1 mA -0.7
1. Valid for VNL5050S5-E option

10/33 DocID15917 Rev 6

VNL5050N3-E, VNL5050S5-E Electrical characteristics

Table 13. Switching characteristics(1)

SOT-223(2) SO-8
Symbol Parameter Test conditions Unit
Min. Typ. Max Min. Typ. Max.

Turn-on delay RL = 6.5 Ω,

td(ON) — 6 — — 6 — µs
time VCC = 13 V(3)
Turn-off delay RL = 6.5 Ω,
td(OFF) — 20 — — 20 — µs
time VCC = 13 V
RL = 6.5 Ω,
tr Rise time — 10 — — 10 — µs
VCC = 13 V
RL = 6.5 Ω,
tf Fall time — 10 — — 10 — µs
VCC = 13 V
Switching energy RL = 6.5 Ω,
WON — 0.04 — — 0.04 — mJ
losses at turn-on VCC = 13 V
Switching energy RL = 6.5 Ω,
WOFF — 0.06 — — 0.06 — mJ
losses at turn-off VCC = 13 V
1. see Figure 16: VNL5050N3-E application schematic and Figure 17: VNL5050S5-E application schematic
2. 3.5 V ≤ Vsupply = VIN ≤ 5.5 V
3. See Figure 15: Switching characteristics

Table 14. Protection and diagnostics

Symbol Parameter Test conditions(1) Min. Typ. Max. Unit

VDS = 13 V;
IlimH DC short-circuit current 19 27 38 A
Vsupply = VIN = 5 V
Short-circuit current VDS = 13 V; TR < Tj < TTSD;
IlimL 11 A
during thermal cycling Vsupply = VIN = 5 V
Step response current
tdlimL VDS = 13 V; Vinput = 5 V 44 µs
limit
TTSD Shutdown temperature — 150 175 200 °C
TR(2) Reset temperature — TRS + 1 TRS + 5 °C
Thermal reset of
TRS (3) — 135 °C
STATUS
Thermal hysteresis
THYST — 7 °C
(TTSD - TR)
1. Vsupply = Vinput in VNL5050N3-E version
2. Valid for VNL5050S5-E option

DocID15917 Rev 6 11/33

32
Electrical characteristics VNL5050N3-E, VNL5050S5-E

3.1 Electrical characteristics curves

Figure 6. Source diode forward characteristics Figure 7. Static drain source on-resistance vs.
drain current
521 PŸ


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&
 
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 ,' $
       
,G $
$7M ƒ& %7M ƒ& &7M ƒ&

1RWH)NPUT AND SUPP LY PINS CONN ECTED TO GETHE R

("1($'5 ("1($'5

Figure 8. Static drain source on-resistance vs. Figure 9. Static drain source on-resistance vs.
input voltage drain current
5' 6 RQ  PŸ
521 PŸ
 
 
 
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&  


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,'  $ 



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$  (

)


       
       
9,1 9 ,G $

$9,1 97 M ƒ& '9,1 97 M ƒ&

$7M ƒ& %7M ƒ& &7M ƒ& %9,1 97 M ƒ& (9,1 97 M ƒ&
&9,1 97 M ƒ& )9,1 97 M ƒ&
1RWH)NPUT AND SUPP LY PINS CONN ECTED TO GETHE R
1RWH)NPUT AND SUPP LY PINS CONN ECTED TO GETHE R
("1($'5
("1($'5

12/33 DocID15917 Rev 6

VNL5050N3-E, VNL5050S5-E Electrical characteristics

Figure 10. Transfer characteristics Figure 11. Transfer characteristics (inside view
for VIN = 2 V to 3 V)

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9 '6 9
  9'6 9
&
 
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9,1 9 9,1 9
$7M ƒ& %7M ƒ& &7M ƒ&
$7M ƒ& %7M ƒ& &7M ƒ&
1RWH)NPUT AND SUPP LY PINS CONN ECTED TO GETHE R 1RWH)NPUT AND SUPP LY PINS CONN ECTED TO GETHE R
("1($'5
("1($'5

Figure 12. Output characteristics Figure 13. Normalized on-resistance vs.

temperature
,' $

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& 






 

 
            

9'6 9 
         
$7M ƒ& %7M ƒ& &7M ƒ&
7M ƒ&
1RWH)NPUT AND SUPP LY PINS CONN ECTED TO GETHE R
("1($'5 ("1($'5

DocID15917 Rev 6 13/33

32
Electrical characteristics VNL5050N3-E, VNL5050S5-E

Figure 14. Normalized input threshold vs.

temperature

9LQWK 9


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7M ƒ&

1RWH,QSXWDQGVXSSO\SLQVFRQQHFWHGWRJHWKHU
("1($'5

Table 15. Truth table(1)

Conditions INPUT DRAIN STATUS

L H H
Normal operation
H L H
L H H
Current limitation
H X H
L H H
Overtemperature
H H L
L H X
Undervoltage
H H X
L L L
Output voltage < VOL
H L H
1. Valid for VNL5050S5-E option

14/33 DocID15917 Rev 6

VNL5050N3-E, VNL5050S5-E Electrical characteristics

Figure 15. Switching characteristics

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Figure 16. VNL5050N3-E application schematic

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DocID15917 Rev 6 15/33

32
Electrical characteristics VNL5050N3-E, VNL5050S5-E

Figure 17. VNL5050S5-E application schematic

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16/33 DocID15917 Rev 6

VNL5050N3-E, VNL5050S5-E Electrical characteristics

3.2 MCU I/O protection

ST suggests to insert a resistor (Rprot) in line to prevent the microcontroller I/O pins from
latching up(a). The value of these resistors is a compromise between the leakage current of
microcontroller and the current required by the LSD I/Os (input levels compatibility) with the
latch-up limit of microcontroller I/Os:

Equation 1
0 .7 (V OH μ C − V IH )
≤ R prot ≤
I latchup I IH max

Let:
• Ilatchup > 20 mA
• VOHµC > 4.5 V
• 35 Ω ≤ Rprot ≤ 100 KΩ
Then, the recommended value is Rprot = 1 KΩ
Figure 18 shows the turn-off current drawn during the demagnetization.

a. In case of negative transient on the drain pin

DocID15917 Rev 6 17/33

32
Electrical characteristics VNL5050N3-E, VNL5050S5-E

Figure 18. Maximum demagnetization energy

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1. The voltage supply is VCC = 13.5 V

18/33 DocID15917 Rev 6

VNL5050N3-E, VNL5050S5-E Package and PC board thermal data

4 Package and PC board thermal data

4.1 SOT-223 thermal data

Figure 19. SOT-223 PC board

1. Layout condition of Rth and Zth measurements (PCB FR4 area = 30 mm x 58 mm, PCB thickness = 2 mm,
Cu thickness = 35 µm, copper areas: from minimum pad lay-out to 0.8 cm2).

Figure 20. Rthj-amb vs. PCB copper area in open box free air condition
RTHjamb (°C/W)

150 footprint

140 RTHj_amb(°C/W)
130
120
110
100
90
80
70
60
0 0.5 1 1.5 2 2.5
2
PCB Cu heatsink area (cm )

DocID15917 Rev 6 19/33

32
Package and PC board thermal data VNL5050N3-E, VNL5050S5-E

Figure 21. SOT-223 thermal impedance junction ambient single pulse

ZTH (°C/W)
1000

Cu footprint
100
Cu=2 cm2

10

0.1
0.0001 0.001 0.01 0.1 1 10 100 1000
Time (s)

Equation 2: pulse calculation formula

Z = R Þδ+Z (1 – δ)
THδ TH THtp

where δ = tP/T

Figure 22. Thermal fitting model of a LSD in SOT-223

1. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

20/33 DocID15917 Rev 6

VNL5050N3-E, VNL5050S5-E Package and PC board thermal data

Table 16. Thermal parameters

Area/island (cm2) Footprint 2

R1 (°C/W) 0.4

R2 (°C/W) 0.8

R3 (°C/W) 4.5

R4 (°C/W) 24

R5 (°C/W) 0.1

R6 (°C/W) 115 45

C1 (W.s/°C) 0.00006

C2 (W.s/°C) 0.0005

C3 (W.s/°C) 0.03

C4 (W.s/°C) 0.16

C5 (W.s/°C) 1000

C6 (W.s/°C) 0.4 2

DocID15917 Rev 6 21/33

32
Package and PC board thermal data VNL5050N3-E, VNL5050S5-E

4.2 SO-8 thermal data

Figure 23. SO-8 PC board

1. Layout condition of Rth and Zth measurements (PCB FR4 area = 58 mm x 58 mm, PCB thickness = 2 mm,
Cu thickness = 35 µm (front and back side), Copper areas: from minimum pad lay-out to 2 cm2).

Figure 24. Rthj-amb vs. PCB copper area in open box free air condition

RTHjamb (°C/W)

105
footprint
RTHj_amb(°C/W)

95

85

75

65
0 0.5 1 1.5 2 2.5
PCB Cu heatsink area (cm2)

22/33 DocID15917 Rev 6

VNL5050N3-E, VNL5050S5-E Package and PC board thermal data

Figure 25. SO-8 thermal impedance junction ambient single pulse

ZTH (°C/W)
1000

Cu=footprint

100
Cu=2 cm2

10

0.1
0.0001 0.001 0.01 0.1 1 10 100 1000
Time (s)

Equation 3: pulse calculation formula

Z = R Þδ+Z (1 – δ)
THδ TH THtp

where δ = tP/T

Figure 26. Thermal fitting model of a LSD in SO-8

1. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

DocID15917 Rev 6 23/33

32
Package and PC board thermal data VNL5050N3-E, VNL5050S5-E

Table 17. Thermal parameters

Area/island (cm2) Footprint 2

R1 (°C/W) 0.4

R2 (°C/W) 2.4

R3 (°C/W) 3.5

R4 (°C/W) 21

R5 (°C/W) 16

R6 (°C/W) 58 28

C1 (W.s/°C) 0.00008

C2 (W.s/°C) 0.0016

C3 (W.s/°C) 0.0075

C4 (W.s/°C) 0.045

C5 (W.s/°C) 0.35

C6 (W.s/°C) 1.05 2

24/33 DocID15917 Rev 6

VNL5050N3-E, VNL5050S5-E Package and packing information

5 Package and packing information

5.1 ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

5.2 SOT-223 mechanical data

Figure 27. SOT-223 package dimensions

0046067

DocID15917 Rev 6 25/33

32
Package and packing information VNL5050N3-E, VNL5050S5-E

Table 18. SOT-223 mechanical data

mm. inch
DIM.
Min. Typ. Max. Min. Typ. Max.

A 1.8 0.071
B 0.6 0.7 0.85 0.024 0.027 0.033
B1 2.9 3 3.15 0.114 0.118 0.124
c 0.24 0.26 0.35 0.009 0.01 0.014
D 6.3 6.5 6.7 0.248 0.256 0.264
e 2.3 0.09
e1 4.6 0.181
E 3.3 3.5 3.7 0.13 0.138 0.146
H 6.7 7 7.3 0.264 0.276 0.287
V 10 (max)
A1 0.02 0.1 0.0008 0.004

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VNL5050N3-E, VNL5050S5-E Package and packing information

5.3 SO-8 mechanical data

Figure 28. SO-8 package dimensions

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Package and packing information VNL5050N3-E, VNL5050S5-E

Table 19. SO-8 mechanical data

Millimeters
Symbol
Min. Typ. Max.

A 1.75

A1 0.10 0.25

A2 1.25

b 0.28 0.48

c 0.17 0.23

D(1) 4.80 4.90 5.00

E 5.80 6.00 6.20

E1(2) 3.80 3.90 4.00

e 1.27

h 0.25 0.50

L 0.40 1.27

L1 1.04

k 0° 8°

ccc 0.10

1. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs
shall not exceed 0.15 mm in total (both side).
2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25 mm per side.

28/33 DocID15917 Rev 6

VNL5050N3-E, VNL5050S5-E Package and packing information

5.4 SOT-223 packing information

The devices can be packed in tube or tape and reel shipments (see the Table 1: Devices
summary on page 1 ).

Figure 29. SOT-223 tape and reel shipment (suffix “TR”)

Reel dimensions
Base Q.ty 1000
Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4

Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width W 12
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 8
Hole Diameter D (+ 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 5.5
Compartment Depth K (max) 4.5
Hole Spacing P1 (± 0.1) 2

All dimensions are in mm.

End

Start

Top No components Components No components

cover
tape 500mm min
Empty components pockets 500mm min
saled with cover tape.

User direction of feed

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32
Package and packing information VNL5050N3-E, VNL5050S5-E

5.5 SO-8 packing information

Figure 30. SO-8 tube shipment (no suffix)

B Base q.ty 100

C
Bulk q.ty 2000
Tube length (± 0.5) 532
A A 3.2
B 6
C (± 0.1) 0.6
All dimensions are in mm.

Figure 31. SO-8 tape and reel shipment (suffix “TR”)

Reel dimensions
Base q.ty 2500
Bulk q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4

All dimensions are in mm.

Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width W 12
Tape hole spacing P0 (± 0.1) 4
Component spacing P 8
Hole diameter D (+ 0.1/-0) 1.5
Hole diameter D1 (min) 1.5
Hole position F (± 0.05) 5.5
Compartment depth K (max) 4.5
Hole spacing P1 (± 0.1) 2

All dimensions are in mm.

End

Start

Top No components Components No components

cover
tape 500mm min
Empty components pockets 500mm min
saled with cover tape.

User direction of feed

30/33 DocID15917 Rev 6

VNL5050N3-E, VNL5050S5-E Revision history

6 Revision history

Table 20. Document revision history

Date Revision Changes

9-Jan-2008 1 Initial release.

Updated corporate template from V2 to V3
Table 3: Suggested connections for unused and n.c. pins
– VESD1: updated parameter and value
– VESD2: changed value
Table 4: Absolute maximum ratings
– Rthj-case: deleted max value for SO-8
– Rthj-amb: added max value for both SOT-223 and SO-8
Table 7: Source drain diode
– VSD: added typ value
Table 8: Input section.
– VICL: added min/max value for IS = 1 mA
– VINTH: added min/max value
Table 9: Status pin
– VSTCL: added max value for ISTAT = 1 mA
Table 10: Logic input
– VICL: added max value for IN = 1 mA
Table 12: Supply section
– IS: changed unit of measurement for ON-state.
– VVSL: added max value for ISTAT = 1 mA
25-Jun-2009 2
Table 13: Switching characteristics
– td(OFF): changed typ value both for SOT-223 and SO-8
– WON: added typ value for SO-8
– WOFF: added typ value for SO-8
– Added all typ column for SOT-223
Table 14: Protection and diagnostics
– IlimL: changed typ value
– tdlimL: changed typ value
– Deleted row TR valid for VNL5050N3-E option
Added Figure 6: Source diode forward characteristics
Added Figure 7: Static drain source on-resistance vs. drain current
Added Figure 8: Static drain source on-resistance vs. input voltage
Added Figure 9: Static drain source on-resistance vs. drain current
Added Figure 10: Transfer characteristics
Added Figure 11: Transfer characteristics (inside view for VIN = 2 V
to 3 V)
Added Figure 12: Output characteristics
Added Figure 13: Normalized on-resistance vs. temperature
Added Chapter 4: Package and PC board thermal data

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32
Revision history VNL5050N3-E, VNL5050S5-E

Table 20. Document revision history (continued)

Date Revision Changes

Deleted table 25: SOT-223 mechanical data & package outline

Added Figure 27: SOT-223 package dimensions
2 Added Table 18: SOT-223 mechanical data
25-Jun-2009
(continued) Deleted table 26: SO-8 mechanical data & package outline
Added Figure 28: SO-8 package dimensions
Added Table 19: SO-8 mechanical data
Updated corporate template from V3 to V3-1
19-Aug-2009 3
Deleted row for Rthj-case in Table 5: Thermal data
Changed the document title
Took the first line off the bullet list for Features on cover page
Table 4: Absolute maximum ratings
– EAS: added new row
Table 6: Power MOS section
– Vsupply: added new row
– RON: updated test conditions
Table 8: Input section.
– ISS: updated test conditions
– Updated the table footnote
Table 13: Switching characteristics
– Moved footnote 2 and changed its text
– WON: changed typ value
20-Nov-2009 4
– WOFF: changed typ value
Table 14: Protection and diagnostics
– IlimH: updated test conditions
– IlimL: updated test conditions
– tdlimL: changed typ value
Updated Figure 7: Static drain source on-resistance vs. drain current
Updated Figure 8: Static drain source on-resistance vs. input voltage
Updated Figure 9: Static drain source on-resistance vs. drain current
Updated Figure 10: Transfer characteristics
Added Figure 11: Transfer characteristics (inside view for VIN = 2 V
to 3 V)
Updated Figure 14: Normalized input threshold vs. temperature
Added Section 3.2: MCU I/O protection
19-Sep-2013 5 Updated Disclaimer.
Table 4: Absolute maximum ratings:
– -ID: updated value
Table 8: Input section.:
– IISS: updated value
17-Dec-2013 6 Table 12: Supply section:
– IS: updated value
Updated Figure 16: VNL5050N3-E application schematic and
Figure 17: VNL5050S5-E application schematic
Updated Section 3.2: MCU I/O protection

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VNL5050N3-E, VNL5050S5-E

Please Read Carefully:

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