MCP1640/B/C/D: 0.65V Start-Up Synchronous Boost Regulator With True Output Disconnect or Input/Output Bypass Option
MCP1640/B/C/D: 0.65V Start-Up Synchronous Boost Regulator With True Output Disconnect or Input/Output Bypass Option
MCP1640/B/C/D: 0.65V Start-Up Synchronous Boost Regulator With True Output Disconnect or Input/Output Bypass Option
L1
4.7 µH
VOUT
VIN 3.3V @ 100 mA
SW V
0.9V To 1.7V OUT
VIN
976 K
COUT
+ CIN
VFB 10 µF
ALKALINE
4.7 µF EN
562 K
- GND
L1
4.7 µH
VOUT
VIN 5.0V @ 300 mA
SW V
3.0V To 4.2V OUTS
VIN VOUTP 976 K
COUT
+ CIN
4.7 µF VFB 10 µF
EN
LI-ION
309 K
- PGND SGND
100.0
V IN = 2.5V
Efficiency (%)
80.0
V IN = 0.8V V IN = 1.2V
60.0
40.0
0.1 1.0 10.0 100.0 1000.0
Output Current (mA)
DC CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VIN = 1.2V, COUT = CIN = 10 µF, L = 4.7 µH, VOUT = 3.3V, IOUT = 15 mA,
TA = +25°C.
Boldface specifications apply over the TA range of -40oC to +85oC.
Parameters Sym Min Typ Max Units Conditions
Input Characteristics
Minimum Start-Up Voltage VIN — 0.65 0.8 V Note 1
Minimum Input Voltage After VIN — 0.35 — V Note 1
Start-Up
Output Voltage Adjust Range VOUT 2.0 5.5 V VOUT VIN; Note 2
Maximum Output Current IOUT 150 — mA 1.2V VIN, 2.0V VOUT
100 150 — mA 1.5V VIN, 3.3V VOUT
350 — mA 3.3V VIN, 5.0V VOUT
Feedback Voltage VFB 1.175 1.21 1.245 V —
Feedback Input Bias Current IVFB — 10 — pA —
Quiescent Current – PFM IQPFM — 19 30 µA Measured at VOUT = 4.0V;
Mode EN = VIN, IOUT = 0 mA;
Note 3
Quiescent Current – PWM IQPWM — 220 — µA Measured at VOUT; EN = VIN
Mode IOUT = 0 mA; Note 3
Quiescent Current – Shutdown IQSHDN — 0.7 2.3 µA VOUT = EN = GND;
Includes N-Channel and
P-Channel Switch Leakage
NMOS Switch Leakage INLK — 0.3 1 µA VIN = VSW = 5V; VOUT =
5.5V VEN = VFB = GND
PMOS Switch Leakage IPLK — 0.05 0.2 µA VIN = VSW = GND;
VOUT = 5.5V
NMOS Switch ON Resistance RDS(ON)N — 0.6 — VIN = 3.3V, ISW = 100 mA
PMOS Switch ON Resistance RDS(ON)P — 0.9 — VIN = 3.3V, ISW = 100 mA
Note 1: 3.3 K resistive load, 3.3VOUT (1 mA).
2: For VIN > VOUT, VOUT will not remain in regulation.
3: IQ is measured from VOUT; VIN quiescent current will vary with boost ratio. VIN quiescent current can be
estimated by: (IQPFM * (VOUT/VIN)), (IQPWM * (VOUT/VIN)).
4: 220 resistive load, 3.3VOUT (15 mA).
5: Peak current limit determined by characterization, not production tested.
TEMPERATURE SPECIFICATIONS
Electrical Specifications:
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Operating Junction Temperature TJ -40 — +125 °C Steady State
Range
Storage Temperature Range TA -65 — +150 °C
Maximum Junction Temperature TJ — — +150 °C Transient
Package Thermal Resistances
Thermal Resistance, 5L-TSOT23 JA — 192 — °C/W EIA/JESD51-3 Standard
Thermal Resistance, 8L-2x3 DFN JA — 93 — °C/W
Note: Unless otherwise indicated, VIN = EN = 1.2V, COUT = CIN = 10 µF, L = 4.7 µH, VOUT = 3.3V, ILOAD = 15 mA, TA = +25°C.
Efficiency (%)
22.5 70 VIN = 0.8V
VOUT = 3.3V 60
20.0
50 VIN = 1.2V
17.5 40
15.0 30
VOUT = 2.0V PWM / PFM
20
12.5 PWM ONLY
10
10.0 0
-40 -25 -10 5 20 35 50 65 80 0.01 0.1 1 10 100 1000
FIGURE 2-1: VOUT IQ vs. Ambient FIGURE 2-4: 2.0V VOUT PFM / PWM
Temperature in PFM Mode. Mode Efficiency vs. IOUT.
Efficiency (%)
70
250 VIN = 0.8V
60 VIN = 1.2V
225 50
VOUT = 3.3V
40
200 30
PWM / PFM
20
175 PWM ONLY
10
0
150
-40 -25 -10 5 20 35 50 65 80 0.01 0.1 1 10 100 1000
FIGURE 2-2: VOUT IQ vs. Ambient FIGURE 2-5: 3.3V VOUT PFM / PWM
Temperature in PWM Mode. Mode Efficiency vs. IOUT.
60
300 VOUT = 2.0V 50
40
200
30
PWM / PFM
100 20
PWM ONLY
10
0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0.01 0.1 1 10 100 1000
VIN (V) IOUT (mA)
FIGURE 2-3: Maximum IOUT vs. VIN. FIGURE 2-6: 5.0V VOUT PFM / PWM
Mode Efficiency vs. IOUT.
3.33 1.00
IOUT = 15 mA VIN = 1.2V
3.325 VOUT = 3.3V
3.32 0.85
VIN = 1.8V
3.315 Startup
VOUT (V)
0.70
VIN (V)
3.31
3.305
0.55
3.3
Shutdown
VIN = 0.8V
3.295 0.40
3.29
3.285 0.25
-40 -25 -10 5 20 35 50 65 80 0 20 40 60 80 100
FIGURE 2-7: 3.3V VOUT vs. Ambient FIGURE 2-10: Minimum Start-up and
Temperature. Shutdown VIN into Resistive Load vs. IOUT.
3.38 525
VIN = 1.5V VOUT = 3.3V
505
3.32
500
3.30 495
IOUT = 15 mA
490
3.28
IOUT = 50 mA 485
3.26 480
-40 -25 -10 5 20 35 50 65 80 -40 -25 -10 5 20 35 50 65 80
Ambient Temperature (°C) Ambient Temperature (°C)
FIGURE 2-8: 3.3V VOUT vs. Ambient FIGURE 2-11: FOSC vs. Ambient
Temperature. Temperature.
3.40 4.5
TA = 85°C IOUT = 5 mA 4 VOUT = 5.0V
3.36 3.5
3
TA = 25°C V OUT = 3.3V
VOUT (V)
3.32
VIN (V)
2.5
2 VOUT = 2.0V
3.28
TA = - 40°C 1.5
3.24 1
0.5
3.20 0
0.8 1.2 1.6 2 2.4 2.8 0 1 2 3 4 5 6 7 8 9 10
VIN (V) IOUT (mA)
FIGURE 2-9: 3.3V VOUT vs. VIN. FIGURE 2-12: PWM Pulse Skipping Mode
Threshold vs. IOUT.
10000
PWM / PFM
PWM ONLY
100
10
0.8 1.1 1.4 1.7 2 2.3 2.6 2.9 3.2 3.5
VIN (V)
FIGURE 2-13: Input No Load Current vs. FIGURE 2-16: MCP1640 3.3V VOUT PFM
VIN. Mode Waveforms.
5
Switch Resistance (Ohms)
4
P - Channel
3
1
N - Channel
0
1 1.5 2 2.5 3 3.5 4 4.5 5
> VIN or VOUT
FIGURE 2-14: N-Channel and P-Channel FIGURE 2-17: MCP1640B 3.3V VOUT
RDSON vs. > of VIN or VOUT. PWM Mode Waveforms.
16
VOUT = 5.0V
14
VOUT = 2.0V V OUT = 3.3V
12
IOUT (mA)
10
0
0 0.5 1 1.5 2 2.5 3 3.5 4
VIN (V)
FIGURE 2-15: PFM / PWM Threshold FIGURE 2-18: MCP1640/B High Load
Current vs. VIN. Waveforms.
FIGURE 2-19: 3.3V Start-up After Enable. FIGURE 2-22: MCP1640B 3.3V VOUT Load
Transient Waveforms.
FIGURE 2-20: 3.3V Start-up when VIN = FIGURE 2-23: MCP1640B 2.0V VOUT Load
VENABLE. Transient Waveforms.
FIGURE 2-21: MCP1640 3.3V VOUT Load FIGURE 2-24: 3.3V VOUT Line Transient
Transient Waveforms. Waveforms.
3.1 Switch Node Pin (SW) 3.6 Power Supply Input Voltage Pin
Connect the inductor from the input voltage to the SW
(VIN)
pin. The SW pin carries inductor current and can be as Connect the input voltage source to VIN. The input
high as 800 mA peak. The integrated N-Channel switch source should be decoupled to GND with a 4.7 µF
drain and integrated P-Channel switch source are inter- minimum capacitor.
nally connected at the SW node.
3.7 Signal Ground Pin (SGND)
3.2 Ground Pin (GND) The signal ground pin is used as a return for the
integrated VREF and error amplifier. In the 2x3 DFN
The ground or return pin is used for circuit ground con- package, the SGND and power ground (PGND) pins are
nection. Length of trace from input cap return, output connected externally.
cap return and GND pin should be made as short as
possible to minimize noise on the GND pin. In the 3.8 Power Ground Pin (PGND)
SOT23-6 package, a single ground pin is used. The power ground pin is used as a return for the high-
current N-Channel switch. In the 2x3 DFN package, the
3.3 Enable Pin (EN) PGND and signal ground (SGND) pins are connected
externally.
The EN pin is a logic-level input used to enable or
disable device switching and lower quiescent current 3.9 Output Voltage Sense Pin (VOUTS)
while disabled. A logic high (>90% of VIN) will enable
the regulator output. A logic low (<20% of VIN) will The output voltage sense pin connects the regulated
ensure that the regulator is disabled. output voltage to the internal bias circuits. In the 2x3
DFN package, VOUTS and VOUTP are connected
externally.
3.4 Feedback Voltage Pin (FB)
3.10 Output Voltage Power Pin (VOUTP)
The FB pin is used to provide output voltage regulation
by using a resistor divider. The FB voltage will be 1.21V The output voltage power pin connects the output volt-
typical with the output voltage in regulation. age to the switch node. High current flows through the
integrated P-Channel and out of this pin to the output
3.5 Output Voltage Pin (VOUT) capacitor and output. In the 2x3 DFN package, VOUTS
and VOUTP are connected externally.
The output voltage pin connects the integrated
P-Channel MOSFET to the output capacitor. The FB 3.11 Exposed Thermal Pad (EP)
voltage divider is also connected to the VOUT pin for There is no internal electrical connection between the
voltage regulation. Exposed Thermal Pad (EP) and the PGND and SGND
pins. They must be connected to the same potential on
the Printed Circuit Board (PCB).
VOUT
INTERNAL
VIN
BIAS
IZERO
DIRECTION
CONTROL
SW SOFT-START
.3V
GATE DRIVE 0V
AND ILIMIT
SHUTDOWN
EN CONTROL
LOGIC
ISENSE
GND OSCILLATOR
SLOPE
COMP.
PWM/PFM
LOGIC
1.21V
FB
EA
To calculate the resistor divider values for the 5.4 Output Capacitor Selection
MCP1640/B/C/D, the following equation can be used.
Where RTOP is connected to VOUT, RBOT is connected The output capacitor helps provide a stable output
to GND and both are connected to the FB input pin. voltage during sudden load transients and reduces the
output voltage ripple. As with the input capacitor, X5R
EQUATION 5-1: and X7R ceramic capacitors are well suited for this
application.
V OUT
R TOP = R BOT ------------
The MCP1640/B/C/D is internally compensated so
–1
V - output capacitance range is limited. See Table 5-1 for
FB the recommended output capacitor range.
Example A: While the N-Channel switch is on, the output current is
supplied by the output capacitor COUT. The amount of
VOUT = 3.3V output capacitance and equivalent series resistance
VFB = 1.21V will have a significant effect on the output ripple
RBOT = 309 k voltage. While COUT provides load current, a voltage
drop also appears across its internal ESR that results
RTOP = 533.7 k (Standard Value = 536 k) in ripple voltage.
Example B:
VOUT = 5.0V EQUATION 5-2:
VFB = 1.21V
I OUT = C OUT -------
dV
RBOT = 309 k dt
RTOP = 967.9 k (Standard Value = 976 k)
There are some potential issues with higher value Where dV represents the ripple voltage and dt
resistors. For small surface mount resistors, represents the ON time of the N-Channel switch (D * 1/
environment contamination can create leakage paths FSW).
that significantly change the resistor divider that effect Table 5-1 contains the recommended range for the
the output voltage. The FB input leakage current can input and output capacitor value.
also impact the divider and change the output voltage
tolerance. TABLE 5-1: CAPACITOR VALUE RANGE
CIN COUT
Min 4.7 µF 10 µF
Max none 100 µF
RBOT RTOP
+VIN +VOUT
1
GND
Wired on Bottom
L Plane
+VIN
+VOUT
CIN COUT
GND MCP1640 RTOP
1
RBOT
Enable
GND
L1
4.7 µH
VOUT
MANGANESE LITHIUM
5.0V @ 5 mA
DIOXIDE BUTTON CELL SW V
OUT
VIN
+ CIN
976 K
COUT
2.0V TO 3.2V
4.7 µF EN VFB 10 µF
-
309 K
®
FROM PIC MCU I/O GND
Note: For applications that can operate directly from the battery input voltage during Sleep mode and
require a higher voltage during normal run mode, the MCP1640C device provides input to output
bypass when disabled. The PIC Microcontroller is powered by the output of the MCP1640C. One
of its I/O pins is used to enable and disable the MCP1640C to control its bias voltage. While
operating in Sleep mode, the MCP1640C input quiescent current is typically less than 1 uA.
FIGURE 6-1: Manganese Lithium Coin Cell Application using Bypass Mode.
L1
10 µH
VOUT
VIN 5.0V @ 350 mA
SW V
3.3V To 4.2V OUTS
VIN VOUTP 976 K
COUT
+ CIN
10 µF VFB 10 µF
EN
LI-ION
309 K
- PGND SGND
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Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
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ISBN: 978-1-60932-019-5
01/05/10