APW7228B

4-Channel LED Backlight Controller

Features General Description

• 4 Channels The APW7228B is a high efficiency driver for 4 channels
• 5.5V to 30V Input Voltage Supply of LEDs. It contains an adjustable-frequency current-
• Drive up to 68 (17x4) White LEDs mode PWM step-up controller, a 5V linear regulator, dim-
(3.5V/160mA Each) ming control circuit and eight regulated current source
• Current Match (Balance) ±1% (Typ.) circuit.
• Current Accuracy ±1% (Typ.) The APW7228B is capable of driving typically 68 (4x17)
• External PWM Input from 100Hz to 50kHz Dim- pieces of 3.5V/160mA LEDs. It contains 4 channels of
ming Frequency voltage controlled current sources with typical currents
• Time Shift PWM Dimming Control matching of +1%, which compensate for the non-unifor-
• Random Channel Selection for Dynamic Opera- mity effect of forward voltages variance in the LED stacks.
tions To minimize the voltage headroom and power loss in the
• Adjustable Switching Frequency typical multi-strings operation, the APW7228B features a
• Protections dynamic headroom control that monitors the highest LED
- String Open Circuit Detection forward voltage string and uses its feedback signal for
- String Short Circuit Detection output regulation.
- Over-Temperature Protection The APW7228B features extensive protection functions
- Over-Voltage Protection that include LED strings open and short circuit detections,
• Available in TSSOP-16P, SOP-16, DIP-16 and Output Over-Voltage Protection (OVP) and Over-Tempera-
QFN4x4-16A Packages ture Protection (OTP).
• Lead Free and Green Devices Available The APW7228B is available in TSSOP-16P, SOP-16, DIP-
(RoHS Compliant) 16 and QFN4x4-16A package.

Applications Simplified Application Circuit

• NB LED Backlight
• LCD Monitor Backlight VIN VOUT

• LCD TV LED Backlight

APW7228B
ENA
PWM

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.

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Rev. A.9 - Mar., 2013
APW7228B

Ordering and Marking Information

APW7228B Package Code

R : TSSOP-16P K : SOP-16 J: DIP-16 QA : QFN4x4-16A
Assembly Material Operating Ambient Temperature Range
Handling Code I : -40 to 85 oC
Handling Code
Temperature Range
TR : Tape & Reel
Package Code Assembly Material
G : Halogen and Lead Free Device

APW7228B R : W7228B XXXXX - Date Code

XXXXX

APW7228B K : W7228B XXXXX - Date Code

XXXXX

APW7228B J : W7228B XXXXX - Date Code

XXXXX

APW7228B QA : W7228B XXXXX - Date Code

XXXXX

Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).

Pin Configuration

ISEN 1 1 16 PWM ISEN 4 1 16 ISEN 3

ISEN 2 2 15 SSTCMP ISET 2 15 GND
GND 3 14 STATUS OVP 3 14 ISEN 2
ISEN 3 4 13 VIN RT 4 13 ISEN 1
ISEN 4 5 12 VREF ENA 5 12 PWM
ISET 6 11 LDR ISW 6 11 SSTCMP
OVP 7 10 ISW LDR 7 10 STATUS
RT 8 9 ENA VREF 8 9 VIN

TSSOP -16 P SOP - 16

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Rev. A.9 - Mar., 2013
APW7228B

Pin Configuration(Cont.)

SSTCMP 13
ISEN2 16
ISEN1 15
PWM 14
ISEN4 1 16 ISEN 3
OVP 2 15 GND
ISET 3 14 ISEN 2
RT 4 13 ISEN 1 GND 1 12 STATUS

ENA 5 12 PWM ISEN3 2 11 VIN

ISW 6 11 SSTCMP ISEN4 3 10 VREF

LDR 7 10 STATUS OVP 4 9 LDR
VREF 8 9 VIN

5 ISET
6 RT
7 ENA
8 ISW
DIP - 16

QFN 4x4-16A

Absolute Maximum Ratings (Note 1)

Sym bol Parameter Rating Unit

VIN VIN Input Voltage (VIN to GND) -0.3 to 40 V
VISW ISW to GND Voltage -0.3 to 65 V
V ISEN1 – VISEN4 ISEN1 – ISEN4 to GND Voltage -0.3 to 65 V
I ISEN1~4 ISEN1 – ISEN4 LED Current ~ 180 mA
VREF, OVP, ENA, PWM, STATUS to GND Voltage -0.3 to 7 V
VI/O
RT, ISET, SS TCMP, LDR to GND Voltage -0.3 to VREF+0.3 V
o
TJ Maximum Junction Temperature 150 C
o
T STG Storage Temperature -65 to 150 C
o
T SDR Maximum Lead Soldering Temperature (10 Seconds) 260 C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom-
mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability

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Rev. A.9 - Mar., 2013
APW7228B

Thermal Characteristics
Symbol Parameter Typical Value Unit
Junction-to-Ambient Resistance in Free Air (Note 2)
TSSOP-16P 38
θJA
o
SOP-16 80 C/W
DIP-16 45
QFN4x4-16A 40
Junction-to-Case Resistance in Free Air (Note 2)
TSSOP-16P 15
θJC
o
SOP-16 10 C/W
DIP-16 8
QFN4x4-16A 6
Note 2: θJA and θJC are measured with the component mounted on a high effective thermal conductivity test board in free air. The
thermal pad of TSSOP-16P and QFN4x4-24A is soldered directly on the PCB.

Recommended Operating Conditions (Note 3)

Symbol Parameter Range Unit
VIN VIN Input Voltage (VIN to GND) 5.5 to 30 V
VOUT Converter Output Voltage ~60 V
ILED Output LED Current Per String 20~160 mA
VENA ENA Enable Voltage 5 V
FPWM PWM Dimming Frequency 100 to 50k Hz
o
TA Ambient Temperature -40 to 85 C
o
TJ Junction Temperature -40 to 125 C
Note 3: Please refer to the typical application circuit.

Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN=12V, VENA=5V and TA=-40 to 85oC. Typical values are at
TA=25oC.

APW7228B
Symbol Parameter Test Conditions
Min Typ Max Unit
V IN Operating Current ENA=2V, PWM=5V - - 12 mA
I VIN V IN Shutdown Current ENA=0V, PWM=5V - 1 5 uA
V IN Standby Current ENA=2V, PWM=0V - 100 150 uA
Enable and PWM Dimming
High 2.4 - - V
E NA and PWM Logic
Low - - 0.8 V
PWM Dimming maximum frequency - 70 - kHz
Under Voltage Lockout
Lockout Logic Threshold VREF Lockout 4.1 4.2 4.3 V
Resume Logic Hysteresis VREF Resume - 200 - mV
Reference
5.35 5.5 5.65 V
Reference Voltage
Thermal Coefficient - -50 - ppm/O C
V REF Output Current Capability IVREF - 30 - mA

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Rev. A.9 - Mar., 2013
APW7228B

Electrical Characteristics (Cont.)

Unless otherwise specified, these specifications apply over VIN=12V, VENA=5V and TA=-40 to 85oC. Typical values are at
TA=25oC.

APW7228B
Symbol Parameter Test Conditions
Min Typ Max Unit
DRIVE CAPABILITY
LDR Sink Resistance 1 4 8 Ω
LDR Source Resistance 1 5 9 Ω
Minimum MOSFET ON Time - 200 - ns
Minimum MOSFET OFF Time - 100 - ns
REGULATION
Regulation LED Current Per Channel ISET=12kΩ 97 100 103 mA
LED Current Balance Rate Δ -3 - 3 %
PROTECTION
Output Over-Voltage Protection
OVP 1.9 2 2.1 V
Threshold
(Note 4)
LED Open Circuit Protection Threshold Internal MOSFET gate voltage - VREF-0.5 - V
LED Short Circuit Protection Threshold ISEN1 -4 7.8 8.5 9.2 V
OCILLATOR
RRT=100kΩ 440 500 560 kHz
Operation Frequency
Temp. Coefficient - 500 - ppm/oC
SSTCMP Clamp High Voltage - 3.9 - V
SSTCMP Clamp Low voltage - 1.1 - V
STATUS OUTPUT
Sink Resistance Status - - 60 Ω
MOSFET OVER-CURRENT PROTECTION
N-FET Over-Current Protection ISW 0.46 0.54 0.64 V
VREF
Load Regulation - 5 - mV/mA
SEL High Threshold - 0.3 - mV/V
THERMAL PROTECTION
o
Lockout Temp - 150 - C
o
Resume Temp - 120 - C
Note 4: Guaranteed by design, not production tested.

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Rev. A.9 - Mar., 2013
APW7228B

Pin Description (I=Input, O=Output, S=Supply)

PIN
NAME FUNCTION
TSSOP-16P SOP-16 DIP-16 QFN4x4-16A
ISEN1 1 13 13 15 Input 1 to WLED Current source.
ISEN2 2 14 14 16 Input 2 to WLED Current source.
GND 3 15 15 1 Ground pin.
ISEN3 4 16 16 2 Input 3 to WLED Current source.
ISEN4 5 1 1 3 Input 4 to WLED Current source.
Resistor connection for setting maximum LED current. Do not short this
ISET 6 2 3 5
pin to GND.
Over-Voltage Protection input pin. Calculate output over-voltage triggered
OVP 7 3 2 4
point according to VOUT = (1+RUPPER/RLOWER) x 2V.
This pin is allowed to adjust the switching frequency. Connect a resistor
RT 8 4 4 6
RRT from the RT pin to the GND pin.
Enable Control Input. Forcing this pin above 2.4V enables the device, or
forcing this pin below 0.8V to shut it down. In shutdown, all functions are
ENA 9 5 5 7
disabled to decrease the supply current below 1µA. Do not leave this pin
floating.
ISW 10 6 6 8 Power MOSFET Current Sense Pin.
LDR 11 7 7 9 Low Side Power MOSFET gate driver.
5V regulator supply for low voltage block. This pin provides bias supply for
VREF 12 8 8 10
control circuitry and the Low-Side MOSFET LDR gate driver.
Main Supply Pin. Must be closely decoupled to the GND with a 4.7µF or
VIN 13 9 9 11
greater ceramic capacitor.
STATUS 14 10 10 12 LED Operation Status Output.
SSTCMP 15 11 11 13 Soft Start and Control Loop Compensation.
PWM 16 12 12 14 PWM brightness control pin. Do not leave this pin floating.

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Rev. A.9 - Mar., 2013
APW7228B

Typical Operating Characteristics

Standby Current Shutdown Current
ENA=5V, PWM=0V ENA=0V, PWM=5V
100 100

80 80
IVIN Current (µA)

IVIN Current (nA)

60 60

40 40

20 20

0
7 9 11 13 15 17 19 21 23 25 7 9 11 13 15 17 19 21 23 25
Input Voltage (V) Input Voltage (V)

Channel to Channel Current Matching LED Current v.s. Input Voltage

3 550

2
530
Total LED Current (mA)
Current Matching (%)

1
510
0
490
-1

-2 470

-3 450
1 2 3 4 5 6 7 8 7 9 11 13 15 17 19 21 23
Channels Input Voltage (V)
LED Current v.s. Dimming Duty Cycle
600

500
Total LED Current (mA)

400

300

200
PWM=250Hz
100 PWM=1kHz
PWM=10kHz
0
0 20 40 60 80 100
PWM Dimming Duty Cycle (%)
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Rev. A.9 - Mar., 2013
APW7228B

Operating Waveforms

PWM Goes High, ISEN Shift Behavior VIN Power On , PWM=ENA=H

2 1

2
3

4 3

4
5

CH1: VPWM (5V/div) CH1: VIN (5V/div)

CH2: VISEN1 (10V/div) CH2: VVREF (5V/div)
CH3: VISEN2(10V/div) CH3: VOUT (20V/div)
CH4: VISEN3 (10V/div) CH4: IILED (500mA/div)
CH5: VISEN4 (10V/div) Time: 2ms/div
Time: 2µs/div

Enable, Hot Plug-In ENA, PWM=H Enable, Hot Plug-In PWM, ENA=H

1 1

2 2

3 3

4 4

CH1: VENA (5V/div) CH1: VPWM (5V/div)

CH2: VVREF (5V/div) CH2: VVREF (5V/div)
CH3: VLDR (5/div) CH3: VLDR (5/div)
CH4: VOUT (20V/div) CH4: VOUT (20V/div)
Time: 2ms/div Time: 2ms/div

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Rev. A.9 - Mar., 2013
APW7228B

Operating Waveforms (Cont.)

PWM Dimming Enable, 250Hz, 50% PWM Dimming Enable, 250Hz, 1%

1 1

2 2

3 3

4 4

CH1: VPWM (5V/div) CH1: VPWM (5V/div)

CH2: VVREF (5V/div) CH2: VVREF (5V/div)
CH3: VLDR (5/div) CH3: VLDR (5/div)
CH4: VOUT (20V/div) CH4: VOUT (20V/div)
Time: 5ms/div Time: 100ms/div

PWM Dimming Enable, 250Hz, 99% One String Open

1
2
2

3 3

4 4

CH1: VPWM (5V/div) CH1: VOUT (20V/div)

CH2: VVREF (5V/div) CH2: VOVP (1V/div)
CH3: VLDR (5/div) CH3: VLDR (5/div)
CH4: VOUT (20V/div) CH4: IILED (200mA/div)
Time: 2ms/div Time: 1ms/div

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Rev. A.9 - Mar., 2013
APW7228B

Operating Waveforms (Cont.)

One String ISEN Short to V OUT Three LEDs Short in One String

1 2

3 3

4 4

CH1: VISEN1 (50V/div) CH1: VISEN1 (20V/div)

CH2: VOUT (20V/div) CH2: VSTATUS (5V/div)
CH3: IILED (200mA/div) CH3: IILED (200mA/div)
CH4: VLDR (5V/div) CH4: VLDR (5V/div)
Time: 50µs/div Time: 20µs/div

Over-Temperature Protection Released Over-Temperature Protection

1
2
1

3 3

4 4

CH1: VOUT (20V/div) CH1: VOUT (20V/div)

CH2: VSTATUS (5V/div) CH2: VSTATUS (5V/div)
CH3: IILED (500mA/div) CH3: IILED (500mA/div)
CH4: VLDR (5V/div) CH4: VLDR (5V/div)
Time: 50ms/div Time: 2ms/div

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Rev. A.9 - Mar., 2013
APW7228B

Typical Application Circuit

(Using TSSOP-16P)

10K
PWM
1 PWM 16
ISEN1
2 15
ISEN2 SSTCMP
3 GND 14 100K
STATUS 100
4 ISEN3 VIN 13
12 470nF
5 ISNE4 VREF
6 ISET 11
LDR
7 OVP ISW 10
8 RT ENA 9
2.2µF
RISET RRT
12K PAD
100K

10K
ENA

VOUT
VIN Fuse 10uH D1

Q1 C2 C3
APM1101 1M
2.2µF, 2.2µF,
C1 100V 100V
2.2µF/50V
RISW
50m
51K

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Rev. A.9 - Mar., 2013
APW7228B

Block Diagram
VIN VOUT

VIN

VREF

5V
VREF Linear Logic LDR
Regulator Oscillator Slope Control
Compensation ISW
GND

PWM ENA Σ
RT
Current Sense
Over Temperature ICMP Amplifier
Protection

VREF

STATUS
SSTCMP

Over-Voltage Fault Detect Logic

Comparator
gm
2V Adjustable Reference Voltage

OVP
ISEN1

Feedback
0.1V Control
ISEN4

Reference Open/Short
ISET Open/Short
Gennerator Circuit Detect Circuit Detect

To To
Current Source Fault Detect Logic Fault Detect Logic

ENA
PWM/OC/SC Current Source
PWM Generator
PWM

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Rev. A.9 - Mar., 2013
APW7228B

Function Description
The APW7228B is a high efficiency driver for 4 channels Programming the BOOST switching Frequency
of LEDs. It contains an adjustable-frequency current- The resistor RRT that is connected from the RT pin to the
mode PWM step-up controller, a 5V linear regulator, dim- GNDA pin programs the boost converter switching fre-
ming control circuit and eight regulated current source. quency FSW . The approximate PWM switching frequency
The APW7228B contains 4 channels of voltage controlled is written as:
current sources with typical currents matching of +1%,
1
which compensate for the non-uniformity effect of forward FSW =
K ⋅ RRT
voltages variance in the LED stacks. To minimize the volt-
Where:
age headroom and power loss in the typical multi-strings
- FSW is the PWM switching frequency
operation, the APW7228B features a dynamic headroom
- RRT is the FSW programming resistor
control that monitors the highest LED forward voltage
K = 2 x 10-11
string and uses its feedback signal for output regulation.
PWM Dimming Controls
Enable and PWM
The APW7228B uses PWM signal to control LED current,
Driving ENA to the ground places the APW7228B in shut-
and therefore brightness.
down mode. When in shutdown, the internal gate driver
turns off. The PWM can be used for PWM input for dimming. - Maximum LED Current Setting
If the dimming function is not used, connect PWM and EN Placing a resistor from ISET pin to GND sets the maxi-
together. The EN and PWMI pins cannot be floating, thus mum LED current.
a pull-low resistance may needs to be added. ILEDMAX = 1200/RRSET

Current Source - PWM Signal Input

The APW7228B integrated 4 matched current sources to The brightness could be adjusted by a PWM signal from
maintain uniform LED brightness for LCD backlight PWM pin. The average LED current is proportion to duty
application. The maximum LED current is set by RISET pin cycle of PWM signal.
with a scaling factor 1200/R ISET. The minimum voltage ILEDAVG = ILEDMAX x DPWM
drop across each current source is 0.35V when the LED where DPWM = duty cycle of PWM input signal. The PWM
is 20mA. The low drop-voltage reduces power loss to signal operation suggestion can follow the formula as
improve efficiency. below,
The APW7228B detect the voltage from any of ISEN pins. Minimum PWM Signal On Time:
When the lowest current source voltage is lower than the Duty (%) ≥ 1500 x 10-6 x FPWM_Signal (Hz)
short circuit threshold, VSC, such will be use as the feed- Minimum PWM Signal Off Time:
back signal of the error amplifier input. The converter
(1 - Duty) (%) ≥ 50 x 10-6 xFPWM_Signal (Hz)
boosts the output voltage to the corresponding level us-
ing the lowest current source voltage. Since all LED Thus, the PWM dimming frequency could up to 40kHz
strings connect to the same output voltage, the other pins with duty cycle range from 60% to 98%. If the dimming
will have a higher voltage, but the current sources could frequency is below 200Hz, the duty cycle range can be
regulate the same current on all channel within 1%. The 0.3% to 99.99%.
lowest current source voltage is related to RISET resis-
tance setting. When the RISET is bigger, the lowest current
source voltage level is lower.

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Rev. A.9 - Mar., 2013
APW7228B

Function Description (Cont.)

PWM Dimming Controls (Cont.) - Short-Circuit Protection (SCP)

- Phase Shift The APW7228B integrates the LED strings short-circuit

APW7228B provides a phase-shifted feature to reduce protection (SCP) circuit. Such circuit monitors the voltage
on each channel. When any channels exceed short-cir-
audible noise and ripple stresses. Referring to Figure 1,
every two ISEN rising and falling edges are phase-shifted cuit threshold (8.5V typical), the device disable current
channels. All the other good channels work normally.
2µs. ISEN1 follow external PWM signal and its delay time
is about 1µs. - Open Circuit Protection (OCP)

External PWM The output voltage of APW7228B is regulated according

1µs
to the minimum current source voltage on all strings in
use. If one or more strings are opened, the respective
ISEN1 ISEN are pulled to the GND. If any ISEN is below target
current, the corresponding current source is disabled.
2µs
The unaffected LED strings still operate normally. If all
ISEN2 strings are opened, the APW7228B boosts the output
voltage of converter high to the OVP threshold.
2µs
- Over-Voltage Protection (OVP)
ISEN3
When the load is opened, the converter unceasingly
2µs boosts the output voltage high. Therefore, an over-volt-
age protection, monitoring the output voltage via feed-
ISEN4
back input pin (OVP), is integrated into the chip to prevent
the output voltage from exceeding their maximum volt-
Figure 1. Phase-Shifted
age ratings. When the voltage on the OVP pin exceeds
5V Low Dropout Regulator 2V, the converter stops switching and prevents the output
voltage from rising. The converter can work again when
A 5V linear regulator is integrated to supply internal circuit
the falling OVP voltage falls below the OVP voltage
and driver. Because VREF is the LDO output pin, it re-
threshold. The desired OVP threshold on output voltage
quires a bypass capacitor of 1µF or more for the regulation.
can be set as below:
The VREF pin can be used as a coarse reference with
OVP=2V x (1+RUPPER/RLOWER)
25mA sourcing capability.
- Over-Temperature Protection (OTP)
Inrush Current Control and Soft-Start
The over-temperature circuit limits the junction tempera-
The APW7228B integrates independent inrush current ture of the APW7228B. When the junction temperature
control and soft-start functions. When the rising VREF exceeds 150 oC, a thermal sensor turns off the power
voltage reaches the rising POR voltage threshold, the MOSFET, allowing the devices to cool. The thermal sen-
POR signal goes high and the chip initiates soft-start sor allows the converters to start a soft-start process and
ope-rations. to regulate the output voltage again after the junction tem-
During the soft-start, the step-up regulator directly limits perature cools by 30oC. The OTP is designed with a 30oC
the peak inductor current. The current-limit level is in- hysteresis to lower the average Junction Temperature
creased through the soft-start period from zero up to the (TJ) during continuous thermal overload conditions, in-
full current-limit value in eight equal current steps (ILIM/8). creasing the lifetime of the device.

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Rev. A.9 - Mar., 2013
APW7228B

Function Description (Cont.)

Inrush Current Control and Soft-Start (Cont.)

- Output Short-Circuit Protection

Connecting a fuse component between the VIN and in-

ductor terminals prevents the huge current by the output
short to ground. Besides, the APW7228B monitors the
voltage on OVP pin to sense output short to ground
condition. During start-up, the current injects into output
capacitor and then pull VOUT voltage high. If the output is
shortened to the ground, and then the OVP pin voltage
does not exceed 0.1V after soft-start is completed, the
low-side MOSFET is switched off.

Under-Voltage Lockout

The Under-Voltage Lockout (UVLO) circuit compares the

input voltage at VREF with the UVLO threshold (4.2V,
typical) to ensure the input voltage is high enough for
reliable operation. The 0.2V (typical) hysteresis prevents
supply transients from causing a restart. Once the VREF
voltage exceeds the UVLO rising threshold, start-up
begins. When the VREF voltage falls below the UVLO
falling threshold, the controller turns off the converter.

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Rev. A.9 - Mar., 2013
APW7228B

Application Information
Input Capacitor Selection The peak inductor current is calculated as the following
equation:
The input capacitor (CIN) reduces the current peaks drawn
1 VIN ⋅ (VOUT − VIN )
from the input supply and reduces noise injection into the IPEAK = IIN(MAX ) + ⋅
2 VOUT ⋅ L ⋅ FSW
IC. The reflected ripple voltage will be smaller with larger
CIN. For reliable operation, it is recommended to select IL
IOUT
VIN IIN LX D1 VOUT
the capacitor voltage rating at least 1.2 times higher than
the maximum input voltage. The capacitors should be
N-FET ISW ESR
placed close to the VIN and GND.
CIN

COUT
Inductor Selection

For high efficiencies, the inductor should have a low dc IL

resistance to minimize conduction losses. Especially at
ILIM
high-switching frequencies the core material has a higher
IPEAK
impact on efficiency. When using small chip inductors,
the efficiency is reduced mainly due to higher inductor ∆IL

core losses. This needs to be considered when select- IIN

ing the appropriate inductor. The inductor value deter-
mines the inductor ripple current. The larger the inductor ISW

value, the smaller the inductor ripple current and the lower
the conduction losses of the converter. Conversely, larger
inductor values cause a slower load transient response.
A reasonable starting point for setting ripple current, ∆IL,
is 30% to 50% of the average inductor current. The rec- ID
ommended inductor value can be calculated as below:
2
 V  VOUT − VIN η IOUT
L ≥  IN  ×
 F ×I ×
 
 VOUT  SW OUT (MAX )
 ∆IL 
 IL (AVG ) 
  Output Capacitor Selection
where
The current-mode control scheme of the APW7228B al-
VIN = input voltage
lows the use of tiny ceramic capacitors. The higher ca-
VOUT = output voltage pacitor value provides the good load transients response.
FSW = switching frequency in MHz Ceramic capacitors with low ESR values have the lowest
IOUT = maximum output current in amp. output voltage ripple and are recommended. If required,
η = Efficiency tantalum capacitors may be used as well. The output ripple
∆IL /IL(AVG) = inductor ripple current/average current is the sum of the voltages across the ESR and the ideal
(0.3 to 0.5 typical) output capacitor.
ΔVOUT = ΔVESR + ΔVCOUT
To avoid saturation of the inductor, the inductor should be
rated at least for the maximum input current of the con- IOUT  VOUT − VIN 
∆VCOUT ≈ × 
verter plus the inductor ripple current. The maximum in- COUT  VOUT × FSW 

put current is calculated as below:
∆VESR ≈ IPEAK × RESR
IOUT (MAX ) × VOUT
IIN(MAX ) = where IPEAK is the peak inductor current.
VIN × η

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Rev. A.9 - Mar., 2013
APW7228B

Application Information (Cont.)

Output Capacitor Selection (Cont.) Diode Selection
For ceramic capacitor application, the output voltage To achieve high efficiency, a Schottky diode must be used.
ripple is dominated by the ∆VCOUT. When choosing the The current rating of the diode must meet the peak cur-
input and output ceramic capacitors, the X5R or X7R rent rating of the converter.
with their good temperature and voltage characteristics
are recommended.

Recommended Capacitor Selection

Designator Manufacturer Part Number Capacitance (µF) TC Code Rated Voltage (V) Case size
C1 Murata GRM31CR71H225KA88K 2.2 X7R 50 1206 T=1.6mm
C2 Murata GRM32ER72A225KA35K 2.2 X7R 100 1206 T=1.6mm
C3 Murata GRM32ER72A225KA35K 2.2 X7R 100 1206 T=1.6mm

Recommended Diode Selection

Maximum average forward Maximum repetitive peak reverse
Designator Manufacturer Part Number Case size
rectified current (A) voltage (V)
D1 Zowie SSCD210SH 2 100 1206-S T=3.4mm

Recommended MOSFET Selection

Designator Manufacturer Part Number Drain-Source Breakdown Voltage (V) Case size
Q1 ANPEC APM1101 100 To-252-3

Layout Considerations
For all switching power supplies, the layout is an impor-
tant step in the design; especially at high peak currents
and switching frequencies. If the layout is not carefully
done, the regulator might show noise problems and duty
cycle jitter.
1. The input capacitor should be placed close to the VIN
and GND. Connecting the capacitor with VIN and GND
pins by short and wide tracks for filtering and minimizing
the input voltage ripple.
2. Place compensation network components closed to
SSTCMP pin.
3. Frequency setting Resistor R , ILED string current set-
RT
ting resistor R and current sensing resistor R should
ISET ISW
close to the RT, ISET and ISW pins respectively.
4. A star ground connection or ground plane minimizes
ground shifts and noise is recommended.
5. Since the VREF voltage is generated for internally sup-
ply rail. A 2.2µF or greater ceramic capacitor must be
connected as closed as possible to VREF pin for good
filtering.

Copyright  ANPEC Electronics Corp. 17 www.anpec.com.tw

Rev. A.9 - Mar., 2013
APW7228B

Package Information
TSSOP-16P
D

SEE VIEW A

D1

E1
EXPOSED PAD

E
E2

e b

0.25
A2

GAUGE PLANE
A

SEATING PLANE
L
A1

VIEW A

S TSSOP-16P
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 1.20 0.047

A1 0.05 0.15 0.002 0.006

A2 0.80 1.05 0.031 0.041

b 0.19 0.30 0.007 0.012

c 0.09 0.20 0.004 0.008

D 4.90 5.10 0.193 0.201

D1 2.00 3.50 0.079 0.138

E 6.20 6.60 0.244 0.260

E1 4.30 4.50 0.169 0.177

E2 2.50 3.50 0.098 0.138
e 0.65 BSC 0.026 BSC
L 0.45 0.75 0.018 0.030

0 0o 8o 0o 8o

Note : 1. Follow from JEDEC MO-153 AB.

2. Dimension "D" does not include mold flash, protrusions
or gate burrs. Mold flash, protrusion or gate burrs shall not
exceed 6 mil per side.
3. Dimension "E1" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.

Copyright  ANPEC Electronics Corp. 18 www.anpec.com.tw

Rev. A.9 - Mar., 2013
APW7228B

Package Information
SOP-16
D

SEE VIEW A

E1

h x 45o
e b c

0.25
A2

GAUGE PLANE
SEATING PLANE
L
A1

0
VIEW A
S SOP-16
Y
M MILLIMETERS INCHES
B
O MIN. MAX. MIN. MAX.
L
A 1.75 0.069

A1 0.00 0.15 0.000 0.006

A2 1.25 0.049
b 0.31 0.51 0.012 0.020

c 0.17 0.25 0.007 0.010

D 9.80 10.00 0.386 0.394
E 5.80 6.20 0.228 0.244

E1 3.80 4.00 0.150 0.157

e 1.27 BSC 0.050 BSC
h 0.25 0.50 0.010 0.020
L 0.40 1.27 0.016 0.050

θ 0o 8o 0o 8o
Note : 1. Follow from JEDEC MS-012 AC.
2. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.

Copyright  ANPEC Electronics Corp. 19 www.anpec.com.tw

Rev. A.9 - Mar., 2013
APW7228B

Package Information
DIP-16

E1
E

A2

0.38
A1

D1 b b2 e L
c eA

eB

S DIP-16
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 5.33 0.210

A1 0.38 0.015
A2 2.92 4.95 0.115 0.195

b 0.36 0.56 0.014 0.022

b2 1.14 1.78 0.045 0.070

c 0.20 0.35 0.008 0.014

D 18.6 20.31 0.732 0.800

D1 0.13 0.005

E 7.62 8.26 0.300 0.325

E1 6.10 7.11 0.240 0.280

e 2.54 BSC 0.100 BSC

eA 7.62 BSC 0.300 BSC
eB 10.92 0.430

L 2.92 3.81 0.115 0.150

Note : 1. Followed from JEDEC MS-001AB

2. Dimension D, D1 and E1 do not include mold flash or
protrusions. Mold flash or protrusions shall not exceed
10 mil.

Copyright  ANPEC Electronics Corp. 20 www.anpec.com.tw

Rev. A.9 - Mar., 2013
APW7228B

Package Information
QFN4x4-16A

D A

b
Pin 1

D2 A1
A3

Pin 1 Corner
E2
L K

S QFN4x4-16A
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 0.80 1.00 0.031 0.039
A1 0.00 0.05 0.000 0.002
A3 0.20 REF 0.008 REF
b 0.25 0.35 0.010 0.014
D 3.90 4.10 0.154 0.161
D2 2.10 2.50 0.083 0.098
E 3.90 4.10 0.154 0.161
E2 2.10 2.50 0.083 0.098
e 0.65 BSC 0.026 BSC
L 0.30 0.50 0.012 0.020
K 0.20 0.008

Copyright  ANPEC Electronics Corp. 21 www.anpec.com.tw

Rev. A.9 - Mar., 2013
APW7228B

Carrier Tape & Reel Dimensions

OD0 P0 P2 P1 A

E1
F

W
B0

K0 A0 A
B OD1 B

SECTION A-A

T
SECTION B-B

d
H
A

T1

Application A H T1 C d D W E1 F
12.4+2.00 13.0+0.50
330.0±2.00 50 MIN. 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.50±0.05
-0.00 -0.20
TSSOP-16P P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10 0.6+0.00
4.00±0.10 8.00±0.10 2.00±0.05 1.5 MIN. 6.9±0.20 5.40.±0.20 1.60±0.20
-0.00 -0.40
A H T1 C d D W E1 F
16.4+2.00 13.0+0.50
330.0±2.00 50 MIN. 1.5 MIN. 20.2 MIN. 16.0±0.30 1.75±0.10 7.5±0.10
-0.00 -0.20
SOP-16
P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10 0.6+0.00
4.0±0.10 8.0±0.10 2.0±0.10 1.5 MIN. 6.40±0.20 10.30±0.20 2.10±0.20
-0.00 -0.40
A H T1 C d D W E1 F
12.4+2.00 13.0+0.50
330.0±2.00 50 MIN. 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05
-0.00 -0.20
QFN4x4-16A
P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10 0.6+0.00
4.0±0.10 8.0±0.10 2.0±0.05 1.5 MIN. 4.30±0.20 4.30±0.20 1.30±0.20
-0.00 -0.40

(mm)

Copyright  ANPEC Electronics Corp. 22 www.anpec.com.tw

Rev. A.9 - Mar., 2013
APW7228B

Devices Per Unit

Package Type Unit Quantity
TSSOP-16P Tape & Reel 2500
SOP-16 Tape & Reel 2500
QFN4x4-16A Tape & Reel 3000

Taping Direction Information

TSSOP-16P

USER DIRECTION OF FEED

SOP-16

USER DIRECTION OF FEED

Copyright  ANPEC Electronics Corp. 23 www.anpec.com.tw

Rev. A.9 - Mar., 2013
APW7228B

QFN4x4-16A

USER DIRECTION OF FEED

Classification Profile

Copyright  ANPEC Electronics Corp. 24 www.anpec.com.tw

Rev. A.9 - Mar., 2013
APW7228B

Classification Reflow Profiles

Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
100 °C 150 °C
Temperature min (Tsmin)
150 °C 200 °C
Temperature max (Tsmax)
60-120 seconds 60-120 seconds
Time (Tsmin to Tsmax) (ts)

Average ramp-up rate

3 °C/second max. 3°C/second max.
(Tsmax to TP)
Liquidous temperature (TL) 183 °C 217 °C
Time at liquidous (tL) 60-150 seconds 60-150 seconds
Peak package body Temperature
See Classification Temp in table 1 See Classification Temp in table 2
(Tp)*
Time (tP)** within 5°C of the specified
20** seconds 30** seconds
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max.

Time 25°C to peak temperature 6 minutes max. 8 minutes max.

* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.

Classification Reflow Profiles (Cont.)

Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
3 3
Package Volume mm Volume mm
Thickness <350 ≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C

Table 2. Pb-free Process – Classification Temperatures (Tc)

3 3 3
Package Volume mm Volume mm Volume mm
Thickness <350 350-2000 >2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C

Reliability Test Program

Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ Tj=125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
HBM MIL-STD-883-3015.7 VHBM≧2KV
MM JESD-22, A115 VMM≧200V
Latch-Up JESD 78 10ms, 1tr≧100mA

Copyright  ANPEC Electronics Corp. 25 www.anpec.com.tw

Rev. A.9 - Mar., 2013
APW7228B

Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050

Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838

Copyright  ANPEC Electronics Corp. 26 www.anpec.com.tw

Rev. A.9 - Mar., 2013