3054

Data Sheet
27680.1*
MULTIPLEXED TWO-WIRE
HALL-EFFECT SENSOR ICs
The A3054KU and A3054SU Hall-effect sensor ICs are digital mag-
netic sensing ICs capable of communicating over a two-wire power/
X signal bus. Using a sequential addressing scheme, the device re-
sponds to a signal on the bus and returns the diagnostic status of the
IC, as well as the status of each monitored external magnetic field.
As many as 30 devices can function on the same two-wire bus. This
LOGIC IC is ideal for multiple sensor applications where minimizing the wiring
harness size is desirable or essential.

C T Each device consists of high-resolution bipolar Hall-effect switch-

.
ing circuitry, the output of which drives high-density CMOS logic

U y
stages. The logic stages decode the address pulse and enable a

l
response at the appropriate address. The combination of magnetic-

D n
1 2 3 field or switch-status sensing, low-noise amplification of the Hall-
transducer output, and high-density decoding and control logic is made

O o
possible by the development of a new IC DABiC™ (digital analog

R
bipolar CMOS) fabrication technology. The A3054SU is an improved

e
replacement for the original UGN3055U.
GROUND
BUS

SWITCH IN

P nc These unique magnetic sensing ICs are available in two tempera-

D
ture ranges; the A3054SU operates within specifications between

e
-20°C and +85°C, while the A3054KU is rated for operation between

E r
-40°C and +125°C. Alternative magnetic and temperature specifica-

e
Dwg. PH-005
tions are available on special order. Both versions are supplied in

U f
0.060" (1.54 mm) thick, three-pin plastic SIPs. Each device is clearly

N re
Pinning is shown viewed from branded side.
marked with a two-digit device address (XX).

TI r
FEATURES
Complete Multiplexed Hall-Effect ICs with

N o
■

f
Simple Sequential Addressing Protocol

O
■ Allows Power and Communication Over a

n
ABSOLUTE MAXIMUM RATINGS Two-Wire Bus (Supply/Signal and Ground)

C
at TA = +25°C ■ Up to 30 Hall-Effect Devices Can Share a Bus

S ow
■ Diagnostic Capabilities

I
Supply Voltage, VBUS . . . . . . . . . . . . . . 18 V ■ Magnetic-Field or Switch-Status Sensing Applications
■ Low Power of DABiC Technology Favors

D h
Magnetic Flux Density, B . . . . . . . Unlimited
Battery-Powered and Mobile Applications
Operating Temperature Range, T A
■ Ideal for Automotive, Consumer, and Industrial Applications

S
A3054KU . . . . . . . . . . -40°C to +125°C
A3054SU . . . . . . . . . . . . -20°C to +85°C
Always order by complete part number:
Storage Temperature Range,

—
Part Number Operating Temperature Range
TS . . . . . . . . . . . . . . . . -55°C to +150°C
Package Power Dissipation, A3054KU-XX -40°C to +125°C
PD . . . . . . . . . . . . . . . . . . . . . . . 635 mW A3054SU-XX -20°C to +85°C
where XX = address (01, 02, … 29, 30).
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ELECTRICAL CHARACTERISTICS over operating temperature range.

Limits
Characteristic Symbol Test Conditions Min Typ Max Units
Power Supply Voltage VBUS — — 15 V
Signal Current IS DUT Addressed, B > 300 G 12 15 20 mA
Quiescent Current IQL VBUS = 6 V — 1.5 2.5 mA
IQH VBUS = 9 V — 1.4 2.5 mA
∆IQ IQL – IQH — 100 300 µA
Address Range Addr Factory Specified 1 — 30 —
Clock Thresholds VCLH LOW to HIGH — — 8.5 V
VCHL HIGH to LOW 6.5 — — V
VCHYS Hysteresis — 0.8 — V
Max. Clock Frequency* fCLK 50% Duty Cycle 2.5 — — kHz
Address LOW Voltage VL VRST 6.0 VCHL V
Address HIGH Voltage VH VCLH 9.0 VBUS V
Reset Voltage VRST 2.5 3.5 5.5 V
Propagation Delay* tplh LOW to HIGH 10 20 30 µs
tphl HIGH to LOW — 5.0 10 µs
Pin 3-2 Resistance RSWH DUT Addressed, B < 5 G — 50 — kΩ
RSWL DUT Addressed, B > 300 G — 200 — Ω
Pin 3-2 Output Voltage VSWH DUT Addressed, B < 5 G — 3.9 — V
VSWL DUT Addressed, B> 300 G — 30 — mV

MAGNETIC CHARACTERISTICS over operating temperature range.

Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Units
Magnetic Threshold† BOP Turn-On 50 150 300 G
BRP Turn-Off 5.0 100 295 G
Hysteresis BHYS BOP – BRP 5.0 50 — G

Typical Data is at TA = +25°C and is for design information only.

*This parameter, although warranteed, is not production tested.
†Alternative magnetic switch point specifications are available on special order. Please contact the factory.

115 Northeast Cutoff, Box 15036

2 Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1995, 2001 Allegro MicroSystems, Inc.
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ELEMENT LOCATION FUNCTIONAL BLOCK DIAGRAM
(±0.005” [0.13 mm] die placement)
1 BUS
ACTIVE AREA DEPTH
0.0165" 0.090"
0.42 mm 2.29 mm
NOM
REG

0.073" COMP COMP

1.85 mm

CLOCK RESET
CMOS LOGIC

SWITCH IN
A 3
(OPTIONAL)

BRANDED
SURFACE 1 2 3

2 GROUND
Dwg. FH-009

Dwg. MH-002-10B

DEFINITION OF TERMS
Device Address Devuce Quiescent Current Drain (IQ)
Each bus device has a factory-specified predefined The current drain of bus devices when active but not
address. At present, allowable device addresses are addressed. IQH is the quiescent current drain when the
integers from 01 to 30. device is not addressed and is at V H IQL is the quiescent
current drain when the device is not addressed and is at
LOW-to-HlGH Clock Threshold (VCLH) VL. Note that IQL is greater than IQH.
Minimum voltage required during the positive-going Diagnostic Phase
transition to increment the bus address and trigger a
Period on the bus when the address voltage is at V H.
diagnostic response from the bus devices. This is also
During this period, a correctly addressed device responds
the maximum threshold of the on-chip comparator that
by increasing its current drain on the bus. This response
monitors the supply voltage, VBUS.
from the device is called the diagnostic response and
the bus current increase is called the diagnostic current.
HlGH-to-LOW Threshold (VHL)
Maximum voltage required during the negative-going Signal Phase
transition to trigger a signal current response from the bus
Period on the bus when the address voltage is at V L.
devices. This is also the maximum threshold of the
During this period, a correctly addressed device that
on-chip comparator that monitors the supply voltage,
detects a magnetic field greater than the magnetic oper-
VBUS.
ate point, BOP, responds by maintaining a current drain of
IS on the bus. This response from the device is called the
Bus HIGH Voltage (VH)
signal response and the bus current is called the signal
Bus HIGH voltage during addressing. Voltage should current.
be greater than VCLH.
Device Address Response Current (I S)
Address LOW Voltage (VL)
Device current during the diagnostic and the signal
Bus LOW voltage during addressing. Voltage should responses of the bus device. This is accomplished by
be greater than VRST and less than VCHL. enabling an internal constant-current source.

Bus Reset Voltage (VRST)

Voltage level while resetting devices. Allegro
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ADDRESSING PROTOCOL
Magnetic Operate Point (BOP) A device may be addressed by changing the supply
Minimum magnetic field required to switch ON the voltage as shown in Figure 1. A preferred addressing
Hall amplifier and switching circuitry of the addressed protocol is as follows: the bus supply voltage is brought
device. This circuitry is only active when the device is low (<2.5 V) so that all devices on the bus are reset. The
addressed. voltage is then raised to the address LOW voltage (V L) and
the bus quiescent current is measured. The bus is then
Magnetic Release Point (BRP) toggled between VL and VH (address HIGH voltage), with
Magnetic field required to switch OFF the Hall each positive transition representing an increment in the
amplifier and switching circuitry after the output has been bus address. After each voltage transition, the bus current
switched ON. When a device is deactivated by changing may be monitored to check for diagnostic and signal
the bus address, all magnetic memory is lost. responses from sensor ICs.

Magnetic Hysteresis (BHYS) Device Addressing

Difference between the BOP and BRP magnetic field When a device detects a bus address equal to its
thresholds. factory-programmed address, it responds with an increase
in its supply current drain ( I S) during the next HIGH portion

FIGURE 1
BUS TIMING
DIAGNOSTIC DIAGNOSTIC DIAGNOSTIC DIAGNOSTIC DIAGNOSTIC DIAGNOSTIC
ADDRESS 01 ADDRESS 02 ADDRESS 03 ADDRESS 04 ADDRESS n ADDRESS 01
V
H
V
CLH
V
CHL
BUS
VOLTAGE V
L
RESET RESET
V
RST
t plh t phl
0

IS DEVICE 02 —
DIAGNOSTIC CURRENT
DEVICE 02
CURRENT
WITH NO
MAGNETIC
FIELD I QL

I QH
0

DEVICE 03 — DIAGNOSTIC
AND SIGNAL CURRENTS
I
S

DEVICE 03
CURRENT
WITH
MAGNETIC
FIELD I QL

I QH
0

I
S

TOTAL
BUS CURRENT DEVICE 01 DEVICE 01
WITH NOT PRESENT NOT PRESENT
MAGNETIC
FIELD AT
DEVICE 03 n • I QL

n • IQH
0

Dwg. WH-005

115 Northeast Cutoff, Box 15036

4 Worcester, Massachusetts 01615-0036 (508) 853-5000
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ofthe address cycle. This response may be TYPICAL DEVICE QUIESCENT CURRENT
used as an indication that the device is "alive
and well" on the bus and is called the diag- 2.0
nostic response. If the device detects an
ambient magnetic field, it continues with I S
during the low portion of the address cycle.
This response from the device is called the

IN mA
1.5
signal response. When the next positive
(address) transition is detected, the device

O
becomes disabled, and its contribution to the

QUIESCENT CURRENT, I
bus signal current returns to IQ.
1.0
Bus Current
Figure 1 shows the addressing protocol. T A = +25°C
The top trace represents the bus voltage
transitions as controlled by the bus driver
(see Applications Notes for an optimal bus 0.5
driver schematic). The second trace repre-
sents the bus current contribution of Device
02. The diagnostic response from the device
indicates that it detected its address on the
0
bus. However, no signal current is shown, 0 3 6 9 12 15
which indicates that sufficient magnetic field
SUPPLY VOLTAGE, V BUS IN VOLTS
is not detected at the chip surface and that
Dwg. GH-045
pin 3 is open circuited. The third trace
represents the current drain of Device 03
FIGURE 2
when a magnetic field is detected. Note both
the diagnostic and signal currents from the DEVICE CONNECTIONS
device. The last trace represents the overall
POSITIVE BUS SUPPLY
bus current drain. When no devices are
addressed, the net bus current is the sum of
quiescent currents of all devices on the bus
(for 'n' devices, the bus current drain is X X

n • IQ).

Bus Issues
1 2 3 1 2 3
After a reset, while at the address LOW
voltage (VL), and before the first address
NC
pulse, bus current calibration may be per-
SWITCH
formed. This feature allows for fail-safe
detection of signal current and eliminates
detection problems caused by low signal BUS RETURN
current (IS), the operation of devices at Dwg. EH-004

various ambient temperatures, lot-to-lot

variation of quiescent current, and the
addition or replacement of devices to the bus
while in the field. At present, a maximum of
30 active devices can coexist on the same
bus, each with a different address. Address

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FIGURE 3
BUS INTERCONNECTION

ADDRESS (POSITIVE) BUS SUPPLY

MICROPROCESSOR

INTERFACE
RESET
01 02 28 29 30

ANALOG OUT
BUS RETURN
Dwg. EH-005

31 is designed to be inactive to allow for APPLICATIONS NOTES

further address expansion of the bus (to 62
maximum addresses). In order to repeat the Magnetic Actuation
address cycle, the bus must be reset, as
shown in Figure 1, by bringing the supply The left side of Figure 2 shows the wiring of an A3054KU or
voltage to below VRST. Devices have been A3054SU when used as a magnetic threshold detector. Pin 1 of the
designed not to ‘wrap-around’. device is wired to the positive terminal of the bus, pin 2 is connected to
the bus negative terminal, and pin 3 has no connection.
Magnetic Characteristics
The device IC has been designed to Mechanical Actuation
respond to an external magnetic field whose The right side of Figure 2 shows the wiring of an A3054KU or
magnetic strength is greater than B OP. It A3054SU when used to detect the status of a mechanical switch.
accomplishes this by amplifying the output of In this case, pin 3 is connected to the switch. The other side of the
an on-chip Hall transducer and applying it to switch is connected to the bus return (negative bus supply or ground).
a threshold detector. In order that bus When the mechanical switch is closed, and the correct bus address is
current is kept to a minimum, the transducer detected by the IC, the device responds with a signal current. If the
and amplification circuitry is kept powered switch is open, only the diagnostic current is returned.
down until the device is addressed. Hence,
the magnetic status is evaluated only when Bus Configuration
the device is addressed. A maximum of 30 individually addresable devices may be con-
nected across the same two-wire bus as shown in Figure 3. It is
External Switch Sensing recommended that the devices use a dedicated digital ground wire to
Pin 3 of the IC may be used to detect the minimize the effects of changing ground potential (as in the case of
status of an external switch when magnetic chassis ground in the automotive industry).
field sensing is not desired (and in the
absence of a magnetic field). The allowable The bus was not designed to require two-wire twisted pair wiring to
states for the switch are ‘open’ or ‘closed’ the devices. However, in areas of extreme electromagnetic interfer-
(shorted to device ground). ence, it may be advisable to install a small bypass capacitor (0.01 µF
for example) between the supply and ground terminals of each device
instead of using the more expensive wiring.

115 Northeast Cutoff, Box 15036

6 Worcester, Massachusetts 01615-0036 (508) 853-5000
 3054
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HALL-EFFECT SENSOR ICs
Bus Driver • The microprocessor can also be used to filter out random line noise
It is recommended that the bus be controlled by digitally filtering the bus responses.
by microprocessor-based hardware for the • The microprocessor can easily keep track of the signal responses
following reasons: and initiate the appropriate action (e.g., light a lamp or sound an
• Device address information may be stored alarm, and also pinpoint the location of the signal).
in ROM in the form of a look-up table. Optimally, the microprocessor is used to control bus-driving
• Bus faults can be pinpointed by the circuitry that will accept TTL-level inputs to drive the bus and will return
microprocessor by comparing the diagnos- an analog voltage representation of the bus current.
tic response to the expected response in Interface Schematic
the ROM look-up table.
The bus driver is easily designed using a few operational amplifi-
• The microprocessor, along with an A/D ers, resistors, and transistors. Figure 4 shows a schematic of a
converter, can also be used to self cali- recommended bus driver circuit that is capable of providing 6 V to 9 V
brate the quiescent currents in the bus and transitions, resetting the bus, and providing an analog measurement of
hence be able to easily detect a signal the bus current for the A/D input of the microprocessor.
response.

FIGURE 4
BUS INTERFACE SCHEMATIC

+15 V

1 kΩ

10 kΩ R 4
1 kΩ

9V 0.001 Q3
Z1 µF OP1

BUS SUPPLY
20 kΩ
R5
50 Ω R
6
X X
ADDRESS 5 kΩ Q2
Q1

RESET 5 kΩ 1 2 3 1 2 3
50 kΩ 50 kΩ
R8 R7
NC
SWITCH

BUS RETURN
100 kΩ R 9

ANALOG OUT
OP2

100 kΩ
R 10

Dwg. EH-003A

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In Figure 4, the ADDRESS input provides a TTL-compatible input
to control the bus supply. A HIGH (5 V) input switches Q 1 ON and sets
the bus voltage to 6 V through the resistor divider R 4, R5, and Zener
Z1. A LOW input switches Q1 OFF and sets the bus voltage to 9 V
(Z1). This voltage is fed into the positive input of the operational
amplifier OP1 and is buffered and made available at BUS SUPPLY (or
device supply). Bus reset control is also available in the form of a TTL-
compatible input. When the RESET input is HIGH, Q 2 is switched ON
and the positive input of the operational amplifier is set to the satura-
tion voltage of the transistor (approximately 0 V). This resets the bus.
A linear reading of the bus current is made possible by amplifying
the voltage generated across R6 (which is IBUS • R6). The amplifier,
OP2, is a standard differential amplifier of gain R 9/R7 (provided that R7
= R8, R9 = R10). The gain of the total transim-pedance amplifier is
given by:
VOUT = IBUS • R6 • R9/R7

This voltage is available at the ANALOG OUT terminal.

Bus Control Software
The processing of the bus current (available at ANALOG OUT) is
best done by feeding it into the A/D input of a microprocessor. If the
flexibility provided by a microprocessor is not desired, this signal could
be fed into threshold detection circuitry; e.g., comparator, and the
output used to drive a display.
Related References
1. G. AVERY, “Two-Terminal Hall Sensor,” ASSIGNEE: Sprague
Electric Company, North Adams, MA, United States. Patent number
4,374,333; Feb. 1983.
2. T. WROBLEWSKI and F. MEISTERFIELD, “Switch Status
Monitoring System, Single-Wire Bus, Smart Sensor Arrangement
There Of,” ASSIGNEE: Chrysler Motor Corporation, Highland Park, Ml,
United States. Patent number 4,677,308; June 1987.

115 Northeast Cutoff, Box 15036

8 Worcester, Massachusetts 01615-0036 (508) 853-5000
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Dimensions in Inches Dimensions in Millimeters

(controlling dimensions) (for reference only)

0.183 4.65
0.178 4.52

0.063 1.60
0.059 1.50

0.181 4.60
0.176 4.47

45° 45°

0.086 1 2 3 0.018 2.18 1 2 3 0.46

MAX MAX

0.600 0.0173 15.24 0.44

0.560 0.0138 14.23 0.35

0.0189 0.48
0.0142 0.36
SEE NOTE SEE NOTE

0.050 1.27
0.100 2.54
Dwg. MH-003E in Dwg. MH-003E mm

NOTES:1. Tolerances on package height and width represent allowable mold

offsets. Dimensions given are measured at the widest point
(parting line).
2. Exact body and lead configuration at vendor’s option within limits
shown.
3. Height does not include mold gate flash.
4. Recommended minimum PWB hole diameter to clear transition
area is 0.035” (0.89 mm).
5. Where no tolerance is specified, dimension is nominal.
6. Minimum lead length was 0.500” (12.70 mm). If existing product to
the original specifications is not acceptable, contact sales office
before ordering.

www.allegromicro.com 9
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The products described herein are manufactured under one or

more of the following U.S. patents: 5,045,920; 5,264,783; 5,442,283;
5,389,889; 5,581,179; 5,517,112; 5,619,137; 5,621,319; 5,650,719;
5,686,894; 5,694,038; 5,729,130; 5,917,320; and other patents
pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support appliances, devices, or systems without express written
approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringements of patents or other rights of
third parties that may result from its use.

115 Northeast Cutoff, Box 15036

10 Worcester, Massachusetts 01615-0036 (508) 853-5000