Microprocessor

Faculty of Electric, Computer and IT

Qazvin Islamic Azad University (QIAU)

First Semester 1391 (2012)

By
Dr. Vahid Rostami

: ‫ارزشیابی در این درس‬

25% ‫ امتحان میان ترم‬1
75% ‫ امتحان پایان ترم‬2

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References
• Text Books
– M. A. Mazidi &. G. Mazidi,"The 80x86 IBM PC andCompatibleComputers", PrenticeHall,2000.
– Gaonkar, MicroprocessorArchitectureProgrammingandApps/PrenticeHall. Besidestheotheraspectsof
the8085 programmingwewilltalk abouttheprogrammable8085 peripheralsanddata transfer.
8088/6 ‫ از کتاب ریسپردازنده های سری‬9‫و‬8 ‫ و‬3‫و‬2‫و‬1 ‫– فصل های‬
‫دکتر معتمدی‬: ‫نویسنده‬
• Useful Books:
– Antonakos, An IntroductiontotheIntel Familyof Microprocessors, PrenticeHall, 1999
– K.R. Irvine, AssemblyLanguageforIntel BasedComputers, PrenticeHall,1999.
– W. A. TriebelandA. Singh, The8088and 8086 Microprocessors: Programming, Interfacing, Software,
HardwareandApplications” PrenticeHall, 2000
– Flynn, ComputerArchitecturePipelinedandParallelProcessorDesign
– ComputerArchitectureandLogicDesign, Thomas Bartee, McGrawHill
– andin combinationwithothercomputerarchitecturebooksavailable.

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Syllabus
1. Processor Architecture
1. Introduction to Microcomputers and Microprocessors, 80x86 Processor Architecture.
2. 8088/8086 Instruction Set, Machine Codes, Addressing Modes, Debug
3. The 8088 and 8086 Microprocessors and Their Memory and Input/Output Interfaces, ISA
2. Generation of Intel 80XXX
1. Improving Computer Performance Technique
2. From 1st to 4rd generation of processors
3. Memory and Memory Interfacing
1. Types of memory
2. Memory Expanding
3. Buffers and Bus controllers.
4. Loading and running a program in the memory
4. Interface Circuits and Peripheral Devices
1. Input/Output interface 8255
2. Counter/Timer 8284
3. Interrupt Interface and Programmable Interrupt Controller (8259)
4. Serial Data Communication and 16450/8250/8251 chips
5. Microcontrollers
1. An Introduction to AVR
2. Atmega32 architecture
3. Code-vision
4. Designing a controller system using Proteous
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A brief history
• First microprocessor at Intel in 1971---4004
• Intel 4004 was a 4 bit up. Only 45 instructions P Channel Mosfet technology. 50 K instructions per
second (< ENIAC!).
• Later 8008 as an 8 bit μ-processor then it was divided into 8080 and Motorolla6800.
• 8080 was 10x faster than 8008 and TTL compatible (easy interfacing)
• MITS Altair 8800 1974. The BASIC Interpreter was written by Bill-Gates. Assembler program was
written by Digital Research Corporation (Author comp. Of Dr-DOS)
• 1977 8085 microprocessor. Internal clock generator, higher frequency at reduced cost and integration.
There are 200 million8085’s around the world!
• 1978 8086+8088 microprocessors 16 bit. Addressed 1 Mbyte of memory. Small instruction cache (4-
6 bytes) enabled pre-fetch of instructions.
• IBM decided to use 8088 in PC.

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A brief history
• In 1983 80286 released, identical to 8086 except the addressing and higher clock speed.
• 32 bit microprocessor. In 1986 major overhaul on 80286 architecture 80386 DX with 32bit data + 32
bit address (4 G bytes)
• 1989 80486 = 80386 +80387co processor + 8KB cache
• 1993 Pentium (80586). Includes 2 execution engines.
• Pentium Pro included 256K Level 2 cache mechanism as well as Level 1 cache. Also 3 execution
engines which can execute at the same time and can conflict and still execute in parallel. The address
bus was expended to 36.
• Pentium 2 included L2 cache on its circuit board (called slot)
• Later Pentium 3 and 4 released with several architectural and technological innovations.

More Information

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Microprocessors Packaging

Three 14-pin (DIP14) plastic dual in-line A plastic leaded chip carrier (PLCC) has a rectangular
packages containing IC chips. plastic housing. It is a reduced cost evolution of the ceramic
leadless chip carrier (CLCC).

The pin grid array (PGA) at

the bottom of a XC68020, a The topside of a An organic Pin Grid Array
prototype of the Motorola Celeron-400 in a (OPGA) CPU.
68020 microprocessor Plastic pin grid array
(PPGA) packing

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Type of Micro-Computers

Personal Computer (PC) :In 1982, IBM began selling the idea of a personal computer. It featured a system
board designed around the Intel 8088 8-bit microprocessor, 16 K memory and 5 expansion slots.
–This last feature was the most significant one as it opened the door for 3rd party vendors to supply
video, printer, modem, disk drive, and RS 232 serial adapter cards.
–Generic PC: A computer with inter-changable components manufactured by a variety of companies
Microcontroller is an entire computer on a chip, a microprocessor with on-chip memory and I/O.
–These parts are designed into (embedded within) a product and run a program which never changes
–Home appliances, modern automobiles, heat, air-conditioning control, navigation systems
–Intel’s MCS-51 family, for example, is based on an 8-bit microprocessor, but features up to 32K
bytes of on-board ROM, 32 individually programmable digital input/output lines, a serial
communications channel.

More Information

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8086 Pin Layout

MAXIMUM MINIMUM
MODE MODE

GND 1 40 Vcc
AD14 AD15
AD13 A16,S3
AD12 A17,S4
AD11 A18,S5
AD10 A19,S6
AD9 /BHE,S7
AD8 MN,/MX
AD7 /RD
AD6 /RQ,/GT0 HOLD
AD5
8086 /RQ,/GT1 HLDA
AD4 /LOCK /WR
AD3 /S2 IO/M
AD2 /S1 DT/R
AD1 /S0 /DEN
AD0 QS0 ALE
NMI QS1 /INTA
INTR /TEST
CLK READY
GND 20 21 RESET

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8086 and 8088 Pin Layout

MAXIMUM MINIMUM
MAXIMUM MINIMUM
MODE MODE
MODE MODE
GND 1 40 Vcc
GND 1 40 Vcc
A14 A15
AD14 AD15
A13 A16,S3
AD13 A16,S3
A12 A17,S4
AD12 A17,S4
A11 A18,S5
AD11 A18,S5
A10 A19,S6
AD10 A19,S6
A9 high /SS0
AD9 /BHE,S7
A8 MN,/MX
AD8 MN,/MX
AD7 /RD
AD7 /RD
AD6 /RQ,/GT0 HOLD
AD6 /RQ,/GT0 HOLD 8088
AD5
8086 /RQ,/GT1 HLDA
AD5 /RQ,/GT1 HLDA
AD4 /LOCK /WR
AD4 /LOCK /WR
AD3 /S2 IO/M
AD3 /S2 IO/M
AD2 /S1 DT/R
AD2 /S1 DT/R
AD1 /S0 /DEN
AD1 /S0 /DEN
AD0 QS0 ALE
AD0 QS0 ALE
NMI QS1 /INTA
NMI QS1 /INTA
INTR /TEST
INTR /TEST
CLK READY
CLK READY
GND 20 21 RESET
GND 20 21 RESET

Data sheet Pin Definition

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8086/8088 Functional Units

Bus Interface
Unit(BIU)
Execution Unit
Fetches Opcodes,
(EU)
Reads Operands,
Writes Data

8086/8088 MPU

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8086/8088 Internal Organisation

EU BIU

Address Bus 20 bits

AH AL SUMMATION

BH BL
Data Bus

CH CL
CS
DH DL
DS
SP
SS
BP
ES
DI
IO
BI
Internal Bus
Communications Control
Registers
8088 Bus

Temporary
Registers

Instruction Queue

ALU
EU
Control
1 2 3 4

Flags

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8086/8088 units

• 8086/8088 consists of two internal units

– The execution unit (EU) - executes the
instructions
– The bus interface unit (BIU) - fetches
instructions, reads operands and writes results
• The 8086 has a 6B pre-fetch queue
• The 8088 has a 4B pre-fetch queue

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BIU Elements
• Instruction Queue: the next instructions or data can be
fetched from memory while the processor is executing
the current instruction
– The memory interface is slower than the processor execution
time so this speeds up overall performance
• Segment Registers:
– CS, DS, SS and ES are 16b registers
– Used with the 16b Base registers to generate the 20b address
– Allow the 8086/8088 to address 1MB of memory
– Changed under program control to point to different segments as
a program executes
• Instruction Pointer (IP) contains the Offset Address of
the next instruction, the distance in bytes from the
address given by the current CS register
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 i8086 Circuit - Minimum Mode
QIAU

Vcc

S0#
8284A CLK S1#
Clock READY S2#
Generator RESET DEN
RDY DT/R#
8086
CPU
Vcc MN/MX#
ALE LE
OE#
BHE# 74LS373
AD15:AD0 A19:A0,
x3
ADDR/DATA BHE#
A19:A16
INTR

DIR
EN#
74LS245
74LS245 D15:D0
x2
ADDR/Data x2

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i8086 Circuit - Maximum Mode (Can be used in Multi Processor)

Vcc CLK MRDC#

MWTC#
S0# AMWC#
S1#
8288
8284A CLK IORC#
S2# Bus
Clock READY IOWC#
Generator Controller
RESET AIOWC#
DEN
RDY DT/R# INTA#
8086 ALE
CPU
MN/MX#
LE
OE#
BHE# 74LS373
AD15:AD0 A19:A0,
x3
ADDR/DATA BHE#
A19:A16
INTR

DIR
EN#
74LS245
74LS245 D15:D0
x2
ADDR/Data x2

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Memory configuration in Use of BHE# / A0(BLE#)

Byte-Wide addressing
ODD Addresses (8086) EVEN Addresses (8086)
(8088)
FFFFF FFFFF FFFFE
FFFFE FFFFD FFFFC
FFFFD FFFFB FFFFA
FFFFC FFFF9 FFFF8

A19..A1 A19..A1

00002 00005 00004

00001 00003 00002
00000 00001 00000

D15:D8 D7:D0

BHE# A0/BLE#
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Memory control signals

Use of BHE#/BLE# (Minimum/Maximum)
BHE# A0/BLE# Selection
0 0 Whole word (16-bits)
0 1 High byte to/from odd address
1 0 Low byte to/from even address
1 1 No selection

Use of S4/S3(Minimum)
S4 S3 Selection
0 0 Extra
0 1 Stack
1 0 Code
1 1 Data

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 ALE and Address/data Bus Multiplexing

• 8086/8 Multiplexes the Address and Data

signals onto the same set of pins
• Need off-chip logic to separate the signals
• Transparent latches designed just for
address de-multiplexing

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 ALE and 74HC373 Transparent Latch
Clock

Address/
Address Data Time
Data
Time
Bus

ALE

Output of
Microcomputer AddressBus
74HC373

74HC373 or equivalent

Address/
System Address Bus
Data Bus In0:In7 Q0:Q7

ALE
LE
OE#

TriState Control signal, OE#, shown

connected to GND for simplicity

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 Use of ALE (Address Latch Enable)
• ALE is used with an external latch
(74HC373) to demultiplex the address and
data lines
• 74HC373 is transparent when its LE input
(connected to ALE) is high
• When ALE goes low, the ‘373 holds the last
data until ALE goes high again

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8288 Bus Controller and Bus Transceivers
8288 Bus Controller also
generates Direction and
8288 Enable signals for Bi-
Bus Controller Directional Transeivers
DEN# Supports Buffering the
DT/R# System Data Bus
EN#
DIR
DIR

CPU [D15:D8] 74HC245 Buffered [D15:D8]

To Memory and I/O

Systems
EN#
DIR

CPU [D7:D0] 74HC245 Buffered [D7:D0]

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8086 Read Cycle

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8086 Write Cycle

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8086 Read Cycle (1 Wait State)

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Thank you kind attention!

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