SCLS034F − DECEMBER 1982 − REVISED NOVEMBER 2004

D Wide Operating Voltage Range of 2 V to 6 V SN54HC132 . . . J OR W PACKAGE

SN74HC132 . . . D, DB, N, NS, OR PW PACKAGE
D Outputs Can Drive Up To 10 LSTTL Loads (TOP VIEW)
D Low Power Consumption, 20-µA Max ICC
D Typical tpd = 14 ns 1A 1 14 VCC
D ±4-mA Output Drive at 5 V 1B 2 13 4B
1Y 3 4A
D Low Input Current of 1 µA Max 4
12
2A 11 4Y
D Operation From Very Slow Input 2B 5 10 3B
Transitions 2Y 6 9 3A
D Temperature-Compensated Threshold GND 7 8 3Y
Levels
D High Noise Immunity SN54HC132 . . . FK PACKAGE
D Same Pinouts as ’HC00 (TOP VIEW)

VCC
NC
1B
1A

4B
description/ordering information
3 2 1 20 19
Each circuit functions as a NAND gate, but 1Y 4 18 4A
because of the Schmitt action, it has different input NC 5 17 NC
threshold levels for positive- and negative-going 2A 6 16 4Y
signals. The ’HC132 devices perform the Boolean NC 7 15 NC
function Y = A • B or Y = A + B in positive logic. 2B 8 14 3B
9 10 11 12 13
These circuits are temperature compensated and
can be triggered from the slowest of input ramps

2Y

3Y
3A
GND
NC
and still give clean jitter-free output signals.
NC − No internal connection

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
PDIP − N Tube of 25 SN74HC132N SN74HC132N
Tube of 50 SN74HC132D
SOIC − D Reel of 2500 SN74HC132DR HC132
Reel of 250 SN74HC132DT
−40°C
−40 C to 85
85°C
C SOP − NS Reel of 2000 SN74HC132NSR HC132
SSOP − DB Reel of 2000 SN74HC132DBR HC132
Tube of 90 SN74HC132PW
TSSOP − PW Reel of 2000 SN74HC132PWR HC132
Reel of 250 SN74HC132PWT
CDIP − J Tube of 25 SNJ54HC132J SNJ54HC132J
−55°C
−55 C to 125
125°C
C CFP − W Tube of 150 SNJ54HC132W SNJ54HC132W
LCCC − FK Tube of 55 SNJ54HC132FK
SNJ54HC132FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

   !"#$ % &'!!($ #%  )'*+&#$ ,#$(- Copyright  2004, Texas Instruments Incorporated
!,'&$% &!" $ %)(&&#$% )(! $.( $(!"%  (/#% %$!'"($%  )!,'&$% &")+#$ $ 34 #++ )#!#"($(!% #!( $(%$(,
%$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( '+(%% $.(!0%( $(,-  #++ $.(! )!,'&$% )!,'&$
$(%$2  #++ )#!#"($(!%- )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2  #++ )#!#"($(!%-

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1



 
  
 


  

SCLS034F − DECEMBER 1982 − REVISED NOVEMBER 2004

FUNCTION TABLE
(each gate)
INPUTS OUTPUT
A B Y
H H L
L X H
X L H

logic diagram (positive logic)

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

SN54HC132 SN74HC132
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 2 5 6 2 5 6 V
VI Input voltage 0 VCC 0 VCC V
VO Output voltage 0 VCC 0 VCC V
TA Operating free-air temperature −55 125 −40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265



 
  
 


  

SCLS034F − DECEMBER 1982 − REVISED NOVEMBER 2004

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
TA = 25°C SN54HC132 SN74HC132
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
2V 0.7 1.2 1.5 0.7 1.5 0.7 1.5
VT+ 4.5 V 1.55 2.5 3.15 1.55 3.15 1.55 3.15 V
6V 2.1 3.3 4.2 2.1 4.2 2.1 4.2
2V 0.3 0.6 1 0.3 1 0.3 1
VT− 4.5 V 0.9 1.6 2.45 0.9 2.45 0.9 2.45 V
6V 1.2 2 3.2 1.2 3.2 1.2 3.2
2V 0.2 0.6 1.2 0.2 1.2 0.2 1.2
VT+ − VT− 4.5 V 0.4 0.9 2.1 0.4 2.1 0.4 2.1 V
6V 0.5 1.3 2.5 0.5 2.5 0.5 2.5
2V 1.9 1.998 1.9 1.9
IOH = −20 µA 4.5 V 4.4 4.499 4.4 4.4
VOH VI = VIH or VIL 6V 5.9 5.999 5.9 5.9 V
IOH = −4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = −5.2 mA 6V 5.48 5.8 5.2 5.34
2V 0.002 0.1 0.1 0.1
IOL = 20 µA 4.5 V 0.001 0.1 0.1 0.1
VOL VI = VIH or VIL 6V 0.001 0.1 0.1 0.1 V
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6V 0.15 0.26 0.4 0.33
II VI = VCC or 0 6V ±0.1 ±100 ±1000 ±1000 nA
ICC VI = VCC or 0, IO = 0 6V 2 40 20 µA
Ci 2 V to 6 V 3 10 10 10 pF

switching characteristics over recommended operating free-air temperature range, CL = 50 pF

(unless otherwise noted) (see Figure 1)
FROM TO TA = 25°C SN54HC132 SN74HC132
PARAMETER VCC UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
2V 60 120 186 156
tpd A or B Y 4.5 V 18 25 37 31 ns
6V 14 21 32 27
2V 28 75 110 95
tt Any 4.5 V 8 15 22 19 ns
6V 6 13 19 16

operating characteristics, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance per gate No load 20 pF

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3



 
  
 


  

SCLS034F − DECEMBER 1982 − REVISED NOVEMBER 2004

PARAMETER MEASUREMENT INFORMATION

From Output Test VCC

Under Test Point Input 50% 50%
0V
CL = 50 pF
(see Note A) tPLH tPHL

In-Phase VOH
90% 90%
Output 50% 50%
LOAD CIRCUIT 10% 10%
VOL
tr tf
tPHL tPLH
VCC
90% 90% VOH
Input 50% 50% Out-of-Phase 90% 90%
10% 10% 0 V 50% 50%
Output 10% 10%
VOL
tr tf tf tr

VOLTAGE WAVEFORM VOLTAGE WAVEFORMS

INPUT RISE AND FALL TIMES PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

NOTES: A. CL includes probe and test-fixture capacitance.

B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time, with one input transition per measurement.
D. tPLH and tPHL are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OPTION ADDENDUM
www.ti.com 18-Jul-2006

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
5962-89845022A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-8984502CA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
5962-8984502DA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
5962-8984502VCA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
5962-8984502VDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
SN54HC132J ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
SN74HC132D ACTIVE SOIC D 14 50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC132DBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI
SN74HC132DBR ACTIVE SSOP DB 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC132DBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC132DE4 ACTIVE SOIC D 14 50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC132DG4 ACTIVE SOIC D 14 50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC132DR ACTIVE SOIC D 14 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC132DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC132DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC132DT ACTIVE SOIC D 14 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC132DTE4 ACTIVE SOIC D 14 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC132N ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
SN74HC132NE4 ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
SN74HC132NSR ACTIVE SO NS 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC132NSRE4 ACTIVE SO NS 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC132PW ACTIVE TSSOP PW 14 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC132PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC132PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI
SN74HC132PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC132PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC132PWT ACTIVE TSSOP PW 14 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC132PWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM
www.ti.com 18-Jul-2006

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
SNJ54HC132FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54HC132J ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
SNJ54HC132W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
SNV54HC132J ACTIVE CDIP J 14 TBD Call TI Call TI
SNV54HC132W ACTIVE CFP W 14 TBD Call TI Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 2
 MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

NO. OF A B
18 17 16 15 14 13 12
TERMINALS
** MIN MAX MIN MAX

0.342 0.358 0.307 0.358

19 11 20
(8,69) (9,09) (7,80) (9,09)
20 10 0.442 0.458 0.406 0.458
28
(11,23) (11,63) (10,31) (11,63)
21 9
B SQ 0.640 0.660 0.495 0.560
22 8 44
(16,26) (16,76) (12,58) (14,22)
A SQ
23 7 0.739 0.761 0.495 0.560
52
(18,78) (19,32) (12,58) (14,22)
24 6
0.938 0.962 0.850 0.858
68
(23,83) (24,43) (21,6) (21,8)
25 5
1.141 1.165 1.047 1.063
84
(28,99) (29,59) (26,6) (27,0)
26 27 28 1 2 3 4

0.020 (0,51) 0.080 (2,03)

0.010 (0,25) 0.064 (1,63)

0.020 (0,51)
0.010 (0,25)

0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)

0.028 (0,71) 0.045 (1,14)

0.022 (0,54) 0.035 (0,89)
0.050 (1,27)

4040140 / D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30
0,65 0,10 M
0,19
14 8

0,15 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25
1 7
0°– 8°
A 0,75
0,50

Seating Plane

1,20 MAX 0,15 0,10

0,05

PINS **
8 14 16 20 24 28
DIM

A MAX 3,10 5,10 5,10 6,60 7,90 9,80

A MIN 2,90 4,90 4,90 6,40 7,70 9,60

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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