   
 



SLCS114E − NOVEMBER 1983 − REVISED JULY 2008

D Single or Dual-Supply Operation TLC372C, TLC372I, TLC372M, TLC372Q

D, P, OR PW PACKAGE
D Wide Range of Supply Voltages 2 V to 18 V TLC372M . . . JG PACKAGE
D Low Supply Current Drain (TOP VIEW)
150 µA Typ at 5 V
1OUT VCC
D Fast Response Time . . . 200 ns Typ for
1 8
1IN − 2 7 2OUT
TTL-Level Input Step
1IN + 3 6 2IN −
D Built-in ESD Protection GND 4 5 2IN +
D High Input Impedance . . . 1012 Ω Typ
D Extremely Low Input Bias Current TLC372M . . . FK PACKAGE
5 pA Typ (TOP VIEW)
D Ultrastable Low Input Offset Voltage

1OUT
D

VDD
Input Offset Voltage Change at Worst-Case

NC

NC

NC
Input Conditions Typically 0.23 µV/Month,
Including the First 30 Days 3 2 1 20 19
NC NC
D Common-Mode Input Voltage Range 4 18
1IN − 5 17 2OUT
Includes Ground
NC 6 16 NC
D Output Compatible With TTL, MOS, and 1IN + 7 15 2IN −
CMOS NC
NC 8 14
D Pin-Compatible With LM393 9 10 11 12 13

GND

2IN+
NC

NC

NC
description
This device is fabricated using LinCMOS
NC − No internal connection
technology and consists of two independent
voltage comparators, each designed to operate TLC372M
from a single power supply. Operation from dual U PACKAGE
supplies is also possible if the difference between (TOP VIEW)
the two supplies is 2 V to 18 V. Each device
features extremely high input impedance NC 1 10 NC
(typically greater than 1012 Ω), allowing direct 1OUT 2 9 VCC
interfacing with high-impedance sources. The 1IN− 3 8 2OUT
outputs are n-channel open-drain configurations 1IN+ 4 7 2IN−
and can be connected to achieve positive-logic GND 5 6 2IN+
wired-AND relationships.
The TLC372 has internal electrostatic discharge
(ESD) protection circuits and has been classified symbol (each comparator)
with a 1000-V ESD rating using human body
model testing. However, care should be exercised IN +
in handling this device as exposure to ESD may
OUT
result in a degradation of the device parametric
performance. IN −

The TLC372C is characterized for operation from 0°C to 70°C. The TLC372I is characterized for operation from
−40°C to 85°C. The TLC372M is characterized for operation over the full military temperature range of −55°C
to 125°C. The TLC372Q is characterized for operation from − 40°C to 125°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

LinCMOS is a trademark of Texas Instruments Incorporated. All other trademarks are the property of their respective owners.

 

 
      !" #$ Copyright  1983−2008, Texas Instruments Incorporated
#     %  
& 
## '($ # ) #  "( "#
)  "" $

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1




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SLCS114E − NOVEMBER 1983 − REVISED JULY 2008

equivalent schematic (each comparator)

Common to All Channels
VDD

OUT

GND
IN + IN −

AVAILABLE OPTIONS(1)
PACKAGED DEVICES
VIO max SMALL CHIP CERAMIC PLASTIC CERAMIC
TA TSSOP
AT 25°C OUTLINE CARRIER DIP DIP FLAT PACK
(PW)
(D)(2) (FK) (JG) (P) (U)
0°C to 70°C 5 mV TLC372CD — — TLC372CP TLC372CPW —
−40°C to 85°C 5 mV TLC372ID — — TLC372IP — —
−55°C to 125°C 5 mV TLC372MD TLC372MFK TLC372MJG TLC372MP — TLC372MU
−40°C to 125°C 5 mV TLC372QD — — TLC372QP — —
1. For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web
site at www.ti.com.
2. The D packages are available taped and reeled. Add R suffix to device type (e.g., TLC372CDR).

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265




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SLCS114E − NOVEMBER 1983 − REVISED JULY 2008

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 18 V
Output voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Duration of output short circuit to ground (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Package thermal impedance, θJA (see Notes 6 and 7): D package . . . . . . . . . . . . . . . . . . . . . . . . . . 97.1°C/W
P package . . . . . . . . . . . . . . . . . . . . . . . . . . 84.6°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W
Package thermal impedance, θJC (see Notes 6 and 7): FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6°C/W
JG package . . . . . . . . . . . . . . . . . . . . . . . . . 14.5°C/W
U package . . . . . . . . . . . . . . . . . . . . . . . . . . 14.7°C/W
Operating free-air temperature range, TA: TLC372C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TLC372I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
TLC372M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
TLC372Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, P, or PW package . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG or U package . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 3. All voltage values except differential voltages are with respect to network ground.
4. Differential voltages are at IN+ with respect to IN −.
5. Short circuits from outputs to VDD can cause excessive heating and eventual device destruction.
6. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
7. The package thermal impedance is calculated in accordance with JESD 51-7 (plastic) or MIL-STD-883 Method 1012 (ceramic).

recommended operating conditions

TLC372C TLC372I TLC372M TLC372Q
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
Supply voltage, VDD 3 16 3 16 4 16 4 16 V
VDD = 5 V 0 3.5 0 3.5 0 3.5 0 3.5
Common-mode input voltage, VIC V
VDD = 10 V 0 8.5 0 8.5 0 8.5 0 8.5
Operating free-air temperature, TA 0 70 −40 85 −55 125 −40 125 °C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

 4
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
TLC372C TLC372I TLC372M, TLC372Q
PARAMETER TEST CONDITIONS TA† UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX



25°C 1 5 1 5 1 5
VIO Input offset voltage VIC = VICRmin, See Note 4 mV
Full range 6.5 7 10
25°C 1 1 1 pA
IIO Input offset current
MAX 0.3 1 10 nA
25°C 5 5 5 pA
IIB Input bias current
MAX 0.6 2 20 nA
0 to 0 to 0 to
25°C VDD −1 VDD −1 VDD −1
Common-mode input
VICR voltage range V
0 to 0 to 0 to
Full range VDD −1.5 VDD −1.5 VDD −1.5
SLCS114E − NOVEMBER 1983 − REVISED JULY 2008

VOH = 5 V 25°C 0.1 0.1 0.1 nA

IOH High-level output current VID = 1 V
VOH = 15 V Full range 1 1 3 µA
Template Release Date: 7−11−94

25°C 150 400 150 400 150 400

VOL Low-level output voltage VID = − 1 V, IOL = 4 mA mV
Full range 700 700 700
IOL Low-level output current VID = − 1 V, VOL = 1.5 V 25°C 6 16 6 16 6 16 mA

Supply current 25°C 150 300 150 300 150 300

IDD VID = 1 V, No load µA
(two comparators) Full range 400 400 400
† All characteristics are measured with zero common-mode input voltage unless otherwise noted. Full range is 0°C to 70°C for TLC372C, − 40°C to 85°C for TLC372I, and − 55°C to

**  *
*




125°C for TLC372M and − 40°C to 125°C for TLC372Q. IMPORTANT: See Parameter Measurement Information.
NOTE 8: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-kΩ resistor between the output and VDD. They can
be verified by applying the limit value to the input and checking for the appropriate output state.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics, VDD = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

RL connected to 5 V through 5.1 kΩ, CL = 15 pF ‡, 100-mV input step with 5-mV overdrive 650
Response time ns
See Note 5 TTL-level input step 200
‡ CL includes probe and jig capacitance.
NOTE 9: The response time specified is the interval between the input step function and the instant when the output crosses 1.4 V.



   
 



SLCS114E − NOVEMBER 1983 − REVISED JULY 2008

electrical characteristics at specified free-air temperature, VDD = 5 V, TA = 25°C (unless otherwise

noted)
TLC372Y
PARAMETER TEST CONDITIONS† UNIT
MIN TYP MAX
VIO Input offset voltage VIC = VICRmin, See Note 4 1 5 mV
IIO Input offset current 1 pA
IIB Input bias current 5 pA
0 to
VICR Common-mode input voltage range VDD −1 V

IOH High-level output current VID = 1 V, VOH = 5 V 0.1 nA

VOL Low-level output voltage VID = − 1 V, IOL = 4 mA 150 400 mV
IOL Low-level output current VID = − 1 V, VOL = 1.5 V 6 16 mA
IDD Supply current (two comparators) VID = 1 V, No load 150 300 µA
† All characteristics are measured with zero common-mode input voltage unless otherwise noted. IMPORTANT: See Parameter Measurement
Information.
NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-kΩ resistor
between the output and VDD. They can be verified by applying the limit value to the input and checking for the appropriate output state.

PARAMETER MEASUREMENT INFORMATION

The digital output stage of the TLC372 can be damaged if it is held in the linear region of the transfer curve.
Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to force
the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the
following alternatives for measuring parameters such as input offset voltage, common-mode rejection, etc., are
offered.
To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown
in Figure 1(a). With the noninverting input positive with respect to the inverting input, the output should be high. With
the input polarity reversed, the output should be low.
A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can
be slewed as shown in Figure 1(b) for the VICR test, rather than changing the input voltages, to provide greater
accuracy.
5V
1V

5.1 kΩ
+ 5.1 kΩ
+
−
−
Applied VIO
Applied VIO
Limit
VO Limit
VO
−4 V

(a) VIO WITH VIC = 0 (b) VIO WITH VIC = 4 V

Figure 1. Method for Verifying That Input Offset Voltage is Within Specified Limits

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5




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SLCS114E − NOVEMBER 1983 − REVISED JULY 2008

PARAMETER MEASUREMENT INFORMATION

A close approximation of the input offset voltage can be obtained by using a binary search method to vary the
differential input voltage while monitoring the output state. When the applied input voltage differential is equal, but
opposite in polarity, to the input offset voltage, the output changes states.
Figure 2 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the
comparator into the linear region. The circuit consists of a switching-mode servo loop in which U1a generates a
triangular waveform of approximately 20-mV amplitude. U1b acts as a buffer, with C2 and R4 removing any residual
dc offset. The signal is then applied to the inverting input of the comparator under test, while the noninverting input
is driven by the output of the integrator formed by U1c through the voltage divider formed by R9 and R10. The loop
reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which
can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input
exactly equals the input offset voltage.
Voltage divider R9 and R10 provides a step up of the input offset voltage by a factor of 100 to make measurement
easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is
suggested that their tolerance level be 1% or lower.
Measuring the extremely low values of input current requires isolation from all other sources of leakage current and
compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage
can be measured with no device in the socket. Subsequently, this open-socket leakage value can be subtracted from
the measurement obtained with a device in the socket to obtain the actual input current of the device.
C3
VDD R5 0.68 µF
1.8 kΩ, 1%

U1b
1/4 TLC274C
C2 R6 U1c
+ Buffer 1 µF 5.1 kΩ 1/4 TLC274CN
−
− DUT
R7 VIO
R4
1 MΩ + (X100)
R1 47 kΩ
240 kΩ R8 Integrator
1.8 kΩ, 1% C4
U1a 0.1 µF
−
1/4 TLC274CN
C1 + Triangle
0.1 µF Generator R9
10 kΩ, 1%
R10
R2 100 Ω, 1%
R3 10 kΩ
100 kΩ

Figure 2. Circuit for Input Offset Voltage Measurement

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265




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SLCS114E − NOVEMBER 1983 − REVISED JULY 2008

PARAMETER MEASUREMENT INFORMATION

Response time is defined as the interval between the application of an input step function and the instant when the
output reaches 50% of its maximum value. Response time, low-to-high level output, is measured from the leading
edge of the input pulse, while response time, high-to-low level output, is measured from the trailing edge of the input
pulse. Response-time measurement at low input signal levels can be greatly affected by the input offset voltage. The
offset voltage should be balanced by the adjustment at the inverting input as shown in Figure 3, so that the circuit
is just at the transition point. Then a low signal, for example 105-mV or 5-mV overdrive, causes the output to change
state.
VDD

5.1 kΩ 1 µF
Pulse
Generator
DUT
50 Ω

1V CL
(see Note A)
Input Offset Voltage 10 Ω
Compensation Adjustment 10 Turn 1 kΩ
−1 V
0.1 µF

TEST CIRCUIT

Overdrive 100 mV
Overdrive
Input Input

100 mV

90% 90%

ÁÁÁ
50% 50%
Low-to-High- High-to-Low-
Level Output 10% Level Output 10%

tr tf
tPLH tPHL

VOLTAGE WAVEFORMS
NOTE A: CL includes probe and jig capacitance.

Figure 3. Response, Rise, and Fall Times Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7




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SLCS114E − NOVEMBER 1983 − REVISED JULY 2008

PRINCIPLES OF OPERATION

LinCMOS process
The LinCMOS process is a Linear polysilicon-gate complementary-MOS process. Primarily designed for
single-supply applications, LinCMOS products facilitate the design of a wide range of high-performance
analog functions, from operational amplifiers to complex mixed-mode converters.
While digital designers are experienced with CMOS, MOS technologies are relatively new for analog designers.
This short guide is intended to answer the most frequently asked questions related to the quality and reliability
of LinCMOS products. Further questions should be directed to the nearest Texas Instruments field sales office.

electrostatic discharge
CMOS circuits are prone to gate oxide breakdown when exposed to high voltages even if the exposure is only
for very short periods of time. Electrostatic discharge (ESD) is one of the most common causes of damage to
CMOS devices. It can occur when a device is handled without proper consideration for environmental
electrostatic charges, e.g. during board assembly. If a circuit in which one amplifier from a dual operational
amplifier is being used and the unused pins are left open, high voltages tends to develop. If there is no provision
for ESD protection, these voltages may eventually punch through the gate oxide and cause the device to fail.
To prevent voltage buildup, each pin is protected by internal circuitry.
Standard ESD-protection circuits safely shunt the ESD current by providing a mechanism whereby one or more
transistors break down at voltages higher than the normal operating voltages but lower than the breakdown
voltage of the input gate. This type of protection scheme is limited by leakage currents which flow through the
shunting transistors during normal operation after an ESD voltage has occurred. Although these currents are
small, on the order of tens of nanoamps, CMOS amplifiers are often specified to draw input currents as low as
tens of picoamps.
To overcome this limitation, Texas Instruments design engineers developed the patented ESD-protection circuit
shown in Figure 4. This circuit can withstand several successive 1-kV ESD pulses, while reducing or eliminating
leakage currents that may be drawn through the input pins. A more detailed discussion of the operation of Texas
Instruments’s ESD- protection circuit is presented on the next page.
All input and output pins on LinCMOS and Advanced LinCMOS products have associated ESD-protection
circuitry that undergoes qualification testing to withstand 1000 V discharged from a 100-pF capacitor through
a 1500-Ω resistor (human body model) and 200 V from a 100-pF capacitor with no current-limiting resistor
(charged device model). These tests simulate both operator and machine handling of devices during normal
test and assembly operations.
VDD
R1
Input To Protected Circuit

R2

Q1
Q2

D1 D2 D3

VSS

Figure 4. LinCMOS ESD-Protection Schematic

Advanced LinCMOS is a trademark of Texas Instruments Incorporated.

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265




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SLCS114E − NOVEMBER 1983 − REVISED JULY 2008

PRINCIPLES OF OPERATION

input protection circuit operation

Texas Instruments’ patented protection circuitry allows for both positive-and negative-going ESD transients.
These transients are characterized by extremely fast rise times and usually low energies, and can occur both
when the device has all pins open and when it is installed in a circuit.

positive ESD transients

Initial positive charged energy is shunted through Q1 to VSS. Q1 turns on when the voltage at the input rises
above the voltage on the VDD pin by a value equal to the VEB of Q1. The base current increases through R2
with input current as Q1 saturates. The base current through R2 forces the voltage at the drain and gate of Q2
to exceed its threshold level (VT ~ 22 V to 26 V) and turn Q2 on. The shunted input current through Q1 to VSS
is now shunted through the n-channel enhancement-type MOSFET Q2 to VSS. If the voltage on the input pin
continues to rise, the breakdown voltage of the zener diode D3 is exceeded, and all remaining energy is
dissipated in R1 and D3. The breakdown voltage of D3 is designed to be 24 V to 27 V, which is well below the
gate oxide voltage of the circuit to be protected.

negative ESD transients

The negative charged ESD transients are shunted directly through D1. Additional energy is dissipated in R1
and D2 as D2 becomes forward biased. The voltage seen by the protected circuit is −0.3 V to −1 V (the forward
voltage of D1 and D2).

circuit-design considerations
LinCMOS products are being used in actual circuit environments that have input voltages that exceed the
recommended common-mode input voltage range and activate the input protection circuit. Even under normal
operation, these conditions occur during circuit power up or power down, and in many cases, when the device
is being used for a signal conditioning function. The input voltages can exceed VICR and not damage the device
only if the inputs are current limited. The recommended current limit shown on most product data sheets is
± 5 mA. Figure 5 and Figure 6 show typical characteristics for input voltage versus input current.
Normal operation and correct output state can be expected even when the input voltage exceeds the positive
supply voltage. Again, the input current should be externally limited even though internal positive current limiting
is achieved in the input protection circuit by the action of Q1. When Q1 is on, it saturates and limits the current
to approximately 5-mA collector current by design. When saturated, Q1 base current increases with input
current. This base current is forced into the VDD pin and into the device IDD or the VDD supply through R2
producing the current limiting effects shown in Figure 5. This internal limiting lasts only as long as the input
voltage is below the VT of Q2.
When the input voltage exceeds the negative supply voltage, normal operation is affected and output voltage
states may not be correct. Also, the isolation between channels of multiple devices (duals and quads) can be
severely affected. External current limiting must be used since this current is directly shunted by D1 and D2 and
no internal limiting is achieved. If normal output voltage states are required, an external input voltage clamp is
required (see Figure 7).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9




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SLCS114E − NOVEMBER 1983 − REVISED JULY 2008

PRINCIPLES OF OPERATION

circuit-design considerations (continued)

INPUT CURRENT INPUT CURRENT

vs vs
POSITIVE INPUT VOLTAGE NEGATIVE INPUT VOLTAGE
8 −10
TA = 25°C TA = 25°C
7 −9

−8
6
−7
Input Current (mA)

Input Current (mA)

5
−6

4 −5

3 −4

−3
2
−2
1
−1

0 0
VDD VDD + 4 VDD + 8 VDD + 12 −0.3 −0.5 −0.7 −0.9
Input Voltage (V) Input Voltage (V)

Figure 5 Figure 6
VDD
Positive Voltage Input Current Limit:
+VI − VDD − 0.3 V
RI =
5 mA
RI RL Negative Voltage Input Current Limit:
VI +
| − VI | − 0.3 V
RI =
TLC372 5 mA
See Note A Vref −

NOTE A: If the correct output state is required when the negative input is less than GND, a schottky clamp is required.

Figure 7. Typical Input Current-Limiting Configuration for a LinCMOS Comparator

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
5962-87658012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-8765801PA ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type
5962-9554901NXD ACTIVE SOIC D 8 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
5962-9554901NXDR ACTIVE SOIC D 8 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC372CD ACTIVE SOIC D 8 75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC372CDG4 ACTIVE SOIC D 8 75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC372CDR ACTIVE SOIC D 8 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC372CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC372CP ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
TLC372CPE4 ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
TLC372CPSR ACTIVE SO PS 8 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC372CPSRG4 ACTIVE SO PS 8 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC372CPW ACTIVE TSSOP PW 8 150 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC372CPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC372CPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI
TLC372CPWR ACTIVE TSSOP PW 8 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC372CPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC372ID ACTIVE SOIC D 8 75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC372IDG4 ACTIVE SOIC D 8 75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC372IDR ACTIVE SOIC D 8 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC372IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC372IP ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
TLC372IPE4 ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
TLC372MD ACTIVE SOIC D 8 75 TBD CU NIPDAU Level-1-220C-UNLIM
TLC372MDG4 ACTIVE SOIC D 8 75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC372MDR ACTIVE SOIC D 8 2500 TBD CU NIPDAU Level-3-245C-168 HR
TLC372MDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
TLC372MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
TLC372MJG ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type
TLC372MJGB ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type
TLC372MP ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
TLC372MUB ACTIVE CFP U 10 1 TBD A42 SNPB N / A for Pkg Type
TLC372QD ACTIVE SOIC D 8 75 TBD CU NIPDAU Level-1-220C-UNLIM
TLC372QDG4 ACTIVE SOIC D 8 75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC372QDR ACTIVE SOIC D 8 2500 TBD CU NIPDAU Level-1-220C-UNLIM
TLC372QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TLC372, TLC372M :

• Enhanced Product: TLC372-EP
NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION
www.ti.com 22-Jul-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 (mm) B0 (mm) K0 (mm) P1 W Pin1
Type Drawing Diameter Width (mm) (mm) Quadrant
(mm) W1 (mm)
5962-9554901NXDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC372CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC372CPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
TLC372CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TLC372IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION
www.ti.com 22-Jul-2008

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
5962-9554901NXDR SOIC D 8 2500 346.0 346.0 29.0
TLC372CDR SOIC D 8 2500 340.5 338.1 20.6
TLC372CPSR SO PS 8 2000 346.0 346.0 33.0
TLC372CPWR TSSOP PW 8 2000 346.0 346.0 29.0
TLC372IDR SOIC D 8 2500 340.5 338.1 20.6

Pack Materials-Page 2
 MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30
0,65 0,10 M
0,19
14 8

0,15 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25
1 7
0°– 8°
A 0,75
0,50

Seating Plane

1,20 MAX 0,15 0,10

0,05

PINS **
8 14 16 20 24 28
DIM

A MAX 3,10 5,10 5,10 6,60 7,90 9,80

A MIN 2,90 4,90 4,90 6,40 7,70 9,60

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

NO. OF A B
18 17 16 15 14 13 12
TERMINALS
** MIN MAX MIN MAX

0.342 0.358 0.307 0.358

19 11 20
(8,69) (9,09) (7,80) (9,09)
20 10 0.442 0.458 0.406 0.458
28
(11,23) (11,63) (10,31) (11,63)
21 9
B SQ 0.640 0.660 0.495 0.560
22 8 44
(16,26) (16,76) (12,58) (14,22)
A SQ
23 7 0.739 0.761 0.495 0.560
52
(18,78) (19,32) (12,58) (14,22)
24 6
0.938 0.962 0.850 0.858
68
(23,83) (24,43) (21,6) (21,8)
25 5
1.141 1.165 1.047 1.063
84
(28,99) (29,59) (26,6) (27,0)
26 27 28 1 2 3 4

0.020 (0,51) 0.080 (2,03)

0.010 (0,25) 0.064 (1,63)

0.020 (0,51)
0.010 (0,25)

0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)

0.028 (0,71) 0.045 (1,14)

0.022 (0,54) 0.035 (0,89)
0.050 (1,27)

4040140 / D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 MECHANICAL DATA

MCER001A – JANUARY 1995 – REVISED JANUARY 1997

JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE

0.400 (10,16)
0.355 (9,00)

8 5

0.280 (7,11)
0.245 (6,22)

1 4
0.065 (1,65)
0.045 (1,14)

0.063 (1,60) 0.310 (7,87)

0.020 (0,51) MIN
0.015 (0,38) 0.290 (7,37)

0.200 (5,08) MAX

Seating Plane

0.130 (3,30) MIN

0.023 (0,58)
0°–15°
0.015 (0,38)
0.100 (2,54) 0.014 (0,36)
0.008 (0,20)

4040107/C 08/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 MECHANICAL DATA

MPDI001A – JANUARY 1995 – REVISED JUNE 1999

P (R-PDIP-T8) PLASTIC DUAL-IN-LINE

0.400 (10,60)
0.355 (9,02)
8 5

0.260 (6,60)
0.240 (6,10)

1 4
0.070 (1,78) MAX

0.325 (8,26)
0.020 (0,51) MIN
0.300 (7,62)

0.015 (0,38)

Gage Plane
0.200 (5,08) MAX
Seating Plane

0.125 (3,18) MIN 0.010 (0,25) NOM

0.100 (2,54) 0.430 (10,92)

MAX
0.021 (0,53)
0.010 (0,25) M
0.015 (0,38)

4040082/D 05/98

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001

For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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