Department of Computer

Science & Engineering

LAB MANUAL

DIGITAL ELECTRONICS LAB

21ECH-101

B.E. – 1st & 2nd

Semester

Chandigarh University
Gharuan, Mohali
 Vision of the Department
To be recognized as a leading Computer Science and Engineering department through effective
teaching practices and excellence in research and innovation for creating competent
professionals with ethics, values and entrepreneurial attitude to deliver service to society and
to meet the current industry standards at the global level.

Mission of the Department

M1: To provide practical knowledge using state-of-the-art technological support for the
experiential learning of our students.

M2: To provide industry recommended curriculum and transparent assessment for quality
learning experiences.
M3: To create global linkages for interdisciplinary collaborative learning and research.
M4: To nurture advanced learning platform for research and innovation for students’
profound future growth.
M5: To inculcate leadership qualities and strong ethical values through value based
education.

Program Educational Objectives (PEOs)

PEO 1: To produce computer science graduate engineers with an ability to comprehend,
understand and analyze real life problems for providing sustainable solutions teams in
the light of disruptive technologies.
PEO 2: To inculcate life-long learning skills in graduates preparing them for work in changing
environments and multidisciplinary teams in order to enhance their capability being
globally employable.
PEO 3: To instill leadership qualities in graduates with a sense of confidence, professionalism
and ethical attitude to produce professional leaders for serving the society.
PEO 4: To make the graduates adaptable to changing career opportunities who have the
potential to excel in industry/ public sector/ higher studies or entrepreneurship
exhibiting global competitiveness.
 PROGRAM SPECIFIC OUTCOMES (PSOs)

A Graduate of Computer Science and Engineering Program will be able:

PSO 1. To acquire proficiency in developing and implementing efficient solutions using

emerging technologies, platforms and Free and Open-Source Software (FOSS).

PSO 2. To gain critical understanding of hardware and software tools catering to the
contemporary needs of IT industry.

Program Outcomes (POs):

PO-1: Engineering Knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals and an engineering specialization to the solution of complex engineering
problems.
PO-2: Problem Analysis: Identify, formulate, review research literature and analyze complex
engineering problems reaching substantiated conclusions using first principles mathematics,
natural sciences and engineering sciences.
PO-3: Design/Development of Solutions: Design solutions for complex engineering
problems and design system components or processes that meet the specified needs with
appropriate consideration for the public health and safety and the cultural, societal, and
environmental considerations.
PO-4: Conduct investigations of Complex Problems: Use research-based knowledge and
research methods including design of experiments, analysis and interpretation of data and
synthesis of the information to provide valid conclusions.
PO-5: Modern Tool Usage: Create, select, and apply appropriate techniques, resources and
modern engineering and IT tools including prediction and modeling to complex engineering
activities with an understanding of the limitations.
PO-6: The Engineer and Society: Apply reasoning informed by the contextual knowledge to
assess societal, health, safety, legal and cultural issues and the consequent responsibilities
relevant to the professional engineering practice.
PO-7: Environment and Sustainability: Understand the impact of the professional
engineering solutions in societal and environmental contexts, and demonstrate the knowledge
of, and need for sustainable development.
PO-8: Ethics: Apply ethical principles and commit to professional ethics and responsibilities
and norms of the engineering practice.
PO-9: Individual and Teamwork: Function effectively as an individual, and as a member or
leader in diverse teams, and in multidisciplinary settings.
PO-10: Communication: Communicate effectively on complex engineering activities with
the engineering community and with society at large, such as, being able to comprehend and
write effective reports and design documentation, make effective presentations, and give and
receive clear instructions.
PO-11: Project Management and Finance: Demonstrate knowledge and understanding of
the engineering and management principles and apply these to one's own work, as a member
and leader in a team, to manage projects and in multidisciplinary environments.
PO-12: Life-long Learning: Recognize the need for, and have the preparation and ability to
engage in independent and life-long learning in the broadest context to technological change.
 2ECH-101: Digital Electronics Lab
Course Objective
1. To understand Merits of digitization.
2. To enable learners to understand common forms of number representation
in digital electronic circuits and to be able to convert between different
representations.
3. To impart knowledge about various digital circuits and designing of systems

Course Outcomes
At the end of the course, a student will be able to:

CO1 To identify the different types of digital circuits and their difference and to
illustrate the various types of gates.

CO2 To understand the various elements of digital system and to implement their
applications.

CO3 To illustrate the relation between Combinational & Sequential Circuits and to
apply for practical applications.

CO4 To solve the basic problems related to different types of digital circuits and to
calculate it using various numerical problems.

CO5 To create different hardware and software based digital applications.

List of Experiments
1. Validation of truth tables of logic gates (7400, 7402, 7404, 7408, 7432, and 7486).
2. (a) Design a burglar alarm (AND).
(b) Design a single doorbell ringer for both front and back doors (OR).
(c) Design an automatic fan controller (NOT).
3. (a) Design a two-way switch for room light (XOR).
(b) Design a multiplayer game trigger mechanism (NOR).
4. Design and realize a given function using K-maps and verify its performance.
5. To design and verify operation of half adder and full adder.
6. Design an 8-sensor data acquisition system using multiplexer.
7. Design a home appliance control system with 3-to-8 decoder.
8. Design a traffic light system using D Flip-Flop.
9. Design of a Shift Register Circuit using IC 74HC595.
10. Design a light based object counter with 7-segmentdisplay.
 Mapped
Experiment
Experiment Name with CO
Number
Number(s)

Validation of truth tables of logic gates (7400, 7402,

1 CO1,CO2
7404, 7408, 7432,and 7486).

a. Design a burglar alarm (AND)

b. Design a single doorbell ringer for both front and
2 CO1,CO2
back doors (OR)
c. Design an automatic fan controller (NOT).
a. Design a two-way switch for room light (XOR).
3 b. Design a multiplayer game trigger mechanism CO1,CO2
(NOR).
Design and realize a given function using K-maps and
4 CO1, CO2
verify its performance.
To design and verify operation of half adder and full
5 CO3,CO4
adder.
Design a multiple sensor data acquisition system
6 CO3,CO4
using multiplexer.
Design a home appliance control system with 3-to-8
7 CO3,CO4
decoder.
8 Design a traffic light system using D Flip-Flop. CO4,CO5

9 Design of a Shift Register Circuit using IC 74HC595. CO4,CO5

Design a light based object counter with 7-
10 CO4,CO5
segmentdisplay.
 CO PO Mapping
PO PO PO PO PO PO PO PO PO PO PO PO
PSO1 PSO2
1 2 3 4 5 6 7 8 9 10 11 12

CO1 3 3 3 3 3

CO2 3 3 3 3

CO3 3 3 2 3 2

CO4 3 3 2 3 3 2

CO5 3 3 3 3 3
 Electrical Safety Precautions
1. Use voltmeters and test equipment with ratings and leads sufficient to measure the
highest potential voltage to be found inside the equipment being serviced.
2. Shoes must be worn at all times.
3. Remove all loose conductive jewelry and trinkets, including rings, which may come in
contact with exposed circuits. (Do not wear long loose ties or other loose clothing around
machines)
4. Consider all circuits to be hot unless proven otherwise.
5. When making measurements, form the habit of using only one hand at a time. No part of
a live circuit should be touched by bare hand.
6. Keep the body or any part of it out of the circuit. Where interconnecting wires and cables
are involved, they should be arranged so people will not trip over them.
7. Be as neat as possible. Keep the work area and workbench clear of items not used in the
experiment.
8. Always check to see if the power switch is OFF before plugging into the outlet. Also,
turn instrument or equipment OFF before unplugging from the outlet.
9. When unplugging a power cord, pull on the plug and not the cable.
10. When disassembling a circuit, first remove the source of power.
11. No ungrounded electrical or electronic apparatus is to be used in the laboratory unless it
is double insulated or battery operated.
12. Keep fluids, chemicals and beat away from instruments and circuits.
13. Report any damages to equipment, hazards and potential hazards to the laboratory
instructor.
14. If in doubt about electrical safety, see the laboratory instructor. Regarding specific
equipment, consult the instruction manual provided by the manufacturer of the
equipment.
15. Information regarding safe use and possible hazards should be studied carefully.
Guidelines for Conduct and Evaluation of Digital Electronics Lab
Conduct: The subject is aimed at inculcating skills amongst students which builds up requisites
in achieving outcomes of the course. In order to impart skills efficiently, the course is broken
down into theoretical discussions tagged along with practical implementation of the concepts
simultaneously. A revision of tasks has to be done every semester as per the requirements
of current industry standards and job requirements which will be monitored and
approved by experts in the field. The following guidelines have to be followed for smooth &
efficient conduct:
1. The sessions will be held in labs with students seated in groups ( maximum 3 in a group)
2. Each group shall have the access to internet and requisite hardware for every task.
3. Every session shall start with discussion on mapping of respective contents to course
outcome and its benefits for skill updating as per job requirements.
4. The session should be initiated with a brief review of previous session, followed by
discussion of scheduled topic.
5. Every discussion session has to be followed by a practical task performance &
troubleshooting session which can be elaborated as per requirements.
6. A proper timeline of evaluation elements should be communicated to students on timely
and periodic basis.
7. All evaluation elements must be strictly designed to promote logic building.
8. Every practical/programming/design task of Evaluation has to be strictly designed to
address real-world problems.
9. Students are allowed to access different resource materials (books/internet/notes/
datasheets etc.) while they appear for Evaluation.
10. Evaluation criterion for the same is given below:

Execution of the Experiment (12)

1. Set up the connections on kit properly.
2. Identify the number of inputs & outputs.
3. Taking outputs for various inputs.
Record of Experiment (10)
1. Proper identification of inputs & outputs of circuit.
2. Connections of Bread board kit.
3. Briefly describe the operation with observation table.
4. Important Recommendations and Conclusion.
Viva-Voce (8)
1. Experiment related Theory.
2. Important components and connections.

Note: - Assessment will be based on the level of competence attained by the student in
subject knowledge and operational skill of the experiment.
 Experiment – 1
Aim: Validation of truth tables of logic gates (NAND, NOR, AND, OR, NOT, XOR).
Apparatus: Tinkercad, Windows 10 PC
Theory

One of the most important functions of the CPU in a computer is to perform logical operations
by utilizing hardware like Integrated Circuits, electronic circuits and software technologies.
For a simple operation, computers utilize binary digits rather than digital digits. Binary
information is represented in digital computers by physical quantities called signals. Electrical
signals such as voltages exist throughout the computer in either one of the two recognizable
states. The two states represent a binary variable that can be equal to 1 or 0. For example, a
particular digital computer may employ a signal of 3 volts to represent binary 1 and 0.5 volt to
represent binary 0. Now the input terminals of digital circuits will accept binary signals of only
3 and 0.5 volts to represent binary input and output corresponding to 1 and 0, respectively. So
now we know, that at core level, computer communicates in the form of 0 and 1, which is
nothing but low and high voltage signals.

Binary logic deals with binary variables and with operations that assume a logical meaning. It
is used to describe, in algebraic or tabular form, the manipulation done by logic circuits called
gates. Gates are blocks of hardware that produce graphic symbol and its operation can be
described by means of an algebraic expression. The input-output relationship of the binary
variables for each gate can be represented in tabular form by a truth-table. Digital logic gates
may have more than one input, (A, B, C, etc.) but generally only have one digital output, (Q).
Individual logic gates can be connected together to form combinational or sequential circuits,
or larger logic gate functions.

A good example of a digital state is a simple light switch. The switch can be either “ON” or
“OFF”, one state or the other, but not both at the same time. Then we can summarise the
relationship between these various digital states as being:

Boolean Algebra Boolean Logic Voltage State

Logic “1” TRUE (T) HIGH (H)
Logic “0” FALSE (F) LOW (L)

The various logical gates are:

 AND
 OR
 NOT
 NAND
 NOR
 XOR

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Logic AND Gate

The output state of a digital logic AND gate only returns “LOW” again when ANY of its inputs
are at a logic level “0”. In other words for a logic AND gate, any LOW input will give a LOW
output. The logic or Boolean expression given for a digital logic AND gate is that for Logical
Multiplication which is denoted by a single dot or full stop symbol, (.) giving us the Boolean
expression of: A.B  Q . Then we can define the operation of a digital 2-input logic AND gate
as being:

“If both A and B are true, then Q is true”

Logic OR Gate

The output, Q of a “Logic OR Gate” only returns “LOW” again when ALL of its inputs are at
a logic level “0”. In other words for a logic OR gate, any “HIGH” input will give a “HIGH”,
logic level “1” output. The logic or Boolean expression given for a digital logic OR gate is that
for Logical Addition which is denoted by a plus sign, (+) giving us the Boolean expression of:
A  B  Q . Then we can define the operation of a 2-input logic OR gate as being:

“If either A or B is true, then Q is true”

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Logic NOT Gate

Inverting NOT gates are single input devicse which have an output level that is normally at
logic level “1” and goes “LOW” to a logic level “0” when its single input is at logic level “1”,
in other words it “inverts” (complements) its input signal. The output from a NOT gate only
returns “HIGH” again when its input is at logic level “0” giving us the Boolean expression of:
A  Q . Then we can define the operation of a single input digital logic NOT gate as being:

“If A is NOT true, then Q is true”

Logic NAND Gate

The NAND (Not – AND) gate has an output that is normally at logic level “1” and only goes
“LOW” to logic level “0” when ALL of its inputs are at logic level “1”. The Logic NAND Gate
is the reverse or “Complementary” form of the AND gate. The logic or Boolean expression
given for a logic NAND gate is that for Logical Addition, which is the opposite to the AND
gate, and which it performs on the complements of the inputs. The Boolean expression for a
logic NAND gate is denoted by a single dot or full stop symbol, (.) with a line or Overline, (‾‾)
over the expression to signify the NOT or logical negation of the NAND gate giving us the
Boolean expression of: A.B  Q . Then we can define the operation of a 2-input digital logic
NAND gate as being:

“If either A or B are NOT true, then Q is true”

3
Logic NOR Gate

The inclusive NOR (Not-OR) gate has an output that is normally at logic level “1” and only
goes “LOW” to logic level “0” when ANY of its inputs are at logic level “1”. The Logic NOR
Gate is the reverse or “Complementary” form of the inclusive OR gate. The logic or Boolean
expression given for a logic NOR gate is that for Logical Multiplication which it performs on
the complements of the inputs. The Boolean expression for a logic NOR gate is denoted by a
plus sign, (+) with a line or Overline, (‾‾) over the expression to signify the NOT or logical
negation of the NOR gate giving us the Boolean expression of: A  B  Q . Then we can
definethe operation of a 2-input digital logic NOR gate as being:

“If both A and B are NOT true, then Q is true”

Exclusive-OR Gate

The output of an Exclusive-OR gate ONLY goes “HIGH” when its two input terminals are at
“DIFFERENT” logic levels with respect to each other. An odd number of logic “1’s” on its
inputs gives a logic “1” at the output. These two inputs can be at logic level “1” or at logic level
“0” giving us the Boolean expression of: Q  ( A  B)  A.B  A.B

The applications of logic gates are mainly determined based upon their truth table, i.e., their
mode of operations. The basic logic gates are used in many circuits like a push-button lock,
light-activated burglar alarm, safety thermostat, an automatic watering system, etc.

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Schematic Diagrams

Figure 1. Logic AND Gate

Figure 2. Logic OR Gate

Figure 3. Logic NOT Gate

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 Figure 4. Logic NAND Gate

Figure 5. Logic NOR Gate

Figure 6. Logic EX-OR (XOR) Gate

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Result

The truth tables of logic gates NAND, NOR, AND, NOT, OR, XOR were verified using
simulations.

References

https://www.electronics-tutorials.ws/logic/logic_1.html

https://www.studytonight.com/computer-architecture/logic-gates

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 Experiment – 2
Aim:

(a) Design a burglar alarm (AND).

(b) Design a single doorbell ringer for both front and back doors (OR).
(c) Design an automatic fan controller (NOT).
Apparatus:
7404 (NOT) IC, 7408 (AND) IC, 7432 (OR) IC, 5V Power Supply, Breadboard, Connecting
wires, Tinkercad, Windows 10 PC
Design
Integrated circuits or ICs for short (sometimes just referred to as “chips” are specialized
circuits that serve a huge variety of purposes, such as controlling a robot's motors or making
LEDs respond to music. Many ICs come in something called a dual in-line package, or DIP,
meaning they have two parallel rows of pins. The gap in the middle of a breadboard (between
columns E and F) is just the right width for an IC to fit, straddling the gap, with one set of pins
in column E, and one set of pins in column F. Projects that use ICs will always tell you to
connect them to the breadboard in this manner.

All ICs are polarized, and every pin is unique in terms of both location and function. This
means the package has to have some way to convey which pin is which. Most ICs will use
either a notch or a dot to indicate which pin is the first pin.

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 (a) Burglar Alarm using AND gate

An AND gate gives an output of logic 1 when input A AND input B are at logic 1, i.e., when

the alarm switch is ON and the sensor detects a person, only then the Alarm will ring, otherwise
it will not ring in any of the other cases.

Figure 1. 7408 IC Pinout

AND gates are available in IC packages. The 7408 IC (Figure 1) is a well-known QUAD 2-
Input AND gates IC and contains four independent gates each of which performs the logic
AND function.
In order to design the burglar alarm, the alarm switch which is a SPST (toggle) switch and the
person sensor made from LDR, is used. The schematic of the circuit is shown as below, in
Figure 2.

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 Figure 2. Schematic for burglar alarm.

(a) Single doorbell ringer for both front and back doors, using OR gate.

The Logic OR Gate is a type of digital logic circuit whose output goes HIGH to a logic level 1
only when one or more of its inputs are HIGH. It is required that doorbell should ring, when
someone presses either the front door switch or the back door switch.

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 Figure 3. 7432 IC Pinout.
OR gates are available in IC packages. The 7432 IC (Figure 3) is a well-known QUAD 2-Input
OR gates IC and contains four independent gates each of which performs the logic OR function.
In order to implement the doorbell ringer (Figure 4), the SPST (toggle) switches are used as
inputs to the OR gate, the output of OR gate is attached to a Buzzer which will ring when any
one of the switch is pressed.

Figure 4. Schematic of doorbell ringer.

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(b) Design an automatic fan controller (NOT).

The Logic NOT Gate is the most basic of all the logical gates and is often referred to as an
Inverting Buffer or simply an Inverter. It is required to control the central heating/fan to turn
on/off according to the temperature threshold.

Figure 5. 7404 IC Pinout

Each 7404 NOT gate IC has 6 NOT gates arranged as shown in the Figure 5. 14th pin is the
VCC (+5V) and the 7th pin is the GND (Ground). In order to implement the experiment, the
temp sensor input needs to be given to the input terminal of any one of the NOT gate inside
this IC, and the output actuator can be driven from the output terminal of the same gate.

Figure 6. Schematic of NOT gate circuit.

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Result

The integrated circuits and their connections on the breadboard were studied and implemented.
The practical applications of logic gates (AND, OR & NOT) were studied and implemented.

References

https://www.electronics-tutorials.ws/logic/logic_1.html

https://www.studytonight.com/computer-architecture/logic-gates

https://electronicsforu.com/resources/learn-electronics/not-gate-ic-7400-tutorials

https://learn.sparkfun.com/tutorials/integrated-circuits/all

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 Experiment – 3
Aim:

(a) Design a two-way switch for room light (XOR).

(b) Design a multiplayer game trigger mechanism (NOR).
Apparatus:
7400 (NAND) IC, 7402 (NOR) IC, 7486 (XOR) IC, 5V Power Supply, Breadboard,
Connecting wires, Tinkercad, Windows 10 PC
Design
(a) Two-way switch for room light using XOR gate
The Exclusive-OR logic function is a very useful circuit that can be used in many different
types of computational circuits. There are two other types of digital logic gates which although
they are not a basic gate in their own right as they are constructed by combining together other
logic gates, their output Boolean function is important enough to be considered as complete
logic gates. These two “hybrid” logic gates are called the Exclusive-OR (Ex-OR) Gate and its
complement the Exclusive-NOR (Ex-NOR) Gate. The output of an Exclusive-OR gate ONLY
goes “HIGH” when its two input terminals are at “DIFFERENT” logic levels with respect to
each other. An odd number of logic “1’s” on its inputs gives a logic “1” at the output. These
two inputs can be at logic level “1” or at logic level “0” giving us the Boolean expression of:
Q  A  B  A.B  A.B

The Exclusive-OR Gate function, or Ex-OR for short, is achieved by combining standard logic
gates together to form more complex gate functions that are used extensively in building
arithmetic logic circuits, computational logic comparators and error detection circuits. The
Exclusive-OR Gate is widely available as a standard quad two-input 74LS86 TTL gate or the
4030B CMOS package.

A two-way light switch turns on the light to be switched from any station. This means that at
any time, either switch may be upside-down so that it's on in the down position or off in the up
position. The lighting circuits that save time, like the light switch in the kitchen that switches
the light in the garage off, and the same circuit can be switched off at the front end of the

6
garage, saving you having to return to the kitchen. Another application would be the light on
the stairway on different floors, saving you from having to go up or downstairs to get the
switch.

(b) Multiplayer game trigger using NOR gate

The Logic NOR Gate is a combination of the digital logic OR gate and an inverter or NOT gate
connected together in series. he inclusive NOR (Not-OR) gate has an output that is normally at
logic level “1” and only goes “LOW” to logic level “0” when ANY of its inputs are at logic
level “1”. The Logic NOR Gate is the reverse or “Complementary” form of the inclusive OR
gate. The NOR gate can also be classed as a “Universal” type gate. NOR gates can be used to

6
produce any other type of logic gate function just like the NAND gate and by connecting them
together in various combinations the three basic gate types of AND, OR and NOT function can
be formed using only NOR gates.

In order to implement the multiplayer game trigger mechanism, it required to initiate the game
when the detection of both the players competing in the game as present at the designated
completing stations. The circuit for the same is given below.

Result

The practical applications of logic gates (NAND, NOR & XOR) were studied and
implemented.

References

https://www.electronics-tutorials.ws/logic/logic_1.html

https://www.studytonight.com/computer-architecture/logic-gates

https://electronicsforu.com/resources/learn-electronics/not-gate-ic-7400-tutorials

https://learn.sparkfun.com/tutorials/integrated-circuits/all

EXPERIMENT 4

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Aim: Design and realize a given function using K-maps and verify its performance.

Apparatus: 7486 (XOR) IC, 5V Power Supply, Breadboard, Connecting wires, Simulation
software, Windows 10 PC

Design:

Canonical Forms (Normal Forms): Any Boolean function can be written in disjunctive normal
form (sum of min-terms) or conjunctive normal form (product of max- terms). A Boolean
function can be represented by a Karnaugh map in which each cell corresponds to a minterm.
The cells are arranged in such a way that any two immediately adjacent cells correspond to two
minterms of distance 1. There is more than one way to construct a map with this property.

Karnaugh Maps

2-Variable K-Map
The number of cells in 2 variables K-map is four, since the number of variables is two. The
following figure shows 2 variables K-Map.

There is only one possibility of grouping 4 adjacent min terms.

The possible combinations of grouping 2 adjacent min terms are {(m0, m1), (m2, m3), (m0,
m2) and (m1, m3)}.
3-Variable K-Map
The number of cells in 3 variable K-map is eight, since the number of variables is three. The
following figure shows 3 variable K-Map.

There is only one possibility of grouping 8 adjacent min terms.

The possible combinations of grouping 4 adjacent min terms are {(m0, m1, m3, m2), (m4, m5,
m7, m6), (m0, m1, m4, m5), (m1, m3, m5, m7), (m3, m2, m7, m6) and (m2, m0, m6, m4)}.
The possible combinations of grouping 2 adjacent min terms are {(m0, m1), (m1, m3), (m3,
m2), (m2, m0), (m4, m5), (m5, m7), (m7, m6), (m6, m4), (m0, m4), (m1, m5), (m3, m7) and
(m2, m6)}.
If x=0, then 3 variable K-map becomes 2 variable K-map.
Four Variable K-Map
The number of cells in 4 variables K-map is sixteen, since the number of variables is four. The
following figure shows 4 variables K-Map.

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There is only one possibility of grouping 16 adjacent min terms.

Realization of Boolean Expression:

F(W, X, Y, Z) = Σm(1, 3, 4, 6, 9, 11, 12, 14)

F (W, X, Y, Z)= (W’X + WX) (Y’Z’ + YZ’) + (W’X’ + WX’) (Y’Z + YZ)
= XZ’ + X’Z
=X⊕Z
Thus, minimized Boolean expression is-
F(W, X, Y, Z) = X ⊕ Z

Fig 1: 7486 IC Pinout

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 Fig 2: Schematic for given expression

PROCEDURE:

Check the components for their working.

Insert the appropriate IC into the IC base.

Make connections as shown in the circuit diagram.

Provide the input data via the input switches and observe the output on output LEDs

Verify the Truth Table

RESULT: Simplified and verified the Boolean function using basic gates and universal gates

References

Datasheet XOR gate- https://www.alldatasheet.com/datasheet-pdf/pdf/247375/RENESAS/HD74LS32P.html

Datasheet led - https://pdf1.alldatasheet.com/datasheet-pdf/view/986384/ROITHNER/LED19.html

https://www.electronics-tutorials.ws/logic/logic_1.html

https://www.studytonight.com/computer-architecture/logic-gates

https://electronicsforu.com/resources/learn-electronics/not-gate-ic-7400-tutorials

https://learn.sparkfun.com/tutorials/integrated-circuits/all

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 EXPERIMENT 5
AIM: To design and verify operation of half adder and full adder.

COMPONENTS REQUIRED: IC 7400, IC 7408, IC 7486, and IC 7432, and IC Trainer Kit.

THEORY:
Half-Adder: A combinational logic circuit that performs the addition of two data bits,
A and B, is called a half-adder. Addition will result in two output bits; one of which is
the sum bit, S, and the other is the carry bit, C. The Boolean functions describing the
half-adder are:

S =A XOR B C=AB

Full-Adder: The half-adder does not take the carry bit from its previous stage into
account. This carry bit from its previous stage is called carry-in bit. A combinational
logic circuit that adds two data bits, A and B, and a carry-in bit, Cin, is called a full-
adder. The Boolean functions describing the full-adder are:

S = (x xor y) xor Cin C = xy + Cin (x xor y)

TO REALIZE HALF ADDER

I. FULL ADDER
 TRUTH TABLE BOOLEAN EXPRESSIONS:

BASIC GATES

PROCEDURE:
 Check the components for their working
 Insert the appropriate IC into the IC base
 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs.

RESULT: The truth table of minimized Boolean expression is verified.

 Experiment 6
Aim: Design a data acquisition system using multiplexer.

Apparatus: MC14052B IC, Resistances (470 ohms,1K ohms,1.5 k ohms,2.2 k ohms), 5V

Power Supply, Breadboard, Connecting wires.

Theory
Data acquisition (DAQ) is the process of measuring an electrical or physical phenomenon such
as voltage, current, temperature, pressure, or sound with a computer. A DAQ system consists of
sensors, DAQ measurement hardware, and a computer with programmable software. Compared
to traditional measurement systems, PC-based DAQ systems exploit the processing power,
productivity, display, and connectivity capabilities of industry-standard computers providing a
more powerful, flexible, and cost-effective measurement solution. In this experiment however,
the focus is on DAQ system as an application of multiplexer & thus it is required to select and
observe reading from any one of the input.

Fig 1: MC14052B IC Pinout

Here the pins X0, X1, X2 and X3 are the four input pins and the pin X is its corresponding
output pin. The control pins A and B are used to select the required input to the output pin. The
Vdd pin (pin 16) has to connect to the supply voltage which is +5V and the Vss and Vee pin
should be grounded. The Vee pin is for enable which is an active low pin so we have to ground
it to enable this IC. The MC14052 is an Analog Multiplexer meaning the input pins can also be
supplied with variable voltage and the same can be obtained though the output pins. The below
GIF image shows how the IC outputs variable input voltage based in the control signals
provided. The input pins have the voltage 1.5V, 2.7V, 3.3V and 4.8V which are also obtained
on the Output pin based on the control signal given.

Schematic Diagram

Fig 2: Schematic Diagram showing the functioning of Multiplexer

We can also assemble this circuit over a breadboard and check if they are working. To do that
we have used two push buttons are inputs for the control pins A and B. And, used a series of
potential divider combinations to provide variable voltages for the pins 12, 14, 15 and 11. The
output pin 13 is connected to an LED. The variable voltages supplied to the LED will make it to
vary the brightness based on the control signals. The circuit once build will look something like
this below:-
Circuit Diagram

Fig 3: Circuit Diagram showing the functioning of Multiplexer.

Result
The Data acquisition system using Multiplexer has been designed and implemented.
 Experiment 7
AIM: Design a home appliance control system with 3-to-8 decoder.

Apparatus: 74LS138 IC, 10K Ohms resistances, LED’s, +5v Power Supply, Bread Board
,Connecting Wires.

Theory:

74LS138 is a member from ‘74xx’family of TTL logic gates. The chip is designed
for decoding or de-multiplexing applications and comes with 3 inputs to 8 output setup. The
design is also made for the chip to be used in high-performance memory-decoding or data-
routing applications, requiring very short propagation delay times. In high performance memory
systems these decoders can be used to minimize the effects of system decoding. The three
enable pins of chip (in which Two active-low and one active-high) reduce the need for external
gates or inverters when expanding.

Fig 1: 74LS138 Decoder Pinout

Overview of 74LS138 Decoder

As mentioned earlier the chip is specifically designed to be used in high-performance memory-
decoding or data-routing applications which require very short propagation delay times. The
memory unit data exchange rate determines the performance of any application and the delays
of any kind are not tolerable there. In such applications using 74LS138 line decoder is ideal
because the delay times of this device are less than the typical access time of the memory. This
means that the effective system delay introduced by the decoder is negligible to affect the
performance.

How to use 74LS138 Decoder

For understanding the working of device let us construct a simple application circuit with a few
external components as shown below.

Fig 2: Home Appliance system design using Decoder

About circuit: Here the outputs are connected to LED to show which output pin goes LOW and
do remember the outputs of the device are inverted. We are using a single device so we will
connect G2A and G2B pin to ground followed by connecting G1 to VCC to enable the chip.
The three buttons here represent three input lines for the device.
For understanding the working let us consider the truth table of the device.

Fig 3: Truth Table of Decoder

H = HIGH, L = LOW and X = Don’t Care
Working of circuit
As shown in table first three rows the enable pins needed to be connected appropriately or
irrespective of input lines all outputs will be high. After connecting the enable pins as shown in
circuit diagram you can use the input line to get the output.
After powering, if all buttons are not pressed Y0 will be LOW and remaining output will be
HIGH as shown in table. After only B1 is pressed, A0=HIGH and Y1 will become LOW while
remaining will be HIGH. Following if only B2 is pressed, A1=HIGH and Y2 will become LOW
while remaining will be HIGH. This way we can realize all the truth table by toggling the three
buttons B1, B2 and B3 (Three inputs A0, A1 and A2) and with that we have three input to eight
output decoder.

Schematic Diagram

Fig 4: Schematic Diagram of home appliance control system using Decoder

Result
Home appliance control system has been Designed and Implemented using 3 to 8 Decoder.
 Experiment – 8
Aim:

Design traffic lights using D Flip Flop.

Apparatus:
555 timer IC (NE555), D flip flop IC (CD4013), 5V Power Supply, Breadboard, Connecting
wires, Proteus software, Windows 10 PC
Design

Pictorial representation
Basically D flops follow the input when the clock is enable i.e. it take enable as a positive edge
trigger and remain in the previous state when clock is disabled.

Initially

Input at flip flop 1 is 0

Input at flip flop 2 is 0

So if you code Q of first flip flop as green led, ̅ of second flip flop as red led and
yellow led is coded to the combination ̅ of first and Q of the second. At the first
positive edge trigger
you give input as 0 to flip flop 1 so the output is also 0 and the output at ̅ which is 1
will actas a positive edge trigger at flip flop 2 which will again give input as 0 to Q of flip
flop 2 so
the output is also 0 and the output at ̅ of flip flop 2 which is 1 will turn ON the
red ledconnected to it.

After first positive edge

Input at flip flop 1 is 1 (equal to ̅ of flip flop 1)

Input at flip flop 2 is 1

At the second positive edge at flip flop 1 the input 1 is given to output Q which is connected to
yellow LED and ̅ turns 0 giving the clk at flip flop 2 a 0, turning the red led OFF.

After second positive edge

Input at flip flop 1 is 0 (equal to ̅ of flip flop

1) Input at flip flop 2 is 1

At the third positive edge at flip flop 1 the input which is 0is given to the output which is also
made 0 and the output at ̅ which is 1 will act as a positive edge trigger at flip flop 2
which will again give input as 1 to Q of flip flop 2. Now Q of flip flop 2 and ̅ of flip flop
1 which are both at 1 will give 1 to the yellow LED turning it on.

And the loop will continue.

Now once led glows make sure that the next positive edge trigger will come after the required
time in other words change the frequency of clock pulse according to your requirement
(you can use 555 timer to generate required clock pulse) so that LED will stays glowing and
after that particular time give 1 as Input at positive edge of the clock the other LED glows and
maintain the same clock freq.

Functional diagram

D flip flop pinout

 Circuit Diagram

Result

The practical applications of D flip flop in designing traffic lights is studied and implemented.

References

https://www.electronics-tutorials.ws/logic/logic_1.html

https://www.studytonight.com/computer-architecture/logic-gates

https://electronicsforu.com/resources/learn-electronics/not-gate-ic-7400-tutorials

https://learn.sparkfun.com/tutorials/integrated-circuits/all
 Experiment 9
Aim:
Design a Shift Register Circuit using IC 74HC595.
Apparatus:
74HC595 Shift Register, LEDs, 220Ω resistors, 1KΩ resistors, 10KΩ resistor, Pushbuttons,
47pF capacitor, Tinkercad Simulator.
Theory:
In this project, we are going to show how to build a shift register circuit wired to pushbuttons so
that we can manually see how a shift register works. Even though shift registers are made to
work with microcontrollers such as an Arduino, and in the commercial industry, you always see
them used with microcontrollers, in this circuit; we take a manual approach so that you can see
exactly how a shift register actually works. Using manual control with pushbuttons is great for
demonstration purposes and sees how shift registers work for those who are beginners with
them. For this circuit, we will have 5 pushbuttons. These pushbuttons will control the serial data
input, the clock line, the latch pin, the output enable pin, and the clear pin. Through manual
control of the shift register, you will know exactly how they work in a way that using it with
microcontrollers can't teach you, because you're actually doing the work yourself. The shift
register we will use is the popular 74HC595 shift register. This IC can control up to 8 outputs.
In this circuit, our output devices will be LEDs. So, one 74HC595 can control 8 LEDs on the
output side.

Fig 1: Shift Register Pinout

The table below summarizes these pin connections:-

Pin Description Function

QA-QH Output pins Outputs of the shift register
VCC (Pin
Power Positive voltage for the shift register
16)
GND (Pin 8) Power Ground for the shift register
Serial out is used to shift data to another 74HC595
QH' (Pin 9) Serial Out
shift register
CLEAR (Pin Master Reclear, This sets all the bits in the shift register to 0 or off
10) active low if pulled LOW.
Shift Clock Shift Register Clock If pulled HIGH, this shift all the values in the shift
(Pin 11) Pin register forward one.
Latch Clock Storage Register When pulled HIGH, it outputs the new shift
(Pin 12) Lock Pin register values.
Output
Output enable, active This enables the output when grounded and
Enable (Pin
low disables it when high.
13)
Serial Data
Input for New Serial
Input (Pin This is the input pin for the new serial data.
Data
14)

Manual Shift Register Circuit:

Fig 2: Manual Shift Register Circuit Design with Push buttons.

Working:
This shift register circuit has pretty basic connections.
First we connect power. So we connect VCC of the shift register to 5V. We connect the ground
of the shift register to the power ground. This establishes sufficient power to the shift register.
Next we connect the clock pin (pin 11) to a pull-down resistor.
We connect the latch pin (pin 12) a pull-down resistor.
We connect the serial data input pin to a pull-down resistor.
Since the Output Enable pin is active low, we want it to be LOW. So we connect it to a pull-
down resistor.
The CLEAR pin is an active low pin, so we want it to be HIGH. Therefore, we connect it to the
5V power source, through a voltage divider. The top resistor is 1KΩ and the bottom resistor is a
10KΩ resistor. This way, the majority of the voltage falls across the 10KΩ resistor; this ensures
that the CLEAR pin is active HIGH. Because the 10KΩ resistor is HIGH, however, the LED
will light dimly, but this is fine for demonstration purposes.
Lastly, we connect the LEDs to the output pins, QA - QH. To each of the LEDs, we connect a
current-limiting 220Ω resistor.
How this circuit works is that we first transfer bits to the storage register. In order to do this, we
need the clock to be HIGH in order to transfer bits to the storage register. If the serial data input
line is LOW while we press the clock pushbutton, a 0 is transferred in to the storage register. If
the serial data input line is HIGH while we press the clock pushbutton, then a 1 is transferred
into the storage register. If you press down the clock pushbutton 8 times while the clock is
HIGH, we will transfer 8 1s into the storage register. If we push down 4 times on the serial data
input line while the clock is HIGH and 4 times on the clock pushbutton while the serial data
input pushbutton is not pressed, this will transfer 11110000 into the storage register.
Now, once you have the data transferred into the storage register, the next step is to latch the
data into the output. First, we transferred data into the storage register, but this data does not
show up at the output (to the LEDs) until we latch it to the output. So once we have the data
transferred to the storage register, we have to latch it. Once we press down on the latch
pushbutton, it now goes to output. Now we see the LEDs light up. If the data in the storage
register is 11111111, all the LEDs will turn on. If the data is 10101010, every other LED will
light up. If the data is 11110000, the first 4 LEDs will light up and the next 4 will be off.
If you want to turn off all the LEDs, you can either press down on the output enable pushbutton
or the CLEAR line. This clears all the 1s in the storage register. Next, you have to press down
the latch pin to see all the LEDs turn off. The CLEAR pin and the output enable pin are not the
same. The CLEAR clears all the 1s to 0s in the storage register. You can then add 1s after. The
output enable pin permanently shuts off all outputs.
Result:
The Shift register has been designed and implemented using push buttons.
 Experiment-10
Aim: Design a light based object counter with 7-segment display (CD4026).
Apparatus:
LDR, CD4026 IC, 7-segment display, 5V Power Supply, Breadboard, Connecting wires,
Proteus software, Windows 10 PC

Design
Object counters or product counters are important applications used in industries, shopping
malls, etc. They count objects or products automatically and so reduce human efforts. They are
used at different places for different purposes and different usages. They can be used as visitor
counter, vehicle counter material/product counter etc. Following are some of the examples
where object counters are used.
 In LIFT to count and display number of persons inside the lift at a particular given time
 In any big super market or shopping malls as a visitor counter, to keep track of the number
of visitors who have visited the Mall.
 On the conveyor belt in the industry to count number of objects passed
 In vehicle parking place to count and display number of vehicles inside the parking lot
Thus the application areas are varied where object counters are used. The object counter is
made up of sensor, counter and display. Sensor senses any object that passes in front of it and
gives output pulse to the counter. Counter increments count by one when it gets pulse input
from sensor. Current count is displayed on any type of display like the 7-segment or LCD
display.

The light source from the torch is continually hit on the LDR if so the resistance of LDR is too
low and the voltage drop across LDR and ground is less than 0.6V. When an object is passed
 between the light beams, light will not hit on the LDR so the resistance of LDR becomes
high. We have V=I x R (Voltage = Current x Resistance) i.e., the resistance of LDR is the
high voltage across LDR become high. As soon as the object crosses the light beam a LOW
and HIGH voltage transition occurs, which is given to the Clock (input) of CD4026 IC, it
will start to count with the clock and display the count on 7- segment display.

Result
The working object counter using LDR, CD4026 and 7-segment was verified on simulation
software, and implemented on breadboard.

References
http://www.studentsheart.com/visitor-counter-using-7-segment-display-ldr/

https://www.scribd.com/doc/82165027/Digital-Object-Counter
https://www.engineersgarage.com/electronic-circuits/2-digit-object-counter