Digital Systems Laboratory Manual: Experiment On Testboard Using Digital Ic

VIET NAM NATIONAL UNIVERSITY HO CHI MINH CITY – UNIVERSITY OF TECHNOLOGY
FACULTY OF ELECTRICAL AND ELECTRONICS ENGINEERING

DEPARTMENT OF ELECTRONICS
--oOo—
DIGITAL SYSTEMS LABORATORY MANUAL

EXPERIMENT ON TESTBOARD USING DIGITAL IC.
ABOUT THE MANUAL
This document is intended to serve as a lab manual for students enrolled in Digital System Lab
at HCMC University of Technology. All the Lab Experiment is designed for students to implement
combinational and sequential systems on testboard, using digital ICs.
There are 4 labs:
Lab 1 – Digital Logic Gates.
Lab 2 – Implementation of Boolean function with Logic Gates.
Lab 3 – Combinational Logic Circuits.
Lab 4 – Sequential Logic Circuits.
In order to complete the lab on time, all students are required to do prelabs before each class.
Electronics Department
Ho Chi Minh City University of Technology, Vietnam
1
Lab1: Digital Logic Gates.
Lab 1: Digital Logic Gates
Objective
- Getting to know digital logic gates and verifying its logic operation.
- Getting familiar with TTL 74LS series IC.
1
I- Examination of AND gate

1. Preliminary information:
- In a logic operation, HIGH (H) level is represented by number “1” and LOW (L) level is
represented by number “0”.
- For TTL ICs, H (1) represents voltage levels between 2,4V and 5V. Similarly, L (0)
represents voltage levels between 0 V and 0,4 V.
- For CMOS ICs, voltage equivalent of H (1) is approximately the supply voltage and L (0)
represents voltage levels between 0V and 0,5 V.
- AND gate is the multiplication gate. It has at least two inputs. At least one “0” input
makes the output “0”. The output is “1” only when all the inputs are “1” (Table 1.1).
- The output of a 2-input AND gate is Y= A . B (Fig. 1.1).
- As can be seen from Fig. 1.2, both TTL IC 7408 and CMOS IC 4081 contain 4 AND
gates.
Fig 1.1: 2-input AND gate.
Table 1.1: The truth table of 2-input

AND gate.
Fig 1.2
2
2. Obtaining The Truth Table Of The AND Gate

- Equipment :
o Analog Discovery Studio
o Integrated Circuits (ICs) : 74LS08, 4081
o Connection wires.
Fig 1.3: Examination of a 2-input AND gate (2_in_and_gate).
Fig 1.4: Examination of a 2-input AND gate – application circuit.
3
- Procedure:
o Construct the circuit [as given in Fig. 1.3 and] as drawn by you in Fig. 1.4 and
apply the power.
o Apply logic 0 (L) to both inputs.
o Using the LEDs investigate whether the output of 2-input AND gate is 1 (H) or 0
(L) and take note of the output in Table 1.2.
o Measure the same output with voltmeter and find the voltage value and take note
of the output voltage in Table 1.2.
o Repeat steps 3 and 4 for all the input values given in Table 1.1 and take note of
the outputs in Table 1.2
Table 1.2
NOTE: DO THE SAME EXPERIMENT AGAIN ON BREARDBOARD BY USING

CMOS IC (4081).
4
II- Examination of NAND gate

- NAND Gate provides the output as exactly inverted form of an AND gate.
- Symbolically this situation is shown with an AND gate having a small circle at the output
(Fig. 2.1).
- The operating principle of a NAND gate can be summarized as; If all inputs are 1(H), the
output is 0
- (L) and if there is even only one 0 (L) level at any of the inputs, the output is 1(H) (Table
2.1).
- As can be seen from Fig. 2.2, both TTL IC 7400 and CMOS IC 4011 contain 4 NAND
gates.
- If all inputs of a NAND gate are connected, it can operate as an inverter.

Fig 2.1: 2-input NAND gate
NAND gate.
Fig 2.2
5
2. Obtaining The Truth Table Of The NAND Gate

- Equipment :
o Connection wires.
Fig 2.3: Examination of a 2-input NAND gate (2_in_and_gate).
Fig 2.4: Examination of a 2-input NAND gate – application circuit.
6
- Procedure:
apply the power.
o Using the LEDs investigate whether the output of 2-input NAND gate is 1 (H) or
0 (L) and take note of the output in 2.2
o Repeat step 3 for all remaining input values given in Table 1.6 and take note of
the outputs in the Table. 2.2
Table 2.2

CMOS IC (4011).
7
3. Using a NAND Gate As An Inverter

- Equipment:
o Connection wires.
Fig 2.5: The use of a NAND gate as an INVERTER.
Fig 2.6: The use of a NAND gate as an INVERTER – application circuit.
8
- Procedure:
apply the power.
o Set the input to logic 0.
o Using the LEDs investigate whether the output of NAND gate Y is 1 (H) or 0 (L)
and take note of the output in Table 2.3.
o Using the LEDs investigate whether the output of NAND gate Y is 1 (H) or 0 (L)
and take note of the output in Table 2.3.
Table 2.3
NOTE: DO THE SAME EXPERIMENT AGAIN ON BREARDBOARD BY USING CMOS IC
(4011).
9
III- Examination of Inverter gate

- An inverter reverses the logical level at the input (if input=0 then output=1; if input=1 then
output=0) (Table 3.1).
- Symbolically this situation is denoted with a small circle at the inputs or outputs (Fig. 3.1).
- Putting a small bar on the top of the letter representing the input or output means reversed
logic.
- This situation is simply named as "NOT".
- As can be seen from Fig. 3.2, both TTL IC 7404 and CMOS IC 4063 contain 6 INVERTER
gates.
Table 3.1: The truth table of the

Fig 3.1: Inverter gate INVERTER gate.
Fig 3.2
10
2. Obtaining The Truth Table Of The Inverter Gate

- Equipment :
o Connection wires.
Fig 3.3: Examination of INVERTER gate
Fig 3.4: Examination INVERTER gate – application circuit.
11
- Procedure:
apply the power.
o Using the LEDs investigate whether the output of INVERTER gate Y is 1 (H) or
0 (L) and take note of the output in Table 3.2.
of the output voltage in Table 3.2
o Using the LEDs investigate whether the output of INVERTER gate Y is 1 (H) or
0 (L) and take note of the output in Table 3.2
of the output voltage in Table 3.2
Table 3.2

CMOS IC (4069).
12
IV- Examination of OR gate

- OR Gate is the addition gate. It has at least two inputs. For any of the inputs' 1 (H) condition
the output will be at level 1(H). Only for all inputs are 0 (L), the output will be 0 (L) (Table
1.15).
- The output of a 2-input OR gate is Y= A+B (Fig. 4.1). The truth table of 2-input OR gate
is given in Table 4.1. .
- TTL IC 74LS32 contains quadruple 2-input TTL OR gates (Fig. 4.2).
-
Fig 4.1: OR gate
OR gate.
Fig 4.2
13
2. Obtaining The Truth Table Of The OR Gate

- Equipment :
o Connection wires.
Fig 4.3: Examination of a 2-input OR gate (2_in_or_gate).
Fig 4.4: Examination of a 2-input OR gate – application circuit.
14
- Procedure:
apply the power.
o Using the LEDs investigate whether the output of 2-input OR gate is 1 (H) or 0
(L) and take note of the output in Table 4.2
o Repeat step 3 for all other input values given in Table 4.1 and take note of the
output in the Table. 4.2.
Table 4.2

CMOS IC (4071).
15
V- Examination of NOR gate

- NOR Gate provides the output as exactly inverted form of an OR Gate.
- Symbolically this situation is shown with an OR gate having a small circle at the output
(Fig. 5.1).
- If any of the inputs is 1 (H) then the output is 0 (L) and when all inputs are 0 (L) then the
output is 1 (H).
- If the inputs of the NOR Gate are connected, it can operate as an inverter ( Table 5.1).
- TTL IC 74LS02 contains quadruple 2-input TTL NOR gates (Fig. 5.2).
Table 5.1: The truth table of 2-

- input NOR gate.
Fig 5.1: NOR gate
Fig 5.2
16
2. Obtaining The Truth Table Of The NOR Gate

- Equipment :
o Connection wires.
Fig 5.3: Examination of a 2-input NOR gate (2_in_or_gate).
Fig 5.4: Examination of a 2-input NOR gate – application circuit.
17
- Procedure:
apply the power.
o Using the LEDs investigate whether the output of 2-input NOR gate is 1 (H) or 0
(L) and take note of the output in Table 5.2
output in the Table. 5.2.
Table 5.2

CMOS IC (4001).
18
3. Using a NOR Gate As An Inverter

- Equipment :
o Integrated Circuits (ICs) : 74LS02
o Connection wires.
Fig 5.5: The use of a NOR gate as an INVERTER (nor_inverter).
Fig 5.6: The use of a NOR gate as an INVERTER – application circuit.
19
- Procedure:
apply the power.
o Using the LEDs investigate whether the output of NOR gate Y is 1 (H) or 0 (L)
and take note of the output in Table 5.3
o Using the LEDs investigate whether the output of NOR gate Y is 1 (H) or 0 (L)
and take note of the output in Table 5.3
A (INPUT) Y (OUTPUT)
1
Table 5.3

CMOS IC (4001).
20
VI- Examination of Exclusive-OR gate

- Input EX-OR gate (Fig. 6.1) compares two bits. If the bits are different from each other
then the output becomes 1 (H). If the bits are the same then the output becomes 0 (L)
(Table 6.1).
- EX-OR gate can be formed not only by the help of other gates but also by standard
integrated circuits.
- These circuits are also called Inequality Comparers
- The parity code, which is an equality code is checked by an EX-OR gate.
- TTL IC 7486 and CMOS IC 4030 contain quadruple 2-input TTL EX-OR gates (Fig. 6.2).
-
Fig 6.1: 2 input EX-OR gate Table 6.1: The truth table of 2-input
EX-OR gate.
Fig 6.2
21
2. Obtaining The Truth Table Of The EX-OR Gate

- Equipment :
o Connection wires.
Fig 6.3: Examination of a 2-input EX-OR gate (2_in_or_gate).
Fig 6.4: Examination of a 2-input Ex-OR gate – application circuit.
22
- Procedure:
apply the power.
o Using the LEDs investigate whether the output of 2-input EX-OR gate is 1 (H) or
0 (L) and take note of the output in Table 6.2
outputs in the Table. 6.2
Table 6.2

CMOS IC (4030).
23
VII- Examination of Exclusive-NOR gate

- Input EX-NOR gate (Fig. 7.1) compares two bits. If the bits are the same then the output
becomes 1(H). If the bits are different from each other, then the output becomes 0 (L).
(Table 7.1).
- EX-NOR is the inverted form of EX-OR.
- EX-NOR gate can be formed not only by the help of other gates but also by standard
integrated circuits.
- The parity code, i.e. equality code, is produced with EX-NOR Gate.
- TTL IC 74HC266 and CMOS IC 4077 contain quadruple 2-input TTL EX-NOR gates (Fig.
7.2). Since the outputs of 74HC266 IC are open-drain, in order to observe a logic signal
from an output it is necessary to connect a pull-up resistor from the output to the power
supply.

Fig 7.1: 2-input EX-NOR gate. EX-NOR gate.
Fig 7.2
24
2. Obtaining The Truth Table Of The EX-NOR Gate

- Equipment :
o Connection wires.
Fig 7.3: Examination of a 2-input EX-NOR gate (2_in_or_gate).
Fig 7.4: Examination of a 2-input Ex-NOR gate – application circuit.
25
- Procedure:
apply the power.
o Using the LEDs investigate whether the output of 2-input EX-NOR gate is 1 (H)
or 0 (L) and take note of the output in Table 7.2
outputs in the Table. 7.2
Table 7.2

CMOS IC (4077)
26
Lab 2: Implementation of Boolean Function with Logic Gates.
Lab 2: Implementation of Boolean Function

with Logic Gates
Objective
- Simplification of Boolean functions by means of Boolean algebra and Karnough maps.
- Implementation of simplified Boolean functions with different logic gate combinations.
27
I- Preliminary Information
- In this experiment the realization (implementation) of Boolean functions (expressions) by
using logic gate integrated circuits (ICs) is investigated. Before the implementation of Boolean
functions, it is necessary to simplify these functions, because simple functions mean the
following: the implementation is more economical, the implementation space will be smaller
and you save power. Therefore it is desirable to simplify Boolean functions. Secondly, the
simplified logic expression is implemented by using logic gate ICs. Finally, all possible
combinations of the inputs are applied as logic 0 and logic 1 and the output values
experimentally are obtained.
- Simplification of Boolean Functions
There are a few well-known methods to simplify Boolean functions, namely by using
Boolean algebra, Karnough maps (K-map) and Quine McCluskey method. It is very difficult
to simplify Boolean functions by using Boolean algebra. Karnough maps solve this problem
in an easy way but they are practical to simplify Boolean functions up to 4 variables. If there
are more than 4 variables in that case Quine McCluskey method is preferred to simplify
Boolean functions.
- 3-Variable Karnough Maps
As can be seen from Fig. 2.1, in a 3-variable Karnough map there are eight minterms
(or maxterms), each of which is represented by a cell within the map. The order of numbers
00, 01, 11 and 10 in the row (left) and column (right) are of Gray code type rather than binary
form. Simplification of a function in a 3-variable K-map is shown in Fig. 2.2.
Fig. 2.1. 3-variable Karnough maps.
28
Fig. 2.2. Simplification of a function in a 3-variable K-map.

- 4-Variable Karnough Maps
As can be seen from Fig. 2.3, in a 4-variable Karnough map there are sixteen
minterms (or maxterms), each of which is represented by a cell within the map. The order of
numbers 00, 01, 11 and 10 in the rows and columns are of Gray code type rather than binary
form. Simplification of two functions in 4- variable K-maps are shown in Fig. 2.4. On the left
(respectively right) a 4-variable Boolean function represented by a sum of minterms
(respectively product of maxterms) is simplified by a 4-variable K-map.
Fig. 2.3 4-variable Karnough maps.
𝑓1(𝑎, 𝑏, 𝑐, 𝑑) = ∑ (0,1,2,4,5,6,8,10,12,13,14,15)
𝑚
29
𝑓2(𝑎, 𝑏, 𝑐, 𝑑) = ∏ (0,1,2,4,5,6,8,10,12,13,14,15)
𝑀
Fig. 2.4 Simplification of two functions in 4-variable K-maps.

- Don’t-Care Conditions
Don’t-care conditions are related with incompletely specified functions. In this case,
the function is not specified for certain combinations of the variables. These combinations
may be assigned either 0 or 1 and they are represented by ‘×’ in a K-map. The following is an
example function, where minterms 0, 2 and 5 are the variable combinations that make the
function equal to 1. The minterms of don’t-care conditions 1, 3 and 7 may be assigned either
0 or 1.
𝑓(𝑎, 𝑏, 𝑐) = ∑ (0,2,5) + ∑ (1,3,7)
𝑚 𝑑
We can simplify the given function 𝑓(𝑎, 𝑏, 𝑐) = ∑𝑚(0,2,5) + ∑𝑑(1,3,7) as shown
in Fig. 2.5. In this example, don’t-care conditions, represented by ‘×’, are all assigned 1.
Fig. 3.5. The simplification of function 𝑓(𝑎, 𝑏, 𝑐) = ∑𝑚(0,2,5) + ∑𝑑(1,3,7) in a 3-variable K-map.
30
Function
𝑓(𝑎, 𝑏, 𝑐) = ∑ (0,2,5) + ∑ (1,3,7)

𝑚 𝑑
Can be represented as follows.
𝑓(𝑎, 𝑏, 𝑐) = ∏ (4,6). ∏ (1,3,7)

𝑀 𝑑
We can simplify the given function 𝑓(𝑎, 𝑏, 𝑐) = ∏𝑀(4,6). ∏𝑑(1,3,7) in a 3-variable

K-map.
A given Boolean function can be implemented in several logic gate forms. In the
following sections these forms are considered.
- Sum of Minterms
For ‘n’ Boolean variables there may be 2n different minterms. Every Boolean
function can be represented as sum of minterms. The binary numbers from 0 to 2n-1 are listed
under the n variables. Each minterm is obtained from an AND term of n variables, with each
variable being primed if the corresponding bit of the binary number is a 0 and unprimed if a
1. Sometimes it is more convenient to express a Boolean function as sum of minterms. If a
function is not in standard sum of minterms form it can be converted into the standard form.
The first step is to represent the function as sum of products. Secondly in this case each
product form (if it is not a standard product) is converted into standard product. For example
if a product term is missing variable ‘a’ or its complement then this term is ANDed with the
term (𝑎 + 𝑎̅ ). Sixteen minterms for four variables, together with their symbolic designation
are listed in Table 2.1
- Product of Maxterms
For ‘n’ Boolean variables there may be 2n different maxterms. Every Boolean function
can be represented as product of maxterms. The binary numbers from 0 to 2n-1 are listed under
the n variables. Each maxterm is obtained from an OR term of n variables, with each variable
being unprimed if the corresponding bit of the binary number is a 0 and primed if a 1.
Sometimes it is more convenient to express a Boolean function as product of maxterms. If a
function is not in standard product of maxterms form it can be converted into the standard form.
The first step is to represent the function as product of sums. Secondly in this case each sum
form (if it is not a standard sum) is converted into a standard sum. For example if a sum term
is missing variable ‘a’ or its complement then this term is ORed with the term 𝑎. 𝑎̅. Sixteen
maxterms for four variables, together with their symbolic designation are listed in Table 2.1.
A function given in a sum of minterms form can be converted into product of maxterms form
and vice versa. For example the function 𝑓(𝑎, 𝑏, 𝑐, 𝑑) = ∑𝑚(0,2,10,11,12,14) is given as
sum of minterms form. This function is converted into product of maxterms form as follows:
𝑓(𝑎, 𝑏, 𝑐, 𝑑) = ∏𝑀(1,3,4,5,6,7,8,9,13,15) As can be seen the total number of distinct terms
31
(minterms and maxterms) for four variables are 16 for a given function when considering its
sum of minterms form and product of maxterms form.
Table 2.1. Minterms and maxterms for four binary variables.
- Possible Implementation Forms of a Boolean Function

It is desirable to simplify a Boolean function before its implementation with logic gates.
A Boolean function can be implemented in ten different forms as can be seen in this section.
Firstly eight of these forms are considered. First two forms are the sum of products form (AND-
OR form) and the product of sums form (OR-AND form). By using the involution law ( 𝑥̅̅ =
𝑥) and De Morgan’s Theorems ( 𝑥 ̅̅̅̅̅̅̅
+ 𝑦 = ̅̅̅̅̅
𝑥. 𝑦 ; ̅̅̅̅̅
𝑥. 𝑦 = 𝑥̅ + 𝑦̅ ) of Boolean algebra, AND-
OR form can be converted into NAND-NAND, OR-NAND and NOR-OR forms as can be
seen from Fig. 2.7. Similarly, OR-AND form can be converted into NOR-NOR, AND-NOR
and NAND-AND forms. It is also possible to convert AND-OR form into OR-AND form and
vice versa. Finally as seen from Fig. 2.7, it is possible to implement a Boolean function in these
eight different forms. Now let’s consider these forms in more detail.
32
Fig. 2.7. 8 possible implementation forms of a Boolean function.
- Equivalents of NAND and NOR Gates

In the previous section eight implementation forms of Boolean functions by using logic
gates are considered. In addition there are two more methods considered here. These methods
are based on equivalents of NAND and NOR gates. NAND gates are one of the two basic logic
gates (along with NOR gates) from which any other logic gate can be built as can be seen from
Table 2.3. These methods can be called as
1. The implementation of a Boolean function by using NAND Equivalents.
2. The implementation of a Boolean function by using NOR Equivalents.
It is assumed that the function to be implemented is given in a simplified form. In the
first method the function is implemented either in the simplified sum of products form with
AND-OR gates (plus inverter – NOT gates) or in the simplified product of sums form with
OR-AND gates (plus inverter – NOT gates). Then, AND, OR and NOT gates used in the
implementation of the function are replaced with their NAND equivalents as shown in Table
2.3. As a result we obtain the implementation of a Boolean function by using NAND
Equivalents. The second method is similar, in which AND, OR and NOT gates used in the
implementation of the function are replaced with their NOR equivalents. Once we obtain the
implementation of a function with NAND or NOR equivalents, in the final step successively
connected two NOT gates can be deleted to further simplify the implementation.
Table 2.3. Equivalents of NAND and NOR gates.
33
34
II- Experiment
1. Implementation of A Boolean Function In AND-OR
- ̅̅̅ + 𝑎̅𝑑 + 𝑎𝑐𝑑̅ in AND-OR
Objective: Implementing a function math 𝑓(𝑎, 𝑏, 𝑐, 𝑑) = 𝑎𝑏
form
- Equipment :
o Integrated Circuits (ICs) : 74LS04, 74LS08, 74LS32
o Connection wires.
Fig 2.1.1 : The implementation of the function 𝑓(𝑎, 𝑏, 𝑐, 𝑑) = 𝑎̅ 𝑏̅ + 𝑎̅𝑑 + 𝑎𝑐𝑑̅ in AND-OR
form
Fig 2.1.2 : The implementation of the function 𝑓(𝑎, 𝑏, 𝑐, 𝑑) = 𝑎̅ 𝑏̅ + 𝑎̅𝑑 + 𝑎𝑐𝑑̅ in AND-OR
35
form – application circuit.
- Procedue:
o Construct the circuit [as given in Fig. 2.1.1 and] as drawn by you in Fig. 2.1.2 and
apply the power.
o Apply all possible combinations to the inputs and obtain and take note of the
outputs in the Table 2.1.
Table 2.1
36
2. Implementation of A Boolean Function In OR-AND

- Objective: Implementing a function math 𝑓(𝑎, 𝑏, 𝑐, 𝑑) = (𝑎̅ + 𝑑̅ )(𝑎̅ + 𝑐)(𝑎 + 𝑏̅ + 𝑑) in
OR-AND form
- Equipment :
o Integrated Circuits (ICs) : 74LS04, 74LS08, 74LS32
o Connection wires.
Fig 2.2.1: The implementation of the function 𝑓(𝑎, 𝑏, 𝑐, 𝑑) = (𝑎̅ + 𝑑̅ )(𝑎̅ + 𝑐)(𝑎 + 𝑏̅ +
𝑑) in OR-AND form
Fig 2.2.2 : The implementation of the function in 𝑓(𝑎, 𝑏, 𝑐, 𝑑) = (𝑎̅ + 𝑑̅ )(𝑎̅ + 𝑐)(𝑎 + 𝑏̅ + 𝑑) in
37
OR-AND form – application circuit.
- Procedue:
o Construct the circuit [as given in Fig. 2.2.1. and] as drawn by you in Fig. 2.2.2
and apply the power.
outputs in the Table 2.2
Table 2.2
38
3. Implementation of A Boolean Function By Using NAND

Equivalents
- Objective: The implementation of the function 𝑓(𝑎, 𝑏, 𝑐) = 𝑎̅𝑏 + 𝑎𝑐̅ by using NAND
equivalents
- Equipment :
o Connection wires.
Fig 2.3.1: The implementation of the function 𝑓(𝑎, 𝑏, 𝑐) = 𝑎̅𝑏 + 𝑎𝑐̅ using NAND
equivalents
Fig 2.3.2 : The implementation of the function in 𝑓(𝑎, 𝑏, 𝑐) = 𝑎̅𝑏 + 𝑎𝑐̅ using NAND equivalents
39
- Procedue:
Table 2.3
40
4. Implementation of A Boolean Function By Using NOR

Equivalents
- Objective: The implementation of the function 𝑓(𝑎, 𝑏, 𝑐) = 𝑎̅𝑏 + 𝑎𝑐̅ by using NOR
equivalents
- Equipment :
o Connection wires.
Fig 2.4.1: The implementation of the function 𝑓(𝑎, 𝑏, 𝑐) = 𝑎̅𝑏 + 𝑎𝑐̅ using NOR
equivalents
Fig 2.4.2 : The implementation of the function in 𝑓(𝑎, 𝑏, 𝑐) = 𝑎̅𝑏 + 𝑎𝑐̅ using NOR equivalents
41
- Procedue:
Table 2.4
42
Lab 3: Implementation of Combinational Logic Circuits.
Lab 3: Combinational logic circuits
Objective:
- Investigating some combinational logic circuits: observing their operation and obtaining their truth table.
- Getting to know IC combinational circuits.
43
I- Binary Adders
Circuits that perform addition, subtraction multiplication and division with binary numbers are called
arithmetic circuits. It seems that there are four operations but actually consecutive additions are performed for
multiplication, consecutive subtractions are performed for division. There are basically two types of addition in
logic circuits. Circuits that perform addition of two bits are called “half adders”, circuits that perform addition
of three bits are called “full adders”.
1. Examination of Half Adder
- Preliminary information: The half adder circuit is shown in Fig. 3.1, and its truth table is provided in
Table 3.1.
Fig. 3.1 The Half Adder Circuit Table 3.1 The truth table of the Half Adder
- Equipment:
o Integrated Circuits (ICs) :
o 2 Điện trở 1 KΩ; 2 LED

o Connection wires.
Fig. 3.2 The Half Adder circuits
44
Fig. 3.3 The Half Adder – Application circuits

Note: Do not forget to connect the Vcc pins to +5 V and the GND pins to ground (GND) connection.
- Procedure:
1) Construct the circuit [as given in Fig. 3.2. and as] drawn by you in Fig. 3.3 and apply the power.
2) Apply all possible combinations to the inputs of the circuit and experimentally obtain the output
values given in Table 3.2 and take note of the outputs in the Table.
Table 3. 2
2. Examination of Full Adder
- Preliminary information:
A full adder is a combinational circuit that performs the arithmetic sum of three input bits. It consists of
three inputs and two outputs. Two of the input variables, denoted by A and B, represent the two significant
bits to be added. The third input, Ci (input carry), represents the carry from previous lower significant
position. Two outputs are S (Sum) and Co (output carry). A full adder can be obtained by connecting two
half adders, as seen from Fig. 3.4. The truth table of the full adder is provided in Table 3.3.
45
Table 3.3 The truth table of the full adder

Fig. 3.4 The Full Adder circuit
- Equipment:
o 2 điện trở 1 KΩ; 2 LED

o Connection wires.
Fig. 3.5 The Full Adder circuits
46
Fig. 3.6 The Half Adder – Application circuits

- Procedure:
1) Construct
Note: the circuit
Do not forget [as given
to connect in Fig.
the Vcc pins3.5. and
to +5 V as]
anddrawn by you
the GND pinsin
to Fig. 3.6 (GND)
ground and connection.
apply the power.
2) Apply all possible combinations to the inputs of the circuit and experimentally
obtain the output values given in Table 3.4 and take note of the outputs in the
Table.
Table 3.4
3. Examination of 4 bit Parallel Adder
Figure 3.6 shows an example of a parallel adder: a 4-bit ripple-carry adder. It is composed
of four fulladders. The augend’s bits of “B” are added to the addend bits of “A” respectfully
of their binary position. Each bit addition produces a sum (S) and a carry out (Co). The carry
out is then transmitted to the carry in (Ci) of the next higher-order bit. The final result produces
a sum of four bits S (S4S3S2S1) plus a carry out (Cout) bit.
47
Fig. 3.7 4-bit parallel adder circuit
74LS83 is an IC parallel adder. It adds two 4-bit binary numbers [A (A4A3A2A1) and B
(B4B3B2B1)] and a carry in bit (Cin). The sum is expressed in binary form as Cout(output carry), s4,
s3, s2, and s1. It is possible to add BCD or base-16 numbers with 74LS83 IC by using 4-bit numbers.
The truth table of 74LS83 IC full adder is given in Fig. 3.8. Both connection diagram and logic diagram
of 74LS83 parallel adder are shown in Fig. 3.9. Table 3.5 provides some example operations for
74LS83 parallel adder.
48
Fig. 3.8 The truth table of 74LS83 parallel adder
Table 3.5 Some example operations
49
50
Fig. 3.9 Connection diagram and logic diagram of 74LS83 parallel adder
- Equipment :
o Integrated Circuits (ICs):
o Connection wires.
Fig. 3.10 74LS83 4-bit parallel adder circuit (74LS83)
Fig. 3.11 74LS83 4-bit parallel adder – application circuit.

51
- Procedure:
1) Construct the circuit [as given in Fig. 3.10. and as] drawn by you in Fig. 3.11 and
apply the power.
2) Apply all possible combinations to the inputs (A4 A3 A2 A1 B4 B3 B2 B1) of the
circuit and experimentally obtain the output values given in Table 3.6 and take note
of the outputs (Cout S4 S3 S2 S1) in the Table.
Table 3.6
4. Examination of 4 bit Full Adder/ Full Subtractor

Fig. 3.12 shows a 4 bit full adder / full subtractor circuit. There are two 4 bit inputs A (A4A3A2A1)
and B (B4B3B2B1). The outputs are Cout,S4,S3,S2,S1. In this circuit, if D = 0 then two 4 bit inputs
A and B are added: A+B. In this case, the XOR-gates act as non-inverting buffers, and the carry-input
(Cin) to the adder is 0. Therefore, the adder calculates a four-bit sum plus carry-out:
(Cout,S4,S3,S2,S1) = (A4,A3,A2,A1) + (B4,B3,B2,B1)
If D = 1 then subtraction is applied based on two’s complement as follows: A+B’+1. In this case,
the XOR-gates act as inverting buffers, and the carry-input (Cin) to the adder is 1. Therefore, the circuit
calculates a four-bit subtraction based on two’s complement:
(Cout,S4,S3,S2,S1) = (A4,A3,A2,A1) – (B4,B3,B2,B1)
- Equipment :
52

o Connection wires.
- Procedure:
apply the power.
2) Apply all possible combinations to the inputs (A4 A3 A2 A1 B4 B3 B2 B1) of the
circuit and experimentally obtain the output values given in Table 3.7 and take note
of the outputs (Cout S4 S3 S2 S1) in the Table.
Fig. 3.12 4-bit Full Adder / Full Subtractor circuits.
53
Fig. 3.13 4-bit Full Adder / Full Subtractor – Application circuit.

Note: Do not forget connect the Vcc pins to +5 V and the GND pins to ground (GND)
connection.
54
Table 3. 7
II- Decoders
A decoder is a circuit that changes a code into a set of signals. It is called a decoder because
it does the reverse of encoding. A common type of decoder is the line decoder which takes an
m-bit binary input data and decodes it into 2m data lines. As a standard combinational
55
component, a decoder, asserts one out of n output lines, depending on the value of an m bit
binary input data. The outputs of a decoder can be either active-low or active-high. When the
utputs are active high (respectively active low) the asserted output is high (respectively low)
and the rest of the other outputs are low (respectively high). The general form of an m-to-n
decoder can be seen from Fig. 3.14. In general, an m-to-n decoder has m input lines, im-1, …,
i1, i0, and n output lines, dn-1, …, d1, d0, where n = 2m. As shown in Figure 3.14, in addition
to input lines and output lines, a decoder has an enable line, E, for enabling the decoder. When
the decoder is disabled with E set to 0 (for active high enable input E), all the output lines are
de-asserted. When the decoder is enabled, then the output line whose index is equal to the
value of the input binary data is asserted (set to 1 for active high), while the rest of the output
lines are de-asserted (set to 0 for active high). A decoder is used in a system having multiple
components, and we want only one component to be selected or enabled at any time.
Fig. 3.14 The general form of an m-to-n decoder, where n = 2m.

1. Examination of 74LS138 3x8 Decoder
Fig. 3.15 shows the schematic symbol, the logic diagram and the truth table of 74LS138
3x8 decoder IC. The 74LS138 decodes one-of-eight lines (O7’, O6’, O5’, O4’, O3’, O2’, O1’
and O0’), based upon the conditions at the three binary select inputs (A2, A1 and A0) and the
three enable inputs (E1’, E2’ and E3). The outputs of 74LS138 are active low. Two active-low
(E1’, E2’) and one active-high (E3) enable inputs reduce the need for external gates or inverters
when expanding.
56
- Equipment:
o Connection wires.
57
58
Fig. 3. 15 The schematic symbol, the logic diagram and the truth table 74LS138 3x8 decoder
IC
- Procedure:
apply the power.
2) Apply the combinations to the inputs of the circuit given in Table 3.18 and
experimentally obtain the output values and take note of the outputs in the Table.
Fig. 3.16 74LS138 3x8 decoder circuit.
Fig. 3.17 74LS138 3x8 decoder – application circuit.

connection.
59
Fig. 3.18
2. Implementation of a Boolean function by using a 3x8 Decoder

- Equipment:
o Connection wires.
Fig. 3.19 Implementation of a Boolean function by using a 3x8 decoder with active low
outputs.
60
Fig. 3.20 Implementation of a Boolean function by using a 3x8 decoder with active low outputs –
application circuit
Note1: Do not forget to connect the Vcc pins to +5 V and the GND pins to ground (GND)
connection.
Note2: To obtain an inverter function use a two-input-NAND gate.
Note3: To obtain a four-input-OR gate use two-input-OR gates.
- Procedure:
1) Implement the function S(x,y,z) = Σm(0,1,5,6) by using a 3x8 decoder with active
low outputs, inverters and a four-input-OR gate provided in Fig. 3.19. By means of
a digital simulation software test and verify the operation of your implementation.
Then, draw by hand using pencils an application circuit provided in Fig. 3.20 for the
completed schematic diagram of Fig. 3.19. It is recommended that you use red
colour for Vcc, black colour for GND and other colours for other connections.
2) Construct the circuit [as designed by you in Fig. 3.19 and] as drawn by you in Fig.
3.20 and apply the power.
obtain the output values given in Table 3.8 and take note of the output values in the
Table.
61
Table 3.8
III- Multiplexer
As a standard combinational component, the multiplexer, abbreviated MUX, allows the
selection of one input signal among n signals, where n > 1, and is a power of two. Select lines
connected to the multiplexer determine which input signal is selected and passed to the output
of the multiplexer. As can be seen from Fig. 3.21, in general, an n-to-1 multiplexer has n data
input lines, m select lines where m = log2n, i.e. 2m = n, and one output line. As shown in Fig.
3.21, in addition to the other inputs, the multiplexer has an enable line, E, for enabling it. When
the multiplexer is disabled with E set to 0 (for active-high enable input E), no input signal is
selected and passed to the output. When the multiplexer is enabled with E set to 1 (for active-
high enable input E), an input signal is selected and passed to the output based on the logic
values applied select inputs.
62
Fig. 3.21 The general form of an n-to-1 multiplexer, where n = 2m.

1. Examination of 74LS138 3x8 Decoder
Fig. 3.22 shows the schematic symbol, the logic diagram and the truth table of the 74LS151
8x1 MUX. In this multiplexer, the active-low enable input E’, select inputs S2, S1, S0,
input signals “I0”, “I1”, “I2”,“I3”, “I4”, “I5”, “I6”, and “I7”, and the output Y (and its
complement Y’) are all Boolean variables.
- Equipment:
o Connection wires.
63
64
Fig. 3. 22 The schematic symbol, the logic diagram and the truth table 74LS151 8x1
multiplexer IC
- Procedure:
apply the power.
2) Apply the combinations to the inputs of the circuit given in Table 3.9 and
experimentally obtain the output values and take note of the outputs in the Table.
Fig. 3.23 74LS151 8x1 multiplexer circuit.
Fig. 3.24 74LS151 8x1 multiplexer – application circuit.
65
connection.
Table 3. 9
2. Implementation of a Boolean function by using a 8x1 Multiplexer - 1
- Equipment:
o Connection wires.
66
Fig. 3.25 Implementation of a Boolean function by using a 74151 8x1 multiplexer 1.
Fig. 3.26 Implementation of a Boolean function by using a 74LS151 8x1 multiplexer 1– application
circuit
- Procedure:
1) Implement the function F(x,y,z) = Σm(1,2,4,7) by using a 74LS151 8x1 multiplexer
provided in Fig. 3.25. By means of a digital simulation software test and verify the
operation of your implementation. Then, draw by hand using pencils an application
circuit provided in Fig. 3.26 for the completed schematic diagram of Fig. 3.25. It is
recommended that you use red colour for Vcc, black colour for GND and other
colours for other connections.
67
obtain the output values given in Table 3.10 and take note of the output values in
the Table.
Table 3.10
3. Implementation of a Boolean function by using a 8x1 Multiplexer - 2
- Equipment:
o Connection wires.
68
Fig. 3.27 Implementation of a Boolean function by using a 74151 8x1 multiplexer 2.
Fig. 3.28 Implementation of a Boolean function by using a 74LS151 8x1 multiplexer 2 – application
circuit
Note1: Do not forget to connect the Vcc pins to +5 V and the GND pins to ground (GND)
connection.
Note2: To obtain an inverter function use a two-input-NAND gate.
- Procedure:
1) Implement the function F(x,y,z,t) = Σm(1,2,4,7,8,10,12,15) by using a 74LS151 8x1
multiplexer provided in Fig. 3.27. By means of a digital simulation software test
69
and verify the operation of your implementation. Then, draw by hand using pencils
an application circuit provided in Fig. 3.28 for the completed schematic diagram of
Fig. 3.27. It is recommended that you use red colour for Vcc, black colour for GND
and other colours for other connections.
obtain the output values given in Table 3.10 and take note of the output values in
the Table.
Table 3.11
70
Lab 4: Implementation of Sequential Logic Circuits.
Lab 4: Sequential logic circuits
Objective:
- Verifying flip-flop operation and obtaining their truth table.
- Investigating the binary counters and obtaining their operation principles.
71
I- Flip-flop
In the previous experiments, combinational logic circuits such as decoders, encoders, multiplexers
anddemultiplexers were considered. On the other hand, in a sequential logic circuit; in addition to logic gates
there are also memory elements. Flip-flops are basic memory elements used in a sequential logic circuit. When
the memory elements are removed from a sequential logic circuit the remaining part of the circuit is just the
combinational part. In the experiment, flip-flops are considered. One of the basic devices storing and processing
the digital data (1s and 0s) is the flip-flop. There are basically four types of flip-flops:
1- SR flip-flop (latch)
2- D flip-flop
3- JK flip-flop
4- T flip-flop
1. Examination of JK Flip-flop
- Preliminary information: The schematic symbol and the function table of 74LS112 dual JK flip-flops
with Preset and Clear is shown in Fig. 4.1.
Fig 4. 1 The schematic symbol and the function table 74LS112 dual JK flip-flops with Preset and Clear.
- Equipment:
74LS112 Dual JK Flip-flops with Preset and Clear 1 IC
o Connection wires.
72
Fig 4. 2 The dual JK flip-flop circuit with Preset and Clear.
Fig 4. 3 The dual JK flip-flop circuit with Preset and Clear – Application circuits
- Procedure:
2) Apply first the following Preset, Clear, J and K and then the CLK to the inputs of the circuit, given
in Table 4.1 and experimentally obtain the output values and take note of the outputs in the Table:
Notes: Output status changes only when falling edge clock appears. Falling edge clock is created
when you turn the switch from level 1 to level 0.
73
Table 4. 1
2. Examination of D Flip-flop:
- Preliminary information: The schematic symbol and the function table of 74LS74 dual rising edge
triggered D flip-flops is shown in Fig. 4.4.
Fig 4. 4 The schematic symbol and the function table of 74LS74 dual rising edge triggered D flip-flops.
- Equipment:
74
o Connection wires.
Fig 4. 5 Rising edge triggered D flip-flop circuit.
Fig 4.6 Rising edge triggered D flip-flop – application circuit

- Procedure:
2) Apply first the following Preset, Clear, D and then the CLK to the inputs of the circuit, given in Table
4.2 (follow the given inputs from top to down) and experimentally obtain the output values and take
note of the outputs in the Table.
Notes: Output status changes only when rising edge clock appears. Rising edge clock is created when
you turn the switch from level 0 to level 1.
75
Table 4. 2
3. Converting a JK flip-flop into a D flip-flop
- Equipment :
74LS112 Dual JK Flip-flop with Preset and Clear 1 IC
74LS04 Hex inverters (six independent gates) 1 IC
o Connection wires.
Fig 4. 7 Converting a JK flip-flop into a D flip-flop.
76
Fig 4. 8 Converting a JK flip-flop into a D flip-flop – application circuit
- Procedure:
Notes: Output status changes only when falling edge clock appears. Falling edge clock is created when
Table 4.3
77
4. Examination of T Flip-flop:
- Equipment:
o Connection wires.
Fig 4. 9 Converting a JK flip-flop into a T flip-flop.
Fig 4.10 Converting a JK flip-flop into a T flip-flop – application circuit
- Procedure:
78
Notes: Output status changes only when falling edge clock appears. Falling edge clock is created when
Table 4. 4
II- Asynchronous (Ripple) Counters

In digital logic and computing, a counter is a device which stores (and sometimes displays) the number of
times a particular event or process has occurred, often in relationship to a clock signal. Counters are the logic
circuits that take specific state with the clock ticks applied to their inputs. They are widely used in the digital
electronics area. Some of those application areas are, Digital Clocks, Frequency Counters, Decoders, Digital
Alarms, Traffic Lights etc.
The base of the counters are logic circuits and the flip-flops. Generally counters are obtained with cascade
connection of flip-flops in a specific rule. With each clock tick the counter changes its state. A counter composed
of n flip-flops with no feedback may have 2n different states depending on the number of clock ticks. For
example, if 4 flip-flops are used in the counter structure, there will totally be 24=16 different states. So, the
counter can count from 0 to 15.
The total number of counts or stable states a counter can indicate is called MODULUS (MOD). For instance,
the modulus of a four-stage counter would be 1610, since it is capable of indicating 0000 . The term modulo is
used to describe the count capability of counters; that is, modulo-16(MOD16) for a four-stage binary counter,
modulo-10 (MOD10) for a decade counter, modulo-8 (MOD8) for a three-stage binary counter, and so forth.
79
Counters can be up counters, whose count value increments, and down counters, whose count value decrements,
A counter is usually considered in conjunction with a finite-state machine (FSM).
Counters can be divided into two groups: 1. asynchronous (ripple) counters, 2. synchronous counters.
Asynchronous counters are counters that are configured such that all flip-flops are not triggered
simultaneously by a common clock. Since each flip-flop in the counter is triggered by the flip-flop in series
before it, these counters are also referred to as ripple counters. There are many types of asynchronous counters.
An UP counter counts in an ascending sequence while a DOWN counter counts in a descending sequence. A
counter can also count UP and DOWN on command; such a counter is known as an UP/DOWN counter.
Asynchronous counters are limited in speed since all the flip-flops are not synchronized by the same clock.
Therefore the propagation delay in each flip-flop often affects the counting sequence at very high operation
frequencies. The flip-flops used in asynchronous counters are usually “T” flip-flops or JK or D type flip-flops
that have been configured as T flip-flops.
Asynchronous counters can be constructed from discrete flip-flops or are readily available in the form of ICs.
The IC implementations are designed so that the counters can be configured for a wide variety of applications
ranging from simple counting to frequency division.
The flip-flop output in an asynchronous counter is used to trigger the next flip-flop. In other words, all the
flip-flops except for the first one are triggered with the state transition of the previous flip-flops. However, in
synchronous counters the input ticks are applied to all the Clk inputs of the flip-flops at the same time. The fact
that a flip-flop changes state depends on the states of other flip-flops. All flipflops work in toggle mode in an
asynchronous counter.
3. Examination of 4 bit asynchronous binary up counter:

- Equipment:
74LS112 Dual JK Flip-flops with Preset and Clear 2 ICs
o Connection wires.
80
Fig 4. 11 The 4 bit asynchronous binary up counter circuit.
Fig 4. 12 The 4 bit asynchronous binary up counter – application circuit

Note: Do not forget connect the Vcc pins to +5 V and the GND pins to ground (GND) connection.
- Procedure:
1) Construct the circuit [as given in Fig. 4.11 and as] drawn by you in Fig. 4.12 and apply the power.
In the beginning of the experiment, connect the Clock to a DIO and set it as a switch.
81
2) Set the input A = 0 and B = 1, note the result.

4) Set A = B =1, turn on the switch and then turn off to make a pulse into CLK input. Note down your
observation in Table 4.2.
Table 4. 5
5) Set A = B = 1, supply Clock signal using Digital Pattern Generator. Set the parameter as below:
- Click to Add channels → Signal → DIOx (x: 0 – 15)

- Output: PP (Push – Pull)
- Type: Clock
82
- Parameter1: change the frequency from 1Hz, 10Hz and 100Hz,… and observe the operation of the
counter. After which frequencies you cannot observe the changing of count values by your eyes?
Explain why?
4. Examination of MOD10 asynchronous up counter:

- Equipment:
74LS00 Quad 2-input NAND gates 1 IC
o Connection wires.
Fig 4.13 The MOD10 asynchronous up counter circuit.

`
83
Fig 4. 14 The MOD10 asynchronous up counter – application circuit
84
- Procedure:
2) Set the input A = 0, note the result (this means all preset inputs of flip-flops are inactive).
3) Set A = 1, turn on the switch and then turn off to make a pulse into CLK input. Note down your
observation in Table 4.
Table 4. 6
6) Set A = 1, supply Clock signal using Digital Pattern Generator. Set the parameter as below:

- Type: Clock
85
-Parameter1: change the frequency from 1Hz, 10Hz and 100Hz,… and observe the operation of the
counter. After which frequencies you cannot observe the changing of count values by your eyes?
Explain why?
5. Examination of 4 bit asynchronous binary down counter:
- Equipment:
o Connection wires.
Fig 4. 15 The 4 bit asynchronous binary down counter circuit.
Fig 4. 16 The 4 bit asynchronous binary down counter – application circuit
86
- Procedure:
4) Set A = B =1, turn on the switch and then turn off to make a pulse into CLK input. Note down your
observation in Table 4.7.
Table 4. 7
5) Set A = B = 1, supply Clock signal using Digital Pattern Generator. Set the parameter as below:
- Type: Clock
- Parameter1: change the frequency from 1Hz,
10Hz and 100Hz,… and observe the operation of the
counter. After which frequencies you cannot observe
the changing of count values by your eyes? Explain
- Click to Add channels → Signal → DIOx (x: 0 – why?
15)
87
6. Examination of the 74LS93 4 bit asynchronous binary up counter:

The 74LS93 is an example of a specific TTL IC asynchronous up counter. Fig. 8.8 shows the schematic
symbol, the logic diagram, the reset/count truth table and the count sequence of the 74LS93 4 bit asynchronous
up counter IC. As the logic diagram in Fig. 8.8 shows, this device actually consists of a single flip-flop and a 3-
bit asynchronous counter. This arrangement is for flexibility. It can be used as a divide-by-2 device if only the
single flip-flop is used, or it can be used as a MOD8 counter if only 3-bit counter is used. This device also
provides gated reset inputs, MR1 and MR2. When both of these inputs are HIGH, the counter is reset to 0000
state.
- Equipment:
o Integrated Circuits (ICs): 74LS93 4 bit binary counter 1 IC
o Connection wires.
Fig 4. 17 The 74LS93 4 bit asynchronous up counter circuit.
Fig 4. 18 The 74LS93 4 bit asynchronous up counter circuit – application circuit

88
- Procedure:
2) Set the input A = 1, turn on the switch and then turn off to make a pulse into CLK input and note
the output value.
89
3) Set the input A = 0, turn on the switch and then turn off to make a pulse into CLK input. Note
down your observation in Table 4.8.
Table 4. 8
4) Set the input A = 0, supply Clock signal using Digital Pattern Generator. Set the parameter as
below:

- Type: Clock.
- Parameter1: change the frequency from 1Hz, 10Hz and 100Hz,… and observe the operation of the
counter. After which frequencies you cannot observe the changing of count values by your eyes? Explain
why?
7. Examination of the 74LS93 used as a BCD counter:
90
The 74LS93 can be used as a 4-bit MOD16 counter (counts 0 through 15). It can also be configured as a
decade counter (counts 0 through 9) with asynchronous recycling by using the gated reset inputs MR1 and MR2.
- Equipment:
o Integrated Circuits (ICs): 74LS93 4 bit binary counter 1 IC
o Connection wires.
Fig 4. 19 Configuration of the 74LS93 as a decade counter (74LS93).
Fig 4. 20 Configuration of the 74LS93 as a decade counter (74LS93) – application circuit
- Procedure:
2) Turn on the switch and then turn off to make a pulse into CLK input. Note down your observation
in Table 4.9.
91
Table 4. 9
III- Synchronous Counters

Synchronous counters are counters that are configured such that all flip-flops are triggered simultaneously by
a common clock. All flip-flops are therefore “synchronized” by the same clock. Like asynchronous counters
there are many types of synchronous counters. They can be designed to provide the same functions as
asynchronous counters. Therefore many applications requiring counters can have either asynchronous counters
or synchronous counters.
Unlike asynchronous counters, synchronous counters are not limited in speed since all the flip-flops are
synchronized by the same clock. Since the clock of each flip-flop is not affected by propagation delays,
synchronous counters are not susceptible to adverse effects of high frequency operations. Therefore synchronous
counters are often used in applications that require that the counter be operated at frequencies beyond those that
an asynchronous counter can handle. In an asynchronous counter the count sequence must follow the regular
ascending or descending sequence but in a synchronous counter in addition to the regular ascending or
descending sequences different types of irregular count sequences can also be obtained.
92
Synchronous counters can be constructed from discrete flip-flops or are readily available in the form of ICs.
The IC implementations are designed so that the counters can be configured for a wide variety of applications
ranging from simple counting to frequency division.
1. Examination of the synchronous counter with the counting sequence of 0, 2, 4, 6, 1, 3, 5, 7, 0,...:
- Equipment:
74LS08 Quad 2-input AND gates 1 IC
o Connection wires.
Fig 4. 21 The synchronous counter circuit to count in the count sequence of 0, 2, 4, 6, 1, 3, 5, 7, 0,….
- Procedure:
2) Set the input A to the logic 0 state temporarily. Then set the input A to the logic 1 state permanently.
3) Turn on the switch and then turn off to make a pulse into CLK input. Note down your observation in
Table 4.10.
93
Fig 4. 22 The synchronous counter circuit

to count in the count sequence of 0, 2, 4, 6,
1, 3, 5, 7, 0,…. – application circuit
Note: Do not forget connect

the Vcc pins to +5 V and the
GND pins to ground (GND)
connection.
94
Table 4. 10
- Type: Clock
- Parameter1: change the frequency from
1Hz, 10Hz and 100Hz,… and observe the
operation of the counter. After which
frequencies you cannot observe the
changing of count values by your eyes?
Explain why?
- Click to Add channels → Signal → DIOx
(x: 0 – 15)
2. Examination of the 4 bit synchronous up counter:

- Equipment:
95

o Connection wires.
Fig 4. 23 The 4 bit synchronous up counter
- Procedure:
2) Set the input A to the logic 0 state temporarily. Then set the input A to the logic 1 state permanently.
3) Turn on the switch and then turn off to make a pulse into CLK input. Note down your observation in
Table 4.11.
96
Fig 4. 24 The 4 bit synchronous up counter

connection.
97
Table 4. 11

- Type: Clock
- Parameter1: change the frequency from 1Hz, 10Hz and 100Hz,… and observe the
operation of the counter. After which frequencies you cannot observe the changing
of count values by your eyes? Explain why?
98
3. Examination of the BCD synchronous up counter:

- Equipment:
o Connection wires.
Fig 4. 25 The BCD synchronous up counter circuit
- Procedure:
1) Construct the circuit [as given in Fig. 4.25 and as] drawn by you in Fig. 4.26 and
apply the power. In the beginning of the experiment, connect the Clock to a DIO
and set it as a switch.
2) Set the input A to the logic 0 state temporarily. Then set the input A to the logic 1
state permanently.
3) Turn on the switch and then turn off to make a pulse into CLK input. Note down
your observation in Table 4.12.
99
Fig 4. 26 The BCD synchronous up

counter circuit – application circuit

connection.
100
Table 4. 12
4) Set A = 1, supply Clock signal using Digital Pattern Generator. Set the parameter
as below:

- Type: Clock
Parameter1: change the frequency from 1Hz, 10Hz and 100Hz,… and observe the
operation of the counter. After which frequencies you cannot observe the changing
of count values by your eyes? Explain why?
101

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VIET NAM NATIONAL UNIVERSITY HO CHI MINH CITY – UNIVERSITY OF TECHNOLOGY

FACULTY OF ELECTRICAL AND ELECTRONICS ENGINEERING

DIGITAL SYSTEMS LABORATORY MANUAL

There are 4 labs:

Lab 1 – Digital Logic Gates.

Lab 2 – Implementation of Boolean function with Logic Gates.

Lab 3 – Combinational Logic Circuits.

Lab 4 – Sequential Logic Circuits.

Lab 1: Digital Logic Gates

I- Examination of AND gate

Fig 1.1: 2-input AND gate.

Table 1.1: The truth table of 2-input

2. Obtaining The Truth Table Of The AND Gate

Fig 1.3: Examination of a 2-input AND gate (2_in_and_gate).

Fig 1.4: Examination of a 2-input AND gate – application circuit.

NOTE: DO THE SAME EXPERIMENT AGAIN ON BREARDBOARD BY USING

II- Examination of NAND gate

Table 2.1: The truth table of 2-input

2. Obtaining The Truth Table Of The NAND Gate

Fig 2.3: Examination of a 2-input NAND gate (2_in_and_gate).

Fig 2.4: Examination of a 2-input NAND gate – application circuit.

NOTE: DO THE SAME EXPERIMENT AGAIN ON BREARDBOARD BY USING

3. Using a NAND Gate As An Inverter

Fig 2.5: The use of a NAND gate as an INVERTER.

Fig 2.6: The use of a NAND gate as an INVERTER – application circuit.

III- Examination of Inverter gate

Table 3.1: The truth table of the

2. Obtaining The Truth Table Of The Inverter Gate

Fig 3.3: Examination of INVERTER gate

Fig 3.4: Examination INVERTER gate – application circuit.

NOTE: DO THE SAME EXPERIMENT AGAIN ON BREARDBOARD BY USING

IV- Examination of OR gate

2. Obtaining The Truth Table Of The OR Gate

Fig 4.3: Examination of a 2-input OR gate (2_in_or_gate).

Fig 4.4: Examination of a 2-input OR gate – application circuit.

NOTE: DO THE SAME EXPERIMENT AGAIN ON BREARDBOARD BY USING

V- Examination of NOR gate

Table 5.1: The truth table of 2-

2. Obtaining The Truth Table Of The NOR Gate

Fig 5.3: Examination of a 2-input NOR gate (2_in_or_gate).

Fig 5.4: Examination of a 2-input NOR gate – application circuit.

NOTE: DO THE SAME EXPERIMENT AGAIN ON BREARDBOARD BY USING

3. Using a NOR Gate As An Inverter

Fig 5.5: The use of a NOR gate as an INVERTER (nor_inverter).

Fig 5.6: The use of a NOR gate as an INVERTER – application circuit.

NOTE: DO THE SAME EXPERIMENT AGAIN ON BREARDBOARD BY USING

VI- Examination of Exclusive-OR gate

2. Obtaining The Truth Table Of The EX-OR Gate

Fig 6.3: Examination of a 2-input EX-OR gate (2_in_or_gate).

Fig 6.4: Examination of a 2-input Ex-OR gate – application circuit.

NOTE: DO THE SAME EXPERIMENT AGAIN ON BREARDBOARD BY USING

VII- Examination of Exclusive-NOR gate

Table 7.1: The truth table of 2-input

2. Obtaining The Truth Table Of The EX-NOR Gate

Fig 7.3: Examination of a 2-input EX-NOR gate (2_in_or_gate).

Fig 7.4: Examination of a 2-input Ex-NOR gate – application circuit.

NOTE: DO THE SAME EXPERIMENT AGAIN ON BREARDBOARD BY USING

Lab 2: Implementation of Boolean Function

Fig. 2.1. 3-variable Karnough maps.