Digital System Design using Verilog BEC302

MODULE – 5
Syllabus: Verilog Behavioral description: Structure, Variable Assignment Statement, Sequential
Statements, Loop Statements, Verilog Behavioral Description of Multiplexers (2:1, 4:1, 8:1).
(Section 3.1 to 3.4 (only Verilog)of Text 3)
Verilog Structural description: Highlights of Structural description, Organization of structural
description, Structural description of ripple carry adder.(Section4.1 to 4.2 of Text 3)
Text book: 3. HDL Programming VHDL and Verilog by Nazeih M Botros, 2009 reprint, Dream
techpress.

Verilog Behavioral Description:

Introduction:

 The behavioral description is a powerful tool to describe systems for which digital logic
structures are not known or are hard to generate.
 The behavioral description describes the system by showing how outputs behave with the
changes in inputs. In this description, details of the logic diagram of the system are not needed;
what is needed is how the output behaves in response to a change in the input. In Verilog, the
major behavioral description statements are always and initial.
 With the increasing complexity of digital design, it has become vitally important to make wise
design decisions early in a project.
 Designers need to be able to evaluate the trade-offs of various architectures and algorithms
before they decide on the optimum architecture and algorithm to implement in hardware.
 Thus, architectural evaluation takes place at an algorithmic level where the designers do not
necessarily think in terms of logic gates or data flow but in terms of the algorithm they wish to
implement in hardware. They are more concerned about the behavior of the algorithm and its
performance.
 Only after the high-level architecture and algorithm are finalized, do designers start focusing
on building the digital circuit to implement the algorithm.
 Verilog provides designers the ability to describe design functionality in an algorithmic manner.
 In other words, the designer describes the behavior of the circuit. Thus, behavioral modeling
represents the circuit at a very high level of abstraction. Design at this level resembles C

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programming more than it resembles digital circuit design. Behavioral Verilog constructs are
similar to C language constructs in many ways.
 Verilog is rich in behavioral constructs that provide the designer with a great amount of
flexibility.

Structure of Behavioral Description:

Structured Procedures:

There are two structured procedure statements in Verilog:

 always and initial.

These statements are the two most basic statements in behavioral modeling. All other
behavioral statements can appear only inside these structured procedure statements.

Verilog is a concurrent programming language unlike the C programming language, which

is sequential in nature. Activity flows in Verilog run in parallel rather than in sequence. Each
always and initial statement represents a separate activity flow in Verilog. Each activity flow
starts at simulation time 0. The statements always and initial cannot be nested. The
fundamental difference between the two statements is explained in the following sections.

 initial Statement
o All statements inside an initial statement constitute an initial block.
o An initial block starts at time 0, executes exactly once during a simulation, and then
does not execute again.
o If there are multiple initial blocks, each block starts to execute concurrently at time 0.
o Each block finishes execution independently of other blocks. Multiple behavioral
statements must be grouped, typically using the keywords begin and end.
o If there is only one behavioral statement, grouping is not necessary.
o This is similar to the begin-end blocks in Pascal programming language or the { }
grouping in the C programming language.
Example: illustrates the use of the initial statement.

initial Statement

module stimulus;
reg x,y, a,b, m;

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initial
m = 1'b0; //single statement; does not need to be grouped
initial
begin
#5 a = 1'b1; //multiple statements; need to be grouped
#25 b = 1'b0;
end
initial
begin
#10 x = 1'b0;
#25 y = 1'b1;
end
initial
#50 $finish;
endmodule
In the above example, the three initial statements start to execute in parallel at time 0. If a
delay #<delay> is seen before a statement, the statement is executed <delay> time units after
the current simulation time.

Thus, the execution sequence of the statements inside the initial blocks will be as follows.

time statement executed

0 m = 1'b0;

5 a = 1'b1;

10 x = 1'b0;

30 b = 1'b0;

35 y = 1'b1;

50 $finish;

The initial blocks are typically used for initialization, monitoring, waveforms and other
processes that must be executed only once during the entire simulation run.

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always Statement

o All behavioral statements inside an always statement constitute an always block.

o The always statement starts at time 0 and executes the statements in the always block
continuously in a looping fashion.
o This statement is used to model a block of activity that is repeated continuously in a digital
circuit.
o An example is a clock generator module that toggles the clock signal every half cycle.
o In real circuits, the clock generator is active from time 0 to as long as the circuit is powered
on. Example illustrates one method to model a clock generator in Verilog.

Example: always Statement

module clock_gen (output reg clock);

//Initialize clock at time zero

initial

clock = 1'b0;

//Toggle clock every half-cycle (time period = 20)

always

#10 clock = ~clock;

initial

#1000 $finish;

endmodule

In Example:

The always statement starts at time 0 and executes the statement clock = ~clock every 10
time units. Notice that the initialization of clock has to be done inside a separate initial
statement. If we put the initialization of clock inside the always block, clock will be
initialized every time the always is entered. Also, the simulation must be halted inside an
initial statement. If there is no $ stop or $finish statement to halt the simulation, the clock
generator will run foreverC programmers might draw an analogy between the always block
and an infinite loop. But hardware designers tend to view it as a continuously repeated

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activity in a digital circuit starting from power on. The activity is stopped only by power
off ($finish) or by an interrupt ($stop).

2. Procedural Assignments

 Procedural assignments update values of reg, integer, real, or time variables.

 The value placed on a variable will remain unchanged until another procedural assignment
updates the variable with a different value.
 Dataflow Modeling, where one assignment statement can cause the value of the right-hand
-side expression to be continuously placed onto the left-hand-side net.
 The syntax for the simplest form of procedural assignment is shown below.
assignment ::= variable_lvalue = [ delay_or_event_control ] expression

The left-hand side of a procedural assignment <lvalue> can be one of the following:

 A reg, integer, real, or time register variable or a memory element

 A bit select of these variables (e.g., addr[0])
 A part select of these variables (e.g., addr[31:16])
 A concatenation of any of the above

There are two types of procedural assignment statements: blocking and nonblocking.

 Blocking Assignments

o Blocking assignment statements are executed in the order they are specified in a
sequential block.
o A blocking assignment will not block execution of statements that follow in a
parallel block..
o The = operator is used to specify blocking assignments.
Example: Blocking Statements

reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;
//All behavioral statements must be inside an initial or always block
initial
begin
x = 0; y = 1; z = 1; //Scalar assignments

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count = 0; //Assignment to integer variables

reg_a = 16'b0; reg_b = reg_a; //initialize vectors
#15 reg_a[2] = 1'b1; //Bit select assignment with delay
#10 reg_b[15:13] = {x, y, z} //Assign result of concatenation to// part select of a vector
count = count + 1; //Assignment to an integer (increment)

end

In Example, the statement y = 1 is executed only after x = 0 is executed. The behavior in a

particular block is sequential in a begin-end block if blocking statements are used, because
the statements can execute only in sequence. The statement count = count 1 is executed last.
The simulation times at which the statements are executed are as follows:

o All statements x = 0 through reg_b = reg_a are executed at time 0

o Statement reg_a[2] = 0 at time = 15
o Statement reg_b[15:13] = {x, y, z} at time = 25
o Statement count = count + 1 at time = 25
o Since there is a delay of 15 and 10 in the preceding statements, count = count + 1 will
be executed at time = 25 units
Note that for procedural assignments to registers, if the right-hand side has more bits than
the register variable, the right-hand side is truncated to match the width of the register
variable. The least significant bits are selected and the most significant bits are discarded. If
the right-hand side has fewer bits, zeros are filled in the most significant bits of the register
variable.

 Nonblocking Assignments

 Nonblocking assignments allow scheduling of assignments without blocking execution of

the statements that follow in a sequential block.
 A <= operator is used to specify nonblocking assignments.
Note that this operator has the same symbol as a relational operator, less_than_equal_to.

The operator <= is interpreted as a relational operator in an expression and as an assignment

operator in the context of a nonblocking assignment

To illustrate the behavior of nonblocking statements and its difference from blocking
statements, let us consider Example, where we convert some blocking assignments to
nonblocking assignments, and observe the behavior.
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Example 4-7 Nonblocking Assignments

reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;
//All behavioral statements must be inside an initial or always block
initial
begin
x = 0; y = 1; z = 1; //Scalar assignments
count = 0; //Assignment to integer variables
reg_a = 16'b0; reg_b = reg_a; //Initialize vectors

reg_a[2] <= #15 1'b1; //Bit select assignment with delay

reg_b[15:13] <= #10 {x, y, z}; //Assign result of concatenation //to part select
of a vector

count <= count + 1; //Assignment to an integer (increment)

end

In this example, the statements x = 0 through reg_b = reg_a are executed sequentially at
time 0. Then the three nonblocking assignments are processed at the same simulation time.

reg_a[2] = 0 is scheduled to execute after 15 units (i.e., time = 15)

reg_b[15:13] = {x, y, z} is scheduled to execute after 10 time units (i.e.,
time = 10)
count = count + 1 is scheduled to be executed without any delay (i.e., time = 0)
Thus, the simulator schedules a nonblocking assignment statement to execute and
continues to the next statement in the block without waiting for the nonblocking statement
to complete execution. Typically, nonblocking assignment statements are executed last
in the time step in which they are scheduled, that is, after all the blocking assignments in
that time step are executed.

In the example above, we mixed blocking and nonblocking assignments to illustrate their
behavior. However, it is recommended that blocking and nonblocking assignments not be
mixed in the same always block.

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Conditional Statements

Conditional statements are used for making decisions based upon certain conditions. These
conditions are used to decide whether or not a statement should be executed. Keywords if
and else are used for conditional statements. There are three types of conditional
statements. Usage of conditional statements is shown below.

//Type 1 conditional statement. No else statement.

//Statement executes or does not execute.

 if (<expression>) true_statement ;
//Type 2 conditional statement. One else statement //Either true_statement
or false_statement is evaluated

 if (<expression>) true_statement ; else false_statement ;

//Type 3 conditional statement. Nested if-else-if. //Choice of multiple
statements. Only one is executed.

 if (<expression1>) true_statement1 ;
else if (<expression2>) true_statement2 ;

else if (<expression3>) true_statement3 ;

else default_statement ;

The <expression> is evaluated. If it is true (1 or a non-zero value), the true_statement is

executed. However, if it is false (zero) or ambiguous (x), the false_statement is executed.
Each true_statement or false_statement can be a single statement or a block of multiple
statements. A block must be grouped, typically by using keywords begin and end. A single
statement need not be grouped.

Example:

//Execute statements based on ALU control signal.

if (alu_control == 0)
y = x + z;
else if(alu_control == 1)

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y = x - z;

else if(alu_control == 2)

y = x * z;
else
$display("Invalid ALU control signal");

Multiway Branching

1 case Statement

The keywords case, endcase, and default are used in the case statement..

case (expression)
alternative1: statement1;
alternative2: statement2;
alternative3: statement3;
...
...
default: default_statement;
endcase
 Each of statement1, statement2 , default_statement can be a single statement or a block of
multiple statements. A block of multiple statements must be grouped by keywords begin and
end.
 The expression is compared to the alternatives in the order they are written. For the first
alternative that matches, the corresponding statement or block is executed.
 If none of the alternatives matches, the default_statement is executed.
 The default_statement is optional.
 Placing of multiple default statements in one case statement is not allowed.
 The case statements can be nested.

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//Execute statements based on the ALU control signal

reg [1:0] alu_control;

...

...

case (alu_control)

2'd0 : y = x + z;

2'd1 : y = x - z;

2'd2 : y = x * z;

default : $display("Invalid ALU control signal");

endcase

The case statement can also act like a many-to-one multiplexer.

Example : 4-to-1 Multiplexer with Case Statement

module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);

Port declarations from the I/O diagram output out;

input i0, i1, i2, i3; input s1, s0;

reg out;

always @(s1 or s0 or i0 or i1 or i2 or i3)

case ({s1, s0}) //Switch based on concatenation of control signals 2'd0 : out = i0;
2'd1 : out = i1;

2'd2 : out = i2;

2'd3 : out = i3;

default: $display("Invalid control signals");

endcase

endmodule

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The case statement compares 0, 1, x, and z values in the expression and the alternative bit
for bit. If the expression and the alternative are of unequal bit width, they are zero filled to
match the bit width of the widest of the expression and the alternative. In Example 4-20 , we
will define a 1-to-4 demultiplexer for which outputs are completely specified, that is,
definitive results are provided even for x and z values on the select signal.

2 casex, casez Keywords

 There are two variations of the case statement.

 They are denoted by keywords, casex and casez.

 casez treats all z values in the case alternatives or the case expression as don't cares.
All bit positions with z can also represented by ? in that position.
 casex treats all x and z values in the case item or the case expression as don't cares.
 The use of casex and casez allows comparison of only non-x or -z positions in the case
expression and the case alternatives. Example 4-21 illustrates the decoding of state bits
in a finite state machine using a casex statement.
 The use of casez is similar. Only one bit is considered to determine the next state and
the other bits are ignored.

Example: casex Use

reg [3:0] encoding;

integer state;
casex (encoding) //logic value x represents a don't care bit.
4'b1xxx : next_state = 3;
4'bx1xx : next_state = 2;
4'bxx1x : next_state = 1;
4'bxxx1 : next_state = 0;
default : next_state = 0;

endcase

Thus, an input encoding = 4'b10xz would cause next_state = 3 to be executed.

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Loops

There are four types of looping statements in Verilog: while, for, repeat, and forever. The
syntax of these loops is very similar to the syntax of loops in the C programming language.
All looping statements can appear only inside an initial or always block. Loops may contain
delay expressions.

1 While Loop

The keyword while is used to specify this loop. The while loop executes until the while-
expression is not true. If the loop is entered when the while-expression is not true, the loop
is not executed at all. Any logical expression can be specified with these operators. If
multiple statements are to be executed in the loop, they must be grouped typically using
keywords begin and end. Example bwlow illustrates the use of the while loop.

Example : While Loop

//Illustration 1: Increment count from 0 to 127. Exit at count 128.

//Display the count variable.
integer count;
initial
begin

count = 0;

while (count < 128) //Execute loop till count is 127.,exit at count 128

begin

$display("Count = %d", count);

count = count + 1;
end

end

2 For Loop

The keyword for is used to specify this loop. The for loop contains three parts:

 An initial condition
 A check to see if the terminating condition is true
 A procedural assignment to change value of the control variable

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The counter described in Example 4-22 can be coded as a for loop (Example 4-23). The
initialization condition and the incrementing procedural assignment are included in the for
loop and do not need to be specified separately. Thus, the for loop provides a more compact
loop structure than the while loop. Note, however, that the while loop is more general-
purpose than the for loop. The for loop cannot be used in place of the while loop in all
situations.

Example: For Loop

integer count;

initial

for ( count=0; count < 128; count = count + 1)

$display("Count = %d", count);

 for loops are generally used when there is a fixed beginning and end to the loop. If the
loop is simply looping on a certain condition, it is better to use the while loop.

3 Repeat Loop

 The keyword repeat is used for this loop

 The repeat construct executes the loop a fixed number of times.
 A repeat construct cannot be used to loop on a general logical expression.
 A while loop is used for that purpose.
 A repeat construct must contain a number, which can be a constant, a variable or a signal
value.
 However, if the number is a variable or signal value, it is evaluated only when the loop starts
and not during the loop execution.
The counter in Example can be expressed with the repeat loop, as shown in Illustration 1 in
Example.

Example: Repeat Loop

//Illustration 1 : increment and display count from 0 to 127 integer count;

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initial

begin

count = 0;

repeat(128)

begin

$display("Count = %d", count);

count = count + 1;

end

end

4 Forever loop

 The keyword forever is used to express this loop.

 The loop does not contain any expression and executes forever until the $finish task is
encountered.
 The loop is equivalent to a while loop with an expression that always evaluates to true,
e.g., while (1).
 A forever loop can be exited by use of the disable statement.
A forever loop is typically used in conjunction with timing control constructs. If timing
control constructs are not used, the Verilog simulator would execute this statement
infinitely without advancing simulation time and the rest of the design would never be
executed. Example explains the use of the forever statement.

Example:Forever Loop

: Clock generation

//Use forever loop instead of always block

reg clock;

initial

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begin

clock = 1'b0;

forever #10 clock = ~clock; //Clock with period of 20 units

end

Sequential and Parallel Blocks

Block statements are used to group multiple statements to act together as one. In previous
examples, we used keywords begin and end to group multiple statements. Thus, we used
sequential blocks where the statements in the block execute one after another. In this section
we discuss the block types: sequential blocks and parallel blocks. We also discuss three special
features of blocks: named blocks, disabling named blocks, and nested blocks.

1 Block Types

There are two types of blocks: sequential blocks and parallel blocks.

Sequential blocks

The keywords begin and end are used to group statements into sequential blocks.

Sequential blocks have the following characteristics:

 The statements in a sequential block are processed in the order they are
specified. A statement is executed only after its preceding statement completes execution
(except for nonblocking assignments with intra-assignment timing control).

 If delay or event control is specified, it is relative to the simulation time when

the previous statement in the block completed execution.
We have used numerous examples of sequential blocks in this book. Two more examples
of sequential blocks are given in Example . Statements in the sequential block execute in
order. In Illustration 1, the final values are x = 0, y= 1, z = 1, w = 2 at simulation time 0. In

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Example: Sequential Blocks

//Illustration 1: Sequential block without delay

reg x, y;

reg [1:0] z, w;

initial

begin

x = 1'b0;

y = 1'b1;

z = {x, y};

w = {y, x};

end

Parallel blocks

Parallel blocks, specified by keywords fork and join, provide interesting simulation
features. Parallel blocks have the following characteristics:

 Statements in a parallel block are executed concurrently.

 Ordering of statements is controlled by the delay or event control assigned to each

statement.

 If delay or event control is specified, it is relative to the time the block was entered.

Notice the fundamental difference between sequential and parallel blocks. All statements
in a parallel block start at the time when the block was entered. Thus, the order in which the
statements are written in the block is not important.\

Example:Parallel Blocks

Parallel blocks with delay.

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reg x, y;
reg [1:0] z, w;
initial
fork
x = 1'b0; //completes at simulation time 0
#5 y = 1'b1; //completes at simulation time 5
#10 z = {x, y}; //completes at simulation time 10
#20 w = {y, x}; //completes at simulation time 20

join

 Parallel blocks provide a mechanism to execute statements in parallel.

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Examples

1 4-to-1 Multiplexer

We can define a 4-to-1 multiplexer with the behavioral case statement.

Example: Behavioral 4-to-1 Multiplexer

module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);

output out;
input i0, i1, i2, i3; input s1,
s0;

reg out;

//recompute the signal out if any input signal changes. //All input signals
that cause a recomputation of out to //occur must go into the always @(...)
sensitivity list.
always @(s1 or s0 or i0 or i1 or i2 or i3)
begin

case ({s1, s0})

2'b00: out = i0;

2'b01: out = i1;

2'b10: out = i2;

2'b11: out = i3;

default: out = 1'bx;

endcase

end

endmodule

2) 4-bit Counter-Behavioral 4-bit Counter Description

//4-bit Binary counter

module counter(Q , clock, clear);

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I/O ports

output [3:0] Q;
input clock, clear; //output defined as
register
reg [3:0] Q;
always @( posedge clear or negedge clock)

begin

if (clear)

Q <= 4'd0; //Nonblocking assignments are recommended

//for creating sequential logic such as flipflops

else

Q <= Q + 1;// Modulo 16 is not necessary because Q is a

// 4-bit value and wraps around.

end

endmodule

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