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    Basic VLSI Design

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    Basic VLSI Design

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    Basic VLSI Design

    Uploaded by

    gunikuntlahariprasad
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    Code: EC20AOE501 R 20

    B.Tech III Year I Semester Regular Examinations February - 2023


    BASIC VLSI DESIGN
    (Common to CSE and CSE(AI&ML))
    Time: 3 hrs. Max Marks: 60
    PART-A
    (Compulsory Question)
    1. Answer the following 05 x 02 = 10 Marks
    a) Write the ids and vds relationship/equation of MOS transistor in saturation mode. 2M
    b) What are design rules? 2M
    c) List the issues involved in driving large capacitor loads in VLSI circuit regions. 2M
    d) Draw the circuit diagram of two input NMOS NAND gate. 2M
    e) Write the Advantages and Disadvantages of BIST. 2M
    PART-B
    Answer All five Units 05 x 10 = 50 Marks
    UNIT-I
    2. a) Explain the transistor operation with the help of neat sketches in the following 5M
    Modes (i) Enhancement mode (ii) Depletion mode
    b) A PMOS transistor is operated in the triode region with following parameters: 5M
    2
    VGS = - 4.5 V, Vtp = -1 V, VDS= -10 V, W/L = 95, µpcox = 35 µA/V . Find the drain
    current and drain to source resistance.
    OR
    3. With neat sketches explain the NMOS transistor fabrication procedure. 10 M
    UNIT-II
    4. Draw the stick diagram and mask layout for CMOS inverter. 10 M
    OR
    5. a) Draw the NMOS transistors inverter model indicating all the components. 5M
    b) Draw the characteristics of CMOS inverter and explain the characteristics. 5M
    UNIT-III
    6. Discuss in detail about the various scaling factors in IC Design. 10 M
    OR
    7. a) Explain about sheet resistance and sheet capacitance. 5M
    b) Describe three sources of wiring capacitances in detail. 5M
    UNIT-IV
    8. a) Draw the circuit diagram of two input BiCMOS NAND gate and explain its 5M
    operation.
    b) Explain the concept of NORA CMOS logic. 5M
    OR
    9. a) Explain pseudo NMOS logic. 5M
    b) Write short notes on Clocked CMOS logic. 5M
    UNIT-V
    10. a) What are different categories of DFT techniques? Explain. 5M
    b) Explain Combinational logic testing with example. 5M
    OR
    11. a) Explain Sequential logic testing with example. 6M
    b) Mention the drawbacks of serial scan. 4M
    *****

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