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(AUTONOMOUS)

I M. Tech I Semester Regular Examinations, April – 2022


(Regulations: VCE-R21)
LOW POWER VLSI DESIGN
(Digital Electronics and Communication Systems)
Date: 29 April, 2022 Time: 3 hours Max Marks: 100
Answer All Questions

PART-A
1. a) Briefly discuss about short channel effect. 3M
b) List the sources of power dissipation in CMOS circuits. 3M
c) Inspect the power estimation using input vector compaction. 3M
d) List the different sources of software power dissipation. 3M
e) Briefly discuss about pin ordering of two input NAND gate. 3M
f) Realize the mux based combinational flip flops. 3M
g) Briefly explain about clocked logic family. 3M
h) With neat sketch, briefly explain self-adjusting threshold voltages scheme. 3M
i) Briefly explain about time multiplexed charge recycling bus. 3M
j) Realize two input mux using pass transistor logic. 3M

PART-B
2. a) Explain the device limits in low power VLSI design. 7M
b) With relevant sketches, obtain an expression for the threshold voltage of a MIS diode. 7M
(OR)
c) With relevant sketches, develop an expression for dynamic power dissipation for a 7M
CMOS inverter driving load capacitance (CL).
d) Explain how drain induced barrier lowering (DIBL), and gate induced drain leakage 7M
(GIDL) affects the power dissipation in submicron MOSFET.

3. a) Discuss the procedure to perform the Monte Carlo based power estimation of 7M
glitching power.
b) Explain how operator reduction helps in realization of summation, comment on power 7M
dissipation.
(OR)
c) Explain the role of instruction level power analysis (ILPA) in software power 7M
estimation.
d Explain in detail, how to minimize the power budget due to memory access. 7M

4. a) Derive an expression for power consumption of inverter chain driving the large 7M
capacitive load.
b) Explain how self-gating Flip-Flop helps to reduce the power of clocking circuits. 7M
(OR)
c) With an example, discuss how transistor networking restructuring technique helps to 7M
reduce the power dissipation.
d) Realize single edge triggered and double edge trigged flip flops, comment an area, 7M
speed and power.
5. a) Realize the following function Y = (a + bc) using static CMOS and Dynamic logic, and 7M
comment on area and power dissipation.
b) List the sources of transistor leakage current mechanisms, and explain any one source 7M
in detail.

Cont…2

::2::

(OR)
c) Explain differential cascade voltage switch logic pre-charged high and low circuits. 7M
d) With relevant sketches, explain short channel threshold voltage roll-off in deep sub 7M
micrometer devices.

6. a) Explain clock gating and reducing swing in clocked circuits. 7M


b) Briefly explain about pass transistor logic synthesis system. 7M
(OR)
c) Discuss the need of delay balancing in an array multiplier. 7M
d) With relevant sketches, explain the operation of asynchronous systems. 7M

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