(Wear-out Failure) (Infant Mortality Failure) (Time-

Dependent Dielectric Breakdown, TDDB) (Hard Breakdown, HBD)

(Soft Breakdown, SBD) (Stress-Induced Leakage Current, SILC)
(Channel Hot Electron, CHE) (Drain Avalanche Hot Carrier,
DAHC) (Electromigration) (Grain Boundary Diffusion)
(Lattice Diffusion)

( We a r - o u t
8 49
 Failure) Temperature (°C)
150 100 50 25 0
(Infant Mortality Fai- 5

lure) γ ≈ 0.78 + 0.064/kBT (cm/MV)

4
(Stress)

γ (T) (cm/MV)
3

2 2.5 3 3.5 4
( Ti m e - 1000/T (K–1)

Dependent Dielectric Breakdown, TDDB)

E 1/E

C2 γ
1µA Fowler-Nordheim
(Tunneling Current)
(Anode Hole Injection Model)
(tbd) 1/E

tbd=C2exp(-γ/E)

E 1/E
(Lifetime)
E
(Accelerated Model) TDDB

Arrhenius Equation t bd = C ⋅ 10 – γE ⋅ exp Ea

kT

tbd=C1exp(Ea/kT) TDDB
Ea γ
C1 k T Ea
Ea
(Activation Energy) γ
Ea
γ
E

tbd=C2exp(-γE) (Constant Voltage Stressing,

50 8
CVS) CRVS (Constant CVS
Ramped Voltage Stressing) TDDB C RV S
(Breakdown Voltage, V bd) Vbd

(Charge To
E bd ~V bd /T α Breakdown, Q bd)
A (A Q bd

Mode) B (B Mode) C (C CCS(Constant Current Stressing)

Mode) A ERCS(Exponential Ramped Current
1MV/cm B Stressing)
2~6MV/cm C Q bd
8MV/cm A B Q bd
(Extrinsic Failure)
(Defect) CCS
C Q bd J stress ERCS
(Intrinsic Failure) Q bd t d(Delay Time)
CCS ERCS Q bd

Temperature (°C)
150 100 50 25 0 [3]
1010

108
QBD=AERCS(td)-n, for ERCS
Intrinsic tBD (sec)

EG = –10MV/cm
106 EG = –11MV/cm
QBD=ACCS(J)-m, for CCS
ACCS=(101/s/(101/s-1)-m(AERCS)m+1
104
n=m/(1+m)
102
EG = –12MV/cm
s ERCS decade
100
2 2.5 3 3.5 4
1000/T (K–1)
100
1.0
Activation Energy Ea (eV)

Ea ≈ 1.15 – 0.07 Eox (eV)

0.8 80
Breakdown Frequency

0.6
60 B MODE

0.4

0.2 40
C MODE

EG 6 7 8 9 10 11 12 13 14 20
A MODE
Eox 5 6 7 8 9 10 11 12 13
(MV/cm)
0
0 5 10
Breakdown Field (MV/cm)

8 51
 MOSFET
(Drain)

(Hard Carrier
Breakdown, HBD) (Depletion Region)

(Stress-
Induced Leakage Current, SILC) (Impact Ionization)
(Soft Breakdown, SBD) NMOS
(Substrate)
Si/SiO2
(Barrier Height)
(Charge Trapping)
(channel length) (Interface-State Generation)

(Threshold Voltage,
100 Vt) (Transconductance, Gm)
BD
Current Density (A/cm2)

10–2
Soft BD
(Injection Mechanism)
10–4
SILC (Channel Hot Electron, CHE)
10–6 (Drain Avalanche
fresh
Hot Carrier, DAHC) CHE
10–8
0 1 2 3 4 5 6 (Gate)
Gate Voltage
(Electron Trapping)
(Lucky Electron Model)
DAHC

VGS < VDS

IG Poly-Si gate
+7.0E–0.3 PRE-STRESS
Vs = 0 VDS POST-STRESS
tox Leff
IDS +6.0E–0.3
– +– +5.0E–0.3
Drain Current Ids (A)

χj –– D
S +– +4.0E–0.3
Inversion
+ –
+3.0E–0.3
layer
+ Depletion
layer edge +2.0E–0.3

p-Si (substrate) Isub +1.0E–0.3

+0.0E+0.0
0 1 2 3 4 5 6
VBB < 0 Drain Voltage Vds (V)

52 8
 Ids 10%
(1) (Worst-Case)
Power
(2) Vt Gm Ids Law Y(t)=Ct n Y(t)
(3)
(Vt) Gm
Ids t C n
NMOSFET

Substrate/Drain Current Ratio Method

JEDEC 90% Substrate
Current Method
Vt 100mV Gm 10% Drain Voltage Acceleration
Method

VD,S = 6.5V
t f ⋅ I DS I – m1
= C 1 ⋅ BS
W I DS
7.0V

tf ID,S 7.5V I BS – m 3
log
Yf1/nW
tf = C3 ⋅
W
8.0V
m2
t f = C 2 ⋅ exp
V DS

tf W I BS
IB,S
log I DS V DS
ID,S
C1 C2 C3 m1 m2 m3

log tf
ln tf

IB,S 1
log
W VD,S

8 53
 PMOSFET

(Effective Mass)

(Electron Wind)

Blech Length

(Grain Size)
(Poly-Grain)

(Vacancy) (Grain
Boundary Diffusion)
(Open Circuit)
(Hillock) (Single-Grain)
(Short
Circuit) (Lattice Diffusion)

(Grain Boundary)

(Black Equation)

t 50 = A ⋅ J – n ⋅ exp Ea
kT

t 50 50% Median
Time J n
Ea (Activation Energy)

10
Normalized 150

Voids
Hillocks
1
– +

0.1
0 1 2 3 4 5 6 7
Aluminium Conductor Test Pattern Linewidth (µm)

54 8
 45
Gate Delay
40 Sum of Delays, Al & SiO2
(2)
Sum of Delays, Cu & Low κ
35
Interconnect Delay, Al & SiO2 (3)
30 Interconnect Delay, Cu & Low κ
Delay (ps)

25
Gate wi Al & SiO2 Al 3.0 µΩ –cm
20 Cu 1.7 µΩ –cm
Gate wi Cu SiO2 κ = 4.0
15 & Low κ
Low κ κ = 2.0
10 Al & Cu .8 µ Thick (Dual Damascene)
Gate
Al & Cu Line 43 µ Long
5

0
650 500 350 250 180 130 100
Generation (nm) IC

T k

(Log-Normal Distribution) n
2 Ea

0.6~0.7 eV
1.0~1.2 eV
1. J.W. Mcpherson and D.A. Baglee,
Acceleration Factors for Thin Gate Oxide
(Intrinsic Gate Delay)
Stressing, IRPS, 1985, p. 1.
(Interconnect Delay) 2. J.C. Lee, I.C. Chen, and C. Hu, Modeling
and Characterization of Gate Oxide
Reliability, ED-35, 1988, p. 2268.
3. C.H. Liu, T.J. Cheng, and K.Y. Fu, An
Efficient Process Evaluation Method for Ultra-
Thin Gate Oxides, , SSDM, 1999, p. 336.
4. M.G. Chen, C.H. Liu, M.T. Lee, and K.Y. Fu,
New Experimental Findings on SILC and Soft
Breakdown of Ultra-Thin Gate Oxides, IRW,
1999, p. 114.
(Resistivity) 1.7µΩ
5. C Hu, S. Tam, F.C. Hsu, P.K. Ko, T.Y. Chan,
-cm 2.7µΩ-cm
and K.W. Terill, Hot-Electron Induced
40% MOSFET Degradation-Model, Monitor, AND
1090°C 660°C Improvement, ED-32, 1985, p. 375.
6. M.L. Dryer, K.Y. Fu and C.J. Varker, The
Effects of Temperature and Microstructure on
the Components of Electromigration Mass
Transport, IRPS, 1993, p. 304.
7. B.N. Agarwala, M.J. Attardo, and A.P.
Ingraham, Dependence of Electro-migration-
Induced Failure Time on Length and Width of
(1)
Aluminum Thin-Film Conductor, JAP-41,
1970, p. 3954.
(Barrier Layer)
8 55