AN2586

Application note
STM32F10xxx hardware development:
getting started

Introduction
This application note is intended for system designers who require a hardware
implementation overview of the development board features such as the power supply, the
clock management, the reset control, the boot mode settings and the debug management. It
shows how to use the STM32F10xxx product family and describes the minimum hardware
resources required to develop an STM32F10xxx application.
Detailed reference design schematics are also contained in this document with descriptions
of the main components, interfaces and modes.

July 2007 Rev 1 1/23

www.st.com
Contents AN2586 - Application note

Contents

1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.1 Independent A/D converter supply and reference voltage . . . . . . . . . . . . 6
1.1.2 Battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 Reset & power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.1 Power on reset (POR) / power down reset (PDR) . . . . . . . . . . . . . . . . . . 8
1.3.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.3 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 HSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.1 External source (HSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.2 External crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . 12
2.2 LSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.1 External source (LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.2 External crystal/ceramic resonator (LSE crystal) . . . . . . . . . . . . . . . . . . 13
2.3 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 Boot pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3 Embedded Boot Loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4 Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3.1 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3.2 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3.3 Internal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . . . 18

2/23
AN2586 - Application note Contents

4.3.4 SWJ debug port connection with Standard JTAG connector . . . . . . . . . 19

5 Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1 Main . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.3 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2 SWJ interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3/23
List of tables AN2586 - Application note

List of tables

Table 1. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 2. Debug port pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3. SWJ I/O pin availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4/23
AN2586 - Application note List of figures

List of figures

Figure 1. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. PVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Clock overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Boot mode selection implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. Host-to-board connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. JTAG connector implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14. STM32F10xxx microcontroller reference schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5/23
Power supplies AN2586 - Application note

1 Power supplies

1.1 Introduction
The device requires a 2.0 V to 3.6 V operating voltage supply (VDD). An embedded regulator
is used to supply the internal 1.8 V digital power.
The real-time clock (RTC) and backup registers can be powered from the VBAT voltage when
the main VDD supply is powered off.

Figure 1. Power supply overview

VDDA domain
VREF-
VREF+ A/D converter
Temp. sensor
VDDA Reset block
PLL
VSSA

VDD domain 1.8 V domain

I/O Ring
VSS Core
Standby circuitry memories'
VDD (Wakeup logic, digital
IWDG) peripherals

Voltage regulator

Low voltage detector

Backup domain
LSE crystal 32K osc
VBAT
BKP registers
RCC BDCR register
RTC

ai14602b

1.1.1 Independent A/D converter supply and reference voltage

To improve conversion accuracy, the ADC has an independent power supply that can be
filtered separately, and shielded from noise on the PCB.
● the ADC voltage supply input is available on a separate VDDA pin
● an isolated supply ground connection is provided on the VSSA pin
When available (depending on package), VREF– must be tied to VSSA.

On 100-pin packages
To ensure a better accuracy on low-voltage inputs, the user can connect a separate external
reference voltage ADC input on VREF+. The voltage on VREF+ may range from 2.0 V to
VDDA.

6/23
AN2586 - Application note Power supplies

On packages with 64 pins or less

The VREF+ and VREF- pins are not available, they are internally connected to the ADC
voltage supply (VDDA) and ground (VSSA).

1.1.2 Battery backup

To retain the content of the Backup registers when VDD is turned off, the VBAT pin can be
connected to an optional standby voltage supplied by a battery or another source.
The VBAT pin also powers the RTC unit, allowing the RTC to operate even when the main
digital supply (VDD) is turned off. The switch to the VBAT supply is controlled by the power
down reset (PDR) circuitry embedded in the Reset block.
If no external battery is used in the application, VBAT must be connected externally to VDD.

1.1.3 Voltage regulator

The voltage regulator is always enabled after reset. It works in three different modes
depending on the application modes.
● in Run mode, the regulator supplies full power to the 1.8 V domain (core, memories and
digital peripherals)
● in Stop mode, the regulator supplies low power to the 1.8 V domain, preserving the
contents of the registers and SRAM
● in Standby mode, the regulator is powered off. The contents of the registers and SRAM
are lost except for those concerned with the Standby circuitry and the Backup domain.

1.2 Power supply schemes

The circuit is powered by a stabilized power supply, VDD.
● Caution:
– If the ADC is used, the VDD range is limited to 2.4 V to 3.6 V
– If the ADC is not used, the VDD range is 2 V to 3.6 V
● The VDD pins must be connected to VDD with external stabilization capacitors (five
100 nF ceramic capacitor + one Tantalum capacitor (min. 4.7 µF typ.10 µF).
● The VBAT pin must be connected to the external battery (1.8 V < VBAT < 3.6 V). if no
external battery is used, this pin must be connected to VDD with a 100 nF external
ceramic stabilization capacitor.
● The VDDA pin must be connected to two external stabilization capacitors (10 nF
ceramic + 1 µF Tantalum).
● The VREF+ pin can be connected to the VDDA external power supply. If a separate,
external reference voltage is applied on VREF+, two 10 nF and 1 µF capacitors must be
connected on this pin. In all cases, VREF+ must be kept between 2.0 V and VDDA.

7/23
Power supplies AN2586 - Application note

Figure 2. Power supply scheme

STM32F10xxx
VBAT VREF
VBAT VREF+
Battery VDD 10 nF + 1 µF
(note 1)
VDDA
VDD 10 nF + 1 µF
VSSA
5 × 100 nF VDD 1/2/3/4/5
+ 1 × 10 µF VREF–
VSS 1/2/3/4/5

ai14363

1. Optional. If a separate, external reference voltage is connected on VREF+, the two capacitors (10 nF and
1 µF) must be connected.
2. VREF+ is either connected to VDDA or to VREF.

1.3 Reset & power supply supervisor

1.3.1 Power on reset (POR) / power down reset (PDR)

The device has an integrated POR/PDR circuitry that allows proper operation starting from
2 V.
The device remains in the Reset mode as long as VDD is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit. For more details concerning the
power on/power down reset threshold, refer to the electrical characteristics in the
STM32F101xx and STM32F103xx datasheets.

Figure 3. Power on reset/power down reset waveform

VDD

POR

40 mV PDR
hysteresis

Temporization
tRSTTEMPO

RESET
ai14364

8/23
AN2586 - Application note Power supplies

1.3.2 Programmable voltage detector (PVD)

You can use the PVD to monitor the VDD power supply by comparing it to a threshold
selected by the PLS[2:0] bits in the Power control register (PWR_CR).
The PVD is enabled by setting the PVDE bit.
A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate
whether VDD is higher or lower than the PVD threshold. This event is internally connected to
EXTI Line16 and can generate an interrupt if enabled through the EXTI registers. The PVD
output interrupt can be generated when VDD drops below the PVD threshold and/or when
VDD rises above the PVD threshold depending on the EXTI Line16 rising/falling edge
configuration. As an example the service routine can perform emergency shutdown tasks.

Figure 4. PVD thresholds

VDD

PVD threshold 100 mV

hysteresis

PVD output

ai14365

1.3.3 System reset

A system reset sets all registers to their reset values except for the reset flags in the clock
controller CSR register and the registers in the Backup domain (see Figure 1).
A system reset is generated when one of the following events occurs:
1. A low level on the NRST pin (external reset)
2. window watchdog end-of-count condition (WWDG reset)
3. Independent watchdog end-of-count condition (IWDG reset)
4. A software reset (SW reset)
5. Low-power management reset
The reset source can be identified by checking the reset flags in the Control/Status register,
RCC_CSR.

9/23
Power supplies AN2586 - Application note

Figure 5. Reset circuit

V DD
External
reset circuit
RON
NRST
Filter System nreset

0.1 µF

Pulse WWDG reset

IWDG reset
generator POR/PDR reset
(min 20 µs) Software reset
Low-power management reset

ai14366

10/23
AN2586 - Application note Clocks

2 Clocks

Three different clock sources can be used to drive the system clock (SYSCLK):
● HSI oscillator clock (high speed internal clock signal)
● HSE oscillator clock (high speed external clock signal)
● PLL clock
The devices have two secondary clock sources:
● 32 kHz low speed internal RC (LSI RC) that drives the independent watchdog and,
optionally, the RTC used for Auto Wake-up from the Stop/Standby modes.
● 32.768 kHz low speed external crystal (LSE crystal) that optionally drives the real-time
clock (RTCCLK)
Each clock source can be switched on or off independently when it is not used, to optimize
the power consumption.

Figure 6. Clock overview

8 MHz
HSI RC HSI USBCLK
USB 48 MHz
Prescaler to USB interface
/2 /1, 1.5
HCLK
72 MHz max to AHB bus, core,
Clock memory and DMA
/8 Enable (3 bits) to Cortex System timer
PLLSRC SW
PLLMUL FCLK Cortex
free running clock
HSI SYSCLK AHB APB1
..., x16 36 MHz max PCLK1
x2, x3, x4 Prescaler Prescaler
PLLCLK 72 MHz to APB1
PLL max /1,2...512 /1, 2, 4, 8, 16 peripherals
HSE Peripheral Clock
Enable (13 bits)
to TIM2, 3
TIM2, 3, 4 and 4
CSS x1, 2 Multiplier TIMXCLK
Peripheral Clock
Enable (3 bits)
PLLXTPRE APB2 72 MHz max PCLK2
Prescaler
OSC_OUT to APB2
4-16 MHz /1, 2, 4, 8, 16 peripherals
Peripheral Clock
HSE OSC
OSC_IN /2 Enable (11 bits)
TIM1 Timer to TIM1
x1, 2 Multiplier TIM1CLK
Peripheral Clock
/128 Enable (1 bit)
ADC to ADC
OSC32_IN LSE to RTC Prescaler
LSE OSC ADCCLK
32.768 kHz RTCCLK /2, 4, 6, 8
OS32_OUT
RTCSEL[1:0]

LSI RC LSI to independent watchdog (IWDG)

32 kHz IWDGCLK

Main /2 PLLCLK
Clock Output
MCO HSI
HSE
SYSCLK
MCO ai14367

1. HSE = High-speed external clock signal; HSI = high-speed internal clock signal; LSI = low-speed internal
clock signal; LSE = low-speed external clock signal.

11/23
Clocks AN2586 - Application note

2.1 HSE OSC clock

The high speed external clock signal (HSE) can be generated from two possible clock
sources:
● HSE external crystal/ceramic resonator (see Figure 8)
● HSE user external clock (see Figure 7)

Figure 7. External clock Figure 8. Crystal/ceramic resonators

Hardware configuration

STM32F10xxx
Hardware configuration
OSC_IN OSC_OUT
OSC_IN OSC_OUT
REXT(1)

(Hi-Z)
External source
ai14369 CL1 CL2

ai14370

1. CL1 and CL2 represent the load capacitances.

2. The value of REXT depends on the crystal characteristics. Typical value is in the range of 5 to 6 RS
(resonator series resistance).

2.1.1 External source (HSE bypass)

In this mode, an external clock source must be provided. It can have a frequency of up to
25 MHz. The external clock signal (square, sine or triangle) with a duty cycle of about 50%,
has to drive the OSC_IN pin while the OSC_OUT pin must be left in the high impedance
state (see Figure 8 and Figure 7).

2.1.2 External crystal/ceramic resonator (HSE crystal)

The 4-to-16 MHz external oscillator has the advantage of producing a very accurate rate on
the main clock. The associated hardware configuration is shown in Figure 8.
The resonator and the load capacitors have to be connected as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The load
capacitance values must be adjusted according to the selected oscillator.
For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF-to-
25 pF range (typ.), designed for high-frequency applications and selected to meet the
requirements of the crystal or resonator. CL1 and CL2, are usually the same value. The
crystal manufacturer typically specifies a load capacitance that is the series combination of
CL1 and CL2. The PCB and MCU pin capacitances must be included when sizing CL1 and
CL2 (10 pF can be used as a rough estimate of the combined pin and board capacitance).
Refer to the electrical characteristics sections in the STM32F101xx and STM32F103xx
datasheets for more details.

12/23
AN2586 - Application note Clocks

2.2 LSE OSC clock

The low-speed external clock signal (LSE) can be generated from two possible clock
sources:
● LSE external crystal/ceramic resonator (see Figure 10)
● LSE user external clock (see Figure 9)

Figure 9. External clock Figure 10. Crystal/ceramic resonators

Hardware configuration

Hardware configuration STM32F10xxx

OSC32_IN OSC32_OUT
OSC32_IN OSC32_OUT

(Hi-Z)
External source
CL1 CL2
ai14371

ai14372

2.2.1 External source (LSE bypass)

In this mode, an external clock source must be provided. It must have a frequency of
32.768 kHz. The external clock signal (square, sine or triangle) with a duty cycle of about
50% has to drive the OSC32_IN pin while the OSC32_OUT pin must be left high impedance
(see Figure 10 and Figure 9).

2.2.2 External crystal/ceramic resonator (LSE crystal)

The LSE crystal is a 32.768 kHz low speed external crystal or ceramic resonator. It has the
advantage of providing a low-power, but highly accurate clock source to the real-time clock
peripheral (RTC) for clock/calendar or other timing functions.
The resonator and the load capacitors have to be connected as close as possible to the
oscillator pins in order to minimize output distortion and start-up stabilization time. The load
capacitance values must be adjusted according to the selected oscillator.

2.3 Clock-out capability

The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin. The configuration registers of the corresponding GPIO port must be
programmed in alternate function mode. One out of four clock signals can be selected as
the MCO clock:
● SYSCLK
● HSI
● HSE
● PLL clock divided by 2

13/23
Clocks AN2586 - Application note

2.4 Clock security system (CSS)

The clock security system can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
● If a failure is detected on the HSE oscillator clock, the oscillator is automatically
disabled. A clock failure event is sent to the break input of the TIM1 advanced control
timer and an interrupt is generated to inform the software about the failure (clock
security system interrupt CSSI), allowing the MCU to perform rescue operations. The
CSSI is linked to the Cortex™-M3 NMI (non-maskable interrupt) exception vector.
● If the HSE oscillator is used directly or indirectly as the system clock (indirectly means
that it is used as the PLL input clock, and the PLL clock is used as the system clock), a
detected failure causes a switch of the system clock to the HSI oscillator and the
disabling of the external HSE oscillator. If the HSE oscillator clock (divided or not) is the
clock entry of the PLL used as system clock when the failure occurs, the PLL is
disabled too.
For details, see reference manual UM0306 available from the STMicroelectronics website
www.st.com.

14/23
AN2586 - Application note Boot configuration

3 Boot configuration

3.1 Boot mode selection

In the STM32F10xxx, three different boot modes can be selected by means of the
BOOT[1:0] pins as shown in Table 1.

Table 1. Boot modes

BOOT mode selection pins
Boot mode Aliasing
BOOT1 BOOT0

User Flash memory is selected as boot

x 0 User Flash memory
space
System memory is selected as boot
0 1 System memory
space
Embedded SRAM is selected as boot
1 1 Embedded SRAM
space

This selection aliases the physical memory associated with each boot mode to Block 000
(boot memory). The values on the BOOT pins are latched on the 4th rising edge of SYSCLK
after a reset. It is up to the user to set the BOOT1 and BOOT0 pins after reset to select the
required boot mode.
The BOOT pins are also re-sampled when exiting the Standby mode. Consequently, they
must be kept in the required Boot mode configuration in the Standby mode.
Even when aliased in the boot memory space, the related memory (Flash memory or
SRAM) is still accessible at its original memory space.
After this startup delay has elapsed, the CPU starts code execution from the boot memory,
located at the bottom of the memory address space starting from 0x0000_0000.

3.2 Boot pin connection

Figure 11 shows the external connection required to select the boot memory of the
STM32F10xxx.

Figure 11. Boot mode selection implementation example

STM32F10xxx

VDD
10 kΩ
BOOT0
VDD
10 kΩ
BOOT1

ai14373

1. Resistor values are given only as a typical example.

15/23
Boot configuration AN2586 - Application note

3.3 Embedded Boot Loader mode

The Embedded Boot Loader mode is used to reprogram the Flash memory using one of the
serial interfaces (typically a UART). This program is located in the system memory and is
programmed by ST during production.
For details, refer to the STM32F10xxx Flash programming manual, PM0042, available from
the STMicroelectronics website, www.st.com.

16/23
AN2586 - Application note Debug management

4 Debug management

4.1 Introduction
The Host/Target interface is the hardware equipment that connects the host to the
application board. This interface is made of three components: a hardware debug tool, a
JTAG or SW connector and a cable connecting the host to the debug tool.
Figure 12 shows the connection of the host to the STM3210B-EVAL board.

Figure 12. Host-to-board connection

Debug tool JTAG/SW connector

Host PC Power supply

STM3210B-EVAL
ai14374

4.2 SWJ debug port (serial wire and JTAG)

The STM32F10xxx core integrates the serial wire / JTAG debug port (SWJ-DP). It is an
ARM® standard CoreSight™ debug port that combines a JTAG-DP (5-pin) interface and a
SW-DP (2-pin) interface.
● The JTAG debug port (JTAG-DP) provides a 5-pin standard JTAG interface to the AHP-
AP port
● The serial wire debug port (SW-DP) provides a 2-pin (clock + data) interface to the
AHP-AP port
In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG
pins of the JTAG-DP.

4.3 Pinout and debug port pins

The STM32F10xxx MCU is offered in various packages with different numbers of available
pins. As a result, some functionality related to the pin availability may differ from one
package to another.

4.3.1 SWJ debug port pins

Five pins are used as outputs for the SWJ-DP as alternate functions of general-purpose
I/Os (GPIOs). These pins, shown in Table 2, are available on all packages.

17/23
Debug management AN2586 - Application note

Table 2. Debug port pin assignment

JTAG debug port SW debug port
Pin
SWJ-DP pin name
assignment
Type Description Type Debug assignment

JTAG Test Mode Serial Wire Data

JTMS/SWDIO I I/O PA13
Selection Input/Output
JTCK/SWCLK I JTAG Test Clock I Serial Wire Clock PA14
JTDI I JTAG Test Data Input - - PA15
TRACESWO if async trace
JTDO/TRACESWO O JTAG Test Data Output - PB3
is enabled
JNTRST I JTAG Test nReset - - PB4

4.3.2 Flexible SWJ-DP pin assignment

After reset (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned as
dedicated pins immediately usable by the debugger host (note that the trace outputs are not
assigned except if explicitly programmed by the debugger host).
However, the STM32F10xxx MCU implements a register to disable some part or all of the
SWJ-DP port, and so releases the associated pins for general-purpose I/Os usage. This
register is mapped on an APB bridge connected to the Cortex™-M3 system bus. This
register is programmed by the user software program and not by the debugger host.

Table 3. SWJ I/O pin availability

SWJ I/O pin assigned

Available Debug ports PA13 / PA14 /

PA15 / PB3 / PB4/
JTMS/ JTCK/
JTDI JTDO JNTRST
SWDIO SWCLK

Full SWJ (JTAG-DP + SW-DP) - reset state X X X X X

Full SWJ (JTAG-DP + SW-DP) but without

X X X X
JNTRST

JTAG-DP disabled and SW-DP enabled X X

JTAG-DP disabled and SW-DP disabled Released

Table 3 shows the different possibilities to release some pins.

For more details, see the STM32F10xxx reference manual, UM0306, available from the
STMicroelectronics website www.st.com.

4.3.3 Internal pull-up and pull-down on JTAG pins

The JTAG input pins must not be floating since they are directly connected to flip-flops to
control the debug mode features. Special care must be taken with the SWCLK/TCK pin that
is directly connected to the clock of some of these flip-flops.

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AN2586 - Application note Debug management

To avoid any uncontrolled I/O levels, the STM32F10xxx embeds internal pull-up and pull-
down resistors on JTAG input pins:
● JNTRST: Internal pull-up
● JTDI: Internal pull-up
● JTMS/SWDIO: Internal pull-up
● TCK/SWCLK: Internal pull-down
Once a JTAG I/O is released by the user software, the GPIO controller takes control again.
The reset states of the GPIO control registers put the I/Os in the equivalent state:
● JNTRST: Input pull-up
● JTDI: Input pull-up
● JTMS/SWDIO: Input pull-up
● JTCK/SWCLK: Input pull-down
● JTDO: Input floating
The software can then use these I/Os as standard GPIOs.
Note: The JTAG IEEE standard recommends to add pull-up resistors on TDI, TMS and nTRST but
there is no special recommendation for TCK. However, for the STM32F10xxx, an integrated
pull-down resistor is used for JTCK.
Having embedded pull-up and pull-down resistors removes the need to add external
resistors.

4.3.4 SWJ debug port connection with Standard JTAG connector

Figure 13 shows the connection between the STM32F10xxx and a standard JTAG
connector.

Figure 13. JTAG connector implementation

JTAG connector CN9
VDD VDD
Connector 2 × 10
STM32F10xxx

(1) VTREF (2)

nJTRST (3) nTRST (4)
JTDI (5) TDI (6)
JSTM/SWDIO (7) TMS (8)
JTCK/SWCLK (9) TCK (10)
(11) RTCK (12)
JTDO (13)TDO (14)
nRSTIN (15) nSRST (16)
(17) DBGRQ (18)
10 kΩ (19) DBGACK (20)
10 kΩ
10 kΩ VSS

ai14376

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Reference design AN2586 - Application note

5 Reference design

5.1 Main
The reference design shown in Figure 14, is based on the STM32F10xxx, a highly
integrated microcontroller running at 72 MHz, that combines the new Cortex™-M3 32-bit
RISC CPU core with 128 Kbytes of embedded Flash memory and up to 20 Kbytes of high
speed SRAM.

5.1.1 Clock
Two clock sources are used for the microcontroller:
● X1– 32.768 kHz crystal for the embedded RTC
● X2– 8 MHz crystal for the STM32F10xxx microcontroller
Refer to Section 2: Clocks on page 11.

5.1.2 Reset
The reset signal in Figure 14 is active low. The reset sources include:
● Reset button (B1)
● Debugging tools via the connector CN1
Refer to Section 1.3: Reset & power supply supervisor on page 8.

5.1.3 Boot mode

The STM32F10xxx is able to boot from the:
● embedded user Flash memory
● embedded SRAM for debugging
● system memory
The boot option is configured by setting switches SW2 (Boot 0) and SW1 (Boot 1). Refer to
Section 3: Boot configuration on page 15.

5.2 SWJ interface

The STM32F10xxx core integrates the serial wire / JTAG debug port (SWJ-DP). The
reference design shows the connection between the STM32F10xxx and a standard JTAG
connector. Refer to Section 4: Debug management on page 17.

5.3 Power supply

Refer to Section 1: Power supplies on page 6.

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 C1
U1A 10 pF
PA0 23 9 PC15

4
3
PA0-WKUP/USART2_CTS/ADC_IN0/TIM2_CH1_ETR PC15-OSC32_OUT
PA1 24 8 PC14 0
PA1/USART2_RTS/ADC_IN1 PC14-OSC32_IN X1
JTAG connector PA2 25 7 PC13
PA2/USART2_TX/ADC_IN2/ PC13-ANTI_TAMP MC306-G-06Q-32.768 (manufacturer JFVNY)
PA3 26 80 PC12
PA3/USART2_RX/ADC_IN3/ PC12
CN1 PA4 29 79 PC11

2
PA4/SPI1_NSS/USART2_CK/ADC_IN4 PC11
AN2586 - Application note

JTAG VCC PA5 30 78 PC10

PA5/SPI1_SCK/ADC_IN5 PC10
1 PA6 31 66 PC9 C2
TP1 PA6/SPI1_MISO/ADC_IN6/TIM3_CH1 PC9
2 PA7 32 65 PC8 10 pF
PA7/SPI1_MOSI/ADC_IN7/TIM3_CH2 PC8
3 TRST PA8 67 64 PC7
PA8/USART1_CK/ TIM1_CH1/MCO PC7
4 MCO PA9 68 63 PC6
PA9/USART1_TX/TIM1_CH2 PC6
5 TDI PA10 69 34 PC5
PA10/USART1_RX/TIM1_CH3 PC5/ADC_IN15
6 PA11 70 33 PC4
PA11 / USART1_CTS/CANRX / USBDM (2)/TIM1_CH4 PC4/ADC_IN14
7 TMS/SWDIO PA12 71 18 PC3
PA12 / USART1_RTS/CANTX / USBDP (2)/TIM1_ETR PC3/ADC_IN13
8 PA13 72 17 PC2
PA13/JTMS-SWDAT PC2/ADC_IN12
9 TCK/SWCLK PA14 76 16 PC1
PA14/JTCK-SWCLK PC1/ADC_IN11
10 PA15 77 15 PC0 VCC VDD U1B
R2 PA15/JTDI PC0/ADC_IN10 JP1
11 RTCK 21
VREF+
12 10 kΩ 62 PD15 22
PD15 VDDA
13 TDO PB0 35 61 PD14 11 20
PB0/ADC_IN8/TIM3_CH3 PD14 VDD_5 VREF-
14 PB1 36 60 PD13 C3 C4 28 19
PB1/ADC_IN9/TIM3_CH4 PD13 VDD_4 VSSA
15 RESET# PB2 37 59 PD12 1 µF 10 nF 50
PB2 / BOOT1 PD12 VDD_1
16 PB3 89 58 PD11 75 74
PB3/JTDO PD11 VDD_2 VSS_2
17 DBGRQ R3 10 kΩ PB4 90 57 PD10 100 99
PB4/JTRST PD10 VDD VDD_3 VSS_3
18 PB5 91 56 PD9 49
PB5/I2C1_SMBAl PD9 VSS_1
19 DBGACK R4 10 kΩ PB6 92 55 PD8 6 27
PB6/I2C1_SCL/TIM4_CH1 PD8 VBAT VSS_4
20 PB7 93 88 PD7 10
PB7/I2C1_SDA/ PD7 VSS_5
PB8 95 87 PD6 VBAT
PB8/TIM4_CH3 PD6 BT1
PB9 96 86 PD5 STM32F103VBH6
PB9/TIM4_CH4 PD5 CR1220 holder
PB10 47 85 PD4
PB10/I2C2_SCL/USART3_TX PD4
PB11 48 84 PD3
PB11/I2C2_SDA / PD3
PB12 51 83 PD2
PB12/SPI2_NSS /I2C2_SMBAl/USART3_CK /TIM1_BKIN PD2/TIM3_ETR
PB13 52 82 PD1
PB13/SPI2_SCK /USART3_CTS /TIM1_CH1N PD1
PB14 53 81 PD0
PB14/SPI2_MISO /USART3_RTS /TIM1_CH2N PD0
PB15 54
PB15/SPI2_MOSI/TIM1_CH3N
X2 46 PE15 VDD
PE15
8 MHz 45 PE14
PE14
OSC_IN 12 44 PE13
OSC_IN PE13
C5 OSC_OUT 13 43 PE12 C7 C8 C9 C10 C11 C12
OSC_OUT PE12
20 pF RESET# 14 42 PE11 4.7 µF 100 nF 100 nF 100 nF 100 nF 100 nF
NRST PE11
41 PE10
PE10
BOOT1 BOOT0 94 40 PE9
BOOT0 PE9
C6 39 PE8
REXT PE8
R5 R6 73 38 PE7
Not connected PE7
10 kΩ 10 kΩ 5 PE6
PE6
20 pF 4 PE5
PE5
3 PE4

2
2
Figure 14. STM32F10xxx microcontroller reference schematic

B1 PE4
2 PE3
PE3
1 2 SW1 SW2 1 PE2
PE2
98 PE1
PE1
4 3 97 PE0

1
3
1
3
PE0/TIM4_ETR
RESET
STM32F103VBH6
C13 VCC VCC

100 nF

Notes:
- Capacitors (C3,C4,C7-12) should be placed on the PCB tracks closest to the VDD, VDDA and GND pins of the Microcontrollers
- VCC: mains power supply: the range is between 2.0 and 3.6 Volts (see Section 1 Power supplies) ai14360
- The value of REXT depends on the crystal characteristics. Typical value is in the range of 5 to 6 RS (resonator series resistance) as indicated in Section 2.1.

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Reference design
Revision history AN2586 - Application note

6 Revision history

Table 4. Document revision history

Date Revision Changes

12-Jul-2007 1 Initial release.

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AN2586 - Application note

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