1.

Full adder
 Thiết kế logic

 Bảng trạng thái

 Mô phỏng

module Adder1bit(
input wire a,b, cin, output wire s, cout
);

assign s = a^b^cin;
assign cout = (a&b)|(cin*(a^b));
endmodule

 Test bench
module banch1bit;

// Inputs
reg a;
reg b;
reg cin;

// Outputs
wire s;
wire cout;

// Instantiate the Unit Under Test (UUT)

Adder1bit uut (
.a(a),
.b(b),
.cin(cin),
.s(s),
.cout(cout)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;
cin = 0;

// Wait 100 ns for global reset to finish

#10;
a=1;
b=0;
cin=0;
#10;
a=0;
b=1;
cin=1;
#10;
a=1;
b=1;
cin=1;
#10;
 // Add stimulus here

end

endmodule

 Mô phỏng

2. Full adder 4 bit

  Thiết kế logic

 Mô tả phần cứng

module Adder1bit(
input wire a,b, cin, output wire s, cout
);

assign s = a^b^cin;
assign cout = (a&b) | (cin*(a^b));

endmodule

module Fullader4bit( input [3:0] A,

input [3:0] B, Cin,
output Cout,
output [3:0]S
);
wire c0,c1,c2;
Adder1bit F1 (A[0], B[0], Cin, S[0], c0);
Adder1bit F2 (A[1], B[1],c0, S[1], c1);
Adder1bit F3 (A[2], B[2],c1, S[2], c2);
Adder1bit F4 (A[3], B[3],c2, S[3], Cout);
Endmodule
 Testcase

module Banch4bit;

// Inputs
reg [3:0] A;
reg [3:0] B;
reg [3:0] Cin;

// Outputs
wire Cout;
wire [3:0] S;

// Instantiate the Unit Under Test (UUT)

Fullader4bit uut (
.A(A),
.B(B),
.Cin(Cin),
.Cout(Cout),
.S(S)
 );

initial begin
// Initialize Inputs
A = 1;
B = 0;
Cin = 0;

// Wait 100 ns for global reset to finish

#100;
A = 1;
B= 1;
Cin = 0;
#100;
A=0;
B=1;
Cin=0;
#100;

// Add stimulus here

end

endmodule
 3. Dercor 2 sang 4
 Thiết kế logic
 Mô tả phần cứng
module mux_2_4 (
input [1:0] A,
output reg [3:0] S
);

always @(*) begin

case (A)
2'b00: S = 4'b0001;
2'b01: S = 4'b0010;
2'b10: S = 4'b0100;
2'b11: S = 4'b1000;
default: S = 4'bxxxx;
endcase
end

endmodule
 Testcase
- Test banch
module Banch4bit;

// Inputs
reg [3:0] A;
 reg [3:0] B;
reg [3:0] Cin;

// Outputs
wire Cout;
wire [3:0] S;

// Instantiate the Unit Under Test (UUT)

Fullader4bit uut (
.A(A),
.B(B),
.Cin(Cin),
.Cout(Cout),
.S(S)
);

initial begin
// Initialize Inputs
A = 1;
B = 0;
Cin = 0;

// Wait 100 ns for global reset to finish

#100;
A = 1;
B= 1;
Cin = 0;
#100;
A=0;
B=1;
Cin=0;
#100;

// Add stimulus here

end

endmodule
 Mô phỏng
 4. Mạch thiết kế giải mã 3 đường sang 8 đường, có Enable tác động mức
cao.
 Thiết kế logic

 Mô tả phần cứng
module Der3_8(
input wire [2:0] A,
input wire din,
output reg [7:0] S
);

always @(A or din ) begin

 if(din)
case (A)
3'b000: S = 8'b0000_0001;
3'b001: S = 8'b0000_0010;
3'b010: S = 8'b0000_0100;
3'b011: S = 8'b0000_1000;
3'b100: S = 8'b0001_0000;
3'b101: S = 8'b0010_0000;
3'b110: S = 8'b0100_0000;
3'b111: S = 8'b1000_0000;
default: S = 8'b0000_0000;
endcase

else
S = 8'b0000000;

end

endmodule
 Test bench
module banc3_8;

// Inputs
reg [2:0] A;
reg din;

// Outputs
wire [7:0] S;

// Instantiate the Unit Under Test (UUT)

Der3_8 uut (
.A(A),
.din(din),
.S(S)
);

initial begin
// Initialize Inputs
A = 111;
din = 0;
 // Wait 100 ns for global reset to finish
#10;
A = 000;
din = 1;
#10;
A = 001;
din = 1;
#10;
A = 010;
din = 0;
#10;
A = 011;
din = 1;
#10;
A = 100;
din = 1;
#10;
A = 101;
din = 1;
#10;
A = 110;
din = 1;
#10;
A = 111;
din = 1;
#10;

// Add stimulus here

end

endmodule

 Mô phỏng
 5. Mạch mã hóa 4 sang 1.
 Thiết kế logic

 Mô phỏng phần cứng

module Encor4_1(
input [3:0] I,
input [1:0] S,
output reg Y );
always @(I,S)
case (S)
0: Y= I[0];
1: Y= I[1];
2: Y= I[2];
3: Y= I[3];
default : Y = 1'b0;
endcase
endmodule
 Test bench
module banch4_1;

// Inputs
reg [3:0] I;
reg [1:0] S;

// Outputs
wire Y;

// Instantiate the Unit Under Test (UUT)

Encor4_1 uut (
.I(I),
.S(S),
.Y(Y)
);

initial begin
// Initialize Inputs
I = 0;
S = 0;

// Wait 100 ns for global reset to finish

#10;
I=1;
S=0;
#10;
I=2;
S=1;
#10;
I=3;
S=0;
#10;

// Add stimulus here

end

endmodule
 Mô phỏng

6. Mạch mã hóa 10 sang 1.

 Thiết kế logic
 Mô tả phần cứng
module Mux10_1( input [9:0] D,
input [3:0] S,
output reg Y
);
always @(*) begin
case(S)
4'b0000: Y= D[0];
4'b0001: Y= D[1];
4'b0010: Y= D[2];
4'b0011: Y= D[3];
4'b0100: Y= D[4];
4'b0101: Y= D[5];
4'b0110: Y= D[6];
 4'b0111: Y= D[7];
4'b1000: Y= D[8];
4'b1001: Y= D[9];
default Y = 0;
endcase
end

endmodule
 Test bench
module Branch10_1;

// Inputs
reg [9:0] D;
reg [3:0] S;

// Outputs
wire Y;

// Instantiate the Unit Under Test (UUT)

Mux10_1 uut (
.D(D),
.S(S),
.Y(Y)
);

initial begin
// Initialize Inputs
S = 4'b0000;
D = 10'b0000000001;

#100;

//2
D = 10'b0000000010;
S = 4'b0001;

#100;

//3
D = 10'b0000000100;
S = 4'b1100;

#100;

//4
D = 10'b0000001000;
S = 4'b0011;

#100;

//5
D = 10'b0000010000;
S = 4'b0100;

#100;

//6
D = 10'b0000100000;
S = 4'b0101;

#100;

//7
D = 10'b0001000000;
S = 4'b0110;

#100;

//8
D = 10'b0010000000;
S = 4'b0111;

#100;

//9
D = 10'b0100000000;
S = 4'b1000;

#100;
 //10
D = 10'b1000000000;
S = 4'b1001;

#100;

// Add stimulus here

end

endmodule

 Mô phỏng

7. Mạch giải mã 1 sang 8.

 Thiết kế logic
 Mô phỏng phần cứng

module Demux1_8(
input D,
input [3:0] S,
output reg[7:0] Y
);
always @(D,S) begin
case (S)
3'b000: Y[0]=D;
3'b001: Y[1]=D;
3'b010: Y[2]=D;
3'b011: Y[3]=D;
3'b100: Y[4]=D;
3'b101: Y[5]=D;
 3'b110: Y[6]=D;
3'b111: Y[7]=D;
default : Y = 3'b000;
endcase
end
endmodule

 Test bench
module Branch1_8;

// Inputs
reg D;
reg [3:0] S;

// Outputs
wire [7:0] Y;

// Instantiate the Unit Under Test (UUT)

Demux1_8 uut (
.D(D),
.S(S),
.Y(Y)
);

initial begin
// Initialize Inputs
D = 1;
S = 3'b000;
#50;
D = 1;
S = 3'b001;
#50;

D = 1;
S = 3'b010;
#50;

D = 0;
S = 3'b011;
#50;
 D = 1;
S = 3'b100;
#50;
D = 1;
S = 3'b101;
#50;
D = 1;
S = 3'b110;
#50;
D = 1;
S = 3'b111;
#50;

// Add stimulus here

end

endmodule

 Mô phỏng

8. Mạch mã hóa 8 sang 3

 Thiết kế logic
 Mô phỏng phần cứng
module E8_3(
input wire E,
input [7:0] I,
output reg [2:0] Y
);
always @(I or E)
if(E)
case(I)
8'b00000001 : Y = 3'b000;
8'b00000010 : Y = 3'b001;
8'b00000100 : Y = 3'b010;
8'b00001000 : Y = 3'b011;
8'b00010000 : Y = 3'b100;
8'b00100000 : Y = 3'b101;
8'b01000000 : Y = 3'b110;
8'b10000000 : Y = 3'b111;
default : Y = 3'b000;
endcase
else
Y = 0;

endmodule
 Test bench
module test;
 // Inputs
reg E;
reg [7:0] I;

// Outputs
wire [2:0] Y;

// Instantiate the Unit Under Test (UUT)

E8_3 uut (
.E(E),
.I(I),
.Y(Y)
);

initial begin
// Initialize Inputs
E = 0;
I = 0;

// Wait 100 ns for global reset to finish

#100;
I = 0;
E = 0;
#200;
E=1;
#100;
I = 8'b00000001;

// Wait 100 ns for global reset to finish

#100;
I = 8'b00000010;
#100;
I = 8'b00000100;
#100;

// Add stimulus here

end

endmodule
 Mô phỏng

9. Mạch giải mã led 7 đoạn.

 Thiết kế logic

 Mô tả phần cứng
module led7doan( input wire [3:0]S,E,
output reg [6:0]Y
);
 always @(*) begin
if(E)
case(S)
4'd0 : Y = 7'b0111111;
4'd1 : Y = 7'b0000110;
4'd2 : Y = 7'b1011011;
4'd3 : Y = 7'b1001111;
4'd4 : Y = 7'b1100110;
4'd5 : Y = 7'b1101101;
4'd6 : Y = 7'b1111101;
4'd7 : Y = 7'b0000111;
4'd8 : Y = 7'b1111111;
4'd9 : Y = 7'b1101111;
default : Y = 4'b0000;
endcase
else
Y = 0;
end
endmodule
 Test bench
module test;

// Inputs
reg [3:0] S;
reg [3:0] E;

// Outputs
wire [6:0] Y;

// Instantiate the Unit Under Test (UUT)

led7doan uut (
.S(S),
.E(E),
.Y(Y)
);

initial begin
// Initialize Inputs
S = 0;
E = 0;
 // Wait 100 ns for global reset to finish
#100;
E=1;

// Add stimulus here

end
always
begin
S=S+1;
#10;
end

endmodule

 Mô phỏng

10. Mạch chia xung

 Thiết kế logic
 Mô tả phần cứng

module Counter
#(parameter M = 50000000)
( input clki,
output wire q
);
reg [30:0] r_reg;
wire [30:0] r_next;
initial r_reg = 0;
always @(posedge clki)

r_reg<=r_next;

assign r_next = (r_reg== M) ? 0 : r_reg+1;

assign q = (r_reg< M/2) ? 0 : 1;

endmodule

module ClocDivision( input d,

input clk,
output clk0
);
wire [1:0]q;
 Counter #(50000000) cd0 (clk,q[0]);
Counter #(25000000) cd1 (clk,q[1]);

assign clk0 = (d)? q[0]: q[1];

endmodule

 Test bench

module text;

// Inputs
reg d;
reg clk;

// Outputs
wire clk0;

// Instantiate the Unit Under Test (UUT)

ClocDivision uut (
.d(d),
.clk(clk),
.clk0(clk0)
);

initial begin
// Initialize Inputs
d = 0;
clk = 0;

// Wait 100 ns for global reset to finish

#1000000000;
d=1;
#1000000000;
d = 0;
end
 always
begin
#10;
clk = ~clk;

end

// Add stimulus here

endmodule

 Mô phỏng

11. Mạch đếm lên 4bits với tần số 1khz

 Thiết kế logic
 Mô tả phần cứng

module counter
#(parameter M=500000000)
( input clki, rs,
output wire [3:0] q);
wire [3:0] r_next;
reg [3:0] r_reg ;
always @(posedge clki,posedge rs)
if (rs)
r_reg <=0;
else
r_reg <= r_next;
assign r_next = r_reg+1;
assign q = r_reg;
endmodule

module clockDiv
#(parameter N= 30, M = 50000000) // for 50Mhz
( input wire clk,
output wire f
);
 // signal declaration
reg [N-1:0] r_reg;
wire [N-1:0] r_next;
// body, register
always @(posedge clk)
r_reg<=r_next;
// next state logic
assign r_next = (r_reg>=M)?0:r_reg + 1;
// output logic
//assign f=(r_reg>M/2)?1:0;
assign f=r_reg[25] ;

endmodule

module U4bit(
input wire clk,rs,
output wire [3:0] q
);
wire clk_o ;
// module instance
clockDiv t1 (clk,clk_o) ;
counter t2 (clk_o,rs, q);

endmodule

 Test bench

module test;

// Inputs
reg clki;
reg rs;

// Outputs
wire [3:0] q;
 // Instantiate the Unit Under Test (UUT)
counter uut (
.clki(clki),
.rs(rs),
.q(q)
);

initial begin
// Initialize Inputs
clki = 0;
rs = 0;

// Wait 100 ns for global reset to finish

#100;

rs =1;
#100;
rs = 0;
#100;
rs = 1;
#100;

// Add stimulus here

end
always begin
#10;
clki = ~clki;
end

endmodule

 Mô phỏng
 12. Mạch đếm xuống 4bits với tần số 1khz
 Thiết kế logic

 Mô tả phần cứng

module clockDiv
#(parameter N= 30, M = 50000) // for 50Mhz
( input wire clki,
 output wire clko
);
// signal declaration
reg [N-1:0] r_reg;
wire [N-1:0] r_next;
// body, register
initial r_reg =0;
always @(posedge clki)
r_reg <=r_next;
assign r_next =(r_reg==M)?0:r_reg+1;
assign clko = (r_reg<=M/2)?0:1 ;
endmodule

module counter
#(parameter M=50000)
( input clki, rs,
output wire [3:0] q);
wire [3:0] r_next;
reg [3:0] r_reg ;
always @(posedge clki,posedge rs)
if (rs)
r_reg <=0;
else
r_reg <= r_next;
assign r_next = r_reg-1;
assign q = r_reg;
endmodule

module Dow4bit(
input wire clk,
input wire rs,
output wire [3:0]clko
);
wire [3:0]q;
clockDiv t1 (clk,q);
counter t2 (q,rs,clko);
 endmodule

 Test bench

module test;

// Inputs
reg clki;
reg rs;

// Outputs
wire [3:0] q;

// Instantiate the Unit Under Test (UUT)

counter uut (
.clki(clki),
.rs(rs),
.q(q)
);

initial begin
// Initialize Inputs
clki = 0;
rs = 0;

// Wait 100 ns for global reset to finish

#100;

rs =1;
#100;
rs = 0;
#100;
rs = 1;
#100;
 // Add stimulus here

end
always begin
#10;
clki = ~clki;
end

endmodule

 Mô phỏng

13. Mạch sáng dần – tắt dần

 Thiết kế logic
 Mô tả phần cứng
module clockDiv
#(parameter N= 30, M = 50000) // for 50Mhz
( input wire clki,
output wire clko
);
// signal declaration
reg [N-1:0] r_reg;
wire [N-1:0] r_next;
 // body, register
initial r_reg =0;
always @(posedge clki)
r_reg <=r_next;
assign r_next =(r_reg==M)?0:r_reg+1;
assign clko = (r_reg<=M/2)?0:1 ;
endmodule
endmodule

module counter(
input wire clk,rs,din,
output wire [7:0] clko
);
// signal declaration
reg [7:0] r_reg;
wire [7:0] r_next;
// body, register
always @(posedge clk, posedge rs)
if (rs)
r_reg<=0;
else
r_reg<=r_next;
// next state logic
assign r_next = {din,r_reg[7:1]};
// output logic
assign clko= r_reg;
 endmodule

module ST_TD(
input wire clk, rs,
output wire [7:0] q );
wire clk_o ;
wire s_in;
// module instance
clockDiv t1 (clk,clk_o) ;
counter t2 (clk_o,rs,s_in, q);
assign s_in = ~q[0] ;

endmodule

 Test bench
module branch;

// Inputs
reg clk;
reg rs;

// Outputs
wire [7:0] q;

// Instantiate the Unit Under Test (UUT)

ST_TD uut (
.clk(clk),
 .rs(rs),
.q(q)
);

initial begin
// Initialize Inputs
clk = 0;
rs = 0;

// Wait 100 ns for global reset to finish

#100;
rs=1;

#10;
rs=0;

// Add stimulus here

end
always
begin
#10;
clk=~clk;
end

endmodule
 Mô phỏng

14. Mạch sáng dần – tắt hết

 Thiết kế logic
 Mô tả phần cứng
module clockDiv
#(parameter N= 30, M = 50000) // for 50Mhz
( input wire clk,
output wire clko
);
// signal declaration
reg [N-1:0] r_reg;
wire [N-1:0] r_next;
// body, register
initial r_reg = 0;
always @(posedge clk)
 r_reg<=r_next;
// next state logic
assign r_next = (r_reg==M)?0:r_reg + 1;
// output logic
//assign f=(r_reg>M/2)?1:0;
assign clko = (r_reg<=M/2) ?0:1;

endmodule

module counter(
input wire clk,rs,din,
output wire [7:0] clko
);
// signal declaration
reg [7:0] r_reg;
wire [7:0] r_next;
wire lk;
or(lk,rs,din);
// body, register
always @(posedge clk, posedge lk)
if (lk)
r_reg<=0;
else begin
r_reg<=r_next;
if(r_reg[7]==1) begin
r_reg <=0;
end
end

// next state logic

assign r_next = {r_reg[6:0],~din};
// output logic
assign clko= r_reg;

endmodule
 module ST_TH(
input wire clk, rs,
output wire [7:0] q );
wire clk_o ;
wire din;
// module instance
clockDiv t1 (clk,clk_o) ;
counter t2 (clk_o,rs,din,q);
assign din = q[7];
endmodule

 Test bench
module branch;

// Inputs
reg clk;
reg rs;

// Outputs
wire [7:0] q;

// Instantiate the Unit Under Test (UUT)

ST_TH uut (
.clk(clk),
.rs(rs),
.q(q)
);

initial begin
// Initialize Inputs
clk = 0;
rs = 0;

// Wait 100 ns for global reset to finish

#100;
 rs = 1;
#100;
rs = 0;
// Add stimulus here

end
always begin
#10;
clk = ~clk;
end

endmodule

 Mô phỏng

15. Mạch dịch 8 bit

 Thiết kế logic
 Mô tả phần cứng
module clockDiv
#(parameter N= 30, M = 50000) // for 50Mhz
( input wire clki,
output wire clko
);
// signal declaration
reg [N-1:0] r_reg;
wire [N-1:0] r_next;
// body, register
initial r_reg =0;
always @(posedge clki)
r_reg <=r_next;
assign r_next =(r_reg==M)?0:r_reg+1;
assign clko = (r_reg<=M/2)?0:1 ;
endmodule

endmodule
 module counter(
input wire clk,rs,din,
output wire [7:0] clko
);
// signal declaration
reg [7:0] r_reg;
wire [7:0] r_next;
// body, register
always @(posedge clk, posedge rs)
if (rs)
r_reg<=0;
else
r_reg<=r_next;
// next state logic
assign r_next = {din,r_reg[7:1]};
// output logic
assign clko= r_reg;

endmodule

module Dich8bit(
input wire clk,rs,
input wire din,
output wire [7:0] clko
);
wire q ;
// module instance
clockDiv t1 (clk, q) ;
counter t2 (q,rs,din,clko);
endmodule

 Test bench
module test;

// Inputs
reg clk;
reg rs;
reg din;

// Outputs
 wire [7:0] clko;

// Instantiate the Unit Under Test (UUT)

counter uut (
.clk(clk),
.rs(rs),
.din(din),
.clko(clko)
);

initial begin
// Initialize Inputs
clk = 0;
rs = 0;
din = 0;

// Wait 100 ns for global reset to finish

#100;
din = 1;
#100;
din = 0;
#100;

// Add stimulus here

end
always begin
#10;
clk = ~clk;
end

endmodule
 Mô phỏng
 16. Thiết kế mạch sáng dần tắt dần tự động
 Thiết kế logic
 Mô tả phần cứng
module FFT(
input clk,rs,T,
output reg q
);
always @ (posedge clk,posedge rs)
if(rs)
q=0;
else
if(T)
q=~q;

endmodule
module counter
#(parameter M=50000)
( input clki, rs,ud,
output wire [3:0] q);
wire [3:0] r_next;
reg [3:0] r_reg ;
always @(posedge clki,posedge rs)
if (rs)
r_reg <=0;
else
r_reg <= r_next;
assign r_next = (ud==0)?r_reg+1:r_reg-1;
assign q = r_reg;
endmodule

module clockDiv
#(parameter N= 30, M = 50000) // for 50Mhz
( input wire clki,
output wire clko
);
// signal declaration
reg [N-1:0] r_reg;
wire [N-1:0] r_next;
// body, register
initial r_reg =0;
always @(posedge clki)
r_reg <=r_next;
assign r_next =(r_reg==M)?0:r_reg+1;
assign clko = (r_reg<=M/2)?0:1 ;
endmodule

module SDtudong(
input clk,rs,
output [3:0]q
);
wire h; //14->15
wire l; // 1->0
wire clkff,ud;
wire clko;
clockDiv t1(clk,clko);
counter t2 (clko,rs,ud,q);
 FFT t3 (clkff,rs,1'b0,ud);

and(h,q[0],q[1],q[2],q[3]);
nor (l,q[0],q[1],q[2],q[3]);
or(clkff,l,m);
endmodule

 Test bench
module test;

// Inputs
reg clk;
reg rs;

// Outputs
wire [3:0] q;

// Instantiate the Unit Under Test (UUT)

SDtudong uut (
.clk(clk),
.rs(rs),
.q(q)
);

initial begin
// Initialize Inputs
clk = 0;
rs = 0;

// Wait 100 ns for global reset to finish

#100;

rs=1;
#100;

rs=0;

// Add stimulus here

 end
always begin
#10;
clk = ~clk;
end

endmodule

 Mô phỏng

17. Đếm 0-59 hiển thị trên led 7 đoạn

 Thiết kế logic

 Mô tả phần cứng
module counterchuc
#(parameter M=50000)
( input clki, rs,
output wire [3:0] q);
wire [3:0] r_next;
reg [3:0] r_reg ;
always @(posedge clki,posedge rs)
if (rs)
r_reg <=0;
else
r_reg <= r_next;
assign r_next = r_reg+1;
assign q = r_reg;
endmodule

module counterdv
#(parameter M=50000)
( input clki, rs,
output wire [3:0] q);
wire [3:0] r_next;
reg [3:0] r_reg ;
always @(posedge clki,posedge rs)
if (rs)
r_reg <=0;
else
r_reg <= r_next;
assign r_next = r_reg+1;
assign q = r_reg;
endmodule

module led7doandv( input wire [3:0]S,

output reg [6:0]Y
);
always @(*) begin
case(S)
4'd0 : Y = 7'b0111111;
4'd1 : Y = 7'b0000110;
4'd2 : Y = 7'b1011011;
4'd3 : Y = 7'b1001111;
4'd4 : Y = 7'b1100110;
4'd5 : Y = 7'b1101101;
4'd6 : Y = 7'b1111101;
4'd7 : Y = 7'b0000111;
4'd8 : Y = 7'b1111111;
4'd9 : Y = 7'b1101111;
default : Y = 4'b0000;
endcase

end
endmodule

module led7doanchuc(
input wire [3:0]S,
output reg [6:0]Y
);
always @(*) begin
 case(S)
4'd0 : Y = 7'b0111111;
4'd1 : Y = 7'b0000110;
4'd2 : Y = 7'b1011011;
4'd3 : Y = 7'b1001111;
4'd4 : Y = 7'b1100110;
4'd5 : Y = 7'b1101101;
4'd6 : Y = 7'b1111101;
4'd7 : Y = 7'b0000111;
4'd8 : Y = 7'b1111111;
4'd9 : Y = 7'b1101111;
default : Y = 4'b0000;
endcase
end
endmodule

 Test bench
module test;

// Inputs
reg ck;
reg rs;

// Outputs
wire [6:0] a;
wire [6:0] b;

// Instantiate the Unit Under Test (UUT)

dem0_59 uut (
.ck(ck),
.rs(rs),
.a(a),
.b(b)
);

initial begin
// Initialize Inputs
 ck = 0;
rs = 0;

// Wait 100 ns for global reset to finish

#10;
rs=1;
#10;
rs=0;

// Add stimulus here

end
always begin
#10;
ck = ~ck;
end

endmodule

 Mô phỏng
 18. Hiển thị đồng hồ số (giờ-phút-giây)
 Thiết kế logic
 Mô tả phần cứng

module clockDiv
#(parameter M=50000)
(
input clki,
output clko);
wire [30:0] r_next;
reg [30:0] r_reg ;
initial r_reg =0;
always @(posedge clki)
r_reg <=r_next;
assign r_next =(r_reg==M)?0:r_reg+1;
assign clko = (r_reg<=M/2)?0:1 ;
endmodule

module Counter(
input wire clk,rs,
output wire [7:0] q
);
wire [7:0] r_next ;
reg [7:0] r_reg;
initial r_reg =0 ;
always @(posedge clk,posedge rs)
if(rs)
r_reg<=0;
else
r_reg <= r_next;
assign r_next =(r_reg==8'b00111011)?0 :r_reg + 1 ;
assign q=r_reg;
endmodule

module add(in,out);
input [3:0] in;
output [3:0] out;
reg [3:0] out;
always @ (in)
case (in)
4'b0000: out <= 4'b0000;
4'b0001: out <= 4'b0001;
4'b0010: out <= 4'b0010;
4'b0011: out <= 4'b0011;
4'b0100: out <= 4'b0100;
4'b0101: out <= 4'b1000;
4'b0110: out <= 4'b1001;
4'b0111: out <= 4'b1010;
4'b1000: out <= 4'b1011;
4'b1001: out <= 4'b1100;
default: out <= 4'b0000;
endcase
endmodule
module HexBcd(
input [7:0] hex,
output wire [3:0] ones,
output wire [3:0] tens
);
wire [3:0] c1,c2,c3,c4,c5,c6,c7;
wire [3:0] d1,d2,d3,d4,d5,d6,d7;
assign d1 = {1'b0,hex[7:5]};
assign d2 = {c1[2:0],hex[4]};
assign d3 = {c2[2:0],hex[3]};
assign d4 = {c3[2:0],hex[2]};
assign d5 = {c4[2:0],hex[1]};
assign d6 = {1'b0,c1[3],c2[3],c3[3]};
assign d7 = {c6[2:0],c4[3]};
add t1(d1,c1);
add1 t2(d2,c2);
add1 t3(d3,c3);
add1 t4(d4,c4);
add1 t5(d5,c5);
add1 t6(d6,c6);
add1 t7(d7,c7);
assign ones = {c5[2:0],hex[0]};
assign tens = {c7[2:0],c5[3]};
assign hundreds = {c6[3],c7[3]};
endmodule

module chinh(input clk,rs,

output [3:0] ones1,tens1,
output [3:0] ones2,tens2,
output [3:0] ones3,tens3

);
wire cko;
wire [7:0] q1,q2,q3;
wire xung1,xung2,xung3,rst;
 clockDiv clock (clk, clko) ;
Counter counter1 (clko,rst,q1 ) ;
Counter counter2 (xung1,rst,q2 ) ;
Counter counter3 (xung2,rst,q3 ) ;
nor (xung1,q1[0],q1[1],q1[2],q1[3],q1[4],q1[5],q1[6],q1[7]);//0
nor (xung2,q2[0],q2[1],q2[2],q2[3],q2[4],q2[5],q2[6],q2[7]);//0
and(xung3,q3[4],q3[3]);
or(rst,rs,xung3);

HexBcd hex_bcd1 (q1,ones1,tens1);

HexBcd hex_bcd2 (q2,ones2,tens2);
HexBcd hex_bcd3 (q3,ones3,tens3);

endmodule

 Test bench
module thu1;

// Inputs
reg clk;
reg rs;

// Outputs
wire [3:0] ones1;
wire [3:0] tens1;
wire [3:0] ones2;
wire [3:0] tens2;
wire [3:0] ones3;
wire [3:0] tens3;

// Instantiate the Unit Under Test (UUT)

chinh uut (
.clk(clk),
.rs(rs),
 .ones1(ones1),
.tens1(tens1),
.ones2(ones2),
.tens2(tens2),
.ones3(ones3),
.tens3(tens3)
);

initial begin
// Initialize Inputs
clk = 0;
rs = 0;

// Wait 100 ns for global reset to finish

#10;
rs=1;
#10;
rs=0;

// Add stimulus here

end

always begin
#10;
clk=~clk;
end

endmodule
 Mô phỏng
 19. Hiển thị MSSV qua led 7 đoạn của kít rời TM1638
 Thiết kế logic
 Mô tả phần cứng
module ClkDiv(
input wire clki,
output reg clko
);
wire [26:0] r_next ;
reg [26:0] r_reg;
initial begin r_reg =0 ;end
always @(posedge clki) begin
r_reg = r_next;
if (r_reg==12500000) clko = ~clko;
end
assign r_next =(r_reg==25000000)?0: r_reg + 1 ;
//assign clko = r_reg[24];// =(r_reg<=50000000/2)?0:1; /*781.250 Khz*/

endmodule

module dich(
input wire CLK,
output wire [7:0] q_out
);
reg [7:0] r_reg;
wire [7:0] r_next;

always@(posedge CLK)
r_reg<=r_next;
assign r_next = {~r_reg[0],r_reg[7:1]};
assign q_out= r_reg;

endmodule

module TM1638(
input wire [7:0] led ,
input wire [3:0] seg7,seg6,seg5,seg4,seg3,seg2,seg1,seg0 ,
input clkinput,
output reg clk,
output reg stb,
output reg dio
);
function [7:0] sseg;
input [3:0] hex;
begin
case (hex)
4'h0: sseg[7:0] = 8'b0111111;
4'h1: sseg[7:0] = 8'b0000110;
4'h2: sseg[7:0] = 8'b1011011;
4'h3: sseg[7:0] = 8'b1001111;
4'h4: sseg[7:0] = 8'b1100110;
4'h5: sseg[7:0] = 8'b1101101;
4'h6: sseg[7:0] = 8'b1111101;
4'h7: sseg[7:0] = 8'b0000111;
4'h8: sseg[7:0] = 8'b1111111;
4'h9: sseg[7:0] = 8'b1101111;
4'hA: sseg[7:0] = 8'b1110111;
4'hB: sseg[7:0] = 8'b1111100;
4'hC: sseg[7:0] = 8'b1011000;
4'hD: sseg[7:0] = 8'b1011110;
4'hE: sseg[7:0] = 8'b1111001;
default : sseg[7:0] = 8'b0000000;
endcase
end
endfunction

integer cs = 0;
integer i ;
reg [7:0] command1 =8'h40, command2 =8'hC0,command3 =8'h8F;
wire [127:0] leddata;
reg [127:0] leddatahold;
assign leddata[0*8+7:0*8+0] = sseg(seg0);
assign leddata[2*8+7:2*8+0] = sseg(seg1);
assign leddata[4*8+7:4*8+0] = sseg(seg2);
assign leddata[6*8+7:6*8+0] = sseg(seg3);
assign leddata[8*8+7:8*8+0] = sseg(seg4);
assign leddata[10*8+7:10*8+0] = sseg(seg5);
assign leddata[12*8+7:12*8+0] = sseg(seg6);
assign leddata[14*8+7:14*8+0] = sseg(seg7);
assign leddata[1*8+7:1*8+0] = led[0] ;
assign leddata[3*8+7:3*8+0] = led[1] ;
assign leddata[5*8+7:5*8+0] = led[2] ;
assign leddata[7*8+7:7*8+0] = led[3] ;
assign leddata[9*8+7:9*8+0] = led[4] ;
assign leddata[11*8+7:11*8+0] = led[5] ;
assign leddata[13*8+7:13*8+0] = led[6] ;
assign leddata[15*8+7:15*8+0] = led[7] ;

wire clk_khz;
 ClkDiv clkdiv0 (clkinput,clk_khz);

initial
begin

clk = 1 ;
stb = 1 ;
dio = 0 ;

end
always @(posedge clkinput)
begin
if (cs==0)
begin
stb = 0;
command1 =8'h40; command2 =8'hC0;command3 =8'h8F;
leddatahold=leddata ;
end

else if ((cs >=1)&&(cs<=16))

begin
dio = command1[0];
clk = ~clk ;
if (clk) command1=command1>>1 ;
end
else if (cs==17)
stb = 1;
else if (cs==18)
stb = 0;

else if ((cs >=19)&&(cs<=34))

begin
dio = command2[0];
clk = ~clk ;
if (clk) command2=command2>>1 ;
end

else if ((cs >=35)&&(cs<=290))

begin
dio = leddatahold[0];
clk = ~clk ;
if (clk) leddatahold=leddatahold>>1 ;
end
else if (cs==291)
stb = 1;

else if (cs==292)
stb = 0;

else if ((cs >=293)&&(cs<=308))

begin
 dio = command3[0];
clk = ~clk ;
if (clk) command3=command3>>1 ;
end

else if (cs==309)
stb = 1;
else if (cs==310)
cs = -1 ;

cs=cs+1;
end
endmodule

module chinh(
input clk,
output wire clko,
output wire stb,
output wire dio
);
wire clk1, CLK_OUT;
wire [7:0]q;
ClkDiv clkdiv0 (clk, clk1);

wire [4:0] seg [7:0];

dich dich (clk1,q);
TM1638 tm (q,1,6,0,9,1,1,2,2,clk1,clko,stb,dio);
endmodule
 Test bench
 Mô phỏng