LAB-1

----------

Verilog code for Full adder using dataflow abstraction.

Code:
-------

module fulladder(
input a,
input b,
input c,
output sum,
output carry
);

assign sum=(a^b^c);
assign carry=(a&b|((a^b)&c));

endmodule

Testbench:
------------
module fulladd_tb;

reg a;
reg b;
reg c;

// Outputs
wire sum;
wire carry;

fulladder uut (.a(a), .b(b), .c(c), .sum(sum), .carry(carry));

reg [2:0] i;

initial begin
// Initialize Inputs
for(i=0;i<=7;i=i+1)
begin
{a,b,c}=i;
#20;
end
end

endmodule
 Waveforms:
-----------------

RTL for 2to4 Decoder using Dataflow abstraction

------------------------------------------------------------
Code :
--------
module decoderlogic(
input [1:0] in,
output [3:0] out,
input en
);
`
assign out[0]=(en & ~in[1] & ~in[0]);
assign out[1]=(en & ~in[1] & in[0]);
assign out[2]=(en & in[1] & ~in[0]);
assign out[3]=(en & in[1] & in[0]);
endmodule

Testbench:
------------
module decoder_tb;

// Inputs
reg [1:0] in;
reg en;

// Outputs
wire [3:0] out;
 decoderlogic uut (
.in(in),
.out(out),
.en(en)
);

initial begin

in = 0;
en = 0;
#100;
en=1;
#250;
$finish;

end

initial fork
forever #10 in[0]=~in[0];
forever #20 in[1]=~in[1];
join

endmodule

Waveforms:
---------------
4 bit Ripple carry adder :
-----------------------------

Code:
-------
module adder_4bit(
input [3:0] a,
input [3:0] b,
input cin,
output [4:0] sum
);
wire w1,w2,w3;
fulladder x1(a[0],b[0],cin,sum[0],w1);
fulladder x2(a[1],b[1],w1,sum[1],w2);
fulladder x3(a[2],b[2],w2,sum[2],w3);
fulladder x4(a[3],b[3],w3,sum[3],sum[4]);

endmodule

Testbench:
_________
module adder4bit_tb;

// Inputs
reg [3:0] a;
reg [3:0] b;
reg cin;

// Outputs
wire [4:0] sum;

adder_4bit uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum)
);

initial begin

a = 4'd3;
b = 4'd4;
cin = 0;

#100;
a = 4'd5;
b = 4'd6;
 cin = 1;
#100;
a = 4'd7;
b = 4'd7;
cin = 0;
#100;

end

endmodule

Waveforms:
-----------------

4:1 MUX using 2:1 MUX

---------------------------------

Code:
-------
module mux4to1(
input [3:0] in,
output out,
input [1:0] sel
);
wire w1,w2;
mux2to1 x1(in[0],in[1],sel[0],w1);
mux2to1 x2(in[2],in[3],sel[0],w2);
mux2to1 x3(w1,w2,sel[1],out);

endmodule
module mux2to1(
input a,
input b,
input sel,
output reg out
);
always@(*)
begin
if(sel)
out=b;
else
out=a;
end

endmodule

Testbench:
------------

module mux4to1_tb;

// Inputs
reg [3:0] in;
reg [1:0] sel;
// Outputs
wire out;

mux4to1 uut (
.in(in),
.out(out),
.sel(sel)
);

initial fork
forever #10 sel[0]=~sel[0];
forever #20 sel[1]=~sel[1];
join

initial begin
in=4'b0101;
sel=0;
end

initial begin
#200;
 $stop;
end

endmodule

Waveforms:

4:1 MUX using decoder and tristate buffers:

-----------------------------------------------------
module mux_decoderbuff(
input [1:0] sel,
input [3:0] in,
output wor out
);
reg [3:0] temp;
always@(*)
begin
case(sel)
2'b00:temp=4'b0001;
2'b01:temp=4'b0010;
2'b10:temp=4'b0100;
2'b11:temp=4'b1000;
endcase
end
assign out=(in[0])?temp[0]:1'bz;
assign out=(in[1])?temp[1]:1'bz;
assign out=(in[2])?temp[2]:1'bz;
assign out=(in[3])?temp[3]:1'bz;
endmodule

Testbench:
-------------

module tb_decodbufmux;

// Inputs
reg [1:0] sel;
reg [3:0] in;

// Outputs
wire out;

// Instantiate the Unit Under Test (UUT)

mux_decoderbuff uut (
.sel(sel),
.in(in),
.out(out)
);

initial begin
// Initialize Inputs
sel = 2'b00;
in = 4'b1010;

// Wait 100 ns for global reset to finish

#100;
sel = 2'b01;
in = 4'b1010;

// Add stimulus here

#100;
sel = 2'b10;
in = 4'b1010;

#100;
sel = 2'b11;
in = 4'b1010;
#100;

end

endmodule
Waveforms:
-------------

Bidirectional Buffer:

code:
_____
module bidirectbuf(
inout inf,
input c,
inout inb
);
`ifdef procedural

buf1 a(inf,c,inb);
buf0 b(inb,c,inf);
`endif
`ifdef gatelevel
bufif1 xx(inb,inf,c);
bufif0 xxx(inf,inb,c);
`endif

endmodule

module buf1(
input in,
input chigh,
output reg out
);
always@(*)
begin
 if(chigh)
out=in;
else
out=1'bz;
end

endmodule

module buf0(
input in,
input clow,
output reg out
);
always@(*)
begin
if(~clow)
out=in;
else
out=1'bz;
end

endmodule

Testbench:
-------------
`define forwardcheck
//`define backwardcheck

module tb_buf;

// Inputs
wire inf;
reg c;
// Outputs
wire inb;

bidirectbuf uut (
.inf(inf),
.c(c),
.inb(inb)
);

`ifdef backwardcheck
 reg tempb;
assign inb=tempb;

initial begin
tempb=1;
c=0;
#50;
tempb=0;
#100;
end
`endif

`ifdef forwardcheck
reg tempa;
assign inf=tempa;

initial
begin
tempa=1;
c=1;
#50;
tempa=0;
#100;
end
`endif

endmodule

Waveforms:
---------------
 LAB-2:
---------------

ALU implementation:
-------------------------
Code:

module alu(input [7:0]a,b,

input [3:0]command_in,
input oe,
output [15:0]d_out);

parameter ADD = 4'b0000, // Add two 8 bit numbers a and b.

INC = 4'b0001, // Increment a by 1.
SUB = 4'b0010, // Subtracts b from a.
DEC = 4'b0011, // Decrement a by 1.
MUL = 4'b0100, // Multiply 4 bit numbers a and b.
DIV = 4'b0101, // Divide a by b.
SHL = 4'b0110, // Shift a to left side by 1 bit.
SHR = 4'b0111, // Shift a to right by 1 bit.
AND = 4'b1000, // Logical AND operation
OR = 4'b1001, // Logical OR operation
INVV = 4'b1010, // Logical Negation
NAND = 4'b1011, // Bitwise NAND
NOR = 4'b1100, // Bitwise NOR
XOR = 4'b1101, // Bitwise XOR
XNOR = 4'b1110, // Bitwise XNOR
BUFF = 4'b1111; // BUF

reg [15:0]out;

/*Step1 : Write down the functionality of ALU based on the commands given above.
*Use arithmetic and logical operators* */
always@(command_in,a,b)
begin
case(command_in)
//--------- write the functionality here -------
ADD:out=a+b;
INC:out=a+1;
SUB:out=a-b;
DEC:out=a-1;
MUL:out=a*b;
DIV:out=a/b;
SHL:out=a<<1;
SHR:out=a>>1;
AND:out=a&b;
OR:out=a|b;
 INVV:out=~a;
NAND:out=~(a&b);
NOR:out=~(a|b);
XOR:out=a^b;
XNOR:out=~(a^b);
BUFF:out=a;
default:out=16'b0;
endcase
end

//Understand the tri-state logic for actual output

assign d_out = (oe) ? out : 16'hzzzz;

endmodule

Test bench:
--------------

module alu_tb;

// Inputs
reg [7:0] a;
reg [7:0] b;
reg [3:0] command;
reg enable;

// Outputs
wire [15:0] out;

// Instantiate the Unit Under Test (UUT)

alu uut (
.a(a),
.b(b),
.command_in(command),
.oe(enable),
.d_out(out)
);

//Variables for iteration of the loops

integer m,n,o;
integer i;

//Parameter constants used for displaying the strings during operation

parameter ADD = 4'b0000, // Add two 8 bit numbers a and b.
INC = 4'b0001, // Increment a by 1.
SUB = 4'b0010, // Subtracts b from a.
DEC = 4'b0011, // Decrement a by 1.
MUL = 4'b0100, // Multiply 4 bit numbers a and b.
DIV = 4'b0101, // Divide a by b.
SHL = 4'b0110, // Shift a to left side by 1 bit.
SHR = 4'b0111, // Shift a to right by 1 bit.
AND = 4'b1000, // Logical AND operation
OR = 4'b1001, // Logical OR operation
INVV = 4'b1010, // Logical Negation
NAND = 4'b1011, // Bitwise NAND
NOR = 4'b1100, // Bitwise NOR
XOR = 4'b1101, // Bitwise XOR
XNOR = 4'b1110, // Bitwise XNOR
BUFF = 4'b1111; // BUF

reg [4*8:0]string_cmd;

task initialize;
begin
a=16'b0;
b=16'b0;
enable=0;
command=4'b0;
end
endtask

task en_oe(input i);

begin
enable=i;
end
endtask

task inputs(input [7:0]j,k);

begin
a=j;
b=k;
end
endtask

task cmd (input [3:0]l);

begin
command=l;
end
endtask
 task delay();
begin
#10;
end
endtask

always@(command)
begin
case(command)
ADD : string_cmd = "ADD";
INC : string_cmd = "INC";
SUB : string_cmd = "SUB";
DEC : string_cmd = "DEC";
MUL : string_cmd = "MUL";
DIV : string_cmd = "DIV";
SHL : string_cmd = "SHL";
SHR : string_cmd = "SHR";
INVV : string_cmd = "INV";
AND : string_cmd = "AND";
OR : string_cmd = "OR";
NAND : string_cmd = "NAND";
NOR : string_cmd = "NOR";
XOR : string_cmd = "XOR";
XNOR : string_cmd = "XNOR";
BUFF : string_cmd = "BUF";
endcase
end

initial
begin
initialize;
en_oe(1'b1);
for(m=0;m<16;m=m+1)
begin
for(n=0;n<16;n=n+1)
begin
inputs(m,n);
for(o=0;o<16;o=o+1)
begin
command=o;
delay;
end
end
 end
en_oe(0);
inputs(8'd20,8'd10);
cmd(ADD);
delay;
en_oe(1);
inputs(8'd25,8'd17);
cmd(ADD);
delay;
$finish;
end

initial
$monitor("Input oe=%b, a=%b, b=%b, command=%s, Output out=
%b",enable,a,b,string_cmd,out);

endmodule

Waveforms:

Verilog operators working:

--------------------------------

module operatorswork;
reg [3:0] a;
reg [3:0] b;
reg [5:0] out;
reg [3:0] outputt;
 reg [3:0] x;
reg [3:0] y;
reg [3:0] z;
reg [3:0] w;
reg r1,r2,r3,r4;

initial begin
//relational operators
a=4'b0011;
b=4'b1100;
out[0]=(a>b);
out[1]=(a<=b);
$display("a(%b)>b(%b)=%b",a,b,out[0]);
$display("a(%b)<=b(%b)=%b",a,b,out[1]);
//conditonal operators
#10;
outputt=(a<b)?a:b;
$display("conditional operators %b",outputt);
#10;
//concatenantion operator and replication operator
out={1'b1,1'b1,outputt};
$display("conactenantion %b",out);
outputt={{2{1'b1}},{2{1'b0}}};
$display("replicate and concatenate %b",outputt);
end

initial begin:balaji
#100;

x=4'b001x;
y=4'b001x;
z=4'b1010;
w=4'b1010;
r1=(x==y);
r2=(x===y);
r3=(z==w);
r4=(z!=w);
$display("x(%b)==y(%b) results in r1=%b",x,y,r1);
$display("x(%b)===y(%b) results in r2=%b",x,y,r2);
$display("z(%b)==w(%b) results in r3=%b",z,w,r3);
$display("z(%b)!=w(%b) results in r4=%b",z,w,r4);

#10;
//logical operators
r4=(1'b1 && 1'b0);
r3=(1'b1 || 1'b0);
 r2=!(1'b1);
$display("(1'b1 && 1'b0) is %b",r4);
$display("(1'b1 || 1'b0) is %b",r3);
$display(" !(1'b1) is %b",r2);

end

endmodule

Output simulation console:

------------------------------------