LC05732ARA

Battery Protection IC,

Integrated Power MOSFET,
1-Cell Lithium-Ion Battery
Overview www.onsemi.com
The LC05732ARA is a protection IC for 1−cell lithium−ion
batteries with integrated power MOS FET. Also it integrates highly MARKING
accurate detection circuits and detection delay circuits to prevent DIAGRAM
batteries from over−charging, over−discharging, over−current
discharging and over−current charging.
XXXXX
In addition, main system can execute the power−on reset of itself AYYWW
by turning off the charge FET and discharge FET of LC05732ARA for ECP30, 1.97x4.01
a certain time period, with a reset signal. SUFFIX
A battery protection system can be made by only LC05732ARA and CASE 971BC
few external parts.
A = Assembly Location
Features YY = Year
WW = Work Week
• Charge−and−Discharge Power MOSFET are Integrated at TA = 25°C,
VCC = 4.0 V
♦ ON Resistance (Total of Charge and Discharge ) 4.8 mW (typ)
ORDERING INFORMATION
• Highly Accurate Detection Voltage/Current at TA = 25°C,
Device Package Shipping†
VCC = 3.7 V
♦ Over−Charge Detection ±25 mV LC05732A02RATBG ECP30 5000 / Tape &
(Pb−Free) Reel
♦ Over−Discharge Detection ±50 mV
LC05732A03RATBG ECP30 5000 / Tape &
♦ Charge Over−Current Detection ±0.7 A
(Pb−Free) Reel
♦ Discharge Over−Current Detection ±0.7 A
†For information on tape and reel specifications,
• Delay Time for Detection and Release (Fixed Internally) including part orientation and tape sizes, please
• Discharge/Charge Over−Current Detection is Compensated for refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Temperature Dependency of Power FET
• 0 V Battery Charging: “Inhibit”
• Auto Wake−up Function Battery Charging: “Inhibit”
• Forcible Charge−FET and Discharge−FET OFF Mode
RSTB>VDD*0.9: Charge−FET and Discharge−FET = ON
RSTB<VDD*0.1: Charge−FET and Discharge−FET = OFF
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant

Typical Applications
• Smart Phone
• Tablet
• Wearable Device

© Semiconductor Components Industries, LLC, 2017 1 Publication Order Number:

March, 2018 − Rev. 3 LC05732ARA/D
 LC05732ARA

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS at TA = 25°C (Notes 1, 2, 3, 5)

Parameter Symbol Conditions Ratings Unit
Supply voltage VCC Between PAC+ and VCC : R1 = 680 W −0.3 to 12.0 V
S1 − S2 voltage VS1−S2 20.0 V
CS terminal Input voltage CS VCC−20.0 to VCC+0.3 V
RSTB input voltage RSTB −0.3 to 7 V
Storage temperature Tstg −55 to +125 °C
Operating ambient Topr −40 to +100 °C
temperature

Allowable power dissipation Pd (Note 4) 800 mW

Junction temperature TJ 125 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Absolute maximum ratings represent the values which cannot be exceeded at any given time
2. If you intend to use this IC continuously under high temperature, high current, high voltage, or drastic temperature change, even if it is used
within the range of absolute maximum ratings or operating conditions, there is a possibility of decrease reliability. Please contact us for
confirmation
3. This device is made for power applications.
4. JESD 51−3 (1S)
5. Please execute appropriate test and take safety measures on your board.

PAC+

R1 VCC
VCC
RSTB R3 RSTB
Controller IC
C1
Battery

S1 S2 CS
R2

PAC-
Figure 1. Example of Application Circuit

Components Min Recommended Value Max Unit Description

R1 330 680 1k W
R2 680 1k 2k W
R3 680 1k 2k W
C1 0.1m 1.0m 2.2m F
*We don’t guarantee the characteristics of the circuit shown above.

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 LC05732ARA

ELECTRICAL CHARACTERISTICS (Notes 6, 7, 8, 9)

Parameter Symbol Conditions Min Typ Max Unit
DETECTION VOLTAGE
Over−charge Vov R1 = 680 W TA = 25°C Vov_set −25 Vov_set Vov_set +25 mV
detection voltage
TA = −30 to 70°C Vov_set −30 Vov_set Vov_set +30
Over−charge Vovr R1 = 680 W TA = 25°C Vovr_set −40 Vovr_set Vovr_set +40 mV
release voltage
TA = −30 to 70°C Vovr_set −70 Vovr_set Vovr_set +70
Over−discharge Vuv R1 = 680 W TA = 25°C Vuv_set −50 Vuv_set Vuv_set +50 mV
detection voltage
TA = −30 to 70°C Vuv_set −80 Vuv_set Vuv_set +80
Over−discharge Vuvr R1=680 W TA = 25°C Vuvr_set −100 Vuvr_set Vuvr_set +100 mV
release voltage CS =0V TA = −30 to 70°C Vuvr_set −120 Vuvr_set Vuvr_set +120
Discharge Ioc R2 = 1 kW TA = 25°C Ioc_set −0.7 Ioc_set Ioc_set +0.7 A
over−current VCC = 3.7 V
detection current
TA = −30 to 70°C Ioc_set −1.2 Ioc_set Ioc_set +1.2
VCC = 3.7 V
Discharge Ioc2 R2 = 1 kW TA = 25°C Ioc2_set*0.8 Ioc2_set Ioc2_set*1.2 A
over−current VCC = 3.7 V
detection current2
(Short circuit) TA = −30 to 70°C Ioc2_set*0.6 Ioc2_set Ioc2_set*1.8
VCC = 3.7 V
Charge Ioch R2 = 1 kW TA = 25°C Ioch_set −0.7 Ioch_set Ioch_set +0.7 A
over−current VCC = 3.7 V
detection current
TA = −30 to 90°C Ioch_set −1.2 Ioch_set Ioch_set +1.2
VCC = 3.7 V

RESET TERMINAL
High−Level Input VIH TA = −30 to 90°C 0.9*VCC V
Voltage
Low−Level Input VIL TA = −30 to 90°C 0.1*VCC V
Voltage
High−Level Input IIH VCC = RSTB TA = −30 to 90°C 1 mA
Leakage Current
Low−Level Input IIL VCC = 3.7 V TA = −30 to 90°C 20 34 48 mA
Leakage Current RSTB = 0 V
Reset pulse width Tw_res VCC = 2.2 to TA = −30 to 90°C 10 20 30 ms
4.3 V

INPUT VOLTAGE
0 V battery Vinh TA = 25°C 0.4 0.9 1.4 V
charging inhibition
battery voltage
CURRENT CONSUMPTION
Operating current ICC At normal TA = 25°C 3 6 mA
state VCC = 3.7 V

Shut down current Ishut At shut down TA = 25°C 0.1 mA

state VCC = 2.0 V

RESISTANCE
ON resistance 1 of Ron1 VCC = 3.1 V TA = 25°C 4.4 5.4 6.9 mW
integrated power
MOSFET I = ±2.0 A

ON resistance 2 of Ron2 VCC = 3.8 V TA = 25°C 4 4.9 5.8 mW

integrated power
MOS FET I = ±2.0 A

ON resistance 3 of Ron3 VCC = 4.0 V TA = 25°C 3.9 4.8 5.7 mW

integrated power
MOSFET I = ±2.0 A

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 LC05732ARA

ELECTRICAL CHARACTERISTICS (Notes 6, 7, 8, 9)

Parameter Symbol Conditions Min Typ Max Unit
RESISTANCE
ON resistance 4 of Ron4 VCC = 4.5V TA = 25°C 3.8 4.7 5.6 mW
integrated power
MOSFET I = ±2.0 A

Internal resistance Rcsu VCC = TA = 25°C 300 kW

(VCC−CS) Vuv_set
CS = 0 V
Internal resistance Rcsd VCC = 3.7 V TA = 25°C 10 kW
(VSS−CS) CS = 0.1 V
Forward Source to Vf(s−s) VCC = 2.0 V TA = 25°C 0.67 1.06 V
Source Voltage Is = 0.25 A

DETECTION AND RELEASE DELAY TIME

Over−charge Tov TA = 25°C 0.8 1 1.2 s
detection delay
time TA = −30 to 70°C 0.6 1 1.5

Over−charge Tovr TA = 25°C 12.8 16 19.2 ms

release delay time
TA = −30 to 70°C 9.6 16 24
Over−discharge Tuv TA = 25°C 14 20 26 ms
detection delay
time TA = −30 to 70°C 12 20 30

Over−discharge Tuvr TA = 25°C 0.9 1.1 1.3 ms

release delay time
TA = −30 to 70°C 0.6 1.1 1.5
Discharge Toc1 VCC = 3.7 V TA = 25°C 9.6 12 14.4 ms
over−current
detection delay TA = −30 to 70°C 7.2 12 18
time 1
Discharge Tocr1 VCC = 3.7 V TA = 25°C 3.2 4 4.8 ms
over−current
release delay time TA = −30 to 70°C 2.4 4 6
1
Discharge Toc2 VCC = 3.7 V TA = 25°C 230 300 420 ms
over−current
detection delay
time 2 (Short TA = −30 to 70°C 200 300 450
circuit)
Charge Toch VCC = 3.7 V TA = 25°C 12.8 16 19.2 ms
Over−current
detection delay TA = −30 to 90°C 9.6 16 24
time
Charge Tochr VCC = 3.7 V TA = 25°C 3.2 4 4.8 ms
Over−current
release delay time TA = −30 to 90°C 2.4 4 6
Reset release time Tres VCC = 3.7 V TA = 25°C 0.8 1 1.2 s
TA = −30 to 70°C 0.6 1 1.5
6. This device is made for power applications.
7. Please execute appropriate test and take safety measures on your board.
8. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. The specification in this parameter and all specification at high and low temperature are guaranteed by design.

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 LC05732ARA

SELECTION GUIDE
Device Vov (V) Vovr (V) Vuv (V) Vuvr (V) Ioc (A) Ioch (A) Ioc2 (A) Tuv (ms) Reset Function
LC05732A02RATBG 4.475 4.475 2.1 2.1 7.0 9.0 25.0 20 Enable
LC05732A03RATBG 4.500 4.300 2.3 2.3 9.0 6.0 15.0 20 Disable

1 2 3 4 5 6 7 8

A
S1 S1 S1 S1 S1 S1 S1 VCC

B S1 S1 S1 S1 S1 S1 NC

C S2 S2 S2 S2 S2 S2 NC

S2 S2 S2 S2 S2 S2 RSTB CS
D

TOP VIEW
Figure 2. Pin Functions

Pin No. Symbol Pin Function Description

A1−7 S1 Source 1 Negative power input
B1−6

A8 VCC VCC terminal

C1−6 S2 Source 2
D1−6

D7 RSTB Charge and discharge off control terminal Connected to VCC with 100 kW
(“L” = Reset )

D8 CS Charger minus voltage input terminal

B7,C7 NC Non connection

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 LC05732ARA

VCC

Power
Control OSC
Level
Control Circuit Shifter

Rcsu

Discharge Rcsd
Over−discharge Over− current
Detector Detector
1.2V

Short−circuit
Detector

Over− charge
Detector

Charge
Over− current
Detector

OTP

VSS RSTB S1 S2 CS

Figure 3. Block Diagram

Figure 4. Pdmax vs TA

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 LC05732ARA

Figure 5. Thermal Resistance vs Time

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 LC05732ARA

DESCRIPTION OF OPERATION

1. Normal mode over−discharging (Tuv), discharging will be shut off,

♦ LC05732ARA controls charging and discharging by internal power FETs as DCHG_SW is turned off.
detecting cell voltage (VCC) and controls S2−S1 This is the over−discharging mode.
current. In case that cell voltage is between After detecting over−discharging, CS pin will be
over−discharge detection voltage (Vuv) and pulled up to VCC by an internal resistor Rcsu and
over−charge detection voltage (Vov), and S2−S1 the bias of internal circuits will be shut off.
current is between charge over−current detection (Shut−down mode)
current (Ioch) and discharge over−current detection In shut−down mode, operating current is suppressed
current (Ioc), internal power MOS FETs as under 0.1 uA (max).
CHG_SW, DCHG_SW are both turned ON. ♦ The recovery from stand−by mode will be made by
This is the normal mode, and it is possible to be internal circuits biased after the connecting charger.
charged and discharged. ♦ By continuing to be charged, if cell voltage
2. Over−charging mode increases more than over−discharge detection
♦ Internal power MOSFET CHG_SW turns off if cell voltage (Vuvr) over the delay time of
voltage becomes greater than or equal to over−discharging (Tuvr), internal power MOS FETs
over−charge detection voltage (Vov) over the delay as DCHG_SW is turned on and normal mode will be
time of over−charging (Tov). resumed.
This is the over−charging detection mode. ♦ In over−discharge detection mode, charging
♦ The recovery from over−charging will be made after over−current detection does not operate.
the following two conditions are satisfied. By continuing to be charged, charging over−current
1. Charger is removed from IC. detection starts to operate after cell voltage goes up
2. Cell voltage decreases under over−charge release more than over−discharge release voltage (Vuvr).
voltage (Vovr) over the delay time of over−charging 4. Discharging over−current detection mode 1
releasing (Tovr) due to discharging through a load. ♦ Internal power MOS FET as DCHG_SW will be
Consequently, internal power MOS FET as turned off and discharging current will be shut off if
CHG_SW will be turned on and normal mode will CS pin voltage becomes greater than or equal to
be resumed. discharging over−current detection current (Ioc) over
♦ In over−charging mode, discharging over−current the delay time of discharging over−current (Toc1).
detection is made only when CS pin increases more This is the discharging over−current detection mode
than discharging over−current detection current 1.
2(Ioc2), because discharge current flows through In discharging over−current detection mode 1, CS
parasitic diode of CHG_SW FET. pin will be pulled down to VSS with internal resistor
If CS pin voltage increases more than discharging Rcsd.
over−current detection current 2 (Ioc2) over the ♦ The recovery from discharging over−current
delay time of discharging over−current 2 (Toc2), detection mode will be made after the following two
discharging will be shut off, because internal power conditions are satisfied.
FETs as DCHG_SW is turned off. (short−circuit 1. Load is removed from IC.
detection mode) 2. CS pin voltage becomes less than or equal to
After detecting short−circuit, CS pin will be pulled discharging over−current release current (Iocr) over
down to VSS by internal resistor Rcsd. the delay time of discharging over−current release
♦ The recovery from short circuit detection in (Tocr1) due to CS pin pulled down through Rcsd.
over−charging mode will be made after the Consequently, internal power MOS FET as
following two conditions are satisfied. DCHG_SW will be turned on, and normal mode will
1. Load is removed from IC. be resumed.
2. CS pin voltage becomes less than or equal to 5. Discharging over−current detection mode 2 (short
discharging over−current detection current 2 (Ioc2) circuit detection)
due to CS pin pulled down through Rcsd. ♦ Internal power MOS FET as DCHG_SW will be
Consequently, internal power MOS FET as turned off and discharging current will be shut off if
DCHG_SW will be turned on, and over−charging CS pin voltage becomes greater than or equal to
detection mode will be resumed. discharging over−current detection current2 (Ioc2)
3. Over−discharging mode without Auto Wake Up over the delay time of discharging over−current 2
function (Toc2).
♦ If cell voltage drops lower than over−discharge This is the short circuit detection mode.
detection voltage (Vuv) over the delay time of

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 LC05732ARA

♦ In short circuit detection mode, CS pin will be *Internal current flows out through CS and S2
pulled down to VSS by internal resistor Rcsd. terminals.
The recovery from short circuit detection mode will After charger is removed, it flows through parasitic
be made after the following two conditions are diode of CHG_SW FET.
satisfied. Therefore, CS pin voltage will go up more than
a. Load is removed from IC. charging over−current release current (Iochr).
b. CS pin voltage becomes less than or equal to So CS pin voltage is not an indispensable condition
discharging over−current release current (Iocr) over for recovery from charging over−current detection.
the delay time of discharging over−current release 7. 0 V Battery Protection Function
(Tocr1) due to CS pin pulled down through Rcsd. This function protects the battery when a short circuit
Consequently, internal power MOS FET as in the battery (0 V battery) is detected, at which point
DCHG_SW will be turned on, and normal mode will charging will be prohibited.
be resumed. When the voltage of a battery is below 1.4 V (max), the
6. Charging over−current detection mode gate of the charging control FET is fixed to the
♦ Internal power MOS FET as CHG_SW will be PAC−Terminal voltage, at which point charging will be
turned off and charging current will be shut off if CS prohibited.
pin voltage becomes less than or equal to charging If the voltage of the battery is greater than the 0 V
over−current detection current (Ioch) over the delay battery prohibit voltage (Vinh), charging will be
time of charging over−current (Toch). enabled.
This is the charging over−current detection mode. 8. Reset mode
♦ In case of normal mode, internal power MOS FET
♦ The recoveries from charging over−current detection
mode will be made after the following two as CHG_SW and DCHG_SW will be turned off and
conditions are satisfied. charging and discharging current will be shut off if
1. Charger is removed from IC and CS pin will RSTB pin voltage becomes less than or equal to
increase by load connection. low−level input voltage (VIL) over the delay time of
2. CS pin voltage becomes greater than or equal to reset pulse width(Tw_res).
charging over−current release current (Iochr) over This is the reset mode.
♦ The recovery from reset mode will be made itself
the delay time of charging over−current release
(Tocrh). after the reset release time (Tres).
Consequently, internal power MOS FET as Consequently, internal power MOS FET as
CHG_SW will be turned on, and normal mode will CHG_SW and DCHG_SW will be turned on, and
be resumed. normal mode will be resumed.

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 LC05732ARA

TIMING CHART

Charger Load Charger

connection connection connection

VCC
Vov
Vovr

Vuv/Vuvr

DCHG_SW (Gate)

VCC

S1

CHG_SW (Gate)

VCC

S2

CS

VCC

S1

Tov Tovr Tuv

Figure 6. Over−charge Detection/Release, Over−discharge Detection/Release (Connect Charger)

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 LC05732ARA

Charger connection Load connection

VCC

Vov
Vovr

Vuv

DCHG_SW (Gate)

VCC

S1

CHG_SW (Gate)

VCC

S2

CS

VCC

S1

Tov Tovr

Figure 7. Over−charge Detection/Release, Over−discharge Detection/Release (Non−connect Charger)

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 LC05732ARA

Load connection Load connection

VCC

Vov

Vuv

DCHG_SW (Gate)

VCC

S1

CHG_SW (Gate)

VCC

S2

CS

VCC

S1
Discharge
Current

Ioc

Toc1 Tocr1 Toc2 Tocr1

Figure 8. Discharge Over−Current Detection1, Discharge Over−current Detection2 (Short Circuit)

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 LC05732ARA

Charger
connection Load connection

VCC
Vov

Vuv

DCHG_SW (Gate)
VCC

S1

CHG_SW (Gate)

VCC

S2

CS

VCC

S1

Charge/Discharge
Current

0
Ioch

Toch
Tochr

Figure 9. Charge Over−current Detection

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 LC05732ARA

Load connection Load connection

RSTB

VCC

Vov

Vuv

DCHG_SW (Gate)

VCC

S1

CHG_SW (Gate)

VCC

S2
Discharge
Current

Tw _res Tres

Figure 10. Reset Function

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 LC05732ARA

PACKAGE DIMENSIONS

ECP30, 1.97x4.01
CASE 971BC
ISSUE A
NOTES:

ÈÈÈ
1. DIMENSIONING AND TOLERANCING PER
E A B ASME Y14.5M, 1994.

ÈÈÈ
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO THE SPHERICAL
ORIENTATION CROWNS OF THE SOLDER BALLS.

ÈÈÈ
MARK 4. DIMENSION b IS MEASURED AT THE MAXIMUM
BALL DIAMETER PARALLEL TO DATUM C.
MILLIMETERS
D DIM MIN MAX
A 0.545 0.625
A1 0.165 0.205
A2 0.380 0.420
2X 0.05 C SUPPORT SI b 0.245 0.285
D 1.970 BSC
ENCAPSULATION E 4.010 BSC
2X 0.05 C TOP VIEW E2 0.860 BSC
E3 0.100 BSC
E4 1.405 BSC
DETAIL A A2 e 0.400 BSC
0.15 C A DETAIL A

0.05 C
SEATING
NOTE 3 A1 SIDE VIEW C PLANE

e E2 E4 e

E3 e
e/2
D
e
C

A
30X b
1 2 3 4 5 6 7 8
0.05 C A B
IC DIE IC DIE 0.03 C
BOTTOM VIEW

RECOMMENDED
SOLDERING FOOTPRINT*
30X
0.24 0.40
0.10 PITCH

A1
PACKAGE
OUTLINE

0.40
PITCH

0.96 0.505
DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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 LC05732ARA

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Mouser Electronics

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