Chapter-3

Introduction to the ARM

Instruction Set
ARM Instruction Set
 3.1 Data Processing Instructions
• The data processing instructions manipulate data
within registers. They are
- move instructions,
- arithmetic instructions,
- logical instructions,
- comparison instructions, and
- multiply instructions.
• Most data processing instructions can process
one of their operands using the barrel shifter.
• If you use the S suffix on a data processing
instruction, then it updates the flags in the cpsr.

• Move and logical operations update the carry flag

C, negative flag N, and zero flag Z.

• The carry flag is set from the result of the barrel

shift as the last bit shifted out.

• The N flag is set to bit 31 of the result.

• The Z flag is set if the result is zero.

 3.1.1 Move Instructions
• Move is the simplest ARM instruction.
• It copies N into a destination register Rd,
where N is a register or immediate value.
• This instruction is useful for setting initial
values and transferring data between
registers.
 Examples

Condition Embedded in ADD Instruction

{cond} Rd, N
MOVEQ r0, r1 ; If zero flag set then…
; ... r0 = r1
 Example
AREA MOV1, CODE, READONLY

START
MOV R0,#5
MOV R1,#6
SUBS R0,R0,#4 ; FIRST SUBTRACT 5 AND NEXT 4
MOVEQ R2,R1
MOV R3,#10
BACK B BACK
END
• For example to move the value zero to
destination register and set the condition
flags:
MOVS Rd, N

MOVS r0,r1 ; r0 = r1
; ... and set flags
 Example
AREA MOV2, CODE, READONLY

START
MOV R0,#0
MOV R1,#6
MOVS R2,R0 ; Z
MOVS R3,R1 ; z
BACK B BACK
END
3.1.2 Barrel Shifter
• In MOV instruction N is a simple register/immediate value.

• It can also be a register Rm that has been preprocessed by the barrel

shifter prior to being used by a data processing instruction.

• Majority of the data processing instructions are processed within the

arithmetic logic unit (ALU).

• A unique and powerful feature of the ARM processor is the ability to shift
the 32-bit binary pattern in one of the source registers left or right by a
specific number of positions before it enters the ALU.

• This shift increases the power and flexibility of many data processing
operations.

• There are data processing instructions that do not use the barrel shift, for
example,
-- the MUL (multiply),
-- CLZ (count leading zeros), and
-- QADD (signed saturated 32-bit add)
Example
Barrel shifter operations

Note: x represents the register being shifted

and y represents the shift amount.
 Barrel Shifter - Left Shift
• Shifts left by the specified amount
• Multiplies by powers of two
• e.g.
LSL #5 = multiply by 32

Logical Shift Left (LSL)

CF Destination 0
 Barrel Shifter - Right Shifts
Logical Shift Right
•Shifts right by the specified amount (divides by
powers of two)
• e.g.
LSR #5 = divide by 32

Logical Shift Right

...0 Destination CF
 Arithmetic Shift Right
Arithmetic Shift Right
•Shifts right (divides by powers of two) and
preserves the sign bit, for 2's complement
operations.
•e.g.
ASR #5 = divide by 32
Arithmetic Shift Right

Destination CF

Sign bit shifted in

 Barrel Shifter - Rotations
Rotate Right (ROR)
•Similar to an ASR but the bits wrap around as
they leave the LSB and appear as the MSB.
e.g. ROR #5
•Note the last bit rotated is also used as the
Carry Out.

Rotate Right

Destination CF
 Barrel Shifter - Rotations
Rotate Right Extended (RRX)
Rotate Right Extended (RRX)
• This operation uses the CPSR C flag as a 33rd
bit.
•Rotates right by 1 bit. Encoded as ROR #0.

Rotate Right through Carry

Destination CF
MOVS - example
3.1.3 Arithmetic Instructions
 Example-1
• Subtract instruction subtracts a value stored in
register r2 from a value stored in register r1.
The result is stored in register r0.
 Example-2
• Reverse Subtract Instruction (RSB) subtracts r1
from the constant value #0, writing the result
to r0. You can use this instruction to negate
numbers.
 Example-3
• SUBS instruction is useful for decrementing loop counters. In
this example we subtract the immediate value one from the
value one stored in register r1. The result value zero is written
to register r1. The cpsr is updated with the ZC flags being set.
 3.1.4 Using the Barrel Shifter with
Arithmetic Instructions
• The wide range of second operand shifts available on
arithmetic and logical instructions is a very powerful feature
of the ARM instruction set.
 Example-1
AREA MOV2, CODE, READONLY

START
MOV R0,#5
MOV R1,#6
add R2,R0,R1, LSL #0x2
BACK B BACK
END
 Example-2
AREA ADD1, CODE, READONLY

START
MOV R0,#5
MOV R1,#6
SUBS R0,R0,#4 ; FIRST SUBTRACT 5 AND NEXT 4
ADDEQ R2,R1,R0
MOV R3,#10
BACK B BACK
END
 3.1.5 Logical Instructions
• Logical instructions perform bitwise logical
operations on the two source registers.
 Example-1
• Logical OR operation between registers r1 and
r2. r0 holds the result.
 Example-2
• A more complicated logical instruction called
BIC, which carries out a logical bit clear.
 Example-3
AREA ADD1, CODE, READONLY

START
MOV R0,#5
MOV R1,#6
AND R2,R1,R0
BACK B BACK
END
 Example-4
AREA ADD1, CODE, READONLY

START
MOV R0,#5
MOV R1,#6
AND R2,R1,R0
BACK B BACK
END
 Example-5
AREA ADD1, CODE, READONLY

START
mov R0,#15
mov R1,#5
bic R2,R0,R1 ; r2=r0 & (~R1)
BACK B BACK
END
 3.1.6 Comparison Instructions
• The comparison instructions are used to compare or test a
register with a 32-bit value.
• They update the cpsr flag bits according to the result, but do
not affect other registers.
• After the bits have been set, the information can then be used
to change program flow by using conditional execution.
CMP Example
 CMN Instruction
• The CMN instruction adds the value of N to
the value in Rn.
• This is the same as an ADDS instruction,
except that the result is discarded.
• The conditional flags are updated accordingly.
RO=50
R1=10
CMN RO, R1
 TEQ
• Test Equivalence.
• The TEQ instruction performs a bitwise
Exclusive OR operation on the value in Rn and
the value of N. the result is discarded.
• Use the TEQ instruction to test if two values
are equal, without affecting the V or C flags
(as CMP does). It affects the N and Z flags.
 TEQ- Example
AREA TEST, CODE, READONLY
ENTRY

START
MOV R0,#6
MOV R1,#5
TEQ R0,R1
BACK B BACK
END
 TST - Instruction
• This instruction tests the value in a register
against N. It updates the condition flags on
the result, but does not place the result in any
register.
• The TST instruction performs a bitwise AND
operation on the value in Rn and the value
of N.
• This is the same as an ANDS instruction,
except that the result is discarded.
 TST – EXAMPLE-1
AREA TEST, CODE, READONLY
ENTRY

START
MOV R0,#6
MOV R1,#9
TST R0,R1 ;6&9=0Z
BACK B BACK
END
 TST – EXAMPLE-2
AREA TEST, CODE, READONLY
ENTRY

START
MOV R0,#6
MOV R1,#5
TST R0,R1 ;6&5=4z
BACK B BACK
END
 3.1.7 Multiply Instructions
• The multiply instructions multiply the
contents of a pair of registers.
 MLA- EXAMPLE-1
AREA TEST, CODE, READONLY
ENTRY

START
MOV R0,#6
MOV R1,#5
MOV R2,#1
MLA R3,R0,R1,R2 ;R3=(R0*R1) + R2
BACK B BACK
END
 MLA- EXAMPLE-2
AREA TEST, CODE, READONLY
ENTRY

START
MOV R0,#6
MOV R1,#5
MOV R2,#1
MLA R0,R0,R1,R2 ;R0=(R0*R1) + R2 NOT ALLOWED
BACK B BACK
END
 MLA- EXAMPLE-3
AREA TEST, CODE, READONLY
ENTRY

START
MOV R0,#6
MOV R1,#5
MOV R2,#1
MLA R1,R0,R1,R2 ;R1=(R0*R1) + R2 ALLOWED
BACK B BACK
END
 MLA- EXAMPLE-4
AREA TEST, CODE, READONLY
ENTRY

START
MOV R0,#6
MOV R1,#5
MOV R2,#1
MLA R2,R0,R1,R2 ;R2=(R0*R1) + R2 ALLOWED
BACK B BACK
END
 MUL – EXAMPLE-1
AREA TEST, CODE, READONLY
ENTRY

START
MOV R0,#6
MOV R1,#5
MUL R3,R0,R1 ;R3=R0*R1
BACK B BACK
END
 MUL- EXAMPLE-2
AREA TEST, CODE, READONLY
ENTRY

START
MOV R0,#6
MOV R1,#5
MUL R0,R0,R1 ; THIS REGISTER SEQUENCE NOT
;ALLOWED
BACK B BACK
END
 MUL- EXAMPLE-2
AREA TEST, CODE, READONLY
ENTRY

START
MOV R0,#6
MOV R1,#5
MUL R1,R0,R1 ; THIS REGISTER SEQUENCE IS
;ALLOWED BECAUSE N IS COPIED TO TEMP REG
BACK B BACK
END
 SMLAL - EXAMPLE
AREA TEST, CODE, READONLY
ENTRY

START
ldr R0,=0x5
ldr R1,=0x5
LDR R2,=0X2
LDR R3,=0X4
SMLAL R3,R2,R0,R1 ;[R3Lo,R2Hi]=[R3,R2]+(R0*R1)
BACK B BACK
END
 SMULL - EXAMPLE
AREA TEST, CODE, READONLY
ENTRY

START
ldr R0,=0x5
ldr R1,=0x5
LDR R2,=0X2
LDR R3,=0X4
SMULL R3,R2,R0,R1 ;[R3Lo,R2Hi]=(R0*R1)
BACK B BACK
END
 UMULL- Example
AREA UMULL1, CODE, READONLY

START
ldr R0,=0xf0000002
ldr R1,=0x00000002
umull r3,R2,R1,R0
MOV R3,#10
BACK B BACK
END
 UMLAL- Example
AREA TEST, CODE, READONLY
ENTRY

START
ldr R0,=0x5
ldr R1,=0x5
LDR R2,=0X2
LDR R3,=0X4
UMLAL R3,R2,R0,R1 ;[RdHi, RdLo] = [RdHi, RdLo] +
(Rm *Rs)
BACK B BACK
END
 3.2 Branch Instructions
• A branch instruction changes the flow of
execution or is used to call a routine.

• This type of instruction allows programs to

have subroutines, if-then-else structures, and
loops.

• The change of execution flow forces the

program counter pc to point to a new address.
•The label is the address stored in the instruction as a signed pc-relative offset and
must be within approximately 32 MB of the branch instruction.

• T refers to the Thumb bit in the cpsr.

•When instructions set T, the ARM switches to Thumb state.

 Forward and Backward branch
• These loops are address specific, we do not include the pre-
and post-conditions.
• Following example the forward branch skips three
instructions. The backward branch creates an infinite loop.
 BL (Branch with Link instruction)
• BL, instruction is similar to the B instruction but overwrites
the link register lr with a return address.
• It performs a subroutine call.

• Example:
 BX (Branch Exchange), BLX (Branch
Exchange with Link)
• The branch exchange (BX) and branch exchange with link (BLX) are the third type
of branch instruction.

• The BX instruction uses an absolute address stored in register Rm.

•
• It is used to branch to and from Thumb code.

• The T bit in the cpsr is updated by the least significant bit of the branch register.

pc = Rm & 0xfffffffe, T = Rm & 1

• Similarly the BLX instruction updates the T bit of the cpsr with the least
significant bit and additionally sets the link register with the return address.

• pc = label, T = 1
• pc = Rm & 0xfffffffe, T = Rm & 1
• lr = address of the next instruction after the BLX
 3.3 Load-Store Instructions
• Load-store instructions transfer data between
memory and processor registers.
• There are three types of load-store
instructions:
- single-register transfer,
- multiple-register transfer, and
- swap.
 3.3.1 Single-Register Transfer
• These instructions are used for moving a single data item in
and out of a register.
• The datatypes supported are signed and unsigned words (32-
bit), halfwords (16-bit), and bytes.
• For example, LDR can only load 32-bit words on a memory
address that is a multiple of four bytes—0, 4, 8, and so on.
• This example shows a load from a memory address contained
in register r1, followed by a store back to the same address in
memory.
 3.3.2 Single-Register Load-Store
Addressing Modes
• The ARM instruction set provides different
modes for addressing memory.
• These modes incorporate one of the indexing
methods:
-- preindex with writeback,
-- preindex, and
-- postindex
Preindexing with writeback: (Base
Register Updated)
Preindexing: (Base Register not
updated)
Postindexing: (Base Register Updated)
 3.3.3 Multiple-Register Load-Store
Instructions
• Load-store multiple instructions can transfer
multiple registers between memory and the
processor in a single instruction.

• The transfer occurs from a base address register

Rn pointing into memory.

• Multiple-register transfer instructions are more

efficient from single-register transfers.

• Load-store multiple instructions increases

interrupt latency.
• For example, on an ARM7 a load multiple
instruction takes
– 2 + Nt cycles,
– where N is the number of registers to load
-- t is the number of cycles required for each sequential
access to memory.
• If an interrupt has been raised, then it has no
effect until the load-store multiple instruction
is complete.
Addressing mode for load-store
multiple instructions.
Example
Graphical Representation (IA).
Graphical Representation (IB).
Load-store multiple pairs when base
update used.
 EXAMPLE-1 LDMIA
AREA ASCENDING , CODE, READONLY

ENTRY ;Mark first instruction to execute

START

LDR R2,=CVALUE ; ADDRESS OF CODE REGION

LDMIA R2!,{R3-R6}
BACK B BACK

CVALUE
DCD 0X44444444 ;
DCD 0X11111111 ;
DCD 0X33333333 ;
DCD 0X22222222 ;

END
 EXAMPLE-2 LDMIB
AREA ASCENDING , CODE, READONLY

ENTRY ;Mark first instruction to execute

START

LDR R2,=CVALUE ; ADDRESS OF CODE REGION

LDMIB R2!,{R3-R6}
BACK B BACK

CVALUE
DCD 0X44444444 ;
DCD 0X11111111 ;
DCD 0X33333333 ;
DCD 0X22222222 ;

END
 EXAMPLE (STMIA)
AREA ASCENDING , CODE, READONLY
ENTRY ;Mark first instruction to execute
START
LDR R2,=CVALUE ; ADDRESS OF CODE REGION
LDMIA R2!,{R3-R6}
LDR R7,=DVALUE
STMIA R7!,{R3-R6}
BACK B BACK
CVALUE
DCD 0X44444444 ;
DCD 0X11111111 ;
DCD 0X33333333 ;
DCD 0X22222222 ;

AREA DATA1, DATA, READWRITE

DVALUE DCD 0X00

END
 EXAMPLE (STMIB and LDMDA)
AREA ASCENDING , CODE, READONLY

ENTRY ;Mark first instruction to execute

START

LDR R0,=0X40000000
LDR R1,=0x00000009
LDR R2,=0x00000008
LDR R3,=0x00000007
STMIB r0!, {r1-r3}
MOV r1, #1
MOV r2, #2
MOV r3, #3
LDMDA r0!, {r1-r3}
BACK B BACK
 EXAMPLE (STMIB and LDMDB)
AREA ASCENDING , CODE, READONLY

ENTRY ;Mark first instruction to execute

START

LDR R0,=0X40000000
LDR R1,=0x00000009
LDR R2,=0x00000008
LDR R3,=0x00000007
STMIB r0!, {r1-r3}
MOV r1, #1
MOV r2, #2
MOV r3, #3
LDMDB r0!, {r1-r3}
BACK B BACK
end
 3.3.3.1 Stack Operations
• The ARM architecture uses the load-store multiple
instructions to carry out stack operations.
– The pop operation (removing data from a stack) uses a load
multiple instruction;
-- The push operation (placing data onto the stack) uses
a store multiple instruction
• We have to decide whether the stack will grow up or
down in memory. A stack is either
-- ascending (A) or
-- descending (D).
Ascending stacks grow towards higher memory
addresses;
Descending stacks grow towards lower memory
addresses.
• In full stack (F), the stack pointer sp points to
an address that is the last used or full location
(i.e., sp points to the last item on the stack).
• In an empty stack (E) the sp points to an
address that is the first unused or empty
location (i.e., it points after the last item on
the stack).
 Example-STMFD
• The STMFD instruction pushes registers onto the stack,
updating the sp. Below example push onto a full descending
stack.
• When the stack grows the stack pointer (sp) points to the last
full entry in the stack. Hence it is called as full and descending
because address decreases.
 Example-STMED
• The STMED instruction pushes the registers
onto the stack but updates register sp to point
to the next empty location downward.
 Example-1
POPING ONE
AREA ASCENDING , CODE, READONLY
AT A TIME
ENTRY ;Mark first instruction to execute
START

LDR SP,=0X40000000
LDR R1,=0x00000009
LDR R2,=0x00000008
LDR R3,=0x00000007
STMFA SP!, {r1-r3}
LDMFA SP!,{R4}
LDMFA SP!,{R5}
LDMFA SP!,{R6}
BACK B BACK
END

Note: STMFA == STMIB, LDMFA == LDMDA

 Example-2
POPING ALL 3 ELEMENTS
AREA ASCENDING , CODE, READONLY

ENTRY ;Mark first instruction to execute

START

LDR SP,=0X40000000
LDR R1,=0x00000009
LDR R2,=0x00000008
LDR R3,=0x00000007
STMFA SP!, {r1-r3}
LDMFA SP!,{R4-R6}

BACK B BACK
END
 Example-3
POPING FROM EMPTY STACK
AREA ASCENDING , CODE, READONLY

ENTRY ;Mark first instruction to execute

START

LDR SP,=0X40000000
LDR R1,=0x00000009
LDR R2,=0x00000008
LDR R3,=0x00000007
STMFA SP!, {r1-r3}
LDMFA SP!,{R4-R6}
LDMFA SP!,{R7} ; UNDER FLOW
BACK B BACK
END
 Example-4
Full Descending Stack
AREA ASCENDING , CODE, READONLY

ENTRY ;Mark first instruction to execute

START

LDR SP,=0X4000001F
LDR R1,=0x00000009
LDR R2,=0x00000008
LDR R3,=0x00000007
STMFD SP!, {r1-r3}
LDMFD SP!,{R4-R6}
LDMFD SP!,{R7}
BACK B BACK
END
 Checking Stack Under Flow
• In handling the stack there are three attributes that need
to be preserved:
– The stack base,
– the stack pointer, and
– the stack limit.

• The stack base is the starting address of the stack in

memory.

• The stack pointer initially points to the stack base; as data is

pushed onto the stack, the stack pointer descends memory
and continuously points to the top of stack.

• If the stack pointer passes the stack limit, then a stack

overflow occurs
• Small piece of code that checks for stack
overflow errors for a descending stack
 Checking Stack Under Flow
; check for stack overflow
Mov r10,rn
CMP sp, r10
BLT _stack_underflow ; condition
 3.3.4 Swap Instruction
• The swap instruction is a special case of a load-store
instruction.

• It swaps the contents of memory with the

contents of a register.

• This instruction is an atomic operation

—it reads and writes a location in the same bus

operation, preventing any other instruction from
reading or writing to that location until it completes.
 Swap Syntax

Note: Swap cannot be interrupted by any other instruction or any other bus
access. The system “holds the bus” until the transaction is complete
Example-1
 Example-2
• This example shows a simple data guard that can be used to
protect data from being written by another task.
• The SWP instruction “holds the bus” until the transaction is
complete.

•The address pointed to by the semaphore either contains the value 0 or 1.

•If current value of the semaphore is 1, the resource is currently used by other process.
•If current value of the semaphore is 0, the resource is currently available/ not used by any of
the process.
•The process that intends to use the resource (register/ memory ) will make the change the
semaphore from 0 to 1
•The process that intends to release the resource (register/memory) will change the
semaphore from 1 to 0
 EXAMPLE-3
AREA ASCENDING , CODE, READONLY
ENTRY ;Mark first instruction to execute
START
LDR R0,=0X11111111
LDR R1,=CVALUE
LDR R2,[R1]
LDR R1,=DVALUE
STR R2,[R1]
SWP R3,R0,[R1]
BACK B BACK
CVALUE DCD 0X22222222

AREA DATA1, DATA, READWRITE

DVALUE DCD 0X22222222

END
3.4 Software Interrupt Instruction
• A software interrupt instruction - (SWI)
• This causes a software interrupt exception,
• Provides a mechanism for applications to call
operating system routines.
• When the processor executes an SWI
instruction, it sets the program counter pc to
the offset 0x8 in the vector table.
• The processor mode changes to SVC, This
allows an operating system routine to be
called in a privileged mode.
• Each SWI instruction has an associated SWI
number, which is used to represent a
particular function call or feature.
 Example
AREA HelloW,CODE,READONLY; declare area
SWIWrite EQU 0x00 ; Angel SWI number
ENTRY ; code entry point
START ADR r1, TEXT-1 ; r1 -> “Hello World” -1
LOOP MOV r0, #0x1 ; Angel write char in [r1]
LDRB r2, [r1,#1]! ; get the next byte
CMP r2, #0 ; check for text end
SWINE SWIWrite ; if not end print ..
BNE LOOP ; .. and loop back
MOV r0, #0x18 ; Angel exception call
LDR r1, =0x20026 ; Exit reason
SWI &11 ; end of execution
TEXT = "Hello World",0xA,0xD,0
END ; end of program source
 3.5 Program Status Register
Instructions
• The ARM instruction set provides two
instructions to directly control a program
status register (psr).
• The MRS instruction transfers the contents of
either the cpsr or spsr into a register; in the
reverse direction
• The MSR instruction transfers the contents of
a register into the cpsr or spsr.
• Together these instructions are used to read
and write the cpsr and spsr.
 MRS, MSR Syntax
• In syntax the label called fields can be any
combination of control (c), extension (x),
status (s), and flags (f ).
 Example

•The MSR first copies the cpsr into register r1.

•The BIC instruction clears bit 7 of r1.

• Register r1 is then copied back into the cpsr, which enables IRQ interrupts.

•This code preserves all the other settings in the cpsr and only modifies the I bit in
the control field.

•This example is in SVC mode. In user mode you can read all cpsr bits, but you can
only update the condition flag field f.
 3.5.1 Coprocessor Instructions
• Coprocessor instructions are used to extend the instruction set.

• A coprocessor provides additional computation capability.

• The coprocessor instructions include

- data processing,
- register transfer, and
- memory transfer instructions.

• We discuss only a short overview since these instructions are

coprocessor specific.

• Note that these instructions are only used by cores with a coprocessor.
 Co-processor Instruction Syntax

•The cp field represents the coprocessor number between p0 and p15.

•The opcode fields describe the operation to take place on the coprocessor.

•The Cn, Cm, and Cd fields describe registers within the coprocessor.

•Coprocessor 15 (CP15) is reserved for system control purposes, such as memory

management, write buffer control, cache control, and identification registers.
 Example

• Transferring the contents of CP15 coprocessor

register c0 to register r10.

Here CP15 register-0 contains the processor identification number. This register is
copied into the general-purpose register r10.
 3.6 Loading Constants
• In ARM there is no ARM instruction to move a 32-bit
constant into a register.
• To aid programming there are two pseudo
instructions to move a 32-bit value into a register.