Module 4
I/O Ports and Their
Programming
1
8051 Pin diagram
Figure 4-1. 8051 Pin
Diagram
The 8051 family members all
have 40 pins.
Vcc, GND, XTAL1,
XTAL2,... (See Chapter 8).
I/O port pins
• The four ports: Port 0, Port
1, Port 2, and Port 3
• Usually we call them as P0,
P1, P2, and P3.
• Each port uses 8 pins.
2
I/O Port Pins
The 8051 has four I/O ports
Port 0 pins 32-39 P0.0 to P0.7
Port 1 pins 1-8 P1.0 to P1.7
Port 2 pins 21-28 P2.0 to P2.7
Port 3 pins 10-17 P3.0 to P3.7
Each port has 8 pins.
• Named P0.X , P1.X, P2.X, P3.X X=0,1,...,7
• P0.0 is the bit 0 (LSB) of P0
• P0.7 is the bit 7 (MSB) of P0
• These 8 bits form a byte.
• Note that 8 pins of port can work independently.
Each port can be used as input or output (bi-
directional).
3
Ports 2 and 3
In an 8031-based system, P2 is
used to provide address A8-
A15.
Although port 3 can be used as
simple I/O port, this is not the
way it is most commonly used.
Port 3 has the additional
function of providing certain
signals.
4
Port P1 Pull-up resistor
is missing at P0
Read latch Vcc
TB2
Load(L1)
Internal CPU D Q P1.X
bus P1.X D pin
G M1
Write to latch Clk Q
TB1
Read pin
5
Port pins
Each pin of I/O ports
Internal CPU bus communicates with CPU
A D latch stores the value of this pin
• D latch is controlled by “Write to latch”
– Write to latch 1: write data into the D latch
Two Tri-state buffers
• TB1: controlled by “Read pin”
– Read pin = 1 (TB1=1) read the data present at the pin
• TB2: controlled by “Read latch”
– Read latch=1 (TB2=1) read value from internal latch
A transistor M gate
• Gate = 0, output = 1
• Gate = 1, output = 0
6
Writing 1 to output pin P1.X
7
Writing 0 to output pin P1.X
8
Reading High at Input Pin
9
Reading Low at the Input Pin
2.MOV A,P1
External
pin=Low
10
Never connect direct Vcc to Port Pins
11
a)
Ways
b)
c)
12
Other Pins
P1, P2, and P3 have internal pull-up resisters.
P1, P2, and P3 are not open drain.
P0 has no internal pull-up resistors and does not
connect to Vcc inside the 8051.
P0 is open drain.
Compare the figures of P1.X and P0.X
However, for a programmer, it is the same to
program P0,P1,P2, and P3.
All the ports, upon a RESET, receive a FFh
13
P0 Structure
14
P0 Structure
P0 is an open drain.
Open drain is a term used for MOS chips in the same
way that open collector is used for TTL chips.
When P0 is used for simple data I/O we must connect
it to external pull-up resistors.
Each pin of P0 must be connected externally to a 10K
ohm pull-up resistor. Then P0 can be an input or output
port.
In an 8031-based system, P0 are used to provide
address A0-A7. (See Chapter 14)
15
Port 0
16
What if the 8051 cannot drive a load
– use buffers
18
74LS244 74LS245
19
How to program for input
In order to make P1 an input port, the port must
be programmed by writing 1 to all the bits.
MOV A,#0FFH ;A=11111111B
MOV P1,A ;make P1 an input port
BACK: MOV A,P1 ;get data from P1
MOV P2,A ;send data to P2
SJMP BACK
The pin value is sent to CPU, but not saved in latch .
To be an input port, P0, P1, P2 and P3 have similar
methods.
20
Port Read
When reading ports, there are two possibilities
：
Read the input pin to CPU (from external pin value)
MOV A, P1
JNB P2.1, TARGET ; jump if P2.1 is not set
JB P2.1, TARGET ; jump if P2.1 is set
21
Port Read - more
Read-Modify-Write Instructions
or Read the internal
latch of the output
port (and then
output).
• ANL P1, A
; P1 ← P1 AND A
• ORL P1, A
; P1 ← P1 OR A
• INC P1
; increment P1
It is not obvious that the last three instructions in this list are read-modify-
write instructions, but they are. They read the port byte, all 8 bits, modify the
addressed bit, then write the new byte back to the latch.
22
Reading the Latch using Read-
Modify-Write Instructions
ANL P1,A
The read latch activates TB2
This data is ANDed with register A
The result is overwritten to the latch
23
