doc004

PRELIMINARY
The Tx descriptor format for words 15 through

22 is described in Table 3-4.
Table 3-4. DMA Tx Descriptor Format for Words 15–22
Word Bits Name Description
15 31 rts_cts Qualifies RTS_ENABLE or CTS_ENABLE in the Tx descriptor for Tx series 1
_qual1 1 Default behavior with respect to RTS_ENABLE and CTS_ENABLE
30:16 packet Packet duration 1 (in μs); Duration of the actual Tx frame associated with
_duration1 TXRate1. This time does not include RTS, CTS, ACK, or any associated SIFS.
15 rts_cts Qualifies RTS_ENABLE or CTS_ENABLE in the Tx descriptor for Tx series 0
16 31 rts_cts Qualifies RTS_ENABLE or CTS_ENABLE in the Tx descriptor for Tx series 3
15 rts_cts Qualifies RTS_ENABLE or CTS_ENABLE in the Tx descriptor for Tx series 2
17 31:30 RES Reserved
29 dc_ap Select for remaining the TBTT between TSF and TSF2, where 0 is from TSF
_sta_sel and 1 is from TSF2. Should be used only when both AP_STA_ENABLE and
TXOP_TBTT_LIMIT_ENABLE are enabled.
28:26 encrypt_type Encryption type; DMA engine must the number of necessary extra Dwords
at the end of a packet to account for the encryption ICV which is generated
by hardware. The encrypt type fields must be valid for all descriptors.
0 None; 0 pad bytes
1 WEP or TKIP (no MIC); 4 pad bytes
2 AES; 8 pad bytes
3 TKIP; 12 pad bytes
4 WAPI; 16 pad bytes
7:5 Reserved
25:18 pad_delim Pad delimiters; Between each packet of an A-MPDU aggregate the hardware
will insert a start delimiter which includes the length of the next frame.
Sometimes hardware on the transmitter or receiver requires some extra time
between packets which can be satisfied by inserting zero length delimiters.
This field indicates the number of extra zero length delimiters to add.
17:16 RES Reserved
15:0 agg_length Aggregate (A-MPDU) length; the aggregate length is the number of bytes of
the entire aggregate. This length should be computed as:
delimiters = start_delim + pad_delim;
frame_pad = (frame_length % 4) ? (4 - (frame_length % 4)) : 0
agg_length = sum_of_all (frame_length + frame_pad + 4 *
delimiters)
For the last packet of an aggregate the FRAME_PAD = 0 and delimiter= 0,
frame_pad aligns to the next delimiter to be Dword aligned. Each delimiter is
4 bytes long. PAD_DELIM is the number of zero-length delimiters used to
introduce an extra time gap between packets. START_DELIM is always 1 and
includes the length of the next packet in the aggregate.
38 • AR9331 802.11n 1x1 2.4 GHz SoC for AP and Router Platforms Atheros Communications, Inc.
38 • December 2010 COMPANY CONFIDENTIAL
PRELIMINARY
Table 3-4. DMA Tx Descriptor Format for Words 15–22 (continued)

27:20 rts_cts_rate RTS or self-CTS rate selection. Specifies the rate the RTS sends at if rts_enable
is set, or self CTS sends at if cts_enable is set; see Table 3-3.
19:17 RES Reserved
16 gi_3 Guard interval control for Tx series 3
0 Normal guard interval
1 Short guard interval
15 20_40_3 20_40 control for Tx series 3
0 HT20 Tx packet
1 HT40 Tx packet
14:12 RES Reserved
9:7 RES Reserved
4:2 RES Reserved
23:0 antenna_0 Antenna switch for Tx series 0
29:24 tpc_1 TPC for Tx series 1. These bits pass unchanged to the baseband, where they
control Tx power for the frame.
Atheros Communications, Inc. AR9331 802.11n 1x1 2.4 GHz SoC for AP and Router Platforms • 39
COMPANY CONFIDENTIAL December 2010 • 39
PRELIMINARY
The Tx descriptor status format for words 0

through 8 is described in Table 3-5.
The words status is only considered valid
when the done bit is set.
Table 3-5. Tx Descriptor Status Format: Words 0–8
0 31:16 atheros_id The unique Atheros identifier of 0x168C is used to visually identify the start
of the descriptor.
15 desc_tx_rx Indicates whether the descriptor is a transmit or receive descriptor. The
value should be set to 1 indicating transmit.
14 desc_ctrl Indicates whether the descriptor is a control or status descriptor. The value
_stat should be set to 0 indicating status descriptor.
13:12 RES Reserved
11:8 tx_qcu_num Tx QCU number. Indicates which QCU this descriptor is part of.
7:0 desc_length Descriptor length. Indicates the number of Dwords in this descriptor. The
value should be set to 0x9 (9 Dwords).
1 31:16 tx_desc_id Tx descriptor sequence number. Software will select a unique sequence
number associated with this descriptor. This value is copied to the
TX_DESC_ID in the Tx status.
15:0 RES Reserved
2 31 RES Reserved
30 ba_status Block ACK status. If set, this bit indicates that the BA_BITMAP values are
valid.
29:24 RES Reserved
23:16 ack_rssi_ant02 Rx ACK signal strength indicator of control channel chain 2.
A value of 0x80 (–128) indicates an invalid number.
PRELIMINARY

19 tx_timer Tx timer expired. This bit is set when the Tx frame is taking longer to send to
_expired the baseband than is allowed based on the TX_TIMER register. Some
regulatory domains require that Tx packets may not exceed a certain amount
of transmit time.
18 RES Reserved
17 tx_data_underrun_ Tx data underrun error. These error conditions occur on aggregate frames
err when the underrun condition happens while the MAC is sending the data
portion of the frame or delimiters.
16 tx_delmtr_underru Tx delimiter underrun error. These error conditions occur on aggregate
n_err frames when the underrun conditions happens while the MAC is sending
delimiters.
15:12 virtual_retry_cnt Virtual collision count. Reports the number of virtual collisions that
occurred before transmission of the frame ended. The counter value
saturates at 0xF. A virtual collision refers to the case, as described in the
802.11e QoS specification, in which two or more output queues are
contending for a TXOP simultaneously. In such cases, all lower-priority
output queues experience a virtual collision in which the frame is treated as
if it had been sent on the air but failed to receive an ACK.
11:8 data_fail_cnt Data failure count. Reports the number of times the actual frame (as
opposed to the RTS) was sent but no ACK was received for the final
transmission series (see the FINAL_TS_INDEX field).
7:4 rts_fail_cnt RTS failure count. Reports the number of times an RTS was sent but no CTS
was received for the final transmission series (see the FINAL_TX_INDEX
field). For frames that have the RTS_ENABLE bit clear, this count always
will be zero. Note that this count is incremented only when the RTS/CTS
exchange fails. In particular, this count is not incremented if the RTS/CTS
exchange succeeds but the frame itself fails because no ACK was received.
3 filtered Frame transmission filter indication. If set, indicates that the frame was not
transmitted because the corresponding destination mask bit was set when
the frame reached the PCU or if the frame violated TXOP on the first packet
of a burst. Valid only if FRM_XMIT_OK is clear.
2 fifo_underrun Tx FIFO underrun flag. If set, transmission of the frame failed because the
DMA engine was not able to supply the PCU with data as quickly as the
baseband was requesting transmit data. Only valid for non-aggregate or
non-RIFS underrun conditions unless the underrun occurred on the first
packet of the aggregate or RIFS burst. See also the description for
TX_DELMTR_UNDERRUN_ERR and TX_DATA_UNDERRUN_ERR. Valid
only if FRM_XMIT_OK is clear.
1 excessive Excessive tries flag. If set, transmission of the frame failed because the try
_retries limit was reached before the frame transmitted. Valid only if
FRM_XMIT_OK is clear.
0 frm_xmit_ok Frame transmission success flag. If set, the frame was transmitted
successfully. If clear, no ACK or BA was received successfully.
4 31:0 send Timestamp at start of transmit. A snapshot of the lower 32 bits of the PCU
_timestamp timestamp (TSF value). This field can be used to aid the software driver in
implementing requirements associated with the
aMaxTransmitMSDULifetime MAC attribute. The transmit timestamp is
sampled on the rising of tx_frame signal which goes from the MAC to the
baseband. This value corresponds to the last attempt at packet transmission
not the first attempt.
For support location mode, this value refers to the fast timestamp value, and
is valid when word 8, bit [27] of the Tx Descriptor Status is high.
PRELIMINARY

5 31:0 ba_bitmap_0-31 Block ACK bitmap 0 to 31. These bits are the values from the block ACK
received after the successful transmission of an aggregate frame. If set, bit [0]
represents the successful reception of the packet with the sequence number
matching the seq_num value.
6 31:0 ba_bitmap_32-63 Block ACK bitmap 32 to 63. These bits are the values from the block ACK
received after the successful transmission of an aggregate frame. If set, bit
[32] represents the successful reception of the packet with the sequence
number matching the seq_num value + 32.
7 31:24 ack_rssi Rx ACK signal strength indicator of combination of all active chains on the
_combined control and extension channels. The value of 0x80 (–128) is used to indicate
an invalid number.
8 31:28 tid Traffic Identifier (TID) of block ACK. Indicates the TID of the response block
ACK. This field is only valid on the last descriptor of the last packet of an
aggregate.
27 tx_location_mode The location mode indicator of the Tx Descriptor Status. This field indicates
that the send_timestamp field (word 8, bit [31:0]) is used for the location
mode, and not as the TSF value for the PCU timestamp.
26 RES Reserved
25 pwr_mgmt Power management state. Indicates the value of the PwrMgt bit in the frame
control field of the response ACK frame.
24:23 RES Reserved
22:21 final_tx_index Final transmission attempt series index. Specifies the number of the Tx series
that caused frame transmission to terminate.
20 RES Reserved
(Cont.) 17 txop_exceeded TXOP has been exceeded. Indicates that this transmit frame had to be
filtered because the amount of time to transmit this packet sequence would
exceeded the TXOP limit. This should only occur when software programs
the TXOP limit improperly.
16:13 RES Reserved
12:1 seq_num The starting sequence number is the value of the Block ACK Starting
Sequence Control field in the response Block ACK. Only consulted if the Tx
frame was an aggregate.
0 done Descriptor completion flag. Set to one by the DMA engine when it has
finished processing the descriptor and has updated the status information.
Valid only for the final descriptor of a non-aggregate frame, regardless of the
state of the FrTxOK flag. For an aggregate frame it is valid for only the final
descriptor of the final packet of an aggregate. The driver is responsible for
tracking what descriptors are associated with a frame. When the DMA
engine sets the DONE flag in the final descriptor of a frame, the driver must
be able to determine what other descriptors belong to the same frame and
thus also have been consumed.
PRELIMINARY
The DMA Rx logic (the DRU block) manages descriptor of each packets. Words 0–11 are
Rx descriptors and transfers the incoming valid for the last descriptor of an aggregate or
frame data and status to the host through the last descriptor of a stand-alone packet.
AHB bus. Additional validity qualifiers are described
Words 0, and 2 are valid for all descriptors. individually. See Table 3-6.
Words 0, 2, and 11 is valid for the last
Table 3-6. DMA Rx Descriptor Format for Words 0–11
0 31:16 atheros_id The unique Atheros identifier of 0x168C is used to visually identify the start
of the descriptor.
15 desc_tx_rx Indicates whether the descriptor is a Tx or Rx descriptor. The value should be
set to 1 indicating transmit.
14 desc_ctrl Indicates whether the descriptor is a control or status descriptor. The value
_stat should be set to 1 indicating status descriptor.
13:9 RES Reserved
8 rx_priority 0 Low priority queue
1 High priority queue
7:0 desc_length Descriptor length. Indicates the number of Dwords in this descriptor. The
value should be set to 0x9 (9 Dwords).
1 31:24 rx_rate Rx rate indication. Indicates the rate at which this frame was transmitted
from the source. Encodings match those used for the TX_RATE*' field in
word 5 of the Tx descriptor. Valid only if the FRAME_RX_OK flag is set or if
the FRAME_RX_OK flag is clear and the PHY_ERROR flag is clear.
23:16 rssi_ant02 Received signal strength indicator of control channel chain 2.
22 hw_upload Indicates the data carried by current descriptor is that HW upload location.
_data The upload data is valid only when the field HW_UPLOAD_DATA_VALID
at RXS 4 bit [7] is set. See RXS 11 bit [26:25] HW_UPLOAD_DATA_TYPE to
know which data type is uploaded. Valid for all descriptors.
21:14 num_delim Number of zero length pad delimiters after current packet. This field does
not include the start delimiter which is required between each packet in an
aggregate. This field is only valid for aggregate packets except for the last
packet of an aggregate.
13 RES Reserved
12 more More descriptors in this frame flag. If set, then this is not the final descriptor
of the frame. If clear, then this descriptor is the final one of the frame. Valid
for all descriptors.
11:0 data_len Received data length. Specifies the length, in bytes, of the data actually
received into the data buffer associated with this descriptor. The actual
received data length will be between zero and the total size of the data buffer,
as specified originally in this field (see the description for the BUF_LEN
field). Valid for all descriptors.

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PRELIMINARY

The Tx descriptor format for words 15 through

Table 3-4. DMA Tx Descriptor Format for Words 15–22 (continued)

The Tx descriptor status format for words 0

Table 3-5. Tx Descriptor Status Format: Words 0–8

Table 3-5. Tx Descriptor Status Format: Words 0–8

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