Infineon IRS2461S DataSheet v01 00 En
Infineon IRS2461S DataSheet v01 00 En
Infineon IRS2461S DataSheet v01 00 En
IRS2461S
400V Class D Audio Amplifier Controller
Features
Single channel integrated analog input Class D audio amplifier driver
400V high voltage gate driver stage
Differential or single-ended input
Versatile protection control enabling latched, non-latched, or host controlled shutdown function
Programmable over current protection
Programmable dead-time generation
External thermal sensor input
Click noise reduction
Under voltage protection
High noise immunity
Product summary
Product feature Key specification
Topology Half-Bridge/Full-Bridge
VOFFSET (max) +/- 200 V
IO+ & IO- (typical) 0.5 A & 0.6 A
Selectable deadtime 165/225/280/340 ns
DC offset <18 mV
OC protection delay 500 ns (max)
Shutdown propagation delay 250 ns (max)
Error amplifier open loop gain >60 dB
Potential applications
High voltage high power Class D audio amplifier
High voltage high power PWM amplifier
Product validation
Qualified for industrial applications according to the relevant JEDEC47/20/22
Ordering information
Base Part Number Package Type Standard Pack
Form and Quantity
IRS2461S 20 Lead SOICWB Tape and Reel 1000
Datasheet Please read the Important Notice and Warnings at the end of this document 2.3
www.infineon.com 1 of 20 2019-05-03
400V Class D Audio Amplifier Controller
Description
Description
The IRS2461S integrates high voltage, high performance Class D audio amplifier drivers with PWM modulator
and protections. In conjunction with external MOSFET, the IRS2461S forms a single channel Class D audio
amplifier. The IRS2461S is designed with floating analog inputs and protection control interface pins
convenient for half bridge applications. High and low side MOSFETs are protected from over current conditions
by a programmable over current protection. Essential elements of PWM modulator section allow flexible
system design. The IRS2461S is a lead-free, ROHS compliant.
U1 IRS2461 R1
C1
-5V
R2
+5V
AGND
C2 VCC
IN+ R8
C5 PTC1
C3
IN- -B
C4 C7 R14 Q1
COMP
R3
R9 R11
R4 U2 GATE BUFF
L1
D1 R13
OUTPU T
C8 R15 Q2 C10
R12 C9
C6
U3 GATE BUFF R16
D3 PGND
R5 R7 R10
R6 D2
+B
Features ........................................................................................................................................ 1
Product summary ........................................................................................................................... 1
Potential applications ..................................................................................................................... 1
Product validation .......................................................................................................................... 1
Qualified for industrial applications according to the relevant JEDEC47/20/22 ...................................... 1
Ordering information ...................................................................................................................... 1
Description .................................................................................................................................... 2
Table of contents ............................................................................................................................ 3
1 Pin configuration and functionality .......................................................................................... 4
2 Functional block diagram........................................................................................................ 5
3 Qualification Information........................................................................................................ 6
4 Characteristics....................................................................................................................... 7
4.1 Package Characteristic............................................................................................................................ 7
4.2 Absolute Maximum Ratings .................................................................................................................... 8
4.3 Operating Conditions .............................................................................................................................. 9
4.4 Electrical Characteristics ...................................................................................................................... 10
4.5 Waveform definitions ............................................................................................................................ 13
5 Package dimensions .............................................................................................................. 16
6 Marking................................................................................................................................ 17
Revision history............................................................................................................................. 18
VSS 1 20 NC
VAA 2 19 DT
GND 3 18 OTP
IN+ 4 17 VCC
IN- 5 16 COM
COMP 6 15 LO
CSD 7 14 CSL
NC 8 13 NC
CSH 9 12 VS
VB 10 11 HO
DT
OCH CSH
COMP
VB
IN-
OTA
GD
PWM DT HO
IN+ VS
UV
GND DETECT OCL SCL
VCC
VSS UVCC
PROT
CTRL
GD
VAA LO
COM
CSD
OTP
3 Qualification Information
Qualification Level Industrial
MSL3
Moisture Sensitivity Level
(per IPC/JEDEC J-STD-020C)
Class B
Machine Model
(per JEDEC standard EIA/JESD22-A115)
Class 1B
ESD Human Body Model
(per EIA/JEDEC standard JESD22-A114)
Class 0B
Charge Device Model
(per EIA/JEDEC standard JESD22-C101)
Class I, Level A
IC Latch-Up Test
(per JESD78)
RoHS Compliant Yes
4 Characteristics
VGND Floating input supply ground voltage VSS -0.3 VAA +0.3 V
Unit
Symbol Definition Min Max
s
VB High side floating supply absolute voltage VSn +10 VSn +14 V
VS High side floating supply offset voltage (Note1) 400 V
VAA Floating input supply voltage VSS + 4.5 VSS + 15 V
IAAZ Floating input positive supply zener clamp current 1 11 mA
VSS Floating input supply absolute voltage 0 200 V
VHO High side floating output voltage Vs VB V
VCC Low side fixed supply voltage 10 14 V
VLO Low side output voltage 0 VCC V
(Note2) (Note2)
VGND GND pin input voltage VSS V AA V
(Note2) (Note2)
VIN- Inverting input voltage VGND -0.5 VGND +0.5 V
VCSD CSD pin input voltage VSS VAA V
VCOMP COMP pin input voltage VSS VAA V
(Note 1) Logic operational for Vs equal to –5V to +400V. Logic state held for Vs equal to –5V to –VBS.
(Note 4) The CLK input frequency needs to be within +/-10% of self-oscillating frequency in order to synchronize PWM in a typical self-
oscillating application.
(Note 4) The CLK input frequency needs to be within +/-10% of self-oscillating frequency in order to synchronize PWM in a typical self-
oscillating application.
Symbol Test
Definition Min Typ Max Units
Conditions
Low Side Supply
UVCC+ Vcc supply UVLO positive 8.4 8.9 9.4 V
threshold
UVCC- Vcc supply UVLO negative 8.2 8.7 9.2 V
threshold
UVCCHYS UVCC hysteresis - 0.2 - V
IQCC Low side quiescent current - - 6 mA VDT=VCC
Low side zener diode clamp
VCLAMPL 14.7 15.3 16.2 V ICC=5mA
voltage
High Side Floating Supply
High side well UVLO positive
UVBS+ 8.0 8.5 9.0 V
threshold
High side well UVLO negative
UVBS- 7.8 8.3 8.8 V
threshold
UVBSHYS UVBS hysteresis - 0.2 - V
IQBS High side quiescent current - - 1 mA
High to Low side leakage
ILKH - - 50 µA VB=VS =400V
current
High side zener diode clamp
VCLAMPH 14.7 15.3 16.2 V IBS=5mA
voltage
Floating Input Supply
UVAA+ VAA floating supply UVLO 8.2 8.7 9.2 V GND pin floating
positive threshold from VSS
UVAA- VAA floating supply UVLO 7.7 8.2 8.7 V GND pin floating
negative threshold from VSS
UVAAHYS UVAA hysteresis - 0.5 - V GND pin floating
IQAASD Floating Input positive - 2 3 mA VCSD =VGND
quiescent supply current in
shutdown mode
IQAA0 Floating Input positive - 4 6 mA VIN- = VSS+5.2V
quiescent supply current,
positive input
IQAA1 Floating Input positive - 3 4 mA VIN- = VSS+4.8V
quiescent supply current,
negative input
IQAAST Floating Input positive - 3 4 mA VCSD = VGND+2.5V
quiescent supply current in
start-up mode
ILKM Floating input side to Low side - - 50 µA VAA=VSS=VGND=
leakage current 100V
VCLAMPM Floating supply zener diode IAA=5mA,
14.7 15.3 16.2 V
clamp voltage VCSD =VGND
Symbol Test
Definition Min Typ Max Units
Conditions
Audio Input (GND=0V, VAA=5V, VSS=-5V, COM =VCC =-5V, VS=CSH=-5V, DT=-5V)
VOs Input offset voltage -18 0 18 mV
IBIN Input bias current - - 40 nA
GBW Small signal bandwidth - 5 - MHz CCOMPn=2.2nF,
Note 1 Rf=10k, Note 1
VCOMP OTA Output voltage VAA-1 - VSS+1 V
gm OTA transconductance 80 200 260 mS VIN-=10mV
GV OTA gain 60 - - dB
VNrms OTA input noise voltage - 250 - mVrms BW=20kHz,
Resolution
BW=22Hz
Fig.8
SR Slew rate - ±5 - V/us CCOMP=2.2nF
CMRR Common-mode rejection ratio - 60 - dB
PSRR Supply voltage rejection ratio - 65 - dB
PWM Comparator
VthPWM PWM comparator threshold in - (VAA – - V
COMP VSS)/2
fOTA COMP pin star-up local MHz VCSD =VGND+2.5V
- 0.6 -
oscillation frequency
Protection
VthOCL Low side OC threshold in VCSL 1.1 1.2 1.3 V
VthOCH High side OC threshold in VCSH 1.1+ Vs 1.2+ Vs 1.3+ Vs V Vs=400V
CSD pin shutdown release 0.68xVAA-
Vth1 0.52xVAA-GND 0.84xVAA-GND V
threshold GND
0.30xVAA-
Vth2 CSD pin self reset threshold 0.26xVAA-GND 0.34xVAA-GND V
GND
ICSD+ CSD pin discharge current 70 100 130 µA VCSD = VGND + 2.4V
ICSD- CSD pin charge current 70 100 130 µA VCSD = VGND + 2.4V
tSSD Shutdown propagation delay - ns
from VCSD < VGND+ Vth1 to 140 250
Shutdown
tOCH Propagation delay time from - ns
400 500
VCSHn > VthOCHn to Shutdown
tOCL Propagation delay time from - ns
270 350
Vsn> VthOCL to Shutdown
VOTP OTP pin input threshold - 2.8 - V
IOTP OTP bias sourcing current - 0.6 - mA OTP=0V
Symbol
Definition Min Typ Max Units Test Conditions
Gate Driver
Output high short circuit current - 0.5 - A Vo=0V, PW<10µS,
Io+
(Source) Note 1
Output low short circuit current - 0.6 - A Vo=12V, PW<10µS,
Io-
(Sink) Note 1
Low level output voltage - - 0.1 V Io=0A
VOL
LO – COM, HO - VS
High level output voltage - - 1.4 V
VOH
VCC – LO, VB - HO
High and low side turn-on
Ton0 - 505 - ns
propagation delay
VDT = COM
High and low side turn-off
Toff0 270 340 410 ns
propagation delay
Toffskw Toff skew, Toffhon – Tofflon -30 0 30 ns
tr Turn-on rise time - 12 25 ns
tf Turn-off fall time - 12 25 ns
Deadtime: LOn turn-off to HOn turn-
VDT>VDT1, VDTM=COM
DT1 on (DTLO-HO) & HOn turn-off to LnO 130 165 200 ns
turn-on (DTHO-LO)
Deadtime: LOn turn-off to HOn turn-
VDT1>VDT> VDT2,
DT2 on (DTLO-HO) & HOn turn-off to LOn 180 225 270 ns
VDTM=COM
turn-on (DTHO-LO)
Deadtime: LOn turn-off to HOn turn- VDT2>VDT> VDT3,
DT3 on (DTLO-HO) & HOn turn-off to LOn 225 280 335 ns VDTM=COM
turn-on (DTHO-LO)
Deadtime: LOn turn-off to HOn turn-
VDT<VDT3, VDTM=COM
DT4 on (DTLO-HO) & HO turn-off to LOn 275 340 405 ns
turn-on (DTHO-LO)VDT= VDT4
VDT1 DT mode select threshold 1 0.51xVcc 0.57xVcc 0.63xVcc V
VDT2 DT mode select threshold 2 0.32xVcc 0.36xVcc 0.40xVcc V VDTM=COM
VDT3 DT mode select threshold 3 0.21xVcc 0.23xVcc 0.25xVcc V
ton(L)
toff(L)
toff(H)
ton(H)
90%
LO
10%
DTHO-LO DTLO-HO
HO 90%
10%
Vth1
CSD
tSSD
90% 90%
HO/LO
10% 10%
100% PSD %
VthOCL
VS
90%
LO
tOCL
VthOCH
CSH
VS
90%
HO
tOCH
DUT
10 Ω VAA
5V GND
10 µF
3.3 µF 100 Ω OTA
IN-
47 kΩ COMP
5V
2nF
10 µF
10 Ω VSS
100 Ω
10 Ω
10 µF
100 kΩ LT1028 100 Ω
` NOISE OUT
47 µF
GND
10 µF 100 Ω 10 kΩ
10 Ω
10 nF
5 Package dimensions
6 Marking
RevisionHistory
IRS2461S
Revision:2019-06-04,Rev.2.3
Previous Revision
Revision Date Subjects (major changes since last revision)
1.2 2018-06-26 unified part name to IRS2461S
2.3 2019-06-04 added ton(typ)
Trademarks
Allreferencedproductorservicenamesandtrademarksarethepropertyoftheirrespectiveowners.
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©2019InfineonTechnologiesAG
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18 Rev.2.3,2019-06-04