tps65131-q1

TPS65131-Q1
SLVSBB2F – MAY 2012 – REVISED AUGUST 2024
TPS65131-Q1 Positive- and Negative-Output DC-DC Converter

1 Features 3 Description
• Qualified for automotive applications The TPS65131-Q1 device is dual-output dc-dc
• AEC-Q100 test guidance with the following results: converter generating a positive output voltage up to
– Device temperature grade 2: –40°C to 105°C 15V and a negative output voltage down to –15V
ambient operating temperature range with output currents of typically 200mA, depending
– Electrical characteristics tested over –40°C to on input-voltage to output-voltage ratio. With a total
125°C junction temperature range efficiency up to 85%, the device is ideal for portable
– Device HBM ESD classification level H1C battery-powered equipment. The input-voltage range
– Device CDM ESD classification level C4B of 2.7V to 5.5V allows, for example, 3.3V and 5V rails
• Dual adjustable output voltages up to 15V and to power the TPS65131-Q1 device. The TPS65131-
down to –15V Q1 device comes in a QFN-24 package with thermal
• 2A typical switch-current limit for boost and pad and wettable flanks. Requiring few and small
inverter main switches external components, the overall solution size can be
• High conversion efficiency small.
– Up to 91% at positive output rail The converter operates with a fixed-frequency PWM
– Up to 85% at negative output rail control topology and, with power-save mode enabled,
– Power-save mode at low load uses a pulse-skipping mode at light load currents. In
• Independent enable inputs for power-up and operation, the typical overall device quiescent current
power-down Sequencing is only 500µA. In shutdown, the device draws typically
• Control output for external PFET to support 0.2µA. Independent enable pins allow power-up and
complete supply Disconnect When Shut Down power-down sequencing for both outputs. The device
• 2.7V to 5.5V input-voltage range has an internal current limit, overvoltage protection,
• Minimum 1.25MHz fixed-frequency PWM and a thermal shutdown for highest reliability under
operation fault conditions.
• Thermal shutdown
• Overvoltage protection on both outputs The TPS65131-Q1 device is qualified for automotive
• 0.2µA typical shutdown current applications, according to AEC-Q100 temperature
• Small 4mm × 4mm QFN-24 package (RGE) with grade 2. The electrical characteristics are tested
wettable flanks over –40°C to 125°C device junction temperature.
This, combined with lowest shutdown currents, small
2 Applications solution size, package with thermal pad, plus good
efficiency and protection features, targets automotive
• Small-to-medium size OLED displays
and industrial applications.
• (TFT) LCD, CCD bias supply
(1)
Package Information
PART NUMBER PACKAGE BODY SIZE (NOM)
TPS65131-Q1 VQFN (24) 4mm × 4mm
(1) For all available packages, see the orderable addendum.

L1
VI Q1 4.7 µH D1 VPOS
C1 C4
4.7 µF R1 22 µF
VPOS C9
INP
FBP
BSW
VREF R2
C8
TPS65131-Q1 R4 220 nF
FBN
INN
R3 C10
VIN VNEG
R7
100 Ω
ENP VNEG
C2 C3
4.7 µF 100 nF PSP OUTN
ENN CN D2
L2 C5
PSN CP C6 C7 4.7 µH 22 µF
10nF 4.7nF
AGND PGND
Copyright © 2017, Texas Instruments Incorporated
Application Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65131-Q1
SLVSBB2F – MAY 2012 – REVISED AUGUST 2024 www.ti.com
Table of Contents
1 Features............................................................................1 7.4 Device Functional Modes............................................9
2 Applications..................................................................... 1 8 Application and Implementation.................................. 10
3 Description.......................................................................1 8.1 Application Information............................................. 10
4 Device Comparison......................................................... 2 8.2 Typical Applications.................................................. 10
5 Pin Configuration and Functions...................................3 8.3 Power Supply Recommendations.............................20
6 Specifications.................................................................. 4 8.4 Layout....................................................................... 21
6.1 Absolute Maximum Ratings........................................ 4 9 Device and Documentation Support............................22
6.2 ESD Ratings............................................................... 4 9.1 Receiving Notification of Documentation Updates....22
6.3 Recommended Operating Conditions.........................4 9.2 Support Resources................................................... 22
6.4 Thermal Information....................................................5 9.3 Trademarks............................................................... 22
6.5 Electrical Characteristics.............................................5 9.4 Electrostatic Discharge Caution................................22
6.6 Switching Characteristics............................................6 9.5 Glossary....................................................................22
6.7 Typical Characteristics................................................ 6 10 Revision History.......................................................... 22
7 Detailed Description........................................................7 11 Mechanical, Packaging, and Orderable
7.1 Overview..................................................................... 7 Information.................................................................... 24
7.2 Functional Block Diagram........................................... 7 11.1 Mechanical Data..................................................... 25
7.3 Feature Description.....................................................8 11.2 Tape and Reel Information...................................... 31
4 Device Comparison
Table 4-1. Device Comparison Table
Part Number Package Wettable Flanks
TPS65131TRGERQ1 VQFN (24) No
TPS65131WTRGERQ1 VQFN (24) Yes
2 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated
Product Folder Links: TPS65131-Q1

TPS65131-Q1
www.ti.com SLVSBB2F – MAY 2012 – REVISED AUGUST 2024
5 Pin Configuration and Functions
AGND
AGND
VPOS
VPOS
FBP
FBP
INP
INP
NC
NC
CP
CP
19 20 21 22 23 24 24 23 22 21 20 19
CN 18 1 INP INP 1 18 CN
VREF 17 2 PGND PGND 2 17 VREF
FBN 16 3 PGND PGND 3 16 FBN
Thermal Pad Thermal Pad
VNEG 15 4 VIN VIN 4 15 VNEG
OUTN 14 5 INN INN 5 14 OUTN
OUTN 13 6 INN INN 6 13 OUTN
12 11 10 9 8 7 7 8 9 10 11 12
NC
PSN
PSP
BSW
BSW
PSP
PSN
NC
ENN
ENN
ENP
ENP
NC – No internal Connection
Figure 5-1. 24-pin VQFN Bottom View Figure 5-2. 24-pin VQFN Top View
Table 5-1. Pin Functions

PIN
I/O DESCRIPTION
NAME NO.
AGND 19 — Analog ground pin
BSW 7 O Gate-control pin for external battery switch. This pin goes low when ENP is set high.
CN 18 I/O Compensation pin for inverting converter control
CP 21 I/O Compensation pin for boost converter control
ENN 10 I Enable pin for the negative-output voltage (0V: disabled, VIN: enabled)
ENP 8 I Enable pin for the positive-output voltage (0V: disabled, VIN: enabled)
FBN 16 I Feedback pin for the negative-output voltage divider
FBP 22 I Feedback pin for the positive-output voltage divider
INN 5, 6 O Inverting converter switch pin
INP 1, 24 O Boost converter switch pin
NC(1) 12, 20 — Not connected
OUTN 13, 14 I/O Inverting converter switch output
PGND 2, 3 — Power ground pin
PSN 11 I Power-save mode enable for inverter stage (0V: disabled, VIN: enabled)
PSP 9 I Power-save mode enable for boost converter stage (0V: disabled, VIN: enabled)
VIN 4 I Control supply input
VNEG 15 I Negative-output voltage-sense input
VPOS 23 I Positive-output voltage-sense input
Reference output voltage. Bypass this pin with a 220nF capacitor to ground. Connect the lower resistor of the
VREF 17 O
negative-output voltage divider to this pin.
Thermal pad Thermal pad for thermal performance, connect to PGND
(1) NC - No internal connection
Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3

TPS65131-Q1
6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature, unless otherwise noted
VALUE
UNIT
MIN MAX
Input voltage range at pins VIN, INN (2) –0.3 6 V
Voltage at pin VPOS (2) –0.3 17 V
Voltage at pin VNEG (2) –17 V(VIN) + 0.3 V
Voltage at pins ENN, ENP, FBP, FBN, CN, CP, PSP, PSN, BSW (2) –0.3 V(VIN) + 0.3 V
Input voltage at pin INP (2) –0.3 17 V
Differential voltage between pins OUTN to INN (2) –0.3 24 V
Thermal pad(2) –0.3 0.3 V
TJ Operating junction temperature –40 150 °C
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to the network ground pin, unless otherwise noted.
6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per AEC Q100-002(1) ±1000 V
V(ESD) Electrostatic discharge
Charged device model (CDM), per AEC Q100-011 ±750 V
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions

over operating free-air temperature, unless otherwise noted
MIN MAX UNIT
VI , V(VIN), Application input voltage range, input voltage range at VIN and INN pins 2.7 5.5 V
V(INN)
VPOS Adjustable output voltage range for the boost converter VI + 0.5 15 V
VNEG Adjustable output voltage range for the inverting converter –15 –2 V
V(ENN), Enable signals voltage 0 5.5 V
V(ENP)
V(PSN), Power-save mode enable signals voltage 0 5.5 V
V(PSP)
TA Operating free-air temperature range(1) –40 105 °C
TJ Operating junction temperature range –40 125 °C
(1) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature
may require derating. See Thermal Information for details.

TPS65131-Q1
6.4 Thermal Information

TPS65131-Q1
THERMAL METRIC RGE PACKAGE UNIT
24 PINS
RθJA Junction-to-ambient thermal resistance 34.1 °C/W
RθJCtop Junction-to-case (top) thermal resistance 36.8 °C/W
RθJB Junction-to-board thermal resistance 12.2 °C/W
ψJT Junction-to-top characterization parameter 0.4 °C/W
ψJB Junction-to-board characterization parameter 12.3 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance 2.8 °C/W
6.5 Electrical Characteristics

This specification applies over the full recommended input voltage range VI = 2.7V to 5.5V and over the temperature range
TJ = –40°C to 125°C unless otherwise noted. Typical values apply for VI = 3.6V and TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC-DC STAGE (V(VPOS), V(VNEG))
Vref Reference voltage Iref = 10µA 1.2 1.213 1.225 V
I(FBP) Positive feedback input bias current V(FBP) = Vref 50 nA
I(FBN) Negative feedback input bias current V(FBN) = 0.1Vref 50 nA
V(FBP) Positive feedback regulation voltage 1.189 1.213 1.237 V
V(FBN) Negative feedback regulation voltage –0.024 0 0.024 V
Total output dc accuracy 3%
V(VIN) = 3.6V 440 620
rDS(on)(N) Inverter switch on-resistance mΩ
V(VIN) = 5V 330 530
I(L IM-N) Inverter switch current limit V(VIN) = 3.6V 1700 1950 2200 mA
V(POS) = 5V 230 390
rDS(on)(P) Boost switch on-resistance mΩ
V(POS) = 10V 170 230
I(LIM-P) Boost switch current limit V(VIN) = 3.6V, V(POS) = 8V 1700 1950 2250 mA
CONTROL STAGE
High-level input voltage, ENP, ENN,
VIH 1.4 V
PSP, PSN
Low-level input voltage, ENP, ENN,
VIL 0.4 V
PSP, PSN
ENP, ENN, PSP, PSN connected
Input current, ENP, ENN, PSP, PSN 0.01 0.1 µA
to GND or VIN
R(BSW) Output resistance 27 kΩ
VIN 300 500
V(VIN) = 3.6V, I(POS) = I(NEG) = 0,
IQ Quiescent current VPOS ENP = ENN = PSP = PSN = V(VIN), 100 120 µA
V(POS) = 8V, V(NEG) = –5V
VNEG 100 120
ENN = ENP = LOW, TA = –40°C to
ISD Shutdown supply current 0.2 1.5 µA
85°C
V(UVLO) Undervoltage lockout threshold 2.1 2.35 2.7 V
T(TS) Thermal shutdown 150 °C
T(TS-HYS) Thermal shutdown hysteresis Junction temperature decreasing 5 °C

TPS65131-Q1
6.6 Switching Characteristics

The specification applies over the full recommended input voltage range VI = 2.7V to 5.5V and over the
temperature range TJ = –40°C to 125°C unless otherwise noted. Typical values apply for VI = 3.6V and TJ =
25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FREQUENCY
f Oscillator frequency 1150 1380 1500 kHz
DUTY CYCLE
D(MAX-P) Maximum-duty-cycle, boost converter 87.5%
Maximum-duty-cycle, inverting
D(MAX-N) 87.5%
converter
D(MIN-P) Minimum-duty-cycle, boost converter 12.5%
D(MIN-N) Minimum-duty-cycle, inverting converter 12.5%
6.7 Typical Characteristics

At 25°C, unless otherwise noted.
0.9 0.6
V POS = 10.5 V V NEG = -10 V
0.8 V POS = 15 V V NEG = -15 V
0.5
0.7
M a x O u tp u t C u rre n t (A )
M a x O u tp u t C u rre n t (A )
0.6 0.4
0.5
0.3
0.4
0.3 0.2
0.2
0.1
0.1
0 0
2.5 3 3.5 4 4.5 5 5.5 2.5 3 3.5 4 4.5 5 5.5
Input Voltage (V) Input Voltage (V)
D001 D002
Figure 6-1. Boost Converter (VPOS) Maximum Figure 6-2. Inverting Converter (VPOS) Output
Output Current vs Input Voltage Current vs Input Voltage
1.2 340
VI = 5.5 V
330
VI = 3.3 V
1
320
Q u ie sce n t C u rre n t ( P A )
Shutdown Current (PA)
310
0.8
300
0.6 290
280
0.4
270
260
0.2
250
0 240
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Temperature (qC) D003
Temperature (qC)
D004
Figure 6-3. Shutdown Current (Into VIN and INN) VI = 3.6V

Over Input Voltage Figure 6-4. Quiescent Current (Into VIN and INN)
Over Input Voltage

TPS65131-Q1
7 Detailed Description
7.1 Overview
The TPS65131-Q1 is a dual-output dc-dc converter that generates two adjustable output voltages. One output
voltage is positive (boost converter), the other is negative (inverting converter). The positive output is adjustable
up to 15V, the negative output is adjustable down to –15V. The device operates with an input voltage range
of 2.7V to 5.5V. Both converters (positive and negative output) work independently of each other. They share
a common clock and a common voltage reference. A fixed-frequency, pulse-width-modulated (PWM) regulator
controls both outputs separately. In general, each converter operates in continuous-conduction mode (CCM). To
improve efficiency at light loads, the converters can operate in discontinuous-conduction mode (DCM). When the
power-save mode is enabled, the converters automatically transition between CCM and DCM operation: As the
load current decreases, the converter enters DCM mode. Power-save mode is individually configurable for both
outputs. The transition as a function of the load current works independently for each converter.
7.2 Functional Block Diagram
INP VPOS
VIN
VPOS
VIN
Gate
Control
VIN
ENP
PSP
Boost Converter Control
CP + FBP
-
VREF
BSW
+
VIN Temperature VIN -
Oscillator
Control
Vref
ENN
VNEG
PSN Inverting Converter Control
CN - FBN
INN
+
VIN
Gate
Control
INN OUTN
AGND PGND

TPS65131-Q1
7.3 Feature Description

7.3.1 Power Conversion
Both converters operate in a fixed-frequency, PWM control scheme. The on-time of the internal switches varies
depending on the input-to-output voltage ratio and the load. During the on-time, the inductors connected to the
converters charge with current. In the remaining time, the off-time with a time period set by the fixed operating
frequency, the inductors discharge into the output capacitors through the rectifier diodes. Usually at higher loads,
the inductor currents are continuous. At lighter loads, the boost converter uses an additional internal switch
to allow current to flow back to the input. This avoids inductor current becoming discontinuous in the boost
converter. At the inverting converter, during light loads, the inductor current can become discontinuous. In this
case, the control circuit of the inverting controller output automatically takes care of these changing conditions to
operate always with an optimum control setup.
7.3.2 Control
The controller circuits of both converters employ a fixed-frequency, multiple-feedforward controller topology.
These circuits monitor input voltage, output voltage, and voltage drop across the switches. Changes in the
operating conditions of the converters directly affect the duty cycle and must not take the indirect and slow way
through the output voltage-control loops. A self-learning control corrects measurement errors in this feedforward
system. An external capacitor damps the output to avoid output-voltage steps due to output changes of this
self-learning control system.
The voltage loops, determined by the error amplifiers, must only handle small signal errors. The error amplifiers
feature internal compensation. Their inputs are the feedback voltages on the FBP and FBN pins. The device
uses a comparison of these voltages with the internal reference voltage to generate an accurate and stable
output voltage.
7.3.3 Output Rails Enable or Disable
Both converters can be enabled or disabled individually. Applying a logic HIGH signal at the enable pins (ENP
for the boost converter, ENN for the inverting converter) enables the corresponding output. After enabling,
internal circuitry, necessary to operate the specific converter, then turns on, followed by the Soft Start .
Applying a low signal at the enable ENP or ENN pin shuts down the corresponding converter. When both enable
pins are low, the device enters shutdown mode, where all internal circuitry turns off. The device now consumes
shutdown current flowing into the VIN pin. The output loads of the converters can be disconnected from the
input, see Load Disconnect .
7.3.4 Load Disconnect
The device supports completely disconnecting the load when the converters are disabled. For the inverting
converter, the device turns off the internal PMOS switch. If the inverting converter is turned off, no dc current
path remains which could discharge the battery or supply.
This is different for the boost converter. The external rectifying diode, together with the boost inductor, form a
dc current path which could discharge the battery or supply if any load connects to the output. The device has
no internal switch to prevent current from flowing. For this reason, the device offers a PMOS gate control output
(BSW) to enable and disable a PMOS switch in this dc current path, ideally directly between the boost inductor
and battery. To be able to fully disconnect the battery, the forward direction of the parasitic backgate diode of this
switch must point to the battery or supply. The external PMOS switch, which connects to BSW, turns on when
the boost converter is enabled and turns off when the boost converter is disabled.

TPS65131-Q1
7.3.5 Soft Start

Both converters have implemented soft-start functions. When each converter is enabled, the implemented switch
current limit ramps up slowly to its nominal programmed value in typically 1ms. The device includes this function
to limit the input current during start-up to avoid high peak input currents, which could interfere with other
systems connected to the same battery or supply.
If the application includes the Load Disconnect PMOS switch, a current flows from the input to the output of the
boost converter at the moment the PMOS switch becomes conducting.
7.3.6 Overvoltage Protection
Both built-in converters (boost and inverter) have implemented individual overvoltage protection. If the feedback
voltage under normal operation exceeds the nominal value by typically 5%, the corresponding converter shuts
down immediately to protect any connected circuitry from possible damage.
7.3.7 Undervoltage Lockout
An undervoltage lockout prevents the device from starting up and operating if the supply voltage at the VIN
pin is lower than the undervoltage lockout threshold. For this case, the device automatically shuts down both
converters when the supply voltage at VIN falls below this threshold. Nevertheless, parts of the control circuits
remain active, which is different than device shutdown using EN inputs. The device includes the undervoltage
lockout function to prevent device malfunction.
7.3.8 Overtemperature Shutdown
The device automatically shuts down both converters if the implemented internal temperature sensor detects
a chip temperature above the thermal shutdown temperature. It automatically starts operating again when
the chip temperature falls below this threshold plus hysteresis threshold. The built-in hysteresis avoids
undefined operation caused by ringing from shutdown and prevents operating at a temperature close to the
overtemperature shutdown threshold.
7.4 Device Functional Modes
7.4.1 Power-Save Mode
The power-save mode can improve efficiency at light loads. In power-save mode, the converter only operates
when the output voltage falls below an device internally set threshold voltage. The converter ramps up the output
voltage with one or several operating pulses and goes again into power-save mode once the inductor current
becomes discontinuous.
The PSN and PSP logic level selects between power-save mode and continuous-conduction mode. If the
specific pins (PSP for the boost converter, PSN for the inverting converter) are HIGH, the power-save mode for
the corresponding converter operates at light loads. Similary, a LOW on the PSP pin or PSN pin disables the
power-save mode for the corresponding converter.

TPS65131-Q1
8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information

The TPS656131-Q1 boost converter output voltage, VPOS, and the inverting converter output voltage, VNEG,
require external components to set the required output voltages. The valid output voltage ranges are as shown
in Recommended Operating Conditions ). The passages below show typical application examples with different
output voltage settings and guidance for external component choices.
8.2 Typical Applications
8.2.1 TPS65131-Q1 With VPOS = 10.5V, VNEG = –10V
L1
VI Q1 4.7 µH D1 VPOS
C1 C4
4.7 µF R1 22 µF
VPOS C9
INP
FBP
BSW
VREF R2
C8
TPS65131-Q1 R4 220 nF
FBN
INN
R3 C10
VIN VNEG
R7
100 Ω
ENP VNEG
C2 C3
4.7 µF 100 nF PSP OUTN
ENN CN D2
L2 C5
PSN CP C6 C7 4.7 µH 22 µF
10nF 4.7nF
AGND PGND
Figure 8-1. Typical Application Schematic With VPOS = 10.5V, VNEG = –10V

TPS65131-Q1
8.2.2 Design Requirements

The design procedure for this setup is similar to the first example, see Detailed Design Procedure . Change
the feedback dividers to set the output voltage, see Programming the Output Voltage . Further, choose the
feed-forward capacitors according to Feedforward Capacitors . Table 8-1 shows the components being changed.
See Figure 8-1.
Table 8-1. Design Parameters
Design Parameter Example Value
Input voltage range 2.7V to 5.5V
R1 = 1MΩ
Boost converter output
R2 = 130kΩ 10.5V
voltage, VPOS
C9 = 6.8pF
R3 = 1MΩ
Inverting converter
R4 = 121.2kΩ –10V
output voltage, VNEG
C10 = 7.5pF
In this example, the converters are operated with power-save mode both enabled and disabled (see Power-Save
Mode ).
8.2.3 Detailed Design Procedure
8.2.3.1 Programming the Output Voltage
8.2.3.1.1 Boost Converter
An external resistor divider adjusts the output voltage of the TPS65131-Q1 boost converter stage. Connect this
divider to the FBP pin. The typical value of the voltage at the FBP pin is the reference voltage, which is 1.213V.
The maximum recommended output voltage at the boost converter is 15V. To achieve appropriate accuracy,
the current through the feedback divider should be about 100 times higher than the current into the FBP pin.
Typical current into the FBP pin is 0.05µA, and the voltage across R2 is 1.213V. Based on those values, the
recommended value for R2 should be lower than 200kΩ in order to set the divider current at 5µA or higher.
Calculate the value of resistor R1, as a function of the needed output voltage (VPOS), with Equation 1:
§V ·
R1 R2 u ¨ POS 1¸
© Vref ¹ (1)
In this example, with R2 = 130kΩ, choose R1 = 1MΩ to set VPOS = 10.5V.

8.2.3.1.2 Inverting Converter
An external resistor divider adjusts the output voltage of the TPS65131-Q1 inverting converter stage. Connect
this divider to the FBN pin. Unlike the feedback divider at the boost converter, the reference point of the
feedback divider is not GND, but Vref. So the typical value of the voltage at the FBN pin is 0V. The minimum
recommended output voltage at the inverting converter is –15V. Feedback divider current considerations are
similar to the considerations for the boost converter. For the same reasons, the feedback divider current should
be in the range of 5µA or higher. The voltage across R4 is 1.213V. Based on those values, the recommended
value for R4 should be lower than 200kΩ in order to set the divider current at the required value.
Calculate the value of resistor R3, as a function of the needed output voltage (VNEG), with Equation 2:
§V ·
R3 R4 u ¨ NEG ¸
© Vref ¹ (2)
In this example, with R4 = 121.2kΩ, choose R3 = 1MΩ to set VNEG = –10V.

TPS65131-Q1
8.2.3.1.3 Inductor Selection

An inductive converter normally requires two main passive components to store energy during the conversion.
Therefore, each converter requires an inductor and a storage capacitor. To select the right inductor, it is
recommended to keep the possible peak inductor current below the current-limit threshold of the power switch
in the chosen configuration. For example, the current-limit threshold of the switch for the boost converter and
for the inverting converters is nominally 1950mA. The highest peak current through the switches and the
inductor depends on the output load (IPOS, INEG), the input voltage (VI), and the output voltages (VPOS, VNEG).
Use Equation 3 to estimate the peak inductor current in the boost converter, I(L-P). Equation 4 shows the
corresponding formula for the inverting converter, I(L-N).
VPOS
I(L P) u IPOS
VI u 0.64 (3)
VI VNEG
I(L N) u INEG
VI u 0.64 (4)
The second parameter for choosing the inductor is the desired current ripple in the inductor. Normally, it is
advisable to work with a ripple of less than 20% of the average inductor current. A smaller ripple reduces the
losses in the inductor, as well as output voltage ripple and EMI. But in the same way, output voltage regulation
gets slower, causing higher voltage changes during fast load changes. In addition, a larger inductor usually
increases the total system cost. Keep those parameters in mind and calculate the possible inductor value with
Equation 5 for the boost converter (L1) and Equation 6 for the inverting converter (L2).
VI u VPOS VI
L1
'I(L P) u f u VPOS (5)
VI u VNEG
L2
'I(L N) u f u VNEG VI (6)
The parameter f is the switching frequency. For the boost converter, ΔI(L-P) is the ripple current in the inductor,
that is, 20% of I(L-P). Accordingly, for the inverting converter, ΔI(L-N) is the ripple current in the inductor, that is,
20% of I(L-N). VI is the input voltage, which is 3.3V in this example. So, the calculated inductance value for the
boost inductor is 5.1µH and for the inverting converter inductor is 5.1µH. With these calculated values and the
calculated currents, it is possible to choose a suitable inductor.

TPS65131-Q1
In typical applications, the recommendation is to choose a 4.7µH inductor. The device is optimized to work with
inductance values between 3.3µH and 6.8µH. Nevertheless, operation with higher inductance values may be
possible in some applications. Perform detailed stability analysis in this case. Be aware of the possibility that
load transients and losses in the circuit can lead to higher currents than estimated in Equation 3 and Equation 4.
Also, the losses caused by magnetic hysteresis and conductor resistance are a major parameter for total circuit
efficiency.
The following table shows inductors from different suppliers used with the TPS65131-Q1 converter:
Table 8-2. List of Inductors
VENDOR(1) INDUCTOR SERIES
EPCOS B8246284-G4
7447789XXX
Wurth Elektronik
744031XXX
VLF3010
TDK
VLF4012
Cooper Electronics Technologies SD12
(1) See Section 9.3
8.2.3.2 Capacitor Selection

8.2.3.2.1 Input Capacitor
As a recommendation, choose an input capacitors of at least 4.7µF for the input of the boost converter (INP)
and accordingly for the input of the inverting converter (INN). This improves transient behavior of the regulators
and EMI behavior of the total power-supply circuit. Choose a ceramic capacitor or a tantalum capacitor. For the
use of a tantalum capcitor, an additonal, smaller ceramic capacitor (100nF) in parallel is required. Place the input
capacitor(s) close to the input pins.

TPS65131-Q1
8.2.3.2.2 Output Capacitors

One of the major parameters necessary to define the capacitance value of the output capacitor is the maximum
allowed output voltage ripple of the converter. Two parameters, which are the capacitance and the equivalent
series resitance (ESR), affect this ripple. It is possible to calculate the minimum capacitance needed for the
defined ripple, supposing that the ESR is zero. Use Equation 7 for the boost-converter output capacitor (C4min)
and Equation 8 for the inverting-converter output capacitor (C5min).
IPOS u VPOS VI
C4min
f u 'VPOS u VPOS (7)
INEG u VNEG
C5min
f u 'VNEG u VNEG VI (8)
The parameter f is the switching frequency. ΔVPOS and ΔVNEG are the maximum allowed ripple voltages for each
converter.
Choosing a ripple voltage in the range of 10mV requires a minimum capacitance of 12µF. The total ripple is
larger due to the ESR of the output capacitor. Use Equation 9 for the boost converter and Equation 10 for the
inverting converter to calculate this additional ripple component.
'V(ESR P) IPOS u R(ESR C4) (9)
'V(ESR N) INEG u R(ESR C5) (10)
In this example, an additional ripple of 2mV is the result of using a typical ceramic capacitor with an ESR in the
10mΩ range. The total ripple is the sum of the ripple caused by the capacitance and the ripple caused by the
ESR of the capacitor. In this example, the total ripple is 10mV.
Load transients can create additional ripple. When the load current increases rapidly, the output capacitor must
provide the additional current until the inductor current increases by the control loop which sets a higher on-time
(duty cycle) of the main switch. The higher duty cycle results in longer inductor charging periods. The inductance
itself also limits the rate of increase of the inductor current. When the load current decreases rapidly, the output
capacitor must store the excess energy (stored in the inductor) until the regulator has decreased the inductor
current by reducing the duty cycle. The recommendation is to use higher capacitance values, as the foregoing
calculations show.

TPS65131-Q1
8.2.3.3 Rectifier Diode Selection

Both converters (the boost and inverting converter) require rectifier diodes, D1 and D2. As a recommendation, to
reduce losses, use Schottky diodes. The forward current rating needed is equal to the maximum output current.
Consider that the maximum currents, IPOSmax and INEGmax, might differ for VPOS and VNEG when choosing the
diodes.
8.2.3.4 External P-MOSFET Selection
During shutdown, when connected to a power supply, a path from the power supply to the positive output
conducts through the inductor and an external diode. Optionally, in oder to fully disconnect the positive output
VPOS during shutdown, add an external p-MOSFET (Q1). The BSW pin controls the gate of the p-MOSFET.
When choosing a proper p-MOSFET, the VGS and VGD voltage ratings must cover the input voltage range,
the drain current rating must not be lower than the maximum input current flowing into the application, and
conditions of the p-MOSFET operating area must fit.
If there is no intention to use an external p-MOSFET, leave the BSW pin floating.
8.2.3.5 Stabilizing the Control Loop
8.2.3.5.1 Feedforward Capacitors
As a recommendation, to speed up the control loop, place feedforward capacitors in the feedback divider,
parallel to R1 (boost converter) and R3 (inverting converter). Equation 11 shows how to calculate the appropriate
value for the boost converter, and Equation 12 for the inverting converter.
6.8 V
C9
R1 (11)
7.5 V
C10
R3 (12)
In this application example, C9 = 6.8pF and C10 = 7.5pF match the choices of R1 and R3.
To avoid coupling noise into the control loop from the feedforward capacitors, it is possible to place a series
resistor to limit the bandwidth of the feedforward effect. Any value between 10kΩ and 100kΩ is suitable. The
higher the resistance, the lower the noise coupled into the control loop system.
8.2.3.5.2 Compensation Capacitors
The device features completely internally compensated control loops for both converters. The internal
feedforward system has built-in error correction which requires external capacitors. As a recommendation, use
a 10nF capacitor at the CP pin of the boost converter and a 4.7nF capacitor at the CN pin of the inverting
converter.

TPS65131-Q1
8.2.4 Analog Supply Input Filter

To ensure a noise free voltage supply of the IC, it is recommended to add an RC or LC filter between IIN and
VIN pins.
8.2.4.1 RC-Filter
For most applications an RC filter can be used with a resistance value of 100Ω minimum and capacitor value of
0.1µF as in the application example Figure 8-1.
8.2.4.2 LC-Filter
For applications where input voltages VI with a fast rising edge (slew rate ≥ 275mV/µs) are expected, it is
recommended to replace the resistor R7 with a ferrite bead to minimize the delay between the signals on
IIN and VIN. A ferrite bead with the lowest possible DCR and a proper current rating should be selected -
BLM18KG101TN1 for example. A conservative approach for the current rating specification is to set it at 1.5
times or twice the maximum input current.
Table 8-3. List of Ferrite Beads
VENDOR FERRITE BEAD SERIES
Murata BLMxKG
8.2.5 Thermal Information

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues, such as thermal coupling, airflow,
added heatsinks and convection surfaces, and the presence of heat-generating components affect the power-
dissipation limits of a given component.
Three basic approaches for enhancing thermal performance follow.
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB
• Introducing airflow to the system
The recommended device junction temperature range, TJ, is –40°C to 125°C. The thermal resistance of the 24-
pin QFN, 4–mm × 4–mm package (RGE) is RθJA = 34.1°C/W. The recommended operating ambient temperature
range for the device is TA = –40°C to 105°C. Use Equation 13 to calculate the maximum power dissipation,
PDmax, as a function of TA. In this equation, use TJ = 125°C to operate the device within the recommended
temperature range, use TJ = T(TS) to determine the absolute maximum threshold when the device might go into
thermal shutdown. If the maximum ambient temperature of the application is lower, more heat dissipation is
possible.
TJ TA
PD max
RTJA (13)

TPS65131-Q1
8.2.6 Application Curves
100 100
90 90
80 80
70 70
Efficiency (%)
Efficiency (%)
60 60
50 50
40 40
30 30
20 20
10 VPOS = 10.5 V PSM OFF 10 VPOS = 10.5 V PSM OFF
VPOS = 10.5 V PSM ON VPOS = 10.5 V PSM ON
0 0
0.001 0.01 0.1 1 0.001 0.01 0.1 1
Output Current (A) D005
VI = 3.3V VPOS = 10.5V Power-save mode VI = 5V VPOS = 10.5V Power-save mode

on and off on and off
Figure 8-2. Boost Converter (VPOS) Efficiency vs Figure 8-3. Boost Converter (VPOS) Efficiency vs
Output Current Output Current
100 100
90 90
80 80
70 70
Efficiency (%)
Efficiency (%)
60 60
50 50
40 40
30 30
20 20
10 VNEG = -10 V PSM OFF 10 VNEG = -10 V PSM OFF
VNEG = -10 V PSM ON VNEG = -10 V PSM ON
0 0
0.001 0.01 0.1 1 0.001 0.01 0.1 1
VI = 3.3V VNEG = –10V Power-save mode VI = 5V VNEG = –10V Power-save mode

Figure 8-4. Inverting Converter (VNEG) Efficiency vs Figure 8-5. Inverting Converter (VNEG) Efficiency vs
Output Current Output Current

TPS65131-Q1
11 11
VPOS = 10.5 V PSM OFF VPOS = 10.5 V PSM OFF
10.9 VPOS = 10.5 V PSM ON 10.9 VPOS = 10.5 V PSM ON
10.8 10.8
10.7 10.7
Output Voltage (V)
Output Voltage (V)

10.6 10.6
10.5 10.5
10.4 10.4
10.3 10.3
10.2 10.2
10.1 10.1
10 10
0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VI = 3.3V VPOS = 10.5V Power-save mode VI = 5V VPOS = 10.5V Power-save mode

Figure 8-6. Boost Converter (VPOS) Output Voltage Figure 8-7. Boost Converter (VPOS) Output Voltage
vs Output Current vs Output Current
-9.5 -9.5
-9.6 -9.6
-9.7 -9.7
-9.8 -9.8
Output Voltage (V)
Output Voltage (V)
-9.9 -9.9
-10 -10
-10.1 -10.1
-10.2 -10.2
-10.3 -10.3
-10.4 VNEG = -10 V PSM OFF -10.4 VNEG = -10 V PSM OFF
VNEG = -10 V PSM ON VNEG = -10 V PSM ON
-10.5 -10.5
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0 0.1 0.2 0.3 0.4 0.5 0.6
Output Current (A) Output Current (A) D012
D011
VI = 3.3V VNEG = –10V Power-save mode VI = 5V VNEG = –10V Power-save mode

Figure 8-8. Inverting Converter (VNEG) Output Figure 8-9. Inverting Converter (VNEG) Output
Voltage vs Output Current Voltage vs Output Current
Output Voltage 10 mV/div Output Voltage 50 mV/div
Inductor Current 200 mA/div

Time = 400 ns/div Time = 20 s/div
VI = 3.3V VPOS = 10.5V IPOS Power-save mode VI = 3.3V VPOS = 10.5V IPOS Power-save mode
= 200mA off = 20mA on
Figure 8-10. Boost Converter (VPOS) Output Ripple Figure 8-11. Boost Converter (VPOS) Output Ripple

TPS65131-Q1
Output Voltage 10 mV/div

Time = 1 s/div Time = 40 s/div
VI = 3.3V VNEG = –10V INEG = Power-save mode VI = 3.3V VNEG = –10V INEG = Power-save mode
200mA off 20mA on
Figure 8-12. Inverting Converter (VNEG) Output Figure 8-13. Inverting Converter (VNEG) Output
Ripple Ripple
Output Current 20 mA/div

Output Current 20 mA/div
Offset = 200 mA
Offset = 150 mA

Time = 1 ms/div Time = 1 ms/div
VI = 3.3V VPOS = 10.5V VI = 3.3V VNEG = –10V

IPOS = 200mA to 250mA INEG = 150mA to 200mA
Figure 8-14. Boost Converter (VPOS) Load Figure 8-15. Inverting Converter (VNEG) Load
Transient Response Transient Response
Input Voltage 500 mV/div Input Voltage 500 mV/div

Offset = 3 V Offset = 3 V

Time = 2 ms/div Time = 2 ms/div
VI = 3V to 3.6V VPOS = 10.5V IPOS = 150mA VI = 3V to 3.6V VNEG = –10V INEG = 100mA
Figure 8-16. Boost Converter (VPOS) Line Transient Figure 8-17. Inverting (VNEG) Converter Line
Response Transient Response

TPS65131-Q1
Input Voltage 2 V/div Input Voltage 2 V/div
Output Voltage 5 V/div
Output Voltage 5 V/div

Inductor Current 1 A/div
Voltage at Switching Pin 10 V/div

Voltage at Switching Pin 10 V/div
Time = 200 s/div Time = 400 s/div
VI = 3.3V VPOS = 10.5V IPOS = 46mA VI = 3.3V VNEG = –10V INEG = 150mA
Figure 8-18. Boost Converter (VPOS) Start-Up Into Figure 8-19. Inverting Converter (VNEG) Start-Up
Load Into Load
Enabling Boost Converter

2 V/div
Output Voltage, Boost Converter

5 V/div
Enabling Inverter Converter

2 V/div
Output Voltage, Inverting Converter

10 V/div
Time = 1 ms/div
VI = 3.3V VPOS = 10.5V VNEG = –10V

IPOS = INEG= 160mA
Figure 8-20. Boost and Inverting Converter Start-Up Into Load
8.3 Power Supply Recommendations

The TPS65131-Q1 input voltage ranges from 2.7V to 5.5V. Consequently, the supply can come, for example,
from a 3.3V or 5V rail. If the device starts into load during the Soft Start phase, the drawn input current can be
higher than during post-start operation. Consider the application requirements when selecting the power supply.
To avoid unintended toggling of the Undervoltage Lockout , connect the TPS65131-Q1 via a low-impedance path
to the power supply.

TPS65131-Q1
8.4 Layout
8.4.1 Layout Guidelines
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. Improper layout might show the symptoms of poor line or load regulation,
ground and output voltage shifts, stability issues, unsatisfying EMI behavior or worsened efficiency. Therefore,
use wide and short traces for the main current paths and for the power ground tracks. The input capacitors
(C1, C2, C3), output capacitors (C4, C5), the inductors (L1, L2), and the rectifying diodes (D1, D2) should be
placed as close as possible to the IC to keep parasitic inductances low. Use a wide PGND plane. Connect the
analog ground pin (AGND) to the PGND plane. Further, connect the PGND plane with the exposed thermal pad.
Place the feedback dividers as close as possible to the control pin (boost converter) or the VREF pin (inverting
converter) of the IC.
Figure 8-21 provides an layout example which is recommended to be followed.
8.4.2 Layout Example
C8 R4 R3 C10
C7
15 VNEG
14 OUTN
13 OUTN
17 VREF
16 FBN
18 CN
AGND 19 12 NC
PGND
L2
C6 NC 20 11 PSN D2
CP 21 10 ENN
FBP 22 9 PSP
C9 R1 R2 VPOS 23 8 ENP
C4 PGND
INP 24 7 BSW
PGND 3
VIN 4
INN 6
INN 5
PGND 2
1
C5
D1
INP
U1
R7
VNEG
C3
VI
PGND
C2
VPOS
L1
C1
Q1
Figure 8-21. TPS65131-Q1 Layout Recommendation

TPS65131-Q1
9 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
9.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
9.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (March 2017) to Revision F (August 2024) Page
• Updated Device InformationTable.......................................................................................................................1
Changes from Revision D (October 2014) to Revision E (March 2017) Page

• Changed Section 1 bullet text from "...Qualified.." to...Test Guidance.." and HBM classification level from "H2"
to "H1C"..............................................................................................................................................................1
• Moved Tstg spec to the Abs Max Ratings table per new data sheet standard....................................................4
• Changed "Handling Ratings" to "ESD Ratings" and HBM Value From "±2 kV" to "±1000 V".............................4
• Changed Electrical Characteristics condition statement to "This specification applies over the full
recommended input voltage range VI = 2.7 V to 5.5 V and over the temperature range TJ = –40°C to 125°C
unless otherwise noted. Typical values apply for VI = 3.6 V and T J = 25°C.".....................................................5
• Changed The specification applies over the full recommended input voltage range VI = 2.7 V to 5.5 V and
over the temperature range TJ = –40 °C to 125°C unless otherwise noted. Typical values apply for VI = 3.6 V
and TJ = 25°....................................................................................................................................................... 6
• Added Section 8.2.4 description ......................................................................................................................16

TPS65131-Q1
Changes from Revision C (March 2014) to Revision D (October 2014) Page

• Global editorial changes bringing the datasheet into the new format.................................................................1
• Changed max. efficiency from 89% to 91% and from 81% to 85% ................................................................... 1
• Deleted "Minimum 1.25 MHz".............................................................................................................................1
• Changed 1-µA shutdown current to typ. 0.2 µA................................................................................................. 1
• Added Thermal Pad to Absolute Maximum Ratings. Added min./max. values where missing.......................... 4
• Added V(VIN), V(INN), VNEG, VPOS, V(ENN), V(ENP), V(PSN) to Recommended Operating Conditions table............ 4
• Changed symbol names to JEDEC compliance.................................................................................................5
• Added frequency and duty cycles to Switching Characteristics table. Removed from Electrical Characteristics
table.................................................................................................................................................................... 6
• Added Rectifier Diode Selection Guide............................................................................................................ 15
• Added P-MOSFET Selection Guide................................................................................................................. 15
Changes from Revision B (February 2013) to Revision C (March 2014) Page

• Added "Electrical Characteristics tested over –40°C to 125°C Junction Temperature Range".......................... 1
• Added Device Information table ........................................................................................................................ 1
• Deleted TA table row...........................................................................................................................................4
• Changed INN to VINN, added pin names VIN and INN........................................................................................ 4
• Added pin name VPOS...................................................................................................................................... 4
• Added pin name VNEG...................................................................................................................................... 4
• Changed INP to VINP, added pin name INP........................................................................................................ 4
• Changed "between pins OUTN to VINN" to "between pins OUTN to INN"..........................................................4
• Added operating junction temperature............................................................................................................... 4
• Added "In applications where high power dissipation and/or poor package thermal resistance is present, the
maximum ambient temperature may require derating. See Section 8.2.5 for details."...................................... 4
• Deleted "virtual" from "Operating virtual junction temperature range"................................................................4
• Changed Electrical Characteristics condition statement to "This specification applies over the full
recommended input voltage range VI = 2.7 V to 5.5 V and over the temperature range TJ = TA = –40°C to
125°C unless otherwise noted. Typical values apply for VI = 3.6 V and TJ = TA = 25°C."................................. 5
• Changed ILIM,min = 1800 mA to 1700 mA........................................................................................................... 5
• Deleted VPOS = 5 V (105°C) row........................................................................................................................ 5
• Changed rDS(on)P,max (VPOS = 5 V) = 300 mΩ to 390 mΩ................................................................................... 5
• Changed rDS(on)P,max (VPOS = 10 V) = 200 mΩ to 230 mΩ................................................................................. 5
• Changed ILIMP,min = 1800 mA to 1700 mA.......................................................................................................... 5
• Changed ILIMP,max = 2200 mA to 2250 mA......................................................................................................... 5
• Added TA = –40°C to 85°C.................................................................................................................................5
• Changed minimum f = 1250 kHz to 1150 kHz.................................................................................................... 6
• Editorially updated Block Diagram......................................................................................................................7
• Changed "The maximum recommended junction temperature (TJ) of the TPS65131-Q1 is 125°C." to "The
recommended device junction temperature range, TJ, is -40°C to 125°C."..................................................... 16
• Changed RθJA = 37.8°C/W to RθJA = 34.1°C/W............................................................................................... 16
• Changed "Specified regulator operation is ensured to a maximum ambient temperature TA of 105°C." to "The
recommended operating ambient temperature range for the device is TA = –40°C to 105°C."....................... 16
• Changed "Therefore, the maximum power dissipation is about 1058 mW" to "Use Equation 13 to calculate the
maximum power dissipation, PDmax, as a function of TA. In this equation, use TJ = 125°C to operate the
device within the recommended temperature range, use TJ = T(TS) to determine the absolute maximum
threshold when the device might go into thermal shutdown.".......................................................................... 16
• Changed Equation 13 ......................................................................................................................................16

TPS65131-Q1
Changes from Revision A (November 2012) to Revision B (February 2013) Page

• Changed CDM ESD rating from C3B to C4B..................................................................................................... 1
Changes from Revision * (May 2012) to Revision A (November 2012) Page

• Device is going from Preview to Production....................................................................................................... 1
• Added thermal information table values............................................................................................................. 5
• Added VPOS = 5 V (105°C) row and values to Electrical Characteristics table...................................................5
11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most-
current data available for the designated device. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

TPS65131-Q1
11.1 Mechanical Data
PACKAGE OUTLINE
RGE0024B SCALE 3.000
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4.1 B
A
3.9
0.5
0.3
PIN 1 INDEX AREA

4.1
3.9
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.05
0.00 0.08 C
2X 2.5
2.45 0.1 (0.2) TYP
7 12
EXPOSED
SEE TERMINAL
THERMAL PAD
DETAIL
6 13
2X 25 SYMM
2.5
1 18
0.3
20X 0.5 24X
0.2
24 19 0.1 C A B
SYMM
PIN 1 ID
(OPTIONAL) 0.05
0.5
24X
0.3
4219013/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com

TPS65131-Q1
EXAMPLE BOARD LAYOUT

RGE0024B VQFN - 1 mm max height
( 2.45)
SYMM
24 19
24X (0.6)
1
18
24X (0.25)
(R0.05)
TYP 25 SYMM
(3.8)
20X (0.5)
13
6
( 0.2) TYP
VIA
7 12
(0.975) TYP
(3.8)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X
0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND
SOLDER MASK
METAL OPENING
EXPOSED EXPOSED
METAL SOLDER MASK METAL UNDER
OPENING METAL SOLDER MASK
NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS

4219013/A 05/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com

TPS65131-Q1
EXAMPLE STENCIL DESIGN

4X ( 1.08)
(0.64) TYP
24 19
24X (0.6)
1
25
18
24X (0.25)
(R0.05) TYP (0.64)

TYP
SYMM
(3.8)
20X (0.5)
13
6
METAL
TYP
7 12
SYMM
(3.8)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219013/A 05/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com

TPS65131-Q1
PACKAGE OUTLINE
RGE0024N VQFN - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
B 4.1 A
3.9
4.1
3.9
PIN 1 INDEX AREA 0.1 MIN
(0.13)
SECTION A-A
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00 2X 2.5
2.45±0.1 (0.2) TYP
7 12
6 13
(0.16)
A A
25 SYMM
2X
2.5
1
18
20X 0.5 24X 0.3
0.2
24 19 0.1 C A B
PIN 1 ID SYMM
0.05 C
(OPTIONAL)
24X 0.5
0.3
4224736/A 12/2018
NOTES:
per ASME Y14.5M.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com

TPS65131-Q1

2X (3.8)
2X (2.5)
( 2.45)
24 19
24X (0.6)
24X (0.25)
1
18
20X (0.5)
25 SYMM 2X 2X
(2.5) (3.8)
2X
(0.975)
6 13
(R0.05) TYP
7 12 (Ø 0.2) VIA
TYP
2X (0.975)
SYMM

EXPOSED METAL SHOWN
SCALE: 18X
0.07 MAX 0.07 MIN

METAL METAL UNDER

SOLDER MASK
SOLDER MASK SOLDER MASK

OPENING OPENING
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS

4224736/A 12/2018
NOTES: (continued)
number SLUA271 (www.ti.com/lit/slua271) .
www.ti.com

TPS65131-Q1

2X (3.8)
2X (2.5)
4X
( 1.08)
24 19
24X (0.6)
24X (0.25)
1 25 18
20X (0.5)
SYMM 2X 2X
(2.5) (3.8)
2X (0.64)
6 13
(R0.05) TYP
METAL
TYP
7 12
2X (0.64)
SYMM

EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 18X
4224736/A 12/2018
NOTES: (continued)
www.ti.com

TPS65131-Q1
11.2 Tape and Reel Information

REEL DIMENSIONS TAPE DIMENSIONS
K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
Reel Reel
Package Package A0 B0 K0 P1 W Pin1
Device Pins SPQ Diameter Width W1
Type Drawing (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) (mm)
TPS65131TRGERQ1 VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS65131WTRGERQ1 VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

TPS65131-Q1
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS65131TRGERQ1 VQFN RGE 24 3000 356.0 356.0 35.0
TPS65131WTRGERQ1 VQFN RGE 24 3000 360.0 360.0 36.0

PACKAGE OPTION ADDENDUM
www.ti.com 15-Sep-2024
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TPS65131TRGERQ1 ACTIVE VQFN RGE 24 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 2U65131 Samples
Q1
TPS65131WTRGERQ1 ACTIVE VQFN RGE 24 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 65131W Samples
Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
OTHER QUALIFIED VERSIONS OF TPS65131-Q1 :
• Catalog : TPS65131
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65131TRGERQ1 VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS65131WTRGERQ1 VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS65131TRGERQ1 VQFN RGE 24 3000 356.0 356.0 35.0
TPS65131WTRGERQ1 VQFN RGE 24 3000 360.0 360.0 36.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGE 24 VQFN - 1 mm max height
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
RGE0024B SCALE 3.000
VQFN - 1 mm max height
4.1 B
A
3.9
0.5
0.3
PIN 1 INDEX AREA

4.1
3.9
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.05
0.00 0.08 C
2X 2.5
2.45 0.1 (0.2) TYP
7 12
EXPOSED
SEE TERMINAL
THERMAL PAD
DETAIL
6 13
2X 25 SYMM
2.5
1 18
0.3
20X 0.5 24X
0.2
24 19 0.1 C A B
SYMM
PIN 1 ID
(OPTIONAL) 0.05
0.5
24X
0.3
4219013/A 05/2017
NOTES:
per ASME Y14.5M.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
( 2.45)
SYMM
24 19
24X (0.6)
1
18
24X (0.25)
(R0.05)
TYP 25 SYMM
(3.8)
20X (0.5)
13
6
( 0.2) TYP
VIA
7 12
(0.975) TYP
(3.8)

EXPOSED METAL SHOWN
SCALE:15X
0.07 MAX 0.07 MIN

SOLDER MASK
METAL OPENING
EXPOSED EXPOSED
METAL SOLDER MASK METAL UNDER
OPENING METAL SOLDER MASK
NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS

4219013/A 05/2017
NOTES: (continued)
www.ti.com
4X ( 1.08)
(0.64) TYP
24 19
24X (0.6)
1
25
18
24X (0.25)
(R0.05) TYP (0.64)

TYP
SYMM
(3.8)
20X (0.5)
13
6
METAL
TYP
7 12
SYMM
(3.8)

EXPOSED PAD 25
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219013/A 05/2017
NOTES: (continued)
www.ti.com
PACKAGE OUTLINE
B 4.1 A
3.9
4.1
3.9
PIN 1 INDEX AREA 0.1 MIN
(0.13)
SECTION A-A
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00 2X 2.5
2.45±0.1 (0.2) TYP
7 12
6 13
(0.16)
A A
25 SYMM
2X
2.5
1
18
20X 0.5 24X 0.3
0.2
24 19 0.1 C A B
PIN 1 ID SYMM
0.05 C
(OPTIONAL)
24X 0.5
0.3
4224736/A 12/2018
NOTES:
per ASME Y14.5M.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
2X (3.8)
2X (2.5)
( 2.45)
24 19
24X (0.6)
24X (0.25)
1
18
20X (0.5)
25 SYMM 2X 2X
(2.5) (3.8)
2X
(0.975)
6 13
(R0.05) TYP
7 12 (Ø 0.2) VIA
TYP
2X (0.975)
SYMM

EXPOSED METAL SHOWN
SCALE: 18X
0.07 MAX 0.07 MIN

METAL METAL UNDER

SOLDER MASK
SOLDER MASK SOLDER MASK

OPENING OPENING
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS

4224736/A 12/2018
NOTES: (continued)
www.ti.com
2X (3.8)
2X (2.5)
4X
( 1.08)
24 19
24X (0.6)
24X (0.25)
1 25 18
20X (0.5)
SYMM 2X 2X
(2.5) (3.8)
2X (0.64)
6 13
(R0.05) TYP
METAL
TYP
7 12
2X (0.64)
SYMM

EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 18X
4224736/A 12/2018
NOTES: (continued)
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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TPS65131-Q1

SLVSBB2F – MAY 2012 – REVISED AUGUST 2024

TPS65131-Q1 Positive- and Negative-Output DC-DC Converter

(1) For all available packages, see the orderable addendum.

Copyright © 2017, Texas Instruments Incorporated

2 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: TPS65131-Q1

5 Pin Configuration and Functions

Table 5-1. Pin Functions

(1) NC - No internal connection

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3

6.2 ESD Ratings

6.3 Recommended Operating Conditions

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6.4 Thermal Information

6.5 Electrical Characteristics

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5

6.6 Switching Characteristics

6.7 Typical Characteristics

Figure 6-3. Shutdown Current (Into VIN and INN) VI = 3.6V

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Copyright © 2017, Texas Instruments Incorporated

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7

7.3 Feature Description

8 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: TPS65131-Q1

7.3.5 Soft Start

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9

8 Application and Implementation

8.1 Application Information

Copyright © 2017, Texas Instruments Incorporated

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Product Folder Links: TPS65131-Q1

8.2.2 Design Requirements

In this example, with R2 = 130kΩ, choose R1 = 1MΩ to set VPOS = 10.5V.

In this example, with R4 = 121.2kΩ, choose R3 = 1MΩ to set VNEG = –10V.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11

8.2.3.1.3 Inductor Selection

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Product Folder Links: TPS65131-Q1

(1) See Section 9.3

8.2.3.2 Capacitor Selection

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13

8.2.3.2.2 Output Capacitors

'V(ESR P) IPOS u R(ESR C4) (9)

'V(ESR N) INEG u R(ESR C5) (10)

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8.2.3.3 Rectifier Diode Selection

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15

8.2.4 Analog Supply Input Filter

8.2.5 Thermal Information

16 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: TPS65131-Q1

8.2.6 Application Curves

VI = 3.3V VPOS = 10.5V Power-save mode VI = 5V VPOS = 10.5V Power-save mode

VI = 3.3V VNEG = –10V Power-save mode VI = 5V VNEG = –10V Power-save mode

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17