ARM INSTRUCTON SET

In the ARM architecture, instructions are divided into several categories based
on their functionality. Below is an explanation of three major types of ARM
instructions: Data Processing Instructions, Data Transfer Instructions, and
Control Flow Instructions.
1. Data Processing Instructions
Data processing instructions perform arithmetic, logical, comparison, or
shifting operations on registers or immediate values. They are used to process
or manipulate data and update the processor's condition flags.
Examples:
 Arithmetic Operations:
o ADD: Adds two operands (e.g., ADD R0, R1, R2 → R0 = R1 + R2).
o SUB: Subtracts two operands (e.g., SUB R0, R1, R2 → R0 = R1 - R2).
o MUL: Multiplies two operands (e.g., MUL R0, R1, R2 → R0 = R1 *
R2).
 Logical Operations:
o AND: Logical AND between two operands (e.g., AND R0, R1, R2 →
R0 = R1 & R2).
o ORR: Logical OR between two operands (e.g., ORR R0, R1, R2 → R0
= R1 | R2).
o EOR: Exclusive OR (e.g., EOR R0, R1, R2 → R0 = R1 ^ R2).
 Shifting Operations:
o LSL: Logical Shift Left (e.g., LSL R0, R1, #2 → Shift R1 left by 2 bits).
o LSR: Logical Shift Right (e.g., LSR R0, R1, #2 → Shift R1 right by 2
bits).
 Comparison:
o CMP: Compares two operands (e.g., CMP R0, R1 → R0 - R1 but
only updates the flags, no result stored).
2. Data Transfer Instructions
Data transfer instructions are used to move data between registers, memory,
and sometimes between registers and special-purpose registers. These
instructions help load data into a register or store data from a register into
memory.
Examples:
 Load Instructions:
o LDR: Loads data from memory into a register (e.g., LDR R0, [R1] →
R0 = [R1], where [R1] is a memory address).
o LDRB: Loads a byte from memory (e.g., LDRB R0, [R1] → R0 = byte
at address R1).
o LDRH: Loads a halfword (16-bit) from memory (e.g., LDRH R0, [R1]
→ R0 = halfword at address R1).
 Store Instructions:
o STR: Stores data from a register into memory (e.g., STR R0, [R1] →
Store the contents of R0 at the memory address R1).
o STRB: Stores a byte (e.g., STRB R0, [R1] → Store the byte from R0
at the address R1).
 Load/Store Multiple:
o LDM: Loads multiple registers from memory (e.g., LDM R0, {R1,
R2, R3} → Loads values from memory into R1, R2, and R3).
o STM: Stores multiple registers into memory (e.g., STM R0, {R1, R2,
R3} → Stores the values of R1, R2, and R3 into memory starting at
address R0).
3. Control Flow Instructions
Control flow instructions determine the execution flow of a program. These
instructions can alter the sequence of execution by branching to a different
part of the code based on certain conditions.
Examples:
 Branch Instructions:
 o B: Unconditional branch (e.g., B label → Jump to the instruction at
label).
o BL: Branch with Link (used for function calls, saves the return
address in the link register LR).
o BX: Branch to address in a register (e.g., BX R0 → Jump to the
address stored in R0).
 Conditional Branches:
o BEQ: Branch if equal (e.g., BEQ label → Branch if the Zero flag is
set).
o BNE: Branch if not equal (e.g., BNE label → Branch if the Zero flag
is not set).
o BGT: Branch if greater than (e.g., BGT label → Branch if the
Negative flag is clear and the Zero flag is clear).`
 Special Control Flow Instructions:
o NOP: No operation, used for a delay or placeholder (e.g., NOP →
Does nothing, just moves to the next instruction).
o SWI (Software Interrupt): Used for making system calls (e.g., SWI 0
→ Triggers a software interrupt).
o WFI (Wait for Interrupt): Puts the processor in a low-power state
until an interrupt occurs.
Thumb Instruction Set

The Thumb instruction set was introduced to achieve better code density
(smaller code size) for embedded systems. It uses 16-bit instructions instead of
the standard 32-bit ARM instructions. However, due to the reduced instruction
size, Thumb instructions have limited functionality compared to ARM
instructions.

Key Features of Thumb:

1. 16-bit Instructions: Smaller instructions result in reduced memory

usage.
2. Improved Code Density: Smaller code size is ideal for memory-limited
embedded systems.
3. Execution: Thumb instructions are decoded into 32-bit ARM
instructions internally by the processor for execution.

Limitations of Thumb:

 Fewer registers can be accessed compared to ARM mode.

 Certain complex operations (like conditional execution or barrel shifter)
are not directly supported.

Types of Thumb Instructions

The original Thumb instruction set includes the following types:

1. Data Processing Instructions:

o MOV (Move Register): Transfers data between registers.
 Example: MOV R0, R1
o ADD (Add): Adds two registers or an immediate value.
 Example: ADD R0, R0, #1
o SUB (Subtract): Subtracts a value.
 Example: SUB R0, R0, #1
o CMP (Compare): Compares two values.
 Example: CMP R0, R1
2. Data Transfer Instructions:
o LDR (Load Register): Load data from memory into a register.
  Example: LDR R0, [R1]
o STR (Store Register): Store data from a register to memory.
 Example: STR R0, [R1]
3. Branch Instructions:
o B (Branch): Unconditional branch to a target address.
 Example: B label
o BEQ (Branch if Equal): Conditional branch based on flags.
 Example: BEQ label
4. Shift and Rotate Instructions:
o LSL (Logical Shift Left): Shift bits to the left.
 Example: LSL R0, R1, #2
o LSR (Logical Shift Right): Shift bits to the right.
 Example: LSR R0, R1, #1
5. Special Instructions:
o BL (Branch with Link): Used for subroutine calls.
o SWI (Software Interrupt): Triggers a software interrupt.

Thumb-2 Instruction Set

The Thumb-2 instruction set was introduced in the ARMv7-M architecture
(e.g., Cortex-M3/M4 processors). It extends the original Thumb instruction set
to include both 16-bit and 32-bit instructions. This combination allows Thumb-
2 to provide both high performance and compact code.

Key Features of Thumb-2:

1. Mixed 16-bit and 32-bit Instructions: Combines compact 16-bit

instructions with powerful 32-bit instructions.
2. Extended Functionality: Includes all ARM instructions, supporting more
operations and addressing modes.
3. Full Processor Features: Supports conditional execution, barrel shifting,
and multiple-register load/store.
4. Performance: Achieves performance similar to ARM instructions while
maintaining Thumb's smaller code size.

Types of Thumb-2 Instructions

The Thumb-2 instruction set includes 16-bit instructions from the original
Thumb and new 32-bit instructions for enhanced functionality. Here's a
breakdown:

1. Data Processing Instructions:

 16-bit:
o MOV (Move): Transfer values between registers.
 Example: MOV R0, R1
o ADD (Add): Perform basic addition.
 Example: ADD R0, R1, #5
 32-bit:
o ADC (Add with Carry): Adds with the carry flag.
 Example: ADC R0, R1, R2
o SUBS (Subtract with Flags): Subtracts and updates condition flags.
 Example: SUBS R0, R1, R2

2. Data Transfer Instructions:

 16-bit:
o LDR and STR for loading and storing single registers.
 32-bit:
o LDRD and STRD (Load/Store Double Word): Access two words of
memory.
 Example: LDRD R0, R1, [R2]
o LDM and STM (Load/Store Multiple): Transfer multiple registers.

3. Branch and Control Instructions:

 16-bit:
o B (Branch): Simple branch to a label.
o BEQ, BNE (Conditional Branch): Branch based on condition flags.
 32-bit:
o BL (Branch with Link): Calls a subroutine and saves the return
address.
o CBZ (Compare and Branch on Zero): Branch if a register is zero.
 Example: CBZ R0, label
o IT (If-Then): Allows conditional execution of a few instructions.

4. Shift and Rotate Instructions:

 Thumb-2 includes advanced shifts:

 o LSL, LSR, ASR (Arithmetic Shift Right), ROR (Rotate Right).
o Example: LSL R0, R1, #3

5. Other Instructions:

 Saturation Arithmetic:
o SSAT: Signed Saturate.
 Example: SSAT R0, #8, R1 → Saturates the value of R1 to 8-
bit signed range.
 Bit Manipulation:
o UBFX: Extracts a field of bits.
 Example: UBFX R0, R1, #4, #3 → Extract 3 bits starting at bit
4.
 Special Purpose:
o NOP: No operation.
o WFI: Wait for interrupt.

Comparison of ARM, Thumb, and Thumb-2 Instruction

Sets
Key Features of Thumb-2

1. Mixed Instruction Size:

o Combines 16-bit instructions (compact, simple tasks) with 32-bit
instructions (advanced, complex operations).
o Reduces code size while maintaining ARM-like performance.
2. Improved Code Density:
o Achieves better code density compared to ARM while being more
functional than Thumb.
3. Full Register Access:
o Access to all 16 registers (R0–R15), unlike Thumb which limits
usage to R0–R7.
4. Advanced Addressing Modes:
o Supports ARM-like addressing: pre-indexed, post-indexed,
immediate offsets, and register-based offsets.
5. Conditional Execution:
o Uses the IT (If-Then) instruction to conditionally execute up to 4
instructions.
Example:
6. Advanced Instructions:
o Includes new instructions like:
 CBZ (Compare and Branch on Zero) → Efficient conditional
branching.
Example: CBZ R0, label
 REV (Byte Reversal) → Reverses byte order in a register.
Example: REV R0, R1
7. Performance and Efficiency:
o Matches ARM's performance for critical tasks with better code
density, making it suitable for embedded systems.