This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTIE.2020.2999595, IEEE Journal
of Emerging and Selected Topics in Industrial Electronics

DCM Based Bridgeless PFC Converter for EV

Charging Application
Abhinandan Dixit, Student Member, IEEE, Karan Pande, Student Member, IEEE, Sivanagaraju
Gangavarapu, Student Member, IEEE, and Akshay K. Rathore, Senior Member, IEEE

Abstract— This paper proposes a single-phase switched-mode phase supply mains line [4]-[7]. The charger converts variable
bridgeless AC-DC buck-boost derived converter which can serve AC input voltage to the desired level of DC voltage and current.
as front-end converter for on-board EV charging application. The The OBC is induced in the EV and takes single-phase AC input
bridgeless scheme rules out the orthodox bridge rectifier and the (50 Hz or 60 Hz) to charge the battery. Thus, OBC desires a
affiliated losses. The proposed converter operates in discontinuous power factor correction (PFC) converter at the AC supply front-
current conduction mode (DCM), thus achieving natural power
factor correction for variable AC input. In addition to this, sensing
end to meet the harmonic limits set by the IEC standards [8]. In
of input voltage and input current is fended off because of DCM addition, these chargers should have isolation to reduce the
operation making the converter reliable, cost-effective and robust common mode noise and provide short circuit protection. These
compared to conventional continuous current conduction mode PFC converters along with isolation can be implemented easily
converters. Further, the control becomes simple with the using two-stage converters [4], [6], [12]. In two-stage
employment of single sensor and elimination of phase-locked loop. converter, the front-end active PFC converter is employed at
The proposed front-end converter is well suited for low voltage first stage followed by an isolated DC-DC converter at second
battery chargers ranging between 1.0 kW to 3.3 kW installed in stage. This paper mainly focusses on active front-end PFC
golf-carts and E-Rickshaws. A comprehensive steady-state converter. Since OBC are mounted on the EV’s, they must have
analysis for one switching cycle and the design equations of the
proposed converter are presented. The proposed converter small-
higher power density, higher efficiency and lower cost which
signal model is presented for implementation of closed-loop are distinctively crucial aim for the EV manufacturers [9]-[11].
control. Experimental results from a 1.0 kW concept-proof The conventional front-end converter employs diode-bridge
hardware prototype have been demonstrated which upholds the rectifier along with a boost converter for PFC. This front-end
converter analysis. converter is the most complex and lossy part because of its high
semiconductor count. As these converters are operated in
Index Terms— EV charger, PFC, AC-DC Converter, DCM,
PLL. continuous current conduction mode (CCM), the control of
such converters requires phase-locked loop (PLL) in order to
I. INTRODUCTION synchronize with grid. For implementation of PLL and unity
power factor (UPF) operation, in total of three sensors, i.e. input
T he automotive industry globally is witnessing a major
transformation. Growing concerns for the environment and
energy security clubbed with rapid advancements in
current, input voltage and output voltage sensors are required.
Higher sensors count not only increases the cost, but also
complicates the control and reduces the converter reliability.
technologies for powertrain electrification are revolutionizing Reference [13] identifies that the bridge rectifiers are
the automotive sector. One of the key facets of such a change is accountable for a sizable part of conduction losses in any front-
the accelerated development in the field of electric mobility end PFC converters. Therefore, to eliminate the diode bridge
which might transform the automotive industry like ever before. rectifiers for improved efficiency and reduced losses, bridgeless
As per Germany’s Centre for Solar Energy and Hydrogen topologies are implemented [14]-[16]. Thus, a viable option
Research (ZSW), there were 5.6 million EVs on the world’s that can work as front-end AC-DC converter is the one which
roads at the beginning of 2019 with China and the United States has the following features:
catering to the majority market shares of about 2.6 million and 1. Achieve PFC over range of input voltage.
1.1 million respectively [1], [2]. Recent market research 2. Maintains low THD (less than 5%).
predicts that between 2040 and 2050 there would be more than 3. Maintains stiff regulated DC voltage.
1.0 billion EVs on road, yet in the present situation EVs are not 4. Simple control and reduced number of semiconductor
holding off in the market due to the high cost of batteries, devices and sensors.
Considering the above features, this paper proposes a
overcomplicated charger design and underdeveloped charging
bridgeless buck-boost derived PFC converter for EV charging
infrastructure. Hence, a need for more smart and intelligent
application. The proffered converter is designed to work in
charging process would be required [1], [2].
discontinuous conduction mode (DCM) to achieve natural PFC
EVs comprises of vehicles that are run by lithium-ion battery
packs with voltage levels of 400 to 450 V and the vehicles such for variable AC input. This operation expels the sensing of input
as golf-cart and E-Rickshaws that run at low voltage battery current, making converter more reliable and cost-effective. The
packs of 48 V [3]. This low voltage battery pack require the converter control is very simple with the requirement of only
chargers ranging between 1.0 kW to 3.3 kW. These on-board one control loop, and a single sensor. A brief discussion on
chargers (OBC) are powered by plugging in household single- state-of-the-art available bridgeless topologies is presented in

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of Emerging and Selected Topics in Industrial Electronics

D1 D2 D1 D2 D1 D2

L1 L1 L1
+ +
vin Co R Vo vin Co R Vo vin Co R Vo
- -

L2 L2 L2
SW1 SW2 SW1 SW2 SW1 SW2
Db Da
Gp1 Gp2

Gp
(b) (c) Gp
(a)

D1 D2 D1 D2 D3 D4
L1
L1 L3
+ +
vin
vin Co R Vo L2 Co R Vo
- -
L4
L2
SW1 SW2 SW1 SW2 SW3 SW4
Db Da Gp1 Gp2 Gp1 Gp3
Gp2 Gp4

(d) (e)
Fig. 1. Schematics of state-of-the-art topologies (a) bridgeless boost PFC; (b) dual boost PFC; (c) semi-bridgeless PFC; (d) phase-shifted semi-bridgeless PFC;
(e) bridgeless interleaved boost PFC converter.

section II. Section III describes the detailed analysis of the switching and conduction losses at light load operation. A low-
proposed converter. Experimental results are presented in frequency transformer is needed to sense the input voltage. As
section IV followed by section V which concludes the paper. the converters have two input inductors, the voltage potential at
the output is pulsating [19], [20].
II. OVERVIEW OF CONVENTIONAL BRIDGELESS TOPOLOGIES
C. Semi-Bridgeless PFC
FOR EV CHARGING
Fig. 1(c) exhibits the semi-bridgeless PFC topology
Bridgeless topologies are gaining popularity in EV charging
consisting of two extra diodes at the input side to address the
applications due to their high efficiency, simple design and low
EMI issues. The conduction losses are very low in the converter
component count. The bridgeless topologies eliminate the use
and it also resolves the issue of floating ground. The converter
of input diode bridge and mostly comprises of boost or boost
control and current sensing are complex and expensive as it
derived topologies to achieve the desired high voltage output.
requires either three current transformers or the use of Hall
The following points show a crisp understanding of each of the
Effect sensors and can also be measured by a differential
bridgeless PFC converter topologies along with their merits and
amplifier with a noise in the signal [21], [22].
demerits.
D. Phase Shifted Semi-Bridgeless(PSSB) PFC
A. Bridgeless Boost PFC
Fig. 1(d) exhibits the phase shifted semi-bridgeless (PSSB)
Fig. 1(a) exhibits the bridgeless boost topology housing two
PFC converter topology. The converter is operated in boost
switches which are driven by similar gating pulses, shutting out
mode where the switches are 180-degree phase-shifted making
the need for input diode bridge. The topology is preferred where
the converter less vulnerable to EMI issues and has a high
the need for higher power density and efficiency is a major
efficiency at light load. The current in the converter is usually
concern. The converter resolves the issues of heat management
sensed with the current synthesizer technique. The converter
at the input side but raises the concern of high EMI. It also
shows low efficiency at high power and makes it costly because
generates high common-mode noise than traditional other
of the higher component count [23]-[25].
bridgeless topologies. Current sensing is challenging making
the control complex [17], [18]. E. Bridgeless Interleaved Boost PFC Converter
B. Dual Boost PFC Fig. 1(e) exhibits the bridgeless interleaved boost PFC
converter consisting of four diodes, four switches, and four
Fig. 1(b) exhibits the dual boost PFC converter topology. The
inductors and is used for power level above 4.0 kW. The
topology resembles two boost topologies connected in parallel
converter demonstrates a high input power factor, high
combination at the input. The gating signals are decoupled in
efficiency and low input current harmonics. The topology has
the converter i.e., when one switch is on then the other switch
the highest number of component count than any other
operates in synchronous mode. The topology diminishes the

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of Emerging and Selected Topics in Industrial Electronics

S = 𝐼𝑜 Co1 𝐼𝑜
D1 Co1 Co1 D1 𝑖 𝐷1 (𝑡)
L L
+ S
+
Lf S L Lf Lf S
Vo vin 𝑖 𝐿 (𝑡) Vo vin 𝑖 𝐿 (𝑡) Vo
vin Cf R
Cf R Cf R
- -

D2 Co2 D2 𝑖𝐷2 (𝑡) Co2 Co2

(a) (b) (c)

Fig. 2(a) Proposed single-phase bridgeless buck-boost derived converter; converter configuration during (b) positive half-line cycle; (c) negative half-line cycle.

bridgeless PFC topology making it costly and bulky in size for source configuration and they are controlled by the same gate
practical usage with complex control strategies [26]- [28]. signal, hence, it is considered as single switch S in the analysis.
As the presented bridgeless topologies are operated in CCM, The proposed converter only operates in boost mode in order to
input voltage and current sensing are required in order to reverse bias the output diodes when the switch S is on.
implement PFC. Moreover, the same topologies can be The proposed converter equivalent circuit during positive
extended to DCM, which does not require input sensing, but and negative half-line cycles are shown in Fig. 2(b) and Fig.
have complications due to the boost structure. The input current 2(c), respectively. It must also be considered that either the
expression 𝑖 (𝑡) for a bridgeless boost can be given as switch S or only one diode (𝐷 𝑜𝑟 𝐷 ) is in the current flowing
𝑣 (𝑡) path which consequently lowers the conduction losses. Another
𝑡, 0<𝑡≤𝑡
𝑖 (𝑡) = 𝐿 (1) supplementary advantage is the reduced voltage stress of 𝑉 +
(𝑣 (𝑡) − 𝑉 )
𝑡, 𝑡 <𝑡<𝑇 on all semiconductor devices in comparison to a traditional
𝐿
where 𝑣 (𝑡) = 𝑉 sin(𝜔𝑡) , 𝑉 = output voltage, 𝑇 = switching buck-boost converter. The converter is designed to be operated
time period, and 𝑉 = peak input voltage. in DCM to achieve natural PFC at AC input.
On performing fast Fourier transform (FFT) analysis of input B. Modes of Operation
current for one switching cycle using (2), one can get
The steady-state graphs of the proposed converter for one
𝑎
𝑖 (𝑡) = + (𝑎 cos(ℎ𝜔 𝑡) + 𝑏 sin(ℎ𝜔 𝑡)) (2) switching cycle are shown in Fig. 3 with the following
2 assumptions.
𝑉 1 1 a) All components are ideal.
𝑎 = 𝐷𝑠𝑖𝑛(2𝜋ℎ𝐷) + cos(2𝜋ℎ𝐷) − (3)
ℎ𝜔 𝐿 2ℎ𝜋 2ℎ𝜋 b) The input voltage and the output voltage are
𝑉 sin(2𝜋ℎ𝐷) 𝑉 considered constant within one switching cycle.
𝑏 = 1 − 𝐷𝑐𝑜𝑠(2𝜋ℎ𝐷) + − (4)
ℎ𝜔 𝐿 2𝜋ℎ ℎ𝜔 𝐿 c) The output side filter capacitors are large enough to
where D is the duty cycle and L is the converter inductance. keep up the output voltage constant in one switching
It is observed that lower order odd harmonics are present cycle.
which leads to poor input current THD which is evident from d) The output capacitors ‘𝐶 ’and ‘𝐶 ’ share half-of the
(3) and (4). Hence, these converters require a complex control output voltage.
and a large input filter which leads to high weight and low
power density. The proposed converter does not exhibit these 1. Mode I (0 < 𝑡 < 𝑡 )
issues as the inductor is connected to the supply during the turn- In mode I, switch S is turned-on with the gate signal 𝑉 .
on period and load side during turn-off. Thus, any non-linearity Inductor 𝐿 stores the energy and capacitors 𝐶 and 𝐶 supply
of the output is not transferred to the input, hence a small input power to the load. The expression for inductor current 𝑖 (𝑡) is
filter is enough which increases the converter power density. given as
𝑣 (𝑡)
III. PROPOSED CONFIGURATION, ANALYSIS, AND DESIGN 𝑖 (𝑡) = 𝑡 (5)
𝐿
A. Topological Derivation and System Configuration 2. Mode II (𝑡 < 𝑡 < 𝑡 )
The proposed single-phase bridgeless buck-boost derived In this mode, gate signal is removed, and switch S is turned
PFC converter is shown in Fig. 2(a). It is derived from the off. The inductor 𝐿 demagnetizes by giving stored energy to
classical buck-boost converter where the diode rectifier is the load while capacitor 𝐶 gets charged. The expression for
removed from the front-end and integrated on the load side in inductor current 𝑖 (𝑡) is given as
the form of voltage doubler configuration. The proposed 𝑉
converter embodies two back-to-back connected MOSFETs, 𝑖 (𝑡) = 𝑖 , − 𝑡 (6)
2𝐿
two diodes, one inductor, and two electrolytic capacitors. The where 𝑖 , is the peak inductor current given by (7)
back-to-back connected MOSFETs are connected in common

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of Emerging and Selected Topics in Industrial Electronics

D. Input Current
Modes
1 2 3 The input current expression of the proposed converter for
one switching cycle can be defined as
𝑣 (𝑡)
𝐼 (𝑡) = 𝑡, 0 < 𝑡 ≤ 𝐷𝑇 (13)
Vg 𝐿
0, 𝐷𝑇 < 𝑡 ≤ 𝑇
On performing FFT of (13) using (2)
t (sec)
𝑖 𝐿,𝑝𝑘
𝑣 (𝑡) (14)
𝑎 = 𝐷 𝑇
𝐿
𝑣 (𝑡) 1 1
𝒊𝑳 (𝒕) 𝑎 = 𝐷𝑠𝑖𝑛(2𝜋ℎ𝐷) + cos(2𝜋ℎ𝐷) − (15)
2𝜋ℎ𝑓 𝐿 2ℎ𝜋 2ℎ𝜋
𝑣 (𝑡) 𝑠𝑖𝑛(2𝜋ℎ𝐷)
𝑏 = − 𝐷𝑐𝑜𝑠(2𝜋ℎ𝐷) (16)
t (sec) 2𝜋ℎ𝑓 𝐿 2ℎ𝜋
DTs Equation (14), tells the fundamental component of the input
𝑣 𝑖𝑛
current and (15), (16) tell the switching order harmonics present
which needs to be filtered out. On comparing (3) and (4) with
VL
t (sec) (15) and (16), it is noted that unlike conventional boost
Vo/2
𝑖 𝐿,𝑝𝑘
converter the proposed converter does not inject higher lower
order amplitude harmonics in the input and thus requires a small
𝒊𝑫 𝟐 (𝑡) filter. By designing a low-pass LC filter with a cutoff frequency
much lower than the switching frequency, the harmonic
t (sec) currents can be filtered out. Therefore, the resulting input
D1Ts
current contains only the fundamental current component, and
t0 t'1 t1 Ts t (sec) is given as,
Fig. 3. Steady-state waveforms for one switching cycle of the positive line 𝑣 (𝑡) 𝑉 𝐷 𝑇
cycle. 𝐼 (𝑡) = 𝐷 𝑇 = sin(𝜔𝑡)
𝐿 2𝐿 (17)
𝑣 (𝑡) = 𝐼 sin(𝜔𝑡)
𝑖 , = 𝐷𝑇
𝐿 where 𝐼 = is peak input current.
where 𝐷𝑇 =switch on-time. Equation (17) shows that the filtered input current is
This mode ends when the current through diode 𝐷 is zero, sinusoidal and is in phase with the input voltage, which proves
that implies the unity power factor (UPF) operation of the converter.
2𝑣 (𝑡) E. DCM operation and Critical Conduction Parameter
𝐷𝑇 = 𝐷𝑇 (8)
𝑉 Following inequality must hold for DCM operation which is
where 𝐷 𝑇 =diode conduction time. given as
𝐷𝑇 + 𝐷 𝑇 < 𝑇 (18)
3. Mode III (𝑡 < 𝑡 < 𝑇 ) On substituting (8) in (18)
In this mode, all semiconductor devices are in off state and 𝑀 (19)
𝐷<
capacitors 𝐶 and 𝐶 supply power to the load. (𝑀 + 2sin(ωt))
where 𝑀 = 𝑉 ⁄𝑉 is converter voltage gain.
C. Average Output Current
In the above equation worst case occurs at sin(𝜔𝑡) = 1,
The current supplied to the load is nothing but the average
thus by substituting 𝜔𝑡 = in (19), the condition to operate
diode current 𝑖 , of diode D2 in the positive half-line cycle.
Since the current is triangular in shape, its average can be given the converter in DCM is given as,
𝑀 (20)
as 𝐷<
𝑖 , 𝐷𝑇 (𝑀 + 2)
𝑖 , = (9) From (20), the critical value of voltage conversion ratio 𝑀
2𝑇
Substituting (7) and (8) in (9) and after simplifying gives for a given duty cycle can be defined, and is given as,
2𝐷
𝑣 (𝑡) ∗ 𝐷 𝑇 𝑀 < (21)
𝑖 , = (10) (1 − 𝐷)
𝐿𝑉
On the other hand, output current can also be given as
Due to the voltage doubler configuration, the diode average 𝑉
current contributes to half-of the total output average current in 𝐼 = (22)
a line cycle. Therefore, the converter average output current for 𝑅
On substituting (12) in (22),
one-line cycle can be defined as
𝐷 = 𝑀 2𝐾 (23)
1
𝐼, = 𝑖 , 𝑑(𝜔𝑡) (11) where 𝐾 =conduction parameter of the converter.
2𝜋
2𝐿
𝑉 𝐷 𝑇 𝐾 = (24)
𝐼, = . (12) 𝑅𝑇
4𝐿𝑉

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of Emerging and Selected Topics in Industrial Electronics

From (20) and (23), the critical conduction parameter 𝐾 converter is obtained by using the current injected equivalent
is calculated as circuit approach (CIECA) [29], [30]. Conventional state-space
1 averaging approach is more cumbersome and complex for
𝐾 = (25)
2(𝑀 + 2) simple DCM based DC-DC converters [31]. On the other hand,
CIECA approach is much easier as it only models transfer
F. Design of Inductor
properties of the converter [29]. In CIECA, the entire circuit can
To maintain PFC all conditions, the inductor current needs be scaled down as shown in Fig. 4(a). The non-linear
to be in DCM for worst case input voltage. The DCM inductor
parameters of the circuit are linearized by injecting the average
can be computed by using (12) and (20), and is given by
output current produced by the non- linear part. From Fig. 4(a),
𝑉 𝑉 𝑇 1
𝐿< (26) 𝚤̂ , = 𝑠𝐶 + 𝑣 (35)
4𝑃 𝑉 + 2𝑉 𝑅
On applying perturbations to (12) we get
G. Design of Output Capacitor 𝑉 𝐷𝑇 𝑉 𝐷 𝑇 𝑖 ,
In single-phase PFC rectifier, the output capacitors are 𝚤̂ , = 𝑑+ 𝑣 − 𝑣 (36)
2𝐿𝑉 2𝐿𝑉 𝑉
designed to filter out second order supply frequency oscillations On equating (37), (38) and substituting 𝑣 = 0
occurring present in output voltage. Thus, by considering 𝐶 =
𝑣 (𝑠) 𝑉 𝐷
𝐶 = 𝐶 , the low-frequency output voltage ripple 𝑉 , is 𝐺(𝑠) = = (37)
given as 𝑑(𝑠) 𝐾 𝑀(𝑠𝑅𝐶 + 2)
1 where 𝐶 = ,𝑀= , and 𝑅 =load resistance.
∆𝑉 , = 𝑖 𝑑𝑡 + 𝑖 𝑑𝑡 (27)
𝐶 As the transfer function is a single pole system, a simple PI
1
= 𝑖 , − 2𝑖 𝑑𝑡 (28) controller 𝐻(𝑠) = 𝐾 + is used to control the output
𝐶
2𝐼 voltage as shown in Fig. 4(b). As the output capacitor see a
𝐶 = (29) voltage ripple of twice the line frequency, a PI controller with
𝜔𝑉 ,
bandwidth lower than the 120Hz is selected with a phase
H. Design of Input Filter margin of 600. The controller is tuned using sisotool in Matlab
The criteria to design low-pass LC Filter is as follows: and the controller is designed at a gain crossover frequency of
1. Selection of cut-off frequency 𝑓 given by 188.5 rad/sec with 𝐾 = 0.00252 and 𝐾 = 0.21. Fig. 5 shows
1 1
𝑓 = (30)
2𝜋 𝐿 𝐶 S =
D1 𝐶𝑜1 𝑖𝑐 𝑖𝑜
2. Minimization of filter reactive power consumption for
60 Hz at 1.0 kW. The reactive power is minimum 𝑖𝑜,𝑎𝑣𝑔
Lf S L +
when filter characteristic impedance is equal to the R C Vo R
Cf -
converter impedance i.e.
𝐿 D2 𝐶𝑜2
𝑍 = =𝑍 (31)
𝐶
(a)
where 𝑍 is the characteristic impedance and 𝑍 is the input 𝑉𝑜
impedance at rated load and is given by -
2𝐿 𝑉𝑜, 𝑟𝑒𝑓 ∑ PI + Switch S
𝑍 = (32) + -
𝐷 𝑇 Limiter
Using (30) and (31), the low-pass filter parameters 𝐿 and 𝐶 Controller
can be obtained as (b)
𝑍 Fig. 4. (a) Equivalent circuit for small signal modelling; (b) Control
𝐿 = (33) diagram.
2𝜋𝑓
1 TABLE I
𝐶 = (34) DESIGN INPUT SPECIFICATIONS
2𝜋𝑍 𝑓
Parameters Value
I. Small-Signal Analysis
Source voltage, Vin RMS 110 VRMS ,60 Hz
Traditional front-end converters of battery charger use
complex control which require input voltage and current Output voltage, Vo 400V
sensing along with PLL. Such systems pose higher burden on Output power, Po 1.0 kW
microcontroller as more computation speed is required. The Output voltage ripple, 5% of output voltage
proposed converter mitigates these problems by eliminating the 𝑉, (Vo)
input sensing and just use one sensor to control the output as Switching frequency, fsw 50 kHz
shown in Fig. 4(b). The small-signal model of the proposed

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of Emerging and Selected Topics in Industrial Electronics

0
GM=inf, PM= 60 (at 188.5 rad/sec)
80
G(s)
Phase (degrees) Magnitude (dB)
60 H(s) Buck-Boost
40 G(s)*H(s) Inductor
20 DSP- Output
0 TM320F28335 Capacitor
-20
-40
0
Input-Filter
-45 Inductor
MOSFETs
Diodes
-90 Voltage
Sensor
-135
100 101 102 103 104 105
Frequency (rad/sec)
Fig. 5 Frequency response of plant G(s), controller H(s) and open loop Input-
Filter
G(s)*H(s). Capacitor

the frequency response of plant transfer function G(s),

controller transfer function H(s) and open loop transfer function (a)
G(s)*H(s). The open loop transfer function has an infinite dc Diodes
MOSFETs Output
gain which indicates the system reference tracking with zero Capacitor
Input-
steady state error, and the system robustness for input and load Filter
Capacitor
disturbances. The open loop phase margin of 600 indicates
enough damping of the system and the -20 dB slope at zero gain
crossover frequency indicates system robustness towards the
high frequency noise rejection. Output voltage is sensed using Input-Filter
Inductor
hall-effect based LV-25P sensor. The sensed voltage is
compared with the reference voltage and error is fed into the PI
controller. The PI controller generates the duty cycle to control
Gate
switch S. A limiter is connected in order to limit the duty during Driver
start-up and overload conditions. Voltage
Sensor
DSP- Buck-Boost
IV. EXPERIMENTAL RESULTS TM320F28335 Inductor

A 1.0 kW proof-of-concept laboratory hardware prototype is (b)

developed in order to validate the converter design for the
Fig. 6. Experimental prototype of bridgeless converter (a) top view; (b)
specifications given in Table I. Fig. 6(a) and Fig. 6(b) show the side view.
top and side views of the experimental setup respectively. The
dimensions of the developed prototype are 7.4 x 9.2 x 0.48 in (l converter PFC operation. Output voltage of 400 V is selected
x b x h) which gives a power density of 30 W/in3. The converter by considering the voltage margins for output capacitors [12].
nominal input voltage of 110 V RMS is been selected as per Table II lists the components employed for development of the
voltage-levels available in the lab. An approximate variation of hardware prototype. The input filter parameters 𝐿 and 𝐶 are
25% in input voltage has been considered to validate the calculated for a corner frequency of 6 kHz.
TABLE II Fig. 7(a) and Fig. 7(b) show that the input current is purely
EXPERIMENTAL SETUP PARAMETERS
sinusoidal and in phase with the input voltage, thus achieving
Components Specifications PFC at 1.0 kW and 250W respectively. Fig. 7(c) shows the input
MOSFET UF3C120040K4S, SIC 1200V, 45mohm current FFT analysis where the input current THD of 3.10 %
Diode RURG80100,1000V, 80A (<5 %) at 1.0 kW with a power factor of 0.9995. The input
Input filter current THD (%) and PF for different output power levels at
0.22 µF*10, 480 V AC, R76QR32204030J
capacitor 𝐶 60Hz input frequency is plotted and is shown in Fig. 7(d). It is
Input filter
371µH, 42 x 21 x 20, EE Ferrite Cores
observed that input current is almost unity (0.999) with a THD
inductor 𝐿 less than 5% for all output range of powers. Fig. 7(e) shows the
Output filter
Cap
82.4 µF*10*2, 450 VDC, UPZ2W820MHD input voltage and input current along with the voltage stresss of
Buck-Boost
24.45µH, 42 x 21 x 20, EE Ferrite Cores 360 V which is approximately equal to 𝑉 + , thus in good
Inductor
agreement with the analysis. Fig. 7(g) shows the inductor
DSP DSP-TMS320F28335
current and switch waveform at 500 W output power where
Gate Driver Gate Driver IC, IXYS-IXDN609SI inductor current is zero before turn-on confirming ZCS turn-on

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of Emerging and Selected Topics in Industrial Electronics

Vout (200 V/div) Vout (200 V/div)

3

% of Fundamental Amplitude
Vin (100 V/div)
Vin (100 V/div)
2.5

2 THD- 3.10%
P.F- 0.9995
1.5
Iin (20 A/div) Iin (5 A/div)
1

Iout (1 A/div) 0.5

0 4 8 10 12 14 16
Iout (5 A/div) 0 2 6
Harmonic order
(a) (b) (c)

Vin (100 V/div)

4.5 0.9996 Vin (100 V/div)
4 0.9995 Iin (10 A/div)
3.5 Iin (10 A/div)
0.9994
Power Factor

3
2.5 0.9993
2 0.9992
THD
1.5
PF 0.9991
1
0.5 0.9990
VSW (200 V/div)
0.9989 VSW (200 V/div)
250 500 750 1000
Power (W)
(d) (e) (f)

VD1 (200 V/div)

VSW (200 V/div)

il (20 A/div) VD2 (200 V/div) il (20 A/div)

(g) (h) (i)

Vout (200 V/div)

MOSFET Losses 10.50% 97
Efficiency %

3.29% 96
Diode Losses 95
VCO1 (100 V/div) 10.29%
Total Power 94
DCM Inductor 93
Loss
92
37.31 W 61.74% 91
110V
Filter Inductor 14.15% 80V
90

VCO2 (100 V/div) Miscellaneous 300 500 700 900

Power (W)
(j) (k) (l)
Fig. 7. Experimental results (a) PFC operation at 1.0 kW; (b) PFC operation at 250W; (c) input current THD at 1.0 kW; (d) THD and power factor at various
power levels; (e) switch voltage waveform along with PFC; (f) zoomed in version for switch voltage waveform; (g) ZCS turn-on of switch; (h) diode voltage
waveform; (i) zoomed in inductor waveform at 1.0 kW; (j) output capacitor voltage; (k) power loss distribution at 1.0 kW; (l) efficiency curve for various
power levels.

Vout (200 V/div)

Vout (200 V/div)

Vin (100 V/div)

Iin (10 A/div) Iin (20 A/div)

Iout (2 A/div) Iout (2 A/div)

(a) (b)
Fig. 8 Converter response (a) load change from 500W to 1.0 kW; (b) load change from 1.0 kW to 500 W.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTIE.2020.2999595, IEEE Journal
of Emerging and Selected Topics in Industrial Electronics

confirming the assumption made in the analysis. Fig. 7(k)

Vout (200 V/div) shows the power loss distribution chart at 1.0 kW. The
semiconductor losses contribute to a significant amount of total
Vin (100 V/div) losses with MOSFET losses contribution up to 61.74 % of the
losses. This is because of higher peak currents due to DCM
operation. The measure efficiency curve of the proposed
converter for different output powers for two different input
voltages is shown in Fig. 7(l). It is observed that measured
efficiency is very close to calculated efficiency from Fig. 7(k).
Fig. 8 shows the converter response to load variation. In both
Iin (20 A/div) cases it is observed that output voltage well tracks the reference
Input Voltage Swell voltage and is getting settled in the design time of 20 ms. To
confirm converter UPF operation for line voltage variation it is
subjected to 25 % line voltage dip and swell conditions. Fig.
(a)
9(a) and Fig. 9(b) show the converter response for input voltage
variation from 80V to 110V and 110V to 80V RMS,
Vout (200 V/div)
respectively. It is observed that during the voltage swell
Vin (100 V/div)
condition, the input current is decreased for maintaining same
power. Conversely, the input current is increased for the voltage
dip condition. In both conditions input current remains
sinusoidal which confirms UPF operation thus validating the
inductor design.
Table III gives a comparison between the proposed bridgeless
configuration with other single-phase CCM and DCM based
bridgeless PFC topologies. It is observed that the proposed
Iin (20 A/div) Input Voltage Dip topology exhibits various advantages in terms of passive and
active component count as compared to other PFC converters.
Despite of high current stress on MOSFETs due to DCM
(b) operation, higher efficiency of 96% is obtained which is
Fig. 9. Closed loop experimental results (a) input voltage swell; (b) input comparable with the state-of-the-art bridgeless topologies.
voltage dip.
V. CONCLUSION
of switch S. Fig. 7(h) shows the diode voltage waveform with a A single-phase switched-mode bridgeless AC-DC buck-
maximum voltage stress of 360 V. It is seen that during one- boost derived converter is proposed in this paper which serve
half cycle only one diode conducts whereas another diode is as a feasible front-end converter for on-board chargers. The
completely in the blocking state. Fig. 7(i) shows the inductor proposed converter benefits from reduced number of
current waveform at 1.0 kW where the inductor current is components and number of sensors which further helps in
discontinous confirming the converter DCM operation of the minimizing the charger cost. The converter is operated in DCM
inductor. Fig. 7(j) shows capacitor voltages 𝑉 and 𝑉 . It is in order to achieve PFC for wide input voltage variation. The
observed that both capacitors are sharing voltage equally PFC control requires one simple voltage control loop to regulate

TABLE III
COMPARISON BETWEEN PROPOSED CONVERTER AND SINGLE PHASE BRIDGELESS PFC CONVERTER
Configuration BL Buck-Boost [32] BL-Luo [33] BL-SEPIC [34] BL-Cuk [34] BL-Boost [13] Proposed
MOSFETs 2 2 2 2 4 2
Inductors 2 3 3 3 4 1
Intermediate Capacitor 0 1 2 2 0 0
Diodes 4 4 3 3 4 2
Mode of Operation DCM DCM DCM DCM CCM DCM
Swittching devices
operating in one 1sw+2D 1sw+2D 1sw+2D 1sw+2D 2sw+2D 2sw+1D
switching cycle
Current stress High High High High Low High
Voltage Stress 𝑉 + 𝑛𝑉 𝑉 +𝑉 𝑉 +𝑉 𝑉 +𝑉 𝑉 𝑉 + 0.5𝑉
Sensor Count 1 1 1 1 4 1
Peak Efficiency Not reported 91.64% 93.6% Not reported 98.9% 96%

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of Emerging and Selected Topics in Industrial Electronics

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTIE.2020.2999595, IEEE Journal
of Emerging and Selected Topics in Industrial Electronics

[31] Z. Li, K. W. E. Cheng and J. Hu, "Modeling of basic DC-DC converters," He was a recipient of the POSOCO power system award, India for his
2017 7th International Conference on Power Electronics Systems and outstanding work in Master’s program and also a recipient of Neysmith
Applications - Smart Mobility, Power Transfer & Security (PESA), Graduate Scholarship, Concordia Merit Scholarship, and Accelerator award for
HongKong, 2017, pp. 1-8. his academic excellence in Ph.D. He received IEEE-IAS CMD
[32] R. Kushwaha and B. Singh, "An Improved Battery Charger for Electric Outstanding Student Branch Chapter Chair Award, 2020 for his contribution
Vehicle with High Power Factor," 2018 IEEE Industry Applications towards organizing IEEE distinguished and guest lectures. His research
Society Annual Meeting (IAS), Portland, OR, 2018, pp. 1-8, doi: interests include AC-DC converters, DC-DC converters and DC-AC
10.1109/IAS.2018.8544585. converters.
[33] J. Gnanavadivel, P. Yogalakshmi, N. Senthil Kumar and K. S. Krishna
Veni, "Design and development of single phase AC–DC discontinuous
conduction mode modified bridgeless positive output Luo converter for
power quality improvement," in IET Power Electronics, vol. 12, no. 11, Akshay Kumar Rathore (M’05 - SM’12)
pp. 2722-2730, 18 9 2019, doi: 10.1049/iet-pel.2018.6059. received the M.Tech. degree from the Indian
Institute of Technology (BHU), Varanasi,
[34] A. J. Sabzali, E. H. Ismail, M. A. Al-Saffar and A. A. Fardoun, "New India, in 2003. He received the Ph.D. degree
Bridgeless DCM Sepic and Cuk PFC Rectifiers With Low Conduction from the University of Victoria, Victoria, BC,
and Switching Losses," in IEEE Transactions on Industry Applications, Canada, in 2008. He had two subsequent
vol. 47, no. 2, pp. 873-881, March-April 2011, doi: Postdoctoral Research Appointments with the
10.1109/TIA.2010.2102996. University of Wuppertal, Germany, and
University of Illinois at Chicago, IL, USA.
From November 2010 to February 2016, he
was an Assistant Professor in the Department
of Electrical and Computer Engineering, National University of Singapore,
Singapore. He is currently an Associate Professor at the Department of
Electrical and Computer Engineering, Concordia University, Montreal, QC,
Canada. He has published more than 250 research papers in international
journals and conferences including 85 IEEE Transactions. His research is
mainly focused on current-fed converters and multilevel inverters.
Dr. Rathore is a paper review chair for IEEE TRANSACTIONS ON
Abhinandan Dixit (S’19) received his B.Tech INDUSTRY APPLICATIONS for renewable and sustainable energy
degree in Electrical and Electronics Engineering conversion systems. He is a Prominent Lecturer and Awards Department Chair
from Vellore Institute of Technology (V.I.T), of the IEEE Industry Applications Society. He received the Gold Medal during
Vellore, Tamil Nadu, India in August 2018. He is his M.Tech. degree for securing highest academic standing among all electrical
currently working towards his MASc. degree in engineering specializations. He was a recipient of University Ph.D. Fellowship
Electrical and Computer Engineering department and Thouvenelle Graduate Scholarship during his PhD. He also received the
at Concordia University, Montreal, QC, Canada. 2013 IEEE IAS Andrew W. Smith Outstanding Young Member Achievement
During his undergraduation he worked as a Award, 2014 Isao Takahashi Power Electronics Award, 2017 IEEE IES David
Research Assistant at University Of Manitoba, J Irwin Early Career Award, 2019 IES Publications Committee Service
Winnipeg, Canada through Mitacs Globalink recognition, and 2020 IASCMD Outstanding Area Chair Award.
Research Internship Program from May 2017 to
August 2017. His research intereset include ac-dc
converters, dc-dc converters and solar dc
microgrid.
He is the recipient of Mitacs Graduate Fellowship, Concordia University
Split Merit Scholarship and Concordia ENCS Graduate Fellowship.

Karan Pande (S’19) received his B.E. degree

in Electrical Engineering from Rashtrasant
Tukadoji Maharaj Nagpur University
(R.T.M.N.U), India in 2016. Currently Karan is
pursuing his MASc. degree in Electrical and
Computer Engineering department at
Concordia University, Montreal, QC, Canada.
He was working as an Assistant Manager in
India’s leading Business Consulting and market
research firm “BDB India” from August 2016
to August 2018. His research interests include power electronics, battery
charger systems, power factor correction, ac-dc and dc-dc power converters.

Sivanagaraju Gangavarapu (S’17) received his

bachelor’s degree in Electrical and Electronics
Engineering from Andhra University,
Visakhapatnam, India in 2009, master’s degree in
Power and Control from the IIT Kanpur, India in
2012, and PhD degree in Electrical and Computer
Engineering from Concordia University,
Montreal, Canada in March 2020. He was with
Ashok Leyland Ltd, India, as Manager-Product
development of Vehicle Electrical and
Electronics section from 2012 to 2016.

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