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    Ect393 Scheme

    Uploaded by

    anshwaraullas

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Ect393 Scheme

    Uploaded by

    anshwaraullas
    14 views4 pages

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    © © All Rights Reserved

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    Copyright:

    © All Rights Reserved
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    14 views4 pages

    Ect393 Scheme

    Uploaded by

    anshwaraullas

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 4

    1100ECT393122303

    FINAL SCHEME

    Total Pages: 4
    Scheme of Valuation/Answer Key
    (Scheme of evaluation (marks in brackets) and answers of problems/key)
    APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY
    Fifth Semester B.Tech Degree (Honours) Examination December 2023 (2021 Admission)
    Course Code: ECT 393

    Course Name: FPGA BASED SYSTEM DESIGN


    Max. Marks: 100 Duration: 3 Hours

    PART A
    (Answer all questions; each question carries 3 marks) Marks

    1 Write Verilog code for Half Adder 3


    Equation and truth table (1 mark)
    Verilog code(2 marks)
    2 Describe state Machine 3
    Definition (1 mark)
    Figure (1 mark)
    Types (1 mark)
    3 Explain PLA 3
    Block diagram (1 mark)
    Explanation (2 marks)
    4 What are the advantages FPGA over CPLD 3
    List any three advantages, each carries 1 mark
    5 Explain Logic cell in FPGA 3
    Figure (1 mark)
    Explanation (2 marks)
    6 Differentiate coarse grained and Fine-grained FPGA Architecture 3
    Write any 4 differences.
    (Each carries 0.75 marks)
    7 Describe programmable Interconnect 3
    Figure (1 mark)
    Explanation (2 marks)

    Page 1 of 4
    1100ECT393122303

    FINAL SCHEME

    8 Explain Routing 3
    Figure (1 mark)
    Explanation (2 marks)
    9 Describe Actel FPGA 3
    Overview of architecture (2 marks)
    Example (1 mark)
    10 How do you implement a sequential circuit on FPGA 3
    Design steps (3 marks)
    PART B
    (Answer one full question from each module, each question carries 14 marks)

    Module -1

    11 a) Design a Ring counter using D flipflop and write the behavioural level coding using
    10
    Verilog.
    Truth table (2 marks)
    Figure (3 marks)
    Timing diagram (1 mark)
    Verilog code (4 marks)
    b) Explain Behavioural modelling with Example 4
    Definition and explanation (2 marks)
    Example (2 marks)
    12 a) Design a Full Subtractor and write the behavioural level coding using Verilog. 10
    Explanation (1 mark)
    Truth table (2 marks)
    Equation (1 mark)
    Figure (2 marks)
    Verilog code (4 marks)
    b) What is Mealy Model 4
    Figure (2 marks)
    Explanation (2 marks)
    Module -2
    13 a) Design the function F1=XYZ’+Y’ Z+X Y’ , F2 =XYZ+X’YZ+X’Y’Z’ using PAL and
    10
    PLA

    Page 2 of 4
    1100ECT393122303

    FINAL SCHEME
    PLA – Figure (4 marks)
    Explanation (1 mark)
    PAL – Figure ( 4 marks)
    Explanation (1 mark)
    b) Compare CPLD and FPGA 4
    Write any four comparison
    (Each carries 1 mark)
    14 a) Draw the structure of ROM and explain it. 9
    Block diagram (2 marks)
    Circuit diagram (2 marks)
    Explanation (3 marks)
    Example (2 marks)
    b) Comparison between PROM, PLA and PAL 5
    Write any five comparison
    (Each carries 1 mark)
    Module -3
    15 a) Explain timing and power dissipation in Logic block and I/O block. 9
    Logic Block: Timing analysis (2 marks)
    Power dissipation with equations (2.5 marks)
    I/O Block: Timing analysis (2 marks)
    Power dissipation with equations (2.5 marks)
    b) Explain Fine grained Architecture of FPGA 5
    Block diagram (2 marks)
    Explanation (3 marks)
    16 a) With neat diagram explain design flow of FPGA. 8
    Flow diagram (3 marks)
    Explanation of each block (5 marks)
    b) Explain FPGA logic cells with neat diagram. 6
    Block diagram (2 marks)
    Explanation (4 marks)
    Module -4
    17 a) Explain embedded system design using FPGA 9
    Block diagram (3 marks)

    Page 3 of 4
    1100ECT393122303

    FINAL SCHEME
    Design steps (3 marks)
    Explanation (3 marks)
    b) Explain delay models 5
    Equations (3 marks)
    Explanation (2 marks)
    18 a) Explain in detail the types of placements used in FPGA 9
    Types (3 marks)
    Block diagram (2 marks)
    Explanation (4 marks)
    b) Explain Partitioning 5
    Block diagram (2 marks)
    Explanation (4 marks)
    Module -5
    19 a) Explain Xilinx Vertex IOB 9
    Architecture (3 marks)
    Explanation (3 marks)
    Explanation and detailed figure of main blocks (3 marks)
    b) Compare Altera and Actel FPGA 5
    Write any five comparison
    (Each carries 1 mark)
    20 a) With neat diagram explain the architecture of Xilinx Virtex. 14
    Architecture (3 marks)
    Explanation (3 marks)
    CLB (3 marks)
    I/O Block (3 marks)
    Interconnect (2 marks)
    *********

    Page 4 of 4

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