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    HEMAN PRASAD
    The document provides information about a test for a Digital Logic Design course, including the course code, date, duration, and maximum marks. It includes two parts - Part A with 2 multiple choice questions worth 2 marks total and Part B with 2 long answer questions worth 8 marks each. Part C includes circuit design problems worth a total of 15 marks.

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    D Key

    Uploaded by

    HEMAN PRASAD
    21 views6 pages
    The document provides information about a test for a Digital Logic Design course, including the course code, date, duration, and maximum marks. It includes two parts - Part A with 2 multiple choice questions worth 2 marks total and Part B with 2 long answer questions worth 8 marks each. Part C includes circuit design problems worth a total of 15 marks.

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    The document provides information about a test for a Digital Logic Design course, including the course code, date, duration, and maximum marks. It includes two parts - Part A with 2 multiple choice questions worth 2 marks total and Part B with 2 long answer questions worth 8 marks each. Part C includes circuit design problems worth a total of 15 marks.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    21 views6 pages

    D Key

    Uploaded by

    HEMAN PRASAD
    The document provides information about a test for a Digital Logic Design course, including the course code, date, duration, and maximum marks. It includes two parts - Part A with 2 multiple choice questions worth 2 marks total and Part B with 2 long answer questions worth 8 marks each. Part C includes circuit design problems worth a total of 15 marks.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 6

    SRM Institute of Science and Technology

    College of Engineering and Technology


    Batch-2
    SET-D
    DEPARTMENT OF ECE
    SRM Nagar, Kattankulathur – 603203, Chengalpattu District, Tamilnadu
    Academic Year: 2023-2024 (ODD)

    Test: CLAT- I Date: 16.8.2023


    Course Code & Title: 21ECC203T- Digital Logic Design Duration: 02.20- 03.20 PM
    Year & Sem: II & III Max. Marks: 25

    Course Articulation Matrix:


    Program Outcomes (POs)
    21ECC203T- Digital Logic Design
    Graduate Attributes PSO
    Course Outcomes (COs) 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3
    Simplify Boolean expressions; implement gates as well as other types of
    3 - - - 3 - - - - - - - 3 - -
    IC devices using two major IC technologies, TTL and CMOS.
    Identify eight basic types of fixed-function combinational logic
    functions and demonstrate how the devices / circuits can be used in - 2 2 - 3 - - - - - - - 3 - -
    building complete digital systems such as computers.
    Understand and design sequential circuits using several types of flip-
    - 2 2 - 3 - - - - - - - 3 - -
    flops
    Design of advanced circuit and Design the advanced sequential logic
    - 2 2 - 3 - - - - - - - 3 - -
    circuits.
    Implement multiple output combinational logic circuits using PLDs;
    - 2 2 - 3 - - - - - - - 3 - -
    Explain the operation of a CPLD and FPGA.

    Part – A (2x1 = 2 Marks)


    Answer all the questions
    Q. No Question Marks BL CO PO
    1 1 1 1
    1. (d) F(A, B) = ∑m(0,2,3)

    1 1 1 1
    2. b) Noise Immunity
    Part – B (1 x 8 = 8 Marks)
    Instructions: Answer ANY 2 Questions
    3. a) With a neat sketch, explain the operation of the TTL 8 2 1 1
    NAND gate with tri-state output.
    Circuit : 4 marks

    4 3 1 1

    4 3 1 1
    Explanation 3 marks
    Truth table : 1 marks

    (OR)
    b) Minimize the following expression using the
    Boolean algebra method
    Part-C (1 x15 = 15 Marks)
    4. a) Using the K-map method, simplify the following
    Boolean function and implement the circuit diagram

    7 3 1 5

    8 3 1 5

    3 2 1 1

    7 2 1 1

    5 2 1 1

    -- 3 marks

    F = AC'D' + A'D + A'C + AB


    ---2 marks
    Circuit diagram ------ 2 marks
    5 marks

    1 mark
    Circuit 2 marks
    (OR)
    b) Construct the following using a CMOS circuit
    (i) 2 input NOR gate

    3 marks
    7 marks

    5 marks

    Course Outcome (CO) and Bloom’s level (BL) Coverage in Questions


    CO Coverage (%)
    B L C ov e r a ge ( %)

    100
    80 10 0

    60
    50
    40
    20
    0
    0
    B L1 B L2 B L3 B L4
    CO1 CO2 CO3 CO4 CO5

    Evaluation Sheet
    Name of the Student: Register No.:

    Q. No CO PO Maximum Marks Marks Obtained


    1 1 1 1
    2 1 1 1
    3.a 1 1 8
    3.b 1 1 8
    4.a 1 5 15
    4.b 1 1 15

    Consolidated Marks:

    CO Maximum Marks PO Maximum Marks


    Marks Obtained Marks Obtained
    1 25 1 25
    Total 25 5 15
    Total 25

    Signature of Course Teacher

    Signature of the Course Coordinator Signature of the Academic Advisor

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