US008315085B1

(12) United States Patent (10) Patent No.: US 8,315,085 B1

Chang et al. (45) Date of Patent: Nov. 20, 2012
(54) SRAMTIMING TRACKING CIRCUIT OTHER PUBLICATIONS
(75) Inventors: Feng-Ming Chang, Chiayi (TW); Lin, S. et al., “A Low Leakage 9T SRAM Cell for Ultra-Low Power
Chang-Ta Yang, risinchi (TW); s Operation”, GLSVLSI 2008 Proceedings of the 18th ACM Great
Huai-Ying Huang, Jhonghe (TW); Lakes Symposium on VLSI, 4 pages.
Ping-Wei Wang, Hsinchu (TW) Lai, Y.C. et al., “Robust SRAM Design via BIST-Assisted Timing
Tracking (BATT), IEEE Journal of Solid-State Circuits, Feb. 2009,
(73) Assignee: Taiwan Semiconductor Manufacturing 44(2):642-649.
Co., Ltd., Hsin-Chu (TW) * cited by examiner
(*) Notice: Subject to any disclaimer, the term of this Primary Examiner — David Lam
patent is extended or adjusted under 35 (74) Attorney, Agent, or Firm — Duane Morris LLP
U.S.C. 154(b) by 0 days.
(21) Appl. No.: 13/289,030 (57) ABSTRACT
A timing tracking circuit is configured within a functional
(22) Filed: Nov. 4, 2011 memory array, obviating the need for a separate, standalone
timing tracking circuit. A generated pulse is routed circui
(51) Int. Cl. tously through conductors enlisted for timing purposes, to
GIC II/00 (2006.01)
trigger Switching
-
of a test cell in the array, which
- -
discharges
- -

(52) U.S. Cl. ......................... 365/154; 365/201: 365/194 an associated bit line from a pre-charged high value. The
(58) Field of Classification Search .................. 365/154, pulled down signal resulting from the discharge is detected at
365/201, 194, 51, 156 a measurement unit to infer timing characteristics of the
See application file for complete search history. memory array. The timing tracking circuitry is implemented
(56) References Cited by re-purposing certain conductors, test cells and dummy
cells inserting certain conductive or nonconductive regions at
U.S. PATENT DOCUMENTS one or more layers or at Vias between layers to alter operation
6,975,532
B1 12/2005 Kosonocky et al.
of the respective conductors and cells. Cells and conductors
7, 177,177
B2 2/2007 Chuang et al. not enlisted for timing remain available for efficient, reliable
7,787,318
B2 * 8/2010 Satomi .......................... 365,201 memory access performance.
7,898,894
B2 3/2011 Chang et al.
2011 0182112 A1 7, 2011 Houston 20 Claims, 11 Drawing Sheets

110

NOMINAL
SRAM. CELS

120
PULSE X DUMMY SRAM 140
GENERATOR/ E-DIFE
MEASUREMENT
U.S. Patent Nov. 20, 2012 Sheet 1 of 11 US 8,315,085 B1

S.

-
u/
2
.
go
as ast
2
WD

t as
ver
U.S. Patent Nov. 20, 2012 Sheet 2 of 11 US 8,315,085 B1

FIG. 2

/ 200
GENERATE WORD LINE SIGNAL 210

CONDUCT WORD LINE SIGNAL ALONG FIRST PATH 220

CONDUCT WORD LINE SIGNAL ALONG SECOND

PATH COMPRISING FIRST ENLISTED BIT LINE 230

COUPLE SECOND ENLISTED BIT LINE TO POSITIVE

POWER SUPPLY VOLTAGE WIA FIRST SWITCH 240

CONDUCT WORD LINE SIGNAL TO FIRST SWITCH 250

OPEN FIRST SWITCH TO DECOUPLE SECOND ENLISTED

Bir LINE FROM Positive POWER SOPPLY votAGE 1.
CLOSE SECOND SWITCH TO COUPLE 270
SECOND ENLISTED BIT LINE TO GROUND

COUPLESECONDENLISTEDBITLINE TO PULSE
GENERATOR, TO PROVIDE TIMING TRACK SIGNAL
U.S. Patent Nov. 20, 2012 Sheet 3 of 11 US 8,315,085 B1

H.
"f)I,
º
U.S. Patent Nov. 20, 2012 Sheet 4 of 11 US 8,315,085 B1

FIG. 4

TRACKBL TRACKWL V VDD VDD

Yss Vss WL FLOAT

TRACKBL TRACK WL V VDD VDD

U.S. Patent Nov. 20, 2012 Sheet 5 of 11 US 8,315,085 B1
U.S. Patent Nov. 20, 2012 Sheet 6 of 11 US 8,315,085 B1

Nasir
SN N

N. Ni

BL Von BLB

560
U.S. Patent Nov. 20, 2012 Sheet 7 of 11 US 8,315,085 B1

019

H.
"f)I,
9

ZZ9089709

979879
U.S. Patent Nov. 20, 2012 Sheet 9 of 11 US 8,315,085 B1

FIG. 7B
NOMINAL SRAM CELS
VoD BLB BB2 VoD
PU d PU PU d PU
U.S. Patent Nov. 20, 2012 Sheet 11 of 11 US 8,315,085 B1
 US 8,315,085 B1
1. 2
SRAMTIMING TRACKING CIRCUIT Supply Voltage via a first Switch. The word line signal is
conducted to the first switch. The method includes opening
BACKGROUND the first switch, based on the word line signal, to decouple the
second enlisted bit line from the positive power supply volt
Static random access memory (SRAM) is a type of semi 5 age, and closing a second Switch, based on the word line
conductor memory that stores data in the form of bits using signal conducted along the first enlisted bit line, to couple the
bistable circuitry without the need for refreshing. An SRAM second enlisted bit line to a ground node. The second enlisted
cell may be referred to as a bit cell because it stores a bit of bit line is coupled to the pulse generator, to provide a timing
information. Memory arrays include multiple bit cells track signal to the pulse generator.
arranged in rows and columns. Each bit cell in a memory 10 In an embodiment, an apparatus includes multiple SRAM
array typically includes connections to a power Supply Volt bit cells in an array. The bit cells are arranged in a pattern
having multiple word lines and bit lines meeting at the bit
age and to a reference Voltage. Bitlines are used for accessing cells and operated for selecting a given cell by concurrently
a bit cell, with a word line controlling connections to the bit activating a word line and a bit line coupled to that given cell.
lines. A word line may be coupled to the bit cells in a row of The SRAM cells include nominal cells and at least one test
a memory array, with different word lines provided for dif 15 cell. A first bit line and a second bit line are enlisted for
ferent rows. tracking a propagation time between selecting the test cells
The time taken to access an SRAM bit cell, e.g., for a read and sensing of a resulting test current at the test cells. The first
operation, may vary due to factors including the relative posi and second enlisted bit lines are disabled from addressing the
tion of the accessed bit cell within the SRAM array, and test cells. A word line pulse generator is configured to gener
variation in operational characteristics of SRAM components ate a word line signal. A conductor is configured to conduct
such as transistors in bit cells. Reliable estimation of SRAM the word line signal to a first word line. A first electrical path
timing characteristics is important for ensuring consistency in includes the first word line and at least one other word line,
system components and high system performance. with the path intersecting the first enlisted bit line. A switch,
controllable by the word line signal, is configured to selec
SUMMARY 25 tively couple the second enlisted bit line to a positive power
Supply Voltage. A second electrical path couples the second
In an embodiment disclosed herein, a memory apparatus enlisted bit line and the word line pulse generator. At least one
includes a plurality of bit cells in an array, a plurality of word of the test cells includes a first transistor (PG) having a gate
lines and bit lines, a pulse generator, a conductor, and a timing coupled to the first enlisted bit line, and a second transistor
measurement circuit. The word lines and bit lines meet at the 30
(PD) having a gate coupled to a fixed Voltage that forces said
bit cells and are operated for selecting a given bit cell in the PD transistor into a conducting state, with the PG and PD
array by concurrently activating a word line and a bit line transistors configured to couple the second enlisted bit line to
coupled to the given cell, for reading and/or writing to one or a ground node when the word line signal on the first enlisted
bit line controls the PG transistor to conduct current.
more selected bit cells. The pulse generator is configured to
generate a test signal for operating a test bit cell at a prede 35 BRIEF DESCRIPTION OF THE DRAWINGS
termined location in the array. The test bit cell includes at least
one Switching transistor, which may include a passing gate The following will be apparent from elements of the fig
(PG) transistor and a pull down (PD) transistor of the test bit ures, which are provided for illustrative purposes and are not
cell. The conductor is configured to couple the pulse genera necessarily to scale.
tor to the test bit cell and to conduct the test signal to the test 40 FIG. 1 is a schematic diagram of a static random access
bit cell. The conductor comprises an electrical path including memory (SRAM) timing tracking apparatus in accordance
at least a part of one of said bit lines and word lines that is with an exemplary embodiment.
enlisted for timing tracking purposes. The enlisted one of said FIG. 2 is a flow diagram of a process in accordance with an
bit lines and word lines carries the test signal for changing a exemplary embodiment.
state of the Switching transistor at the selected one or more of 45 FIG.3 is a schematic diagram of a nominal SRAM bit cell
the bit cells. The timing measurement circuit is configured to in accordance with an exemplary embodiment.
detect operation of the Switching transistor and to determine FIG. 4 is a schematic diagram of SRAM test cells config
a time delay between generation of the test signal by the pulse ured for timing tracking in accordance with an exemplary
embodiment.
generator and detection of a current switched by the switch FIG. 5A is a layout diagram of a geometric layout of a
ing transistor. The delay is a function of the location of the test 50
nominal cell in accordance with an exemplary embodiment.
bit cell in the array relative to the location at which the pulse FIGS. 5B-5D are layout diagrams showing different layers
generator couples the test signal to the array. of a region of the layout shown in FIG. 5A.
In an embodiment, a method is provided of timing an FIG. 6 is a layout diagram of a geometric layout of a test
operation in a static random access memory including mul cell in accordance with an exemplary embodiment.
tiple SRAM bit cells in an array. The bit cells are arranged in 55 FIG. 7A is schematic diagram showing test cells in accor
a pattern having multiple word lines and bit lines meeting at dance with an exemplary embodiment.
the bit cells and operated for selecting a given cell by concur FIG. 7B is a schematic diagram showing nominal cells in
rently activating a word line and a bit line coupled to that accordance with an exemplary embodiment.
given cell. The method includes generating a word line signal FIGS. 7C-7D are schematic diagrams showing dummy
at a pulse generator and conducting the word line signal along 60 cells in accordance with an exemplary embodiment.
a first path including multiple word lines. The first path has a
first predetermined length. The word line signal is conducted DETAILED DESCRIPTION
along a second path having a second predetermined length.
The second path includes a first bit line enlisted for tracking This description of certain exemplary embodiments is
propagation times. The first enlisted bit line is disabled from 65 intended to be read in connection with the accompanying
addressing an SRAM cell. A second bit line, enlisted for drawings, which are to be considered part of the entire written
tracking propagation times, is coupled to a positive power description.
 US 8,315,085 B1
3 4
Various embodiments of the present disclosure provide of the SRAM and are used as vehicles to transport a signal for
timing tracking functionality for accurate, efficient monitor another purpose. In this example, the signal is transported
ing of static random access memory (SRAM) specific varia along conductor 142 about halfway across a row of the
tion. Timing tracking enables determination of when a bit cell SRAM array, and then is transported back along conductor
finishes a read or write operation. Timing tracking circuitry in 5 144 to the first (leftmost in FIG. 1) column of the array, at a
various embodiments are implemented within an existing junction.J. This topology, in which the path taken by the word
SRAM, i.e., using the SRAM itself Certain SRAM cells are line signal up to junction J has a hairpin shape, models a case
modified at a metal-1 (M1) and VIAO (between metal-0 and in which a bit cell in the last (rightmost in FIG. 1) column
M1) layers and vias, which are described in detail below. No would be accessed, e.g., for a read operation. In other words,
changes to front-end-of-line (FEOL) or MO components (or, 10 the length of the path along conductors 142 and 144 up to
e.g., contact bars or slot contacts) are required to implement junction J may be approximately equal to the width of the
the timing tracking circuitry described herein. This is advan SRAM array (distance across a row from one edge of the array
tageous, at least because FEOL and MO are sensitive to device to the other, according to the orientation of the array in FIG.
performance. 1). This routing along conductors 142 and 144 emulates the
FIG. 1 is a schematic diagram of an SRAM timing tracking 15 signal routing delay in a functional SRAM array. Other
apparatus in accordance with an exemplary embodiment. shapes and lengths for the path from delay block 130 to
FIG. 1 shows a configuration in which a timing tracking junction J may be used in other examples. Thus, the word line
circuit is configured within a functional SRAM array itself, signal is conducted (220) along a first path including multiple
obviating the need for a separate, standalone timing tracking word lines, with the first path having a first predetermined
circuit. Multiple SRAM bit cells are arranged in an SRAM length.
array 110. The nominal bit cells are arranged in a pattern The word line signal is conducted (230) from junction J to
having multiple word lines and bit lines coupled to rows and test cells 114-1 and 114-2 along a second path having a
columns of bit cells such that when a word line and a bit line second predetermined length. The second path is a vertical
are active, they select the bit cell at the point where the word path in the example of FIG. 1 and includes an enlisted bit line
lines and bit lines cross. According to the present embodi 25 TRACK WL, which is enlisted for tracking propagation
ments, certain word lines and bit lines are enlisted to serve times. The sum of the lengths of the first and second paths is
other functions in connection with testing operational delays. Such that the metal routing delay for accessing a cell at the top
The word lines and bit lines are described in greater detail right corner of array 110 is emulated. In this example, the
in the context of FIG. 3. A given bit cell is selected by enlisted conductors, including bit line TRACK WL, are dis
concurrently activating a word line and a bit line coupled to 30 abled permanently from addressing an SRAM cell to read and
the given cell. In the configuration shown in FIG. 1, a subset write a logic value in the normal way, and instead are devoted
of the SRAM cells are adapted for timing tracking, so that a to timing tracking It would also be possible to arrange for
separate timing tracking circuit external to an SRAM array is conductors and/or bit cell transistors to be enlisted tempo
not needed to emulate the array. In an embodiment shown in rarily by Switching them from an operational memory con
FIG.1, SRAM cells that provide normal SRAM functionality, 35 figuration to a timing tracking configuration using additional
including storage of data bits and read and write operations, Switching transistors (not shown).
are referred to as nominal cells 112. A subset of the SRAM Enlisted bit line TRACK BL as shown is coupled to a
cells are enlisted, or re-purposed, for timing tracking and are positive power supply voltage VDD by a switch when the
referred to as test cells 114. Two test cells 114-1 and 114-2 are switch is in the closed state. The switch may be a PMOS
shown in FIG. 1, although various numbers of test cells, 40 transistor 150 as shown in FIG. 1. Thus, TRACKBL is
including one test cell, may be used. In the exemplary pre-charged to a logical high Voltage value. The gate of tran
embodiments, the test cells 114 do not function as the nomi sistor 150 is coupled to conductor 144 to conduct (250) the
nal SRAM cells do in terms of storing data and Supporting word line signal to the transistor, to turn off (260) the transis
read/write operations. Rather, various bit lines that are other tor (open the switch), thereby decoupling TRACK BL from
wise used for addressing cells in the case of nominal cells are 45 V,. In test cell 114-1, NMOS transistor 162 is turned on by
enlisted for other purposes. Three such enlisted bit lines are provision of the word line signal on enlisted bit line
shown in FIG. 1: bit line 152 is enlisted to be coupled (tied) to TRACK WL to the gate of the transistor. NMOS transistor
a fixed voltage denoted Vine, and bit lines 154 and 156 are 164 is maintained in an “on” state by the coupling of the gate
enlisted to conduct signals TRACK BL and TRACK WL, of that transistor to enlisted bit line 152, which is coupled to
respectively, and those signals are detailed in the following 50 fixed Voltage V, which may be a logical high Voltage Such
discussion. as V. Thus, the Switch provided by transistor 162 is closed
FIG. 2 is a flow diagram of a process in accordance with an (270) to couple TRACK BL to ground. Similar functionality
exemplary embodiment. After process 200 begins, a pulse is provided at test cell 114-2 with transistors 166 and 168.
generator 120 generates (210) a word line signal. The pulse Thus, when transistor 150 is turned off, the formerly high
generator 120 may also provide measurement functionality 55 voltage at enlisted bit line TRACK BL discharges to ground
for measuring a return signal described below, e.g., by com via transistors 162 and 164 (at test cell 114-1) and via tran
mencing a timing operation. An optional delay chain 130, sistors 168 and 166 (at test cell 114-2). The pulled-low
which may include a string of inverters or other delay ele TRACK BL is coupled (280) to pulse generator 120, so that
ments, provides a fixed basic delay in case it is convenient to the pulled-down signal on TRACK BL (asserted low) that
insert a delay So as to move ahead the measurement window 60 arrives at the measurement unit (also denoted as 120) may be
in which the tracking delay will be discerned . After the measured for timing tracking, as the read operation emulated
optional delay, the word line signal is applied to cells in a in the functional SRAM (e.g., nominal cells 112) has been
region of the SRAM array 110 designated dummy SRAM completed.
140. In the example shown in FIG. 1, existing word lines 142 In this timing tracking configuration, most of the cells in
and 144 of the SRAM 110 are enlisted to convey the signal for 65 the SRAM array are unaltered from their normal SRAM
timing tracking purposes. Thus, word lines 142 and 144 are configuration and are nominal cells. Because word line con
disabled from addressing bit cells in the corresponding rows ductors 142 and 144 are enlisted to convey a word line signal
 US 8,315,085 B1
5 6
for timing tracking purposes, those conductors are disabled TRACK WL is asserted high to turn on transistor PG1-4a,
from addressing bit cells in their respective rows in the usual current flows from TRACK BL to ground along path P1
SRAM manner, so those rows are effectively disabled from designated by a dashed arrow. The other transistors of the 6T
normal SRAM functionality and are labeled dummy SRAM configuration are repurposed for the test cell as follows.
cells 140 in FIG. 1. Similarly, because enlisted bit lines 152, 5 PMOS transistor PU1-4a is forced into the “off (open
154, and 156 are repurposed to Support timing tracking func Switch) state because its gate is tied to V. CMOS transis
tionality at test cells 114-1 and 114-2 as described above, tors PU2-4a and PD2-4a, which would ordinarily form an
those bit lines are disabled from addressing bit cells in their inverter, are disabled from such inverter functionality by cou
corresponding columns in the usual SRAM manner. Thus,
other bit cells in the first column are denoted dummy SRAM 10 pling a terminal of PU2-4a to V, instead of to the drain of
PD2-4a. A terminal of PG2- 4a is configured to be electrically
cells 170. Dummy cells 140 and 170 enable the capacitive and floating by enlisting a bit line, which would ordinarily pro
resistive environment to be matched closely for accurate vide normal SRAM bit line functionality, for use as a floating
modeling. Bitlines that are tracked typically have two factors bit line FLOAT.
that determine propagation delay of signals that are carried,
namely serial resistance and parallel capacitance. Dummy 15 Thus, the normal SRAM 6T configuration is adapted with
cells have real capacitive load, and mimic the capacitance of a few modifications for timing tracking functionality. The
unenlisted bit lines in nominal cells. If dummy cells were not lower part of FIG. 2 shows how test cell 114-2 may be simi
provided, the length of enlisted bit lines would effectively larly configured to provide a path P2 for current to flow from
appear to be shorter that the lines they are intended to emulate, TRACK BL to ground. Providing multiple test cells, and
which would decrease resistance and capacitance, and which 20 thus multiple paths for the tracked cell current to flow from
might lead tracking circuitry to determine that read or write TRACK BL to ground, increases reliability, as the larger
operations have concluded prematurely. Dummy cells 140 tracked cell currents decrease tracking delay, which may be
and 170 also fill out the array. due to the switching time of transistors in the test cells. The
FIG. 3 is a schematic diagram of a nominal SRAM bit cell layout changes (relative to the layout of nominal SRAM cells)
112 in accordance with an exemplary embodiment. The struc- 25 that implement the test cells in the circuit schematic of FIG. 4
ture and function of bit cell 112 is known to one of ordinary are discussed below.
skill. Bit cell 112 includes a pair of access transistors PG1 and The transistors of the nominal bit cells and the test bit cells
PG2 biased by a word line WL and providing access to cross are formed by p regions, in regions, dielectrically coupledgate
coupled inverters 310-1 and 310-2, respectively. “PG” in PG1 regions and conductive regions, in multiple layers over which
and PG2 may stand for “passing gate' because they pass 30 the regions overlap. The regions are connected to one another
signals on the bit lines to the nodes of the cross coupled along conductors and vias extending along and between lay
inverters when the word line signal at the gate terminal of ers, according to a solid state geometric layout. It is under
transistors PG becomes true. Inverter 310-1 includes a pull-up stood by one of ordinary skill that circuit components may be
PMOS transistor PU1 and a pull-down NMOS transistor formed by forming various regions and layers over a semi
PD1, and inverter 310-2 includes a pull-up PMOS transistor 35 conductor Substrate. For example, a p-well oran n-well may
PU2 and a pull-down be formed over a substrate. Oxide diffusion (OD) regions at
NMOS transistor PD2. Transistors PG1 and PG2 respec the Surface of p or n-wells may be doped n-type or p-type and
tively are coupled to a first bit line BL (“bit line') and to a may form semiconductor active areas. Polysilicon (PO)
second bit line BLB (“bit line bar orbit line complement). regions disposed above p or n-wells may control flow of
This configuration is referred to as a 6T (six-transistor) con- 40 current between OD regions. A layer of metal typically
figuration. During standby mode, WL is not asserted, and the referred to as metal-0 (MO) may beformed above OD regions,
access transistors PG1 and PG2 disconnect the bit cell from in the form of MO oxide diffusions (MOOD). Metal-0 poly
the bit lines. The cross-coupled inverters are coupled to the silicon (MOPO) may be provided above PO regions. Vias
power Supply and reinforce each other to maintain one of two referred to as VIAO vias may be provided between MOOD and
possible logic states with a stored data bit at one of the nodes 45 a higher metal layer referred to as metal-1 (M1). Vias referred
between the inverters (node Q) and the complement of that bit to as VIA1 vias may be provided between M1 and a higher
at the other node between the inverters (node QB). For a read metal layer referred to as metal-2 (M2).
operation, BL and BLB are precharged high, and WL is An example layout for the nominal bit cells is shown in
asserted. The stored data bit at node Q is transferred to BL, FIGS.5A-5D. FIG.5A is atop (plan) view of various nominal
and the data bit at node QB is transferred to BLB. For a write 50 cells, showing components at the metal-0 polysilicon
operation, the value to be written is provided at BL, and the (MOPO) and metal-1 (M1) layers and vias between the
complement of that value is provided at BLB, when WL is metal-0 (M0) and M1 layers (such vias are referred to as VIA0
asserted. vias). FIGS. 5B, 5C, and 5D provide plan views of compo
FIG. 4 is a schematic diagram of SRAM test cells config nents at various layers of a particular nominal cell 502. FIG.
ured for timing tracking in accordance with an exemplary 55 5B shows components at the OD, polysilicon (PO), metal-0
embodiment. The six transistors shown at the top of FIG. 4 oxide diffusion (MOOD), and metal-0 polysilicon (MOPO)
may form test cell 114-1 of FIG. 1, and the six transistors layers, and VIA0 vias. FIG. 5C shows components at the
shown at the bottom of FIG. 4 may form test cell 114-2. In MOP0 and M1 layers and VIAO vias. FIG.5D shows compo
FIG. 1, only certain ones of the transistors providing a current nents at the M1 and metal-2 (M2) layers, and vias between the
path from TRACK BL to ground are shown; in FIG. 4, the 60 M1 and M2 layers (such vias are referred to as VIA1 vias).
other transistors ordinarily used for SRAM functionality (and The layout of regions and vias in and between adjacent layers
present in the nominal cells) are shown with an altered con is substantially the same in the nominal cells and in the test
figuration that is adapted for timing tracking in accordance cells; various differences are discussed below. With reference
with some embodiments. In FIG.4, NMOS transistor PD1-4a to the layout of nominal cells in FIGS.5A-5D, and the layout
is forced into the “on” (closed switch) state because its gate is 65 of test cells in FIG. 6, the alterations for enlisting various
tied to a fixed voltage V, which may be a logical high components of nominal cells for timing tracking functionality
Voltage, e.g., a positive power Supply Voltage. When in the test cells may be understood as follows.
 US 8,315,085 B1
7 8
Certain changes in the layout are made to enlist bit lines SRAM cells and may be an expanded view of dummy SRAM
580, 581,582, and 583 of FIG. 5A for timing tracking func cells 170 of FIG. 1. FIG. 7D shows dummy SRAM cells and
tionality in test cells of FIG. 6, and the equivalents in FIG. 6 may be an expanded view of dummy SRAM cells 140 of FIG.
are enlisted bit lines 680, 681, 682, and 683. Enlisted bit line 1.
680 is tied high; enlisted bit line 681 provides TRACK BL as 5 FIG. 7A shows an example of four test cells, each having
in FIG. 1; enlisted bit line 682 provides TRACK WL as in six transistors. The test cells in FIG. 7A may function like the
FIG. 1; and enlisted bit line 683 is electrically floating. Spe test cells in FIG. 4. Cell currents 703a and 704b may be
cific layout changes to effectuate Such functionality of tracked for timing tracking, e.g., as a precharged enlisted bit
enlisted bit lines are described below with respect to an exem line TRACK BL is discharged to ground as described above.
plary layout. It will be appreciated that similar alterations of 10
An edge region 702 is shown to the left of the test cells in FIG.
other layouts can achieve the same functional results and are 7A. Coupling gates of transistors 721a, 721b to ground (Vs)
encompassed within the scope of this disclosure. or configuring them to be electrically floating reduces leak
In FIG. 5A, VIAO vias 510 are provided in nominal cells age. In the example of FIG. 7A, four test cells in a 2x2
between M0 and M1 layers. These vias are removed in the test arrangement are shown, although other arrangements of test
cells as shown at locations 610 in FIG. 6, e.g., by inserting a 15
nonconductive region into the geometric layout at these loca cells, including other numbers of test cells, are possible. In the
tions. A nonconductive region optionally can be embodied as example 2X2 test cell arrangement, two test cells in the first
a gap. This alteration makes the enlisted bit line 683 float as (left) column each include a transistor (PG) coupled to
denoted by FLOAT in FIG. 6. enlisted bit lines TRACKBL and TRACK WL, and two test
In FIG. 5A, VIAO vias 512 are provided in nominal cells cells in the second (right) column each include a transistor
between M0 and M1 layers. These vias are removed in the test (PG) coupled to enlisted bit line FLOAT BL that is electri
cells as shown at locations 612 in FIG. 6, e.g., by inserting a cally floating.
nonconductive region into the geometric layout at these loca FIG. 7B shows an example of 8 nominal cells arranged in
tions. A conductor 614 is inserted at the M1 layer to bridge two columns and four rows. Other numbers of nominal cells
adjacent M1 conductors as shown in FIG. 6. These alterations 25 are possible and may be arranged in various row/column
enlist bit line 682 as TRACK WL. configurations. Each nominal cell includes transistors that
In FIG. 5D, VIA1 vias 516a and 516b are provided in a may function like the transistors in FIG. 3. Word lines WL1,
nominal cell between M1 and M2 layers. These vias are WL2, WL3, and WL4 and bit lines BL1, BLB1, BL2, BLB2
removed in a test cell as shown at locations 616, e.g., by address the nominal cells as shown in FIG. 7B.
inserting a nonconductive region into the geometric layout at 30 FIG. 7C shows an example arrangement of dummy cells
these locations. 770, which may correspond to dummy SRAM 170 of FIG. 1.
In FIG. 5A, VIAO via 518 is provided in a nominal cell FIG. 7D shows an example arrangement of dummy cells
between M0 and M1 layers. Corresponding via 618 is 740, which may correspond to dummy SRAM 140 of FIG. 1.
retained in a test cell for use in TRACK BL. In this example, word lines WL5, WL6, and WL7 that would
In FIG. 5A, VIAO via 520 is provided in a nominal cell 35 ordinarily address bit cells are enlisted to be tied low exter
between M0 and M1 layers. Corresponding via 620 is nally to support dummy cells 740 in their timing tracking role.
retained in a test cell as the load of TRACK BL. The Snaking, hairpin path provided by conductors 742 and
In FIG. 5A, VIAO vias 522 are provided in nominal cells 744 may correspond to the routing of conductors 142 and 144
between M0 and M1 layers. These vias are removed in the test in FIG.1. As shown in FIG. 7D, WL7 and WL6 are adjacent
cells as shown at locations 622 in FIG. 6, e.g., by inserting a 40 word lines. Conductors 742 and 744 are portions of these
nonconductive region into the geometric layout at these loca word lines that are enlisted to convey a word line signal for
tions. timing tracking Conductors 742 and 744 are coupled as
FIG. 6 shows that VIAO vias 624 are inserted in test cells shown, e.g., with a jumper, at the third column from left in
between MO and M1 layers to bridge MOOD to M1. This ties FIG. 7D. Conductor 744 is coupled to enlisted bit line
enlisted bit line 680 high, i.e., couples the enlisted bit line to 45 TRACK WL as shown at point J. Besides this “U-shaped
Vpp. routing, other shapes are possible as well, e.g., a staircase
At the edge of a test cell, near the edge of the SRAM array, pattern using enlisting additional word lines. Enlistment of
it is desirable to reduce current leakage that may result from additional word lines for Such a path may result in an
the timing tracking circuitry. For example, a possible leakage increased number of dummy cells and a reduced number of
path 692 at the edge of test cell region 604 is shown in FIG. 6. 50 nominal cells available for normal SRAM operations.
To reduce leakage, the following layout modifications may be Thus, various embodiments provide capabilities for moni
implemented. A conductive region 626 may be inserted in the toring full bit line back- end-of-line (BEOL) capacitance
test cell(s) at the M1 layer to reduce leakage. In FIG. 5A, loading. Process variation related to embodying for timing
VIA0 vias 528 are provided in nominal cells between M0 and circuitry is minimized, because the front-end-of-line (FEOL)
M1 layers. These vias are removed in the test cells as shown 55 and MO are kept the same, i.e., not changed for test cells
at locations 628 in edge cells 650 in FIG. 6, e.g., by inserting relative to the layout of nominal cells. Because the timing
a nonconductive region into the geometric layout at these tracking is implemented using the SRAM itself, i.e., within an
locations. AVIA1 via between M1 and M2 layers is removed existing SRAM array to avoid the need for a standalone,
at location 630 in FIG. 6, e.g., by inserting a nonconductive external timing tracking circuit, an existing SPICE model
region into the geometric layout at these locations. 60 may advantageously be used for circuit simulation. Routing
FIGS. 7A-7D are schematic diagrams of an example the path of a generated word line signal in a hairpin configu
implementation in accordance with an exemplary embodi ration, e.g., as with conductors 142 and 144 of FIG. 1, enables
ment; these diagrams provide additional details of circuitry of emulation of particular topographical characteristics, such as
SRAM array 110 of FIG. 1. FIG. 7A shows test cells 714 and an access of a cell in a remote corner (e.g., upper right corner
may be an expanded view of test cells in FIG. 1. FIG. 7B 65 of the array in FIG.1). Current leakage associated with timing
shows nominal SRAM cells and may be an expanded view of tracking functionality is reduced with modifications of the
nominal SRAM cells 112 of FIG. 1. FIG.7C shows dummy layout at test cells as described above.
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9 10
Although SRAM 6T cells have been described above, other 2. The memory apparatus of claim 1, wherein the at least
types of memory cells may be used as well, including other one Switching transistor comprises a passing gate (PG) tran
types of memory than SRAM and other types of SRAM sistor and a pull down (PD) transistor of the test bit cell.
configurations than 6T, e.g., eight transistor (8T) or ten tran 3. The memory apparatus of claim 1, wherein the plurality
sistor (10T) configurations. In Such memory types or configu 5 of bit cells comprises a plurality of static random access
rations: (1) a transistor in at least one storage node is main memory (SRAM) bit cells, said SRAM bit cells including
tained in a conductive (or nonconductive) condition typical of nominal bit cells and said test bit cell,
a predetermined logic State (e.g., forced to a condition repre wherein a first bit line and a second bit line are enlisted for
senting logic high) and used as a test cell, the transistor being testing a propagation time between generation of the test
Switched by a timing test signal along a route otherwise used 10 signal and sensing of the current Switched by the Switch
in the array layout as a bit line in a nominal cell; (2) a word ing transistor,
line similarly is decoupled from a normal (nominal) cell array wherein said first and second enlisted bit lines are disabled
and is coupled to a route (originally used as a bit line in an for random access to the bit cells,
adjacent nominal cell) as a track WL, and (3) when the track wherein each nominal cell comprises a pair of CMOS
WL turns on the transistor (such as a PG transistor and a PD 15 inverters cross coupled between two nodes and opera
transistor of a test cell in an SRAM example), a current from tionally determining a logic state, and a pair of access
track BL to VSS is generated and can be detected to stop a transistors that couple associated bit line signals and
timer that was started when the timing test signal was gener word line signals to the nominal cell for one of reading
ated. In this way, the representative time delay to and from the and changing the logic state, each nominal cell including
test cell provides a measure from which the delays along other 2O a first transistor (PG1), a second transistor (PU1), a third
paths are inferred, e.g., in an SRAM. Timing tracking meth transistor (PD1), a fourth transistor (PG2), a fifth tran
ods and circuits as described above can also be applied to 8T sistor (PU2), and a sixth transistor (PD2); wherein PU1
and 10T configurations such as those disclosed in the follow with PD1 and PU2 with PD2 form the CMOS inverters
ing patents and publications, which are hereby incorporated and have gates coupled to one of the nodes and a junction
by reference herein in their entireties: U.S. Pat. Pub. 2011/ 25 at an output coupled to an other of the nodes, the nodes
0182112 entitled “10T SRAM cell with near dual port func respectively being normally floating and coupled
tionality” to Houston; U.S. Pat. No. 6,975,532 entitled through PG1 and PG2 to complementary said associated
"Quasi-static random access memory’ to Kosonocky et al.: bit line signals when enabled by the word line signals,
U.S. Pat. No. 7,898,894 entitled “Static random access wherein each test cell includes a first transistor (PG1), a
memory (SRAM) cells' to Changet al.: U.S. Pat. No. 7,177, 30 second transistor (PU1), a third transistor (PD1), a
177 entitled “Back-gate controlled read SRAM cell” to fourth transistor (PG2), a fifth transistor (PU2), and a
Chuang et al.; and “A Low Leakage 9T SRAM Cell for sixth transistor (PD2), and at least one test cell is
Ultra-Low Power Operation” by Lin et al., GLSVLSI'08, coupled, by a third bit line enlisted for logic state main
May 4-6, 2008, Orlando, Fla., ACM 978-1-59593-999-9/08/ tenance, to a fixed Voltage to force the logic state of the
05. 35 test cell to a stable logic value Such that accessing said
Although examples are illustrated and described herein, test cell couples the test current through a predetermined
embodiments are nevertheless not limited to the details one of transistors PU1, PD1, PU2, PD2 of said test cell.
shown, since various modifications and structural changes 4. The memory apparatus of claim 3, wherein the transis
may be made therein by those of ordinary skill within the tors of the nominal bit cells and the test bit cells are formed by
Scope and range of equivalents of the claims. 40 p regions, in regions, dielectrically coupled gate regions and
What is claimed is: conductive regions, in multiple layers over which said regions
1. A memory apparatus comprising: overlap and are connected to one another along conductors
a plurality of bit cells in an array, and vias extending along and between layers, according to a
a plurality of word lines and bit lines meeting at the bit cells Solid state geometric layout:
and operated for selecting a given bit cell in the array by 45 wherein said layout of regions and vias in and between
concurrently activating a word line and a bit line coupled adjacent layers is Substantially the same in the nominal
to said given cell, for one of reading and writing to one cells and in the test cells,
or more selected bit cells, wherein at least one of a conductive path to the fixed
a pulse generator configured to generate a test signal for Voltage for forcing the logic state of the test cell, and a
operating a test bit cell at a predetermined location in the 50 conductive path for coupling current through PG1 or
array, said test bit cell including at least one Switching PG2 of a test cell to a corresponding enlisted bit line
transistor, signal when enabled by the second enlisted bit line is
a conductor coupling said pulse generator to said test bit formed by altering the solid state geometric layout of the
cell, said conductor configured to conduct the test signal nominal bit cells at the test bit cell, by one of inserting a
to the test bit cell, said conductor comprising an electri 55 conductive region and inserting a nonconductive region
cal path including at least a part of one of said bit lines into said geometric layout at least at one of the layers
and word lines that is enlisted for timing tracking pur over which the regions overlap and the Vias extending
poses, wherein the enlisted one of said bit lines and word between layers; and
lines carries the test signal for changing a state of the wherein accessing the test bit cell couples the test current
switching transistor at the selected one or more of the bit 60 through said predetermined one of transistors PU1, PD1,
cells; and PU2, PD2 according to a time delay associated with the
a timing measurement circuit configured to detect opera location of the test cell in the array.
tion of the Switching transistor and to determine a time 5. The memory apparatus of claim 4, comprising at least
delay between generation of the test signal by the pulse two said test cells, each of said two test cells including a
generator and detection of a current switched by the 65 transistor coupled to the first and second enlisted bit lines.
Switching transistor, said delay being a function of the 6. The memory apparatus of claim 5, comprising at least
location of the test bit cell in the array. four said test cells arranged in two rows and two columns, the
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11 12
test cells in one of the columns both having a transistor node by altering the Solid state geometric layout of the nomi
coupled to a fourth bit line enlisted to be electrically floating. nal bit cells at one of the test bit cells by inserting a conductive
7. The memory apparatus of claim 5, comprising a plurality region into said geometric layout at one of the layers.
of said test cells arranged adjacent to one another and coupled 16. A method of timing an operation in a static random
commonly to at least one of the enlisted bit lines. access memory including a plurality of SRAM bit cells in an
8. The memory apparatus of claim 4, wherein the SRAM array, the bit cells arranged in a pattern having multiple word
cells include at least two test cells, one of the test cells having lines and bit lines meeting at the bit cells and operated for
a transistor coupled to a fourth bit line enlisted to remain selecting a given cell by concurrently activating a word line
electrically floating. 10
and a bit line coupled to said given cell, the method compris
9. The memory apparatus of claim 4, wherein the SRAM ing:
cells further include at least one dummy bit line tracking cell, generating a word line signal at a pulse generator;
said dummy bit line tracking cell including a first transistor conducting the word line signal along a first path compris
(PG1), a second transistor (PU1), a third transistor (PD1), a ing multiple word lines, the first path having a first
fourth transistor (PG2), a fifth transistor (PU2), and a sixth 15
predetermined length;
transistor (PD2); conducting the word line signal along a second path having
wherein the PU1, PD1, PU2, and PD2 transistors of said a second predetermined length, second path comprising
dummy bit line tracking cell are configured to form a a first bit line enlisted for tracking propagation times,
pair of cross-coupled CMOS inverters, and wherein the wherein the first enlisted bit line is disabled from
PG2 transistor of said dummy bit line tracking cell is addressing an SRAM cell;
coupled to the first enlisted bit line: coupling a second bit line, enlisted for tracking propaga
wherein the transistors of the dummy bit line tracking are tion times, to a power Supply Voltage via a first Switch;
formed by p regions, in regions, dielectrically coupled conducting the word line signal to the first Switch;
gate regions and conductive regions, in multiple layers opening the first Switch, based on the word line signal, to
over which said regions overlap and are connected to one 25 decouple the second enlisted bit line from the power
another along vias extending between layers, according Supply Voltage;
to a solid state geometric layout; and closing a second Switch, based on the word line signal
wherein said layout of regions and vias in and between conducted along the first enlisted bit line, to couple the
adjacent layers is substantially the same in the nominal second enlisted bit line to a ground node; and
cells and in the dummy bit line tracking cells.
30 coupling the second enlisted bit line to the pulse generator,
to provide a timing track signal to the pulse generator.
10. The memory apparatus of claim 9, wherein the solid 17. The method of claim 16, further including turning off
state geometric layout of the nominal bit cells is altered at one the word line signal based on a track signal received at the
of the dummy bit line tracking cells by inserting a noncon pulse generator along the second enlisted bit line.
ductive region into said geometric layout at a via extending 35 18. The method of claim 16, further including:
between two of the layers. receiving a track signal at the pulse generator along the
11. The memory apparatus of claim 4, wherein a fourth bit second enlisted bit line; and
line is enlisted to be electrically floating, and said fourth determining a time interval between generation of the word
enlisted bit line is formed by altering the solid state geometric line signal and reception of the track signal.
layout of the nominal bit cells at one of the test bit cells by 40 19. The method of claim 16, further including coupling a
inserting a nonconductive region into said geometric layout at third switch, in a path between the second switch and the
one of a conductor extending along one of the layers and a via ground node, to a fixed voltage to maintain the third Switch in
extending between at least two of the layers. a closed State.
12. The memory apparatus of claim 4, wherein the second 20. An apparatus comprising:
enlisted bit line is formed by altering the solid state geometric
45 a plurality of SRAM bit cells in an array, the bit cells
layout of the nominal bit cells at one of the test bit cells by: arranged in a pattern having multiple word lines and bit
lines meeting at the bit cells and operated for selecting a
inserting a nonconductive region into said geometric lay given cell by concurrently activating a word line and a
out at one of a conductor extending along one of the bit line coupled to said given cell, the SRAM cells
layers and a via extending between at least two of the 50 including nominal cells and at least one test cell, wherein
layers, and a first bit line and a second bit line are enlisted for
inserting a conductive region into said geometric layout at tracking a propagation time between selecting the at
one of the layers. least one test cell and sensing of a resulting test current
13. The memory apparatus of claim 4, wherein one of the at said test cell, and said first and second enlisted bit lines
word lines is disabled from addressing one of the test cells by 55 are disabled from addressing said at least one test cell;
inserting a nonconductive region into said geometric layout at a word line pulse generator configured to generate a word
one of a conductor extending along one of the layers and a via line signal;
extending between two of the layers. a conductor configured to conduct the word line signal to a
first word line;
14. The memory apparatus of claim 4, wherein the third 60 a first electrical path comprising the first word line and at
enlisted bit line is formed by altering the solid state geometric least one other word line, the path intersecting the first
layout of the nominal bit cells at one of the test bit cells by enlisted bit line;
inserting a conductive region into said geometric layout to a switch, controllable by the word line signal, the first
add one of a conductor extending along one of the layers and Switch configured to selectively couple the second
a via extending between two of the layers. 65 enlisted bit line to a positive power Supply Voltage; and
15. The memory apparatus of claim 4, wherein the gate of a second electrical path coupling the second enlisted bit
a PG1 transistor of one of the test cells is coupled to a ground line and the word line pulse generator;
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13 14
wherein at least one of the test cells includes a passing gate figured to couple the second enlisted bit line to a ground
(PG) transistor having a gate coupled to the first enlisted node when the word line signal on the first enlisted bit
bit line, and a pull down (PD) transistor having a gate line controls the PG transistor to conduct current.
coupled to a fixed voltage that forces said PD transistor
into a conducting state, said PG and PD transistors con- k . . . .