Field Programmable Gate Array
(FPGA)
Prepared
By
Sisay Bogale
Presentation Overview
Fundamental concepts of Field Programmable Gate Arrays (FPGAs).
Architecture of a General FPGA Device.
Design Flow and Programming.
Application and FPGA Families.
Overview of a General FPGA Device
A Field-Programmable Gate Array (FPGA) is an integrated circuit that can be configured
by the user to emulate any digital circuit as long as there are enough resources.
An FPGA can be seen as an array of Configurable Logic Blocks (CLBs) connected
through programmable interconnect (Switch Boxes).
Modern FPGA devices consist of up to two million logic cells that can be configured to
implement a variety of software algorithms.
Modern FPGAs provide the following features:
Configurable Logic Blocks(CLB): To provide capabilities for implementing logic functions as well as
registers.
On-chip memory: To provide on-chip storage.
Hard macro intellectual property (IP) cores: such as (Ethernet MAC, Transceivers, Multipliers, DSP
blocks, …): To provide efficient complex functions.
Clock management resources: Clock distribution and frequency synthesis and clock shifting
capabilities.
Input/Output blocks: To provide the interface to outside world.
Routing resources: To provide interconnectivity among all logic blocks and hard macros.
Architecture of a General FPGA Device
The basic structure of an FPGA is composed of:
Configurable logic blocks: to implement combinational and sequential logic.
Look-up table (LUT): This element performs logic operations.
Flip-Flop (FF): This register element stores the result of the LUT.
Programmable interconnect: These elements connect elements to one another.
Configurable I/O blocks: These physically available ports get data in and out of the FPGA.
Conceptual Structure of an FPGA Device
Configurable Logic Blocks (CLB)
The logic block used in an FPGA strongly influences the FPGA speed and area-efficiency.
While many different logic blocks have been used in FPGAs, most current commercial
FPGAs use logic blocks based on: Look-up Table (LUTs).
Structure of LUT:
Cont.…
The LUT is the basic building block of an FPGA and is capable of implementing any logic
function of N Boolean variables.
this element is a truth table in which different combinations of the inputs implement different
functions to yield output values.
The limit on the size of the truth table is N, where N represents the number of inputs to the
LUT.
For the general N -input LUT, the number of memory locations accessed by the table is:
Which allows the table to implement the following number of functions:
Cont.…
FPGA Routing Architecture
Commercial FPGAs can be classified into the four groups, based on their routing architecture.
Island – Style FPGA
Row – Based FPGA
Sea – Gates FPGA
Hierarchical FPGA
The Four Classes of FPGA
An Island – Based FPGA
Configurable I/O Blocks
Used to bring signals onto the chip and send them back off again.
Typically there are pull up resistors on the outputs and sometimes pull down resistors.
The polarity of the output can usually be programmed for active high or active low output.
The Design Flow and Programming
Application and FPGA Families
Application
Specific Applications of FPGAs include:
Digital signal processing
Software-defined radio
ASIC prototyping
Medical imaging
Speech recognition, cryptography, bioinformatics, radio astronomy
FPGA Families
Two competing methods of programming FPGAs:
1. Fuse and anti-fuse
Fuse makes or breaks link between two wires
Typical connections are 50-300 ohm
One-time programmable
2. RAM-based
Memory bit controls a switch that connects/disconnects two wires
Typical connections are .5K-1K ohm
Can be programmed and re-programmed easily (tested at factory)
Cont.…
Examples of SRAM based FPGA families
Altera FLEX family
Atmel AT6000 and AT40K families
Lucent Technologies ORCA family
Xilinx XC4000 and Virtex families
Examples of Anti-fuse based FPGA families include the following:
Actel SX and MX families
Quicklogic pASIC family
Thank you
Q &A
