MODULE 1 systems, avoiding strict adherence to RISC where

1. Explain RISC design philosophy. it may limit functionality.

 Simple Instructions: o ARM processors are power-efficient, cost-
o RISC processors use basic instructions that are effective, and versatile, making them ideal for
easy for hardware to execute in one clock cycle. embedded systems and mobile devices.
o Complex operations are handled by combining
simple instructions in software. 3. Explain the architecture of a typical embedded
 Fixed Instruction Length: device based on ARM core with a neat
o Instructions have a uniform size, which makes diagram.
them easier to fetch and decode, speeding up An embedded device based on the ARM core
processing. integrates hardware and software components to
 Instruction Pipeline: control and manage specific tasks efficiently
o Tasks are broken into smaller steps that can run 1. ARM Core:
simultaneously in a pipeline, boosting The ARM processor is the heart of the system,
performance. responsible for:
 Many General-Purpose Registers:  Core: Executes instructions and processes data.
o RISC processors have lots of registers to store  Memory and Cache: Interfaces with the
data and addresses, reducing the need to access processor to store and fetch instructions/data.
slower memory. Different ARM processor versions are available
 Load-Store Architecture: to optimize for performance, power, and cost.
o Data is only processed from registers, and 2. Controllers:
separate instructions are used to move data Controllers manage the coordination between
between memory and registers. different system blocks.
Advantages:  Interrupt Controllers: Handle requests from
 Faster processing with simpler hardware. peripherals, ensuring the processor responds to
 Efficient use of memory and power. events efficiently.
 Easy to scale for high clock speeds.  Memory Controllers: Connect and manage
Drawbacks: various memory types, allowing the processor to
 Needs smarter compilers to handle complex tasks. access stored data/code.
 May require more instructions for some 3. Peripherals:
operations compared to CISC.  Provide input-output capabilities for interaction
with external devices or sensors.
2. Explain ARM design philosophy.  Examples include serial communication devices,
o ARM processors are designed to use minimal timers, and wireless modules (e.g., 802.11).
power, making them ideal for portable devices  Controllers like memory and interrupt controllers
like mobile phones and PDAs that rely on may also act as peripherals.
batteries. 4. Buses:
o ARM achieves compact code to save memory,
The bus system enables communication between the
which is important for devices with limited or ARM core, memory, and peripherals.
expensive storage like mobile phones and storage  Bus Master: The ARM processor initiates data
devices. transfers.
o Designed to work with slow, low-cost memory
 Bus Slaves: Peripherals respond to requests from
for cost savings in high-volume products like the bus master.
digital cameras.
o The processor core occupies less physical space
4. Explain the following: i) ARM Bus Technology
on the chip, reducing manufacturing costs.
o ARM processors include hardware debugging
ii)AMBA Bus Protocol iii) Memory
features, allowing software developers to monitor iv)Peripherals.
and troubleshoot code execution more effectively. i) ARM Bus Technology
o While based on RISC principles, ARM balances ARM-based embedded devices use on-chip bus
simplicity with practical needs for embedded technology to enable communication between
components like the ARM core, memory, and
peripherals. Key aspects of ARM bus technology Memory Width:
include: Defines the number of bits returned in each access
Device Classes on the Bus: (e.g., 8, 16, 32, or 64 bits).
1. Bus Masters: The ARM processor core acts as a Types of Memory:
master device, initiating data transfers. 1. ROM (Read-Only Memory): Permanently set at
2. Bus Slaves: Peripherals are typically slaves, production, used for boot code in high-volume
responding to transfer requests from masters. devices.
Bus Architecture Levels: 2. Flash ROM: Writable but slow; stores firmware
1. Physical Level: Deals with electrical or non-volatile data.
characteristics and bus width (e.g., 16, 32, or 64 3. DRAM (Dynamic RAM): Cost-effective but
bits). requires periodic refreshing.
2. Protocol Level: Defines the logical rules 4. SRAM (Static RAM): Faster but more expensive
governing communication between the processor than DRAM.
and peripherals. 5. SDRAM (Synchronous DRAM): A DRAM
ii) AMBA Bus Protocol variant capable of operating at higher clock
The Advanced Microcontroller Bus Architecture speeds.
(AMBA), introduced in 1996, is a widely used on- iv) Peripherals
chip bus protocol for ARM processors. Peripherals allow an embedded system to interact
Key Features: with external devices or sensors.
 Enables the reuse of peripheral designs across Key Characteristics:
multiple projects.  Peripherals often perform single, specific
 Offers a plug-and-play interface, reducing functions (e.g., serial communication, wireless
hardware development complexity and time to connectivity).
market.  Can be on-chip or external to the processor.
Types of AMBA Buses: Controllers as Specialized Peripherals:
1. ASB (ARM System Bus): For general system 1. Memory Controllers:
communication. o Connect and manage different memory types.
2. APB (ARM Peripheral Bus): Optimized for o Ensure that initialization code is executed during
low-power, low-bandwidth peripherals. power-up.
3. AHB (ARM High-Performance Bus): 2. Interrupt Controllers:
o Uses a centralized, multiplexed design for faster o Handle peripheral requests for processor
data throughput. attention.
o Supports higher clock speeds compared to ASB. Types of Interrupt Controllers:
iii) Memory o Standard Interrupt Controller:
Embedded systems require various types of memory Sends signals to the processor core and uses
for code storage and execution. Memory selection bitmaps to identify requesting devices.
depends on price, performance, and power o Vector Interrupt Controller (VIC):
consumption.  Prioritizes interrupts.
Memory Hierarchy:  Simplifies determination of the interrupt source.
1. Cache:
o Fastest memory located closest to the processor.
o Speeds up data transfer between the core and
main memory.
2. Main Memory:
o Larger (e.g., 256 KB to 256 MB or more) but
slower than cache.
o Stores application code and data.
3. Secondary Storage:
o Largest and slowest memory type, used for long-
term storage (e.g., hard drives, CD-ROMs).
5. Explain Embedded System software used in o Manages system resources, including peripherals,
embedded application development. memory, and processing time.
Embedded systems require software to operate and 2. System Organization:
control the hardware components. The software is o Coordinates the operation of multiple software
organized in abstraction layers to ensure efficient components.
operation. o Provides scheduling, multitasking, and resource
1. Initialization (Boot) Code allocation.
The initialization code is the first software executed Types of Operating Systems:
on the hardware. It prepares the system for operation 1. Real-Time Operating Systems (RTOS):
by performing the following steps: o Designed for time-critical applications requiring
Functions of Initialization Code: predictable response times.
1. Hardware Configuration: o Used in systems like automotive controllers,
o Sets up the target platform in a suitable robotics, and medical devices.
configuration for booting the operating system or 2. Platform Operating Systems:
application. o Handle non-real-time applications and often require
o Configures components such as memory a memory management unit (MMU).
controllers, processor caches, and hardware o Examples: Linux, widely used in consumer devices
devices. and networking.
2. Diagnostics: 4. Applications
o Performs hardware tests to verify the functionality Applications are the top layer of embedded system
of components such as memory and peripherals. software and implement the end-user functionality.
o Ensures the hardware is in working order before Features of Applications:
handing control to the operating system.  Can range from simple single-task programs to
3. Booting: complex multitasking systems.
o Loads the operating system image into memory  Built to meet specific requirements, such as
and hands over control to it. networking, imaging, or data processing.
o May involve selecting between multiple operating Examples of Embedded Applications:
systems or versions, depending on the system 1. Networking Devices:
requirements. o Home gateways, DSL modems, and 802.11
2. Device Drivers wireless communication modules.
Device drivers provide a consistent software interface 2. Mobile Devices:
for peripherals. They abstract the details of hardware o Mobile phones, the largest market segment for
devices and allow the operating system and ARM processors.
applications to interact with them seamlessly. 3. Mass Storage:
Features of Device Drivers: o Hard drives and solid-state storage systems.
 Translate high-level commands from the 4. Imaging Systems:
operating system or application into low-level o Printers and scanners, optimized for cost-
hardware instructions. sensitive, high-volume applications.
 Manage communication between the processor
and devices like sensors, displays, and 6. Explain the registers of ARM core.
communication modules. 1. General-Purpose Registers (r0 to r12):
 Ensure hardware-dependent functionality is o Used to store data or memory addresses.
encapsulated for reuse across different systems. o Versatile for arithmetic, logic, and data
3. Operating System manipulation.
An embedded system may include an operating 2. Special-Purpose Registers (r13 to r15):
system (OS) to manage resources and coordinate o r13 (Stack Pointer - SP): Manages the stack
tasks. during function calls.
Functions of the OS: o r14 (Link Register - LR): Stores the return
1. Infrastructure for Applications: address for subroutine calls.
o Provides APIs and services for applications to o r15 (Program Counter - PC): Holds the address
interact with hardware. of the next instruction to execute.
3. Program Status Registers:
o CPSR (Current Program Status Register): Fast Interrupt fiq 10001
Shows the processor's current state (e.g., flags for Request
conditions like zero or carry). Interrupt Request irq 10010
o SPSR (Saved Program Status Register): Saves Supervisor svc 10011
CPSR values during exceptions or interrupts. System sys 11111
4. Key Features: Undefined und 11011
o All registers are 32-bit. User usr 10000
o ARM operates in seven modes (e.g., User,
Supervisor, IRQ). 8. Explain the concept of Exceptions, Interrupts
o Some registers are banked for quick context
and Vector table.
switching in different modes.
Exceptions:
7. Explain the Current Program Status Register  Events that disrupt normal program flow due to
errors or special conditions.
with neat diagram.
 Examples: Undefined instructions, software
The CPSR (Current Program Status Register) is a interrupts, and aborts (e.g., memory access
32-bit register in the ARM core used to monitor and errors).
control internal operations. It holds essential Interrupts:
information about the processor's state, mode, and
 External or internal signals that temporarily stop
flags.
the normal program to execute special routines.
1. Division of CPSR (32 Bits Total):
 Examples:
o Flags (Bits 31–28): Holds condition flags for
o IRQ (Interrupt Request): External signal (e.g.,
execution (e.g., zero, carry).
button press).
o Status (Bits 27–16): Reserved for future use.
o FIQ (Fast Interrupt Request): High-priority
o Extension (Bits 15–8): Reserved for future use.
interrupt for time-sensitive tasks.
o Control (Bits 7–0): Contains the processor mode,
state, and interrupt masks. Vector Table:
2. Condition Flags (Flags Field):  A special area in memory that stores addresses of
o N (Negative Flag, Bit 31): Indicates the result of routines to handle exceptions and interrupts.
an operation is negative.  When an exception/interrupt occurs, the processor
o Z (Zero Flag, Bit 30): Set when the result of an jumps to the correct routine using this table.
operation is zero. How It Works:
o C (Carry Flag, Bit 29): Indicates a carry-out in 1. Trigger: An exception or interrupt occurs.
arithmetic operations. 2. Lookup: The processor uses the vector table to
o V (Overflow Flag, Bit 28): Set if an operation find the appropriate handler address.
causes an overflow. 3. Handler Execution: The processor runs the
3. Processor Modes (Control Field): handler routine.
o The ARM processor operates in 7 modes: 4. Return: After handling, the processor returns to
 Privileged Modes: Abort (abt), Fast Interrupt the normal execution flow.
Request (fiq), Interrupt Request (irq), Supervisor Common Exceptions/Interrupts and Addresses:
(svc), System (sys), and Undefined (und). Event Address Address
 Non-privileged Mode: User (usr). (Low) (High)
o Each mode is represented by a unique Mode[4:0] Reset 0x00000000 0x00000000
value in CPSR. Undefined 0x00000004 0xFFFF0004
4. Privileged vs. Non-Privileged Modes: Instruction
o Privileged Modes: Full read-write access to Software Interrupt 0x00000008 0xFFFF0008
CPSR. Prefetch Abort 0x0000000C 0xFFFF000C
o Non-Privileged Mode (User): Read-only access Data Abort 0x00000010 0xFFFF0010
to the control field; can read/write condition flags. Interrupt Request 0x00000018 0xFFFF0018
Processor Modes and Binary Patterns: Fast Interrupt 0x0000001C 0xFFFF001C
Mode Abbreviation Mode[4:0] in Request
CPSR
Abort abt 10111
9. Explain Core Extensions with neat diagrams o R14: Link Register (LR)—stores the return
Core Extensions in ARM Processors - Simple address for subroutine calls.
Points: o R15: Program Counter (PC)—holds the address
Core extensions are additional hardware components of the current instruction being executed.
placed alongside the ARM core to improve 2. Program Status Register (PSR):
performance, manage resources, and offer extra o Stores information about the processor state, such
functionality. They help in handling specific as condition flags, interrupt states, and operating
applications more efficiently. modes.
Types of Core Extensions: 3. Floating-Point Registers (if available):
1. Cache: o Used for floating-point operations in ARM cores
 Purpose: Provides faster access to data by storing with floating-point units (FPU).
frequently used instructions and data near the 4. Banked Registers:
processor. o In privileged modes, some registers (e.g., SP, LR)
 How It Works: Cache stores data between the are replaced by banked versions specific to the
processor and slow external memory to reduce mode to facilitate efficient interrupt handling.
access time. 5. CPSR (Current Program Status Register):
 Types: o Stores the current processor state, including:
 Von Neumann Architecture: Combines  Condition flags (Zero, Negative, Carry,
both data and instructions in a single unified Overflow).
cache.  Processor mode (User, Supervisor, IRQ, etc.).
 Harvard Architecture: Uses separate caches 6. SPSR (Saved Program Status Register):
for data and instructions. o Holds the state of CPSR during exceptions or
2. Tightly Coupled Memory (TCM): interrupts.
 Purpose: Provides high-speed SRAM memory 7. Special Registers for Debugging and Control:
close to the processor to ensure predictable, o Used for memory access, debugging, or hardware
deterministic execution in real-time systems. control (e.g., Memory Address Register).
 Benefit: Guarantees consistent timing for
fetching instructions/data, which is important in 11. Explain the Pipelining (three stage) used in
applications requiring real-time performance. ARM instruction execution with diagram.
3. Memory Management: ARM processors include Pipelining is a technique used in RISC processors,
hardware components for memory management, like ARM, to improve instruction execution speed. It
which allow efficient access and allocation of allows the processor to work on multiple instructions
memory resources. simultaneously, improving overall performance.
4. Coprocessor Interface: This allows integration In a three-stage pipeline, the instruction execution
of additional specialized processing units (called process is divided into three distinct stages:
coprocessors) for performing specific tasks, such 1. Fetch (F): Fetches the instruction from memory.
as floating-point operations, encryption, etc. 2. Decode (D): Decodes the fetched instruction and
prepares it for execution.
10. Explain ARM core data flow model with a neat 3. Execute (E): Executes the instruction and writes
diagram or Explain ARM processors the result back to the register.
fundamentals with neat diagram. Stages of the Three-Stage Pipeline:
1. Fetch (F): The processor fetches the instruction
Registers in the ARM Core
from memory. The instruction is loaded into the
ARM core registers are critical storage elements used
instruction register for the next step.
during data processing and instruction execution.
2. Decode (D): The instruction is decoded to
1. General-Purpose Registers:
identify which operation to perform. Operands are
o ARM cores have 16 general-purpose registers
read from registers.
(R0–R15).
3. Execute (E): The instruction is executed (e.g.,
o R0 to R12: Data registers for arithmetic, logic,
arithmetic operations, data transfer).The result is
and data storage operations.
written back to a register or memory if needed.
o R13: Stack Pointer (SP)—manages function call
stacks.
MODULE 3  Second Generation:
1. Differentiate Embedded vs General computing o Built around 16-bit microprocessors or 8/16-bit
system microcontrollers.
o More complex instruction sets; some included
Featu General Purpose Embedded System
embedded OS.
re Computing
o Examples: Data acquisition systems, SCADA.
System
 Third Generation:
Defin Combination of Combination of
o Built around 32-bit microprocessors or 16-bit
ition generic hardware special-purpose
microcontrollers.
and a General hardware and
o Use of DSPs, ASICs, and instruction pipelining.
Purpose Operating embedded OS for
o Applications in robotics, media, networking, etc.
System (GPOS) for executing specific
 Fourth Generation:
executing a variety applications.
o Introduction of SoC, multicore processors, and
of applications.
reconfigurable processors.
Oper Contains a General May or may not o High-performance RTOS for advanced
ating Purpose Operating contain an operating
functionalities.
Syste System (GPOS). system for functioning. o Examples: Smartphones, MIDs.
m  Next Generation:
User Applications are Firmware is pre- o Future systems expected to meet growing
Progr alterable by the programmed and demands in performance, power, and efficiency.
amm user. The end-user generally non-alterable 2. Based on Complexity and Performance
abilit can re-install the by the end-user (with
 Small-Scale Embedded Systems:
y OS and add/remove exceptions for kernel
o Simple applications; low performance, low-cost
applications. flashing).
8/16-bit processors.
Perfo Performance is Focused on
o May not include an operating system.
rman key; faster application-specific
o Example: Electronic toys.
ce performance is requirements like
 Medium-Scale Embedded Systems:
Focus usually better. performance, power,
o Moderate complexity in hardware and firmware.
and memory usage.
o Use of 16/32-bit processors; often include
Powe Less tailored Highly tailored for
embedded OS.
r towards reduced power-saving modes
o Example: Home automation systems.
Effici power supported by the
 Large-Scale Embedded Systems:
ency requirements or hardware and OS.
o Highly complex; used in mission-critical
power management
applications.
options.
o Built with high-performance 32/64-bit RISC
Resp Response Response time is
processors or multicore systems.
onse requirements are critical for certain
o Example: Aerospace systems.
Time not time-critical. types, such as mission-
3. Based on Deterministic Behavior
critical systems.
 Hard Real-Time Systems:
Exec Need not be Deterministic
o Strictly time-critical; tasks must execute within a
ution deterministic in execution behavior is
fixed deadline.
Beha execution behavior. required for certain
o Example: Airbag systems in cars.
vior types, such as "Hard
 Soft Real-Time Systems:
Real-Time" systems.
o Deadlines are important but not critical; minor delays
are acceptable. Example: Video streaming.
2. Explain the classification of Embedded System 4. Based on Triggering
1. Based on Generation  Event-Triggered Systems: Actions triggered by
 First Generation: external events (e.g., a button press). Example:
o Built around 8-bit microprocessors or 4-bit Door sensors.
microcontrollers.  Time-Triggered Systems:Actions triggered at
o Simple hardware with firmware in assembly code. specific time intervals. Example: Industrial
o Examples: Digital telephone keypads, stepper process controllers.
motor controllers.
3. List the major applications and puropse of o Example: Mobile phones with keypads, screens,
Embedded system. and alerts.
Major Application Areas of Embedded Systems
1. Consumer Electronics: Camcorders, cameras, 4. Explain the elements of an Embedded System
etc. with block diagram.
2. Household Appliances: TVs, washing machines, An embedded system is composed of multiple
refrigerators, microwaves. functional blocks that work together to achieve the
3. Home Automation and Security: Air desired functionality.
conditioners, fire alarms, CCTV cameras. 1. Processor (Controller)
4. Automotive Industry: ABS, engine control, o Acts as the "brain" of the system.
navigation systems. o Can be a:
5. Telecom: Mobile phones, telephone switches,  Microprocessor: Performs processing and
multimedia apps. control.
6. Computer Peripherals: Printers, scanners, fax  Microcontroller: Combines processing with
machines. peripherals.
7. Networking Systems: Routers, switches, hubs,  DSP: Used for signal processing.
firewalls.  FPGA: Programmable logic for specific tasks.
8. Healthcare: ECG machines, scanners, EEG  ASIC/ASSP: Application-specific processing
systems. chips.
9. Measurement and Instrumentation: 2. Memory
Multimeters, oscilloscopes, PLC systems. o Stores the control algorithm, data, and temporary
10. Banking and Retail: ATMs, POS systems, information.
currency counters. o Types:
11. Card Readers: Barcode scanners, smart card  ROM (e.g., OTP, PROM, EEPROM, FLASH):
readers, handheld devices. Stores firmware, typically non-modifiable by the
Purpose of Embedded Systems user.
1. Data Collection, Storage, and Representation:  RAM (e.g., SRAM, DRAM, NVRAM): Used as
o Collects data (text, voice, image, video). working memory for operations.
o Example: Digital cameras store and display 3. Input Devices
images. o Collects data from the environment or user.
2. Data Communication: o Examples: Sensors, keyboards, push-button
o Transfers data using wired or wireless mediums. switches.
o Example: Routers and switches for network 4. Output Devices
communication. o Provides feedback or actions to the user or
3. Data (Signal) Processing: environment.
o Processes signals like voice, image, or video for o Examples: LEDs, LCD displays, buzzers,
specific functions. actuators.
o Example: Digital hearing aids process sound for 5. Communication Interface
hearing improvement. o Enables data exchange within subsystems or
4. Monitoring: external devices.
o Tracks and monitors variables like heartbeats or o Onboard communication: I2C, SPI, UART,
signals. parallel buses.
o Example: ECG machines monitor heartbeats. o External communication: Infrared, Bluetooth,
5. Control: Wi-Fi.
o Adjusts variables like temperature or speed based 6. Power Supply
on sensor inputs. o Provides the required power for all components to
o Example: Air conditioners control room operate.
temperature. 7. Software/Firmware
6. Application-Specific User Interface: o The control algorithm that drives the system's
o Provides user interaction through buttons, functionality.
screens, or sounds.
5. Differences between Microprocessor and Progra Requires more code; Instructions act
Microcontroller mming simpler instructions. like macros,
Feature Microprocessor Microcontroller Comple achieving
Definiti A CPU chip capable An integrated xity functionality with
on of performing chip with CPU, fewer lines of
arithmetic and logical RAM, ROM, code.
operations. timers, and I/O Instruct Single, fixed-length Variable-length
ports. ion instructions. instructions.
Depend Requires external Self-contained, no Length
ency chips (timers, need for external Silicon Less silicon usage More silicon
memory, etc.) for components for Usage and lower pin count. required for
functioning. basic functioning. complex
Design General-purpose, Application- instruction
suitable for multiple oriented, designed decoding.
applications. for specific tasks. Architec Always uses Harvard Can use either
I/O Requires external Contains built-in ture architecture. Harvard or Von
Ports chips (e.g., 8255) to I/O ports Neumann
implement I/O ports. configurable for architecture.
multiple purposes.
Market High-end Embedded 7. Explain Big and Little Endian formats
Target applications requiring systems where Feature Little-Endian Big-Endian
high performance. performance is Definition Lower-order byte is Higher-order byte
less critical but stored at the lowest is stored at the
integration is key. memory address. lowest memory
Power Limited power- Includes address.
Saving saving features. extensive power- Byte Data stored as: Data stored as:
saving options. Storage Byte0 → Byte1 → Byte3 → Byte2
Order Byte2 → Byte3. → Byte1 →
6. List the differences between RISC and CISC Byte0.
Feature RISC (Reduced CISC (Complex Memory Little end (least Big end (most
Instruction Set Instruction Set Address significant byte) significant byte)
Computing) Computing) Order comes first in comes first in
Instruct Fewer instructions. Greater number memory. memory.
ion of instructions. Example Stored as: Byte0 Stored as: Byte3
Count (4-byte (lowest address), (lowest address),
Instruct Supports pipelining, Generally lacks Data) Byte1, Byte2, Byte2, Byte1,
ion leading to faster instruction Byte3 (highest Byte0 (highest
Pipelini execution. pipelining. address). address).
ng
Instruct Orthogonal (any Non-orthogonal 8. Differentiate Harvard and princeton
ion Set instruction operates (instructions architecture.
on any specific to
register/addressing registers/addressi Feature Harvard Von-Neumann
mode). ng modes). Architecture Architecture
Operati Only memory Operations can be Bus Separate buses for Single shared
ons operations are load register or Structur instruction and data bus for
and store; others are memory-based, e fetching. instruction and
register-based. depending on the data fetching.
instruction. Perform Easier to pipeline, Lower
Register Large number of Limited number ance enabling high performance
s registers available. of general- performance. compared to
purpose registers. Harvard
 architecture. o Allows erasing and reprogramming in sectors or
Cost Comparatively higher Cheaper. pages.
cost. o High storage capacity with faster access
Memory No memory alignment Allows self- compared to EEPROM.
Alignme problems. modifying code. o Commonly used in embedded systems for code
nt storage.
Progra Stored separately, Stored together, 6. Non-Volatile RAM (NVRAM):
m and preventing accidental increasing the o Combines static RAM (SRAM) with a battery
Data program memory risk of backup.
Memory corruption. accidental o Retains data even without external power supply.
program o Used when long-term data retention is required.
memory Types of RAM (Random Access Memory) used in
corruption. Embedded Systems:
1. Static RAM (SRAM):
9. Explain different types of ROMs and RAMs o Stores data in flip-flops using transistors.
o Fastest form of RAM with low latency.
that are used in an Embedded System.
o Does not require refreshing, making it more
Types of ROMs (Read-Only Memory) used in efficient.
Embedded Systems: o Expensive and low in storage capacity compared
1. Masked ROM (MROM): to DRAM.
o One-time programmable device.
2. Dynamic RAM (DRAM):
o Programmed during manufacturing using a
o Stores data as charge in a capacitor, requiring
hardwired technology. periodic refreshing.
o Low cost for high-volume production.
o More cost-effective and has higher storage
o Cannot be modified or updated after capacity than SRAM.
programming. o Slower than SRAM due to the need for constant
2. Programmable Read-Only Memory (PROM) / refreshing.
One-Time Programmable Memory (OTP): o Commonly used for larger memory requirements.
o Not pre-programmed; the user programs it.
3. Non-Volatile RAM (NVRAM):
o Uses fuses that are burned to store data. o A combination of static RAM with battery
o Once programmed, it cannot be reprogrammed.
backup.
o Low-cost option for production after code
o Data is retained even if the power is lost.
finalization. o Suitable for applications requiring persistent data
3. Erasable Programmable Read-Only Memory storage.
(EPROM): o Used when regular RAM is not enough to retain
o Can be erased and reprogrammed. critical data during power loss.
o Erased using ultraviolet (UV) light through a
quartz window.
o Requires removal from the system for erasing and
reprogramming.
o Flexible but tedious reprogramming process.
4. Electrically Erasable Programmable Read-
Only Memory (EEPROM):
o Can be erased and reprogrammed in-circuit using
electrical signals.
o Can be erased and reprogrammed at the byte
level.
o Faster reprogramming compared to EPROM.
o Limited capacity compared to other ROM types.
5. Flash Memory:
o A modern variant of EEPROM with larger
capacity.
10. Explain the following terms Sensors,  Key Features:
Actuators, optocoupler. o Uses two wires: SDA (Serial Data) and SCL
Sensors: (Serial Clock).
 Definition: Sensors are devices that detect o Supports multiple devices on the same bus
physical or environmental changes and convert (master-slave configuration).
them into electrical signals that can be processed o Typically supports speeds from 100 kbps
by an embedded system. (standard mode) to 3.4 Mbps (high-speed mode).
 Function: They serve as input devices that o Low power consumption.
measure various environmental variables such as o Master device controls the clock, and the data is
temperature, humidity, light, pressure, etc. shared between devices via the same bus.
 Example: A temperature sensor detects the 2. SPI (Serial Peripheral Interface)
temperature of the environment and converts it  Type: Synchronous serial communication
into an electrical signal that the embedded system protocol.
can process. Other examples include magnetic  Usage: Primarily used for high-speed
Hall effect sensors and humidity sensors. communication between microcontrollers and
Actuators: peripherals like sensors, SD cards, and displays.
 Definition: Actuators are devices that convert  Key Features:
electrical signals into physical actions or motion. o Typically uses four wires: MISO (Master In Slave
 Function: They serve as output devices that Out), MOSI (Master Out Slave In), SCLK (Serial
perform actions in response to signals from the Clock), and SS (Slave Select).
embedded system. They are used to control o Full-duplex communication (can send and receive
physical systems, such as motors or valves. data simultaneously).
 Example: A stepper motor is a common o Faster than I2C (up to several Mbps).
actuator that moves in precise steps when it o Does not support multiple devices on the same
receives electrical signals, allowing for controlled bus as easily as I2C.
mechanical movements. o Requires more pins for larger systems (compared
Optocoupler: to I2C).
 Definition: An optocoupler (also called an
optoisolator) is a solid-state device used to isolate 5. Zigbee
different parts of a circuit, preventing electrical  Type: Low-power wireless mesh network
noise or high voltages from affecting the sensitive protocol.
parts of the system.  Usage: Zigbee is used in applications such as
 Function: It typically consists of an LED and a home automation, smart meters, and industrial
phototransistor in a single package. When an control systems.
electrical signal is applied to the LED side, it  Key Features:
emits light, which activates the phototransistor on o Operates in the 2.4 GHz, 900 MHz, and 868 MHz
the other side, passing the signal while frequency bands.
maintaining isolation. o Low power consumption, designed for battery-
 Example: Optocouplers are used for circuit operated devices.
isolation, signal amplification, and noise o Supports mesh networking, which allows devices
suppression in both input and output circuits of to relay data, extending the range of the network.
an embedded system, ensuring that high voltages o Typically has a range of 10-100 meters depending
or electrical interference do not affect the rest of on the environment.
the system. o Offers low data rates (up to 250 kbps), making it
suitable for simple control and monitoring
applications.
11. Define the following communication Interface
devices I2C, SPI, Bluetooth, wifi, zigbee.
1. I2C (Inter-Integrated Circuit)
 Type: Serial communication protocol.
 Usage: I2C is commonly used to connect low-
speed devices like sensors, EEPROMs, and
microcontrollers in embedded systems.
MODULE 5 Types of Operating Systems
1. What is kernel. Mention the functions of real 1. General Purpose Operating System (GPOS)
time kernel.  A GPOS is used for everyday tasks on regular
A kernel is the core component of an operating computers like desktops and laptops.
system that manages system resources and provides  It’s flexible and designed to handle a variety of
essential services for software applications. programs, such as web browsers, games, and
Functions of a Real-Time Kernel office software.
1. Task/Process Management  These systems don’t guarantee fast or predictable
o Sets up memory for tasks. performance for specific tasks. For example, if
o Loads task code into memory. many apps are running, some might respond
o Allocates system resources. slower.
o Creates and manages Task Control Blocks Examples: Windows XP, MS-DOS, Linux (like
(TCBs). Ubuntu)
o Handles task termination and deletion. Where it’s used:Home and office computers.
2. Task/Process Scheduling 2. Real-Time Operating System (RTOS)
o Shares CPU time among tasks.  A RTOS is built for tasks that need to happen on
o Uses scheduling algorithms to achieve time and in a predictable way.
deterministic behavior.  It ensures critical tasks are completed within strict
3. Task/Process Synchronization time limits, no matter how many tasks are
o Manages concurrent access to shared resources. running.
o Facilitates communication between tasks.  Used in devices where timing is very important,
4. Error/Exception Handling like robots, medical machines, or airplanes.
o Handles system and task-level errors like Examples: Windows CE , QNX, VxWorks
timeouts, deadlocks, and divide-by-zero. Where it’s used: Industrial machines, medical
o Uses mechanisms like watchdog timers for equipment, and embedded systems (e.g., a car's
timeouts. control system).
5. Memory Management
o Allocates fixed-size memory blocks for tasks to 3. Defferentiate between task, process, thread.
avoid fragmentation. Aspect Task Process Thread
o May implement optional memory protection. Definiti A general A program A smaller
o Supports virtual memory in systems with on unit of work in unit of
secondary storage. to be execution, execution
6. Interrupt Handling performed. including within a
o Manages hardware and software interrupts. resources process.
o Supports nested interrupts to prioritize high- allocated
priority tasks. by the OS.
o Separates handling for synchronous (task-related) Relation Can refer to Contains Exists
and asynchronous (external device) interrupts. either a one or within a
7. Time Management process or a more process;
o Provides accurate time references using a real- thread in the threads. cannot
time clock (RTC). OS context. function
o Handles periodic timer interrupts (timer ticks) to independent
update system time and manage periodic tasks. ly.
Executi Can be Executes Shares
2. Define operating system. Explain types of on mapped to a independen memory
operating system. process or tly with its (code, data,
An Operating System (OS) is software that acts as a thread. own heap) with
bridge between you (the user) and the computer memory. other
hardware. threads of
It helps run applications, manage hardware resources the same
(like memory, CPU, and storage), and makes sure process.
everything works together smoothly. Resourc May involve Allocates Shares
es CPU, and uses
resources of o Process A holds Resource X and waits for
memory, I/O, separate the parent Resource Y, held by Process B.
etc., memory process but o Process B holds Resource Y and waits for
depending on (code, data,
has its own Resource X, creating a cycle.
its mapping. stack). stack and 2. Key Conditions for Deadlock:
registers. o Mutual Exclusion: Only one process can use a
Creatio Depends on Expensive Lightweight resource at a time.
n Cost whether it due to OS and o Hold and Wait: Processes hold resources while
maps to a overhead. inexpensive waiting for others.
process or . o No Preemption: Resources cannot be forcibly
thread. taken from a process.
Concurr Can enable Supports Enables o Circular Wait: A circular chain of processes
ency parallelism concurrenc finer- exists, each waiting for a resource held by the
through y by grained next.
threads or running multitaskin 3. Example:
multiple multiple g within a o Two cars stuck in a narrow alley where each
processes. processes. process. waits for the other to move first.
Exampl Downloading Running a Handling a 4. Solution:
es a file, web web request o Avoid Deadlocks: Use careful resource
updating the browser or within a allocation (e.g., traffic lights).
UI. a text server o Detect and Recover: Identify deadlocks and
editor. process. terminate or restart one process.
o Prevent Deadlocks: Break one of the four
4. Explain Task Synchronisation Issues OR conditions (e.g., allow resource preemption).
Explain Racing Condition and Deadlock
5. Explain Integration and Testing of Embedded
Condition.
Hardware and Firmware.
Racing Condition
A racing condition occurs when multiple processes Out-of-Circuit Programming:
access and modify shared data simultaneously,  Firmware is embedded into the chip outside the
leading to unpredictable outcomes. hardware board using a programming device.
1. What happens in a Race Condition?  Steps:
o Multiple processes or threads compete to modify o Remove the chip, program it, and place it back
shared resources. into the hardware.
o The result depends on the order of execution, o Suitable for small-scale production or
which can vary each time. development prototypes.
2. Example:  Drawbacks:
o Two threads increment a shared variable o Time-consuming and prone to chip damage due to
(counter), but due to process switching, one frequent handling.
thread overwrites the other's changes. o Difficult to upgrade firmware after deployment.
3. Key Issues: In-System Programming (ISP):
o The high-level operation (e.g., counter++) is not  Firmware is embedded directly onto the chip
atomic (doesn’t execute as a single CPU cycle). while it’s still on the board.
o Intermediate steps can be interrupted by another  Uses serial communication (e.g., SPI, JTAG).
process, causing incorrect results.  Steps:
4. Solution: Use mutual exclusion mechanisms like o Connect the board to a PC.
semaphores, mutexes, or locks to ensure only one o Use an ISP utility to send and embed the
process can access the shared data at a time. firmware.
Deadlock Condition o Restart the device to test functionality.
A deadlock condition occurs when processes wait  Advantages:
indefinitely for resources held by one another, and no o Easy and quick for development and updates.
process can proceed. o Suitable for upgrading firmware after
1. What happens in a Deadlock? deployment.
6. Explain Functional Requirements and non- o The RTOS should be straightforward to integrate
Functional Requirements for Choosing an and operate.
RTOS. 5. After-Sales Support
o For commercial RTOS, ensure support services
Functional Requirements
for bug fixes, patches, and issue resolution are
These are the technical capabilities an RTOS must
reliable.
support to meet the needs of the embedded system:
7. Explain IDE Embedded System Development
1. Processor Support
o Ensure the RTOS supports the processor
Environment.
The Embedded System Development Environment
architecture you are using.
is the setup used to design, develop, and test
2. Memory Requirements
embedded systems. It includes both hardware and
o Check the ROM and RAM required by the RTOS.
software tools.
o Confirm it fits within the memory constraints of
1. Development Computer (Host PC): The main
the system.
computer used for writing and debugging
3. Real-Time Capabilities
embedded software.
o Evaluate if the RTOS meets the timing and
scheduling needs of the system. 2. Integrated Development Environment (IDE)
o A software tool for writing, compiling, and
o Analyze task scheduling and standards for real-
debugging code for the embedded system.
time behavior.
o Bundles key tools:
4. Kernel and Interrupt Latency
 Text Editor (for writing code)
o Ensure the kernel minimizes delays when
 Cross-Compiler (for converting code to
handling interrupts.
machine language)
5. Inter-Process Communication (IPC) and
 Linker (for combining program parts)
Synchronization
 Debugger (for testing and fixing issues).
o Verify the RTOS provides adequate tools for task
3. Electronic Design Automation (EDA) Tools:
communication and synchronization.
Used for designing the hardware of the embedded
6. Modularization Support
system.
o Check if the RTOS allows selecting only the
4. Emulator Hardware: A device used for testing
needed modules for optimization.
and debugging the embedded system.
7. Networking and Communication Support
5. Signal Sources: Tools like function generators
o Confirm the RTOS supports the necessary
that simulate input signals for testing.
communication protocols and interfaces.
6. Debugging Tools: Devices like Digital CRO
8. Development Language Support
(oscilloscope), multimeter, and logic analyzers
o Check if the RTOS supports programming
used to analyze the system during testing.
languages like Java, C#, or others, along with
7. Target Hardware: The actual embedded device
their required runtime environments (e.g., JVM or
where the code will run.
.NETCF).
Non-Functional Requirements
These factors consider the usability, cost, and support
aspects of the RTOS:
1. Custom or Off-the-Shelf
o Decide between developing a custom RTOS or
using a prebuilt one.
o Consider costs, licensing, development time, and
skill availability.
2. Cost
o Evaluate the total cost, including development,
licensing, and maintenance.
3. Development and Debugging Tools
Availability
o Ensure there are adequate tools for developing,
testing, and debugging with the RTOS.
4. Ease of Use