2021 IEEE 6th International Conference on Intelligent Computing and Signal Processing (ICSP 2021)

Analysis of Low-Noise Amplifier

Jipeng Liu
ECSE Department
2021 6th International Conference on Intelligent Computing and Signal Processing (ICSP) | 978-1-6654-0413-6/20/$31.00 ©2021 IEEE | DOI: 10.1109/ICSP51882.2021.9408677

Rensselaer Polytechnic Institute

Troy, NY, 12180, USA
E-mail: ljpljp99@163.com

Abstract—Low-noise amplifiers (LNAs) are some of the main variables to encounter LNA design limitations. It is a
simplest yet the most essential devices in the field of engineering. well-known fact that remote communication systems with high
In its most basic sense, an LNA is an electronic device that boosts speed have been developing for the past five years [1]. To
a lower-power signal to a sufficient level without creating solve the problem of high data rate, remote interchanges with a
significant disruption in the circuit's signal-to-noise ratio. In this frequency range from 3.1 to 10.6 GHz, and short separation as
study, the author tried to create an LNA design through various well as ultra-wideband are rising. To execute a UWB
techniques and optimization. Specifically, the researcher focused framework, two robust methodologies have been proposed.
on several ways to achieve the goals of creating an LNA, such as
The two methodologies the use of a Multi-band OFDM
the Multi-band OFDM modulation, polarity modulation or short
modulation and the use of polarity modulation or short pulses
pulses transmission, and other types of techniques that have been
utilized in various studies. Accordingly, the study proceeds with
transmission. A front wideband LNA is fundamentally
the creation of the circuit design and the analysis of various unconcerned with receiver architecture, unless standards have
aspects related to it, such as the use of complementary not been finished. Accordingly, some strict requirements must
metal-oxide–semiconductors (CMOS), designing of bias circuits, be met by the amplifier itself. This includes the reduction of
creation of linear dynamic indicators, and the balancing of return loss through the use of broadband input matching,
power consumption and functional stability. By the end of the suppression of mixer noise by increasing gain, enhancing and
study, the author has found out that despite the effectiveness of improving receiver sensitivity through Low Noise Figure
the use of inductive source degeneration, the inevitable (LNF), as well as increasing battery duration through lower
performance loss suggests the need for further research in better energy consumption. In CMOS innovation, few solutions are
materials and the improvement of the input matching network existing for high-frequency wideband amplifiers. To bring the
layout. bandwidth to work near gadget, distributed amplifiers will
devour massive power and zone.
Keywords-Low Noise Amplifier; CMOS; Linear Dynamic
Indicators; MM-Wave Circuits II. METHOD
I. INTRODUCTION In order to reach this study's objectives, LNA analysis is
done in the research paper. LNA is attached to BPF
LNA is also called a low noise amplifier. Remote appropriately and lumped components are used to design LNA.
communication systems have a very significant part, which is Particularly, lumped components are used to design BPF.
known as a low noise amplifier. The execution of the reception Accordingly, although it is possible, the author believes that it
of the complete system is conditioned by the LNA, which is is not necessary to design the IMN (Input Matching Network)
the receiver's main phase. To fulfill various restrictions in the in the amplifier's front side. Rather, both the BPF and LNA
design of radio frequency, it is not easy to acquire complete will be coordinated as they remain in the same block therefore
specifications. Depending on the primary specification, two acting as a singular block. The ISM band is used in every
specific methods, including low noise figure search and the electronic gadget from simple devices such as Bluetooth to a
high value of gain, are used to design an LNA. Nonetheless, microwave oven. As it is liberated from the ISM band's cost,
designing a high-frequency MOS configuration could be components design provides excellent help for engineers and
tedious, which means that it requires a careful approach on the innovative business people to remember the short range of
specifications of the circuit. This usually leads to an iterative electromagnets. The receiver dimensions will be diminished.
cycle that is helped by software tools in order to fulfill the Circuit complexity will be reduced when BPF with LNA is
design specifications. arranged in one practical block. To level up the antenna signal,
Therefore, the dispersing parameters, also known as placing an LNA is more practical to avoid feed line losses
S-parameters, are the most emblematic methodology in from reception (outside) to recipient (indoor) rather than
portraying these circuits. Other than currents and voltages, building a larger radio wire, i.e., antenna. Such a transistor will
simply power signal contemplations are evaluated and be used to output the least noise figure and high gain to design
calculated in the process. What is more, in coordinating with BPF-LNA. Because of cost adequacy and strength, it is highly
the circuit, these parameters or variables mirror the expected that business individuals will value this research.
input/output and gain the power. That is because no model is ISM radio, GPS receiver, cordless telephone, remote LNA,
available there, which relates or links physical qualities of the satellite correspondence, cell handset, and many more
semiconductor (transistor) and the S-parameters that show the numerous applications are presented in which LNA is utilized.

978-1-6654-0413-6/21/$31.00 ©2021 IEEE

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 III. OVERVIEW OF LOW NOISE CMOS AMPLIFIER cascade degrade during high frequencies. This is because of
In receiver execution, the central aspect of the receiver the fact that as frequency increases in the circuit so the
front end is LNA. The circuit must be appropriately designed substrate parasitic admittance located at the drain-source
in order to make an LNA circuit. Various and numerous common node. In turn, it will have a noticeable drain noise in
strategies have been put forward for the advancement of LNA the output due to the decrease of impedance in origin found in
design. This part has reviewed the accessible features of LNA the upper transistor. In mm-wave frequencies, the cascade is
circuit designs and their advancement methods. In CMOS generally utilized. Similar to the CS stage, cascade is
configuration, stages are build-up, which are called Common appropriate for narrowband applications. Additionally, in both
Source (CS) or Common Gate (CG). Cascade is also a stage multi- and wideband applications, the utilization of feedback
that can be reviewed as a CS stage reuse arrangement that is mechanisms (or methods) help make the use of cascade stage
extensively utilized in CMOS RF LNAs [2]. Experiences of conceivable. Another approach to utilize cascade setup in a
designers plus LNA are configured by a particular application wideband application is utilizing confounded LC coordinating
on which picking the appropriate circuit relies. The designer's organizations at the input.
regulation is to pick an appropriate LNA circuit where some of IV. CIRCUIT DESIGN
the LNA attributes are a higher priority than the others and for
each application. The two most extensively utilized transistors CS at the principal and cascade at the subsequent stage is
in CMOS LNA are CS and CG [1]. the best geography for two-phase LNA. It explains that the
mm-wave band cascade contains a helpless noise figure
Great noise execution plus gain is executed by CS LNA. because it consists of capacitances and parasitic admittance,
The inductive degenerated source is constructed when putting yet contains significant gain plus fantastic opposite separation.
an inductor in the CS stage source. This LNA influences noise Subsequently, CS-Cascade geography incorporates excellent
execution and gain. CG design is opposite to stable circuit in noise execution of CS, having excellent reverse isolation. High
terms of low power, and robust opposite to stable circuit, DC power utilization done by two-phase LNA plus
which creates a powerless noise execution. Accordingly, subsequently is unreasonable for the research, which is the
capacitive cross coupling was also used in order to improve reason why the author picked single cascade geography for
this effect. Input of wideband coordinating are feasible for CG LNA. Examination of different input matching is performed
design so that setup is generally utilized in LNA's broadband lately, while the standard organization will perform the output
circuits. Anyway, CS design might be utilized in applications matching. In order to acquire high linearity, it will be
of wideband by using unique coordinating circuits. Cascade fundamental to ignore degenerated inductor. An examination
LNA guarantees significant power gain, good noise of cascade LNA was introduced in this segment. Accordingly,
performance and less power utilization. In the upper cascade the whole analysis is developed by explaining the process of
transistor, noise sources are declined by the output of the lower input plus output matching. At that point, utilization of
semiconductor's impedance in lower bands microwave outcomes was done in the following segment, in analytic
frequencies. In this way, the cascade has predominant noise design plus LNA optimization.
execution. Tragically phenomenal gain and noise execution of

Figure 1. Diagram for SSC LNA with Input Matching varying inductors located in the input transistor gate. Images (a) and (b) refers to serial and parallel,
respectively.

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 In the lower semiconductor source, the degenerating c1 
inductor is Ls, while gate resistance is Rg, so a straightforward A  C gs  Rs  Rg  b1   a1
equation dismisses Cgd feedback capacitance and conductance Qg 
of drain-source, GDS. It is being utilized interestingly in c2 
numerous old plus ongoing works because of effortlessness. B  C gs  Rs  Rg  b2   a2
Hence, it provides a decent sense of the impact of diminishing Qg 
inductance or other kinds of feedback in the drain current. c3
Utilizing this straightforward equation, a cascade input C  C gs  Rs  Rg  b3 
coordinating framework or LNA primary source can be Qg
(4)
designed. In frequencies up to any GHz, an ordinary equation
could be utilized. Downsizing CMOS innovations, the In frequencies of mm-wave, coordinating input faces few
conductance of drain-source increments and capacitances of restrictions utilizing series inductor at the gate. By doing this,
gate-drain turn out to be well compared with the capacitances no opportunity is left for the value of degenerating inductor.
of gate-source. In this way, in current CMOS advancements, Although now and again inductor proves importance to
precision is diminished by the equation of mm-wave circuits. improve LNA linearity, its design is little that could reasonably
Accordingly, in order to determine the resulting input be expected to dodge power gain degradation. Another issue is
impedance of the cascade stages CS, the following formula that the transmission line's inductors at the gate are not
(formula 1) is used: reasonable for the transmission line's inductors. For improving
1 the inductor configuration measure plus diminishing inductor
 1 L   g mL  CgdL 
1    g mL Z d    Rg (1) parasitic effects, such sorts of inductors are utilized at a shorted
 C 
Z ingL    s  1
 jC C  end setup. Another method of coordinating input is portrayed
 gsL gsL  gsL 
here. As a rule, the input matching can be clarified.
RdsL Considering this figure, the following equations could be
Where:  derived.
RdsL  Z d  j Ls
1
Z in  jX m 
 j  Bm  Bingl 
A. Bias Circuit and Input Matching Design
GingL
For each input coordinating circuits, different coordinating
strategies are created. For input coordination, a series capacitor
plus parallel inductor is utilized, and in the gate, a series Ging  Bm  BingL 
inductor is used. Optimization plus LNA design improvement   j Xm  
  Bm  BingL   
2
is made when systematic equations are solved for coordinating 2
GingL  G 2
 B  B
2

components. In the enhancement cycle, provided with  ingL m ingL 
adequate accuracy, analytic equations can decrease few
advancement factors. For conjugate matching we must have
Z in  Rs and
hence we deduce:
 Rs  RLg  RingL
 （2）  GingL
 sign  Bm    sign  BingL 
 Lg   X ingL if Rs  2 2
 GingL  BingL
 GingL
Lg
is the matching inductor in the gate and
RLg
is if Rs  2 2
 sign  Bm   sign  BingL 
 G  BingL
calculated from: ingL
 1
 Lg if Rs   there is no response
RLg  （3）  GingL
(5)
Qg
Practically, resistive input impedance to the gate of the
lower transistor is minimal as compared to the Rs. Thus, the
Here, Qg is the inductor quality factor. Accordingly the primary condition stands. Then again, the input impedance is
analytic matching design equations acquired are as follows: capacitive to the gate of the lower transistor. From this
2 perspective, the inductive component is Bm. Albeit
ABsN  BBsN  C  0 hypothetically, Xm indication might be positive or negative.
Because of experience, Xm must be practically capacitive.
in which: Hence, the author utilized a coordinating framework for the
design. Additionally, at any point where Xm is indicated as
positive, the designer can utilize the equivalent inductor.

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 Figure 2. Coordinating Framework for the Circuit

Vd ygg  g m  g ds   jCgs  jCgd  g m 

B. Analysis and Design of Noise Index and Voltage Gain
At first, the voltage gain at the common source stage plus Ads  
one transistor's common gate is derived. At that point, Vs jCgd  g m  jC gd   ygg ydd
outcomes were utilized to figure out the cascade stage's power
gain, just like noise analysis in later problems. In which:
 g m  jC gs Vgi  Vs   g dx Vd  Vs   Vs Ys  Ysb   0 Yg

 ygg  jCgs  jCgd 
 g m Vgi  Vs   g ds Vd  Vs   jC gd Vd  Vgi   Vd Yd  Ydb   0 1  Rg Yg
And after some calculations and defining:
ydd  g ds  jCgd  Yd  Ydb
(9)
yss  g m  jC gs  g ds  Ys  Ysb
ydd  g ds  jCgd  Yd  Ydb C. Analysis and Design of Linear(6)
Dynamic Indicators
(6) For common source plus cascade LNA noise execution
estimation, various analytic equations are determined. The
we deduce: detailed works have a few restrictions that can help in mm
Vd  g m  g ds   g m  jCgs   yss  g m  jCgd 
waveband for preventing appropriate noise execution based
Adgi   from the author's insight. The model of an uncomplicated
Vgi yss ydd  g ds  g m  g ds  transistor is utilized. Upper transistor noise commitment is
disregarded. This results in a decent estimate in lower
frequencies, where substrate impact is not significant, and
henceforth source impedance degenerates upper transistor
Considering the effect of Rg, another voltage gain was noise, such as inputting impedance into lower transistor drain.
defined: Nevertheless, in the mm-wave range, substrate admittance
turns out to be well compared to cascade nodal admittance.
Vgi Hence, it brings down the degenerating impact of noise,
Agig   1  YingL Rg
Vg leading to the commitment of upper transistor noise in all noise
output increments. In addition, substrate noise is disregarded.
Already clarified, substrate noise enters circuits when substrate
And finally:
admittance increments in mm-wave frequencies.
Vd To address the restrictions above, the analytic equation is
Adg   Adgi Agig (7)
Vg proposed to solve cascade noise execution. Point that in noise
figure estimation, the load impedance is replaced by a short
circuit because it has no impact. Some of the distinctive noise
Moreover, for the common gate stage, the author writes:
sources for this amplifier are those “induced by the gates in the
 jCgs Vg  Vs   jC gd Vg  Vd   Vg Yg  0 lower and upper transistors and (8)the IngL plus IngU” [3].

 Additionally, IndL plus IndU (separately) are the drain thermal
 g m Vg  Vs   g ds Vd  Vs   jC gd Vd  Vg   Vd Yd  Ydb   0 noises of the circuit's lower and upper transistors. The substrate
(8)
thermal noises are InsbL, IndbL, InsbU, and IndbU, because of
Consequently we deduce: the genuine aspect of substrate admittance at upper and lower
transistors drain plus source nodes, separately. Ins is thermal
noise because of the source resistance of the input signal. The
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 InM1 plus InM2 of the circuit's input coordinating network are source impedance Zs. The active device in an amplifier must
also equal to current noise sources of the said network. InRg is be genuinely stable for the ideal performance of the speaker [5].
thermal noise because of gate poly-silicon resistance. Little A functioning gadget is viewed as unequivocally stable when
semiconductors get this significant noise [4]. InLs is thermal the Rolled strength factor (K) > 1 and |Δ| < 1. Numerically,
noise because of viable degenerating inductor parallel these two are the Rolled dependability factor K and the extent
resistance, and the resistance is because of the restricted of the determinant of the S-boundaries |Δ|.
inductor quality factor.
E. Complete circuit
D. Power Consumption and Functional Stability Design When the cascade amplifier's physical boundaries have
In LNA design, stability analysis ought to include the been set up, the LNA configuration is finished with the input
following stage. Stability is completely decided by gadget and output matching networks and the bias network areas.
S-parameters, coordinating frameworks, and terminations. One Specifically, the last part set the gate-source voltage (Vgs) of
significant consideration in the design is the amplifier's the CS transistor, which in turn decides the bias state of the
stability or its resistance to oscillate. Whenever negative whole cascade arrangement, while the previous part permits
resistance is presented by the output or input port, oscillations the LNA to accomplish the most extreme energy transfer. Only
will be conceivable in the two-port framework. It happens the most extreme power gain examination is considered at this
when output or input reflection coefficients are positive stage. Both the input and the output matching networks involve
(|ΓIN| > 1 or |ΓOUT| > 1), for one-sided gadget happens when a series capacitor and a parallel inductor. The total LNA
|S11| > 1 or |S22| > 1). The two port-network appearing in the schematic circuit, including matching and bias networks,
figure is genuinely stable at working frequency 2.4 GHz, if real which intended for most extreme gain condition, is shown in
parts of Zout plus Zin are larger than (0) for load ZL plus the following figure 3 [6].

Figure 3. Complete LNA Schematic Circuit with matching and bias networks

V. CONCLUSION noise performance), the significant effects of minimal changes

in optimizer's performance levels were used as metrics. As a
A very well understanding of principles must be required to result of predetermined specifications, sufficient execution is
design a low-noise amplifier by using traditional methods. In performed by the initial run based on the original circuit.
the study, some of these compromising factors have become Insufficient execution is performed in case of stability plus
compulsory since each parameter execution level could be noise figure even when the gain is rational in the second run. It
negatively influenced by the enhancement of the opposite stabilizes the feedback stage effects by detaching it from the
parameter. In other words, the design cycle becomes highly third run circuit [8]. All in all, this led to the creation of a
complex since a small freedom degree is permitted for circuit that it does not only meet all stability requirements but
compromising factors to achieve the requirements as a whole also indicate a higher gain. The conclusion contains the fact
[7]. Accordingly, in order to attain this research's goal of that feedback is unessential having existing criteria. The
finding an LNA topology with an excellent performance (i.e.,
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 inductor is connected to the source terminal, hence concluding https://ieeexplore.ieee.org/document/Design-and-Analysis-of-a-Low-No
the circuit worked as inductive source degeneration. ise-Amplifier-for-5G-Systems
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CMOS Low Noise Amplifier Using ADS and Cadence. Sciencedirect.
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CMOS low-noise amplifier design optimization techniques. IEEE
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ACKNOWLEDGMENT ysis_of_low_noise_amplifier
[7] Castagnola, Juan L., Fortunato C. Dualibe, Agustín M. Laprovitta, and
I would like to thank all the professors in ECSE department. Hugo García-Vázquez. "A Novel Design and Optimization Approach
Thank you for your thoughtful and earnest teaching to me in for Low Noise Amplifiers (LNA) Based on MOST Scattering
my study, which has greatly benefited me. Second, I would Parameters and the gm/ID Ratio." Electronics 9, no. 5 (2020): 785.
appreciate all the authors who I cited their articles in my paper. [8] Su, Y. (2006, June). An 800-/spl mu/W 26-GHz CMOS tuned amplifier.
Without their valuable information, I cannot finish my essay. In IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006
Finally, I want to thank my family who supporting me and (pp. 4-pp). IEEE.
warming me with their love during my sleepless nights of [9] Palhewar, S. (2018). Analysis of Low Noise Amplifier. International
Journal of Electronics and Communication Engineering.
writing and revising papers. http://www.irphouse.com/ijece/ijecev8n1_04.pdf
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inductively degenerated CMOS low noise amplifier. IEEE Transactions
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Amplifier for 5G Systems. IEEE. 835-841.

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