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FPGAProgrammingHandcodeFrameworkFPGAInterfaceReference

The document is the FPGA Programming Handcode Framework reference for the 2024-A release by dSPACE, detailing various FPGA frameworks and their I/O functions. It includes contact information for dSPACE and support, as well as important notices regarding copyright and proprietary information. The contents cover a comprehensive overview of different FPGA base boards and modules, along with their respective input/output functionalities.

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0% found this document useful (0 votes)

6 views

FPGAProgrammingHandcodeFrameworkFPGAInterfaceReference

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mohamed azarudeen

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Download as PDF, TXT or read online on Scribd

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FPGA Programming Handcode Framework

FPGA Interface Reference

For FPGA Programming Blockset 2024-A

Release 2024-A – May 2024

How to Contact dSPACE
Mail: dSPACE GmbH
Rathenaustraße 26
33102 Paderborn
Germany
Tel.: +49 5251 1638-0
E-mail: info@dspace.de
Web: https://www.dspace.com

How to Contact dSPACE Support

If you encounter a problem when using dSPACE products, contact your local dSPACE
representative:
§ Local dSPACE companies and distributors: https://www.dspace.com/go/locations
§ For countries not listed, contact dSPACE GmbH in Paderborn, Germany.
Tel.: +49 5251 1638-941 or e-mail: support@dspace.de

You can also use the support request form: https://www.dspace.com/go/supportrequest. If

you are logged on to mydSPACE, you are automatically identified and do not have to add
your contact details manually.

If possible, always provide the serial number of the hardware, the relevant dSPACE License
ID, or the serial number of the CmContainer in your support request.

Software Updates and Patches

dSPACE strongly recommends that you download and install the most recent patches
for your current dSPACE installation. Visit https://www.dspace.com/go/patches for the
software updates and patches themselves and for more information, such as how to
receive an automatic notification when an update or a patch is available for your dSPACE
software.

Important Notice
This publication contains proprietary information that is protected by copyright. All rights
are reserved. The publication may be printed for personal or internal use provided all the
proprietary markings are retained on all printed copies. In all other cases, the publication
must not be copied, photocopied, reproduced, translated, or reduced to any electronic
medium or machine-readable form, in whole or in part, without the prior written consent
of dSPACE GmbH.

© 2010 - 2024 by:

dSPACE GmbH
Rathenaustraße 26
33102 Paderborn
Germany

This publication and the contents hereof are subject to change without notice.

AURELION, AUTERA, ConfigurationDesk, ControlDesk, MicroAutoBox, MicroLabBox,

SCALEXIO, SIMPHERA, SYNECT, SystemDesk, TargetLink, and VEOS are registered
trademarks of dSPACE GmbH in the United States or other countries, or both. Other
brand names or product names are trademarks or registered trademarks of their respective
companies or organizations.
Contents

Contents

About This Reference 11

General Information on the I/O Functions Available with

FPGA Frameworks 13
Overview of the Frameworks Available for MicroLabBox................................ 14
Overview of the Frameworks Available for MicroLabBox II................. ............ 16
Overview of the DS2655 FPGA Base Board Frameworks.................... ............ 19
Overview of the DS6601 FPGA Base Board Frameworks.................... ............ 21
Overview of the DS6602 FPGA Base Board Frameworks.................... ............ 23
Overview of the DS2655M1 I/O Module Framework...................................... 25
Overview of the DS2655M2 I/O Module Framework...................................... 27
Overview of the DS6651 Multi-I/O Module Framework.................................. 29
Overview of the DS660X_MGT Framework.................................................... 31
Overview of the Inter-FPGA Interface Framework........................................... 32
Overview of the Frameworks Available for MicroAutoBox II
(FPGA1401Tp1)............................................................................................. 34
Overview of the Frameworks Available for MicroAutoBox III
(FPGA1403Tp1)............................................................................................. 37
Unsupported Features of the FPGA Programming Handcode
Framework.................................................................................................... 41

I/O Functions of the DS1202 FPGA I/O Type 1

Framework 43
ADC (Class 1)................................................................................................ 44
ADC (Class 2)................................................................................................ 46
Buffer In........................................................................................................ 47
Buffer64 In.................................................................................................... 49
Buffer Out..................................................................................................... 50
Buffer64 Out................................................................................................. 52
Buzzer........................................................................................................... 54
DAC (Class 1)................................................................................................ 56
Digital InOut (Class 1).................................................................................... 57
Digital InOut (Class 2).................................................................................... 60
Interrupt........................................................................................... ............ 62
LED Out........................................................................................................ 62
Proc App Status............................................................................................. 63
Register In..................................................................................................... 64

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Register64 In................................................................................................. 66
Register Out.................................................................................................. 68
Register64 Out.............................................................................................. 69
Resolver........................................................................................................ 71
Status In........................................................................................................ 74
UART (RS232)................................................................................... ............ 74
UART (RS422/485)............................................................................ ............ 79

I/O Functions of the DS1303 (KU15P) Multi-I/O Board

Framework 85
Analog In 23................................................................................................. 86
Analog In 24................................................................................................. 88
Analog In 25................................................................................................. 89
Analog Out 19.............................................................................................. 90
Analog Out 20.............................................................................................. 92
APU Master................................................................................................... 93
APU Slave......................................................................................... ............ 95
Buffer In........................................................................................................ 97
Buffer Out..................................................................................................... 99
Buffer64 In.................................................................................................. 101
Buffer64 Out............................................................................................... 103
CN App Status............................................................................................ 105
Digital In/Out 14 (In).................................................................................... 106
Digital In/Out 14 (In/Out-Z).......................................................................... 107
Digital In/Out 15............................................................................... .......... 110
Interrupt........................................................................................... .......... 113
IOCNET Global Time.................................................................................... 113
LED Out...................................................................................................... 114
Register In................................................................................................... 115
Register Out................................................................................................ 117
Register64 In............................................................................................... 118
Register64 Out............................................................................................ 120
Status In...................................................................................................... 122

I/O Functions of the DS2655 FPGA Base Board

Framework 125
APU Master................................................................................................. 127
APU Slave......................................................................................... .......... 129
Buffer In...................................................................................................... 131
Buffer64 In.................................................................................................. 133
Buffer Out................................................................................................... 135

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Buffer64 Out............................................................................................... 137

CN App Status............................................................................................ 140
I-FPGA In (IOCNET)...................................................................................... 141
I-FPGA64 In (IOCNET).................................................................................. 142
I-FPGA Out (IOCNET)................................................................................... 144
I-FPGA64 Out (IOCNET)............................................................................... 146
Interrupt........................................................................................... .......... 148
IOCNET Global Time.................................................................................... 149
LED Out...................................................................................................... 149
Register In................................................................................................... 150
Register64 In............................................................................................... 152
Register Out................................................................................................ 154
Register64 Out............................................................................................ 155
Status In...................................................................................................... 157

I/O Functions of the DS6601 FPGA Base Board

Framework 159
APU Master................................................................................................. 161
APU Slave......................................................................................... .......... 163
Buffer In...................................................................................................... 165
Buffer64 In.................................................................................................. 167
Buffer Out................................................................................................... 169
Buffer64 Out............................................................................................... 171
CN App Status............................................................................................ 174
I-FPGA In (IOCNET)...................................................................................... 175
I-FPGA64 In (IOCNET).................................................................................. 176
I-FPGA Out (IOCNET)................................................................................... 178
I-FPGA64 Out (IOCNET)............................................................................... 180
Interrupt........................................................................................... .......... 182
IOCNET Global Time.................................................................................... 183
LED Out...................................................................................................... 183
Register In................................................................................................... 184
Register64 In............................................................................................... 186
Register Out................................................................................................ 188
Register64 Out............................................................................................ 189
Status In...................................................................................................... 191
Watchdog................................................................................................... 191

I/O Functions of the DS6602 FPGA Base Board

Framework 193
APU Master................................................................................................. 195

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APU Slave......................................................................................... .......... 197

Buffer In...................................................................................................... 199
Buffer64 In.................................................................................................. 201
Buffer Out................................................................................................... 203
Buffer64 Out............................................................................................... 206
CN App Status............................................................................................ 208
DDR4 32 Mode 1........................................................................................ 209
DDR4 32 Mode 2........................................................................................ 211
DDR4 64 Mode 1........................................................................................ 214
DDR4 64 Mode 2........................................................................................ 216
I-FPGA In (IOCNET)...................................................................................... 218
I-FPGA64 In (IOCNET).................................................................................. 220
I-FPGA Out (IOCNET)................................................................................... 222
I-FPGA64 Out (IOCNET)............................................................................... 224
Interrupt........................................................................................... .......... 226
IOCNET Global Time.................................................................................... 227
LED Out...................................................................................................... 227
Register In................................................................................................... 228
Register64 In............................................................................................... 230
Register Out................................................................................................ 232
Register64 Out............................................................................................ 233
Status In...................................................................................................... 235
Watchdog................................................................................................... 235

I/O Functions of the DS2655M1 I/O Module Framework 237

Analog In.................................................................................................... 238
Analog Out................................................................................................. 240
Digital In..................................................................................................... 242
Digital InOut..................................................................................... .......... 243
Digital Out.................................................................................................. 246

I/O Functions of the DS2655M2 I/O Module Framework 249

Digital In..................................................................................................... 250
Digital Out.................................................................................................. 253
Digital Out-Z............................................................................................... 255
RS232 Rx.......................................................................................... .......... 258
RS232 Tx..................................................................................................... 259
RS485 Rx.......................................................................................... .......... 261
RS485 RxTx................................................................................................. 263
RS485 Tx..................................................................................................... 265

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I/O Functions of the DS6651 Multi-I/O Module

Framework 269
Analog In.................................................................................................... 270
Analog In-L................................................................................................. 273
Analog Out................................................................................................. 276
Analog Out-T.............................................................................................. 278
Digital In..................................................................................................... 279
Digital In/Out-Z................................................................................. .......... 281
Digital Out.................................................................................................. 284
Digital Out-Z............................................................................................... 287
RS485 Rx.......................................................................................... .......... 289
RS485 Rx/Tx................................................................................................ 291
RS485 Tx..................................................................................................... 294
Trigger.............................................................................................. .......... 296

I/O Functions of the DS660X_MGT Framework 299

Aurora 64b66b In........................................................................................ 300
Aurora 64b66b Out..................................................................................... 302
Aurora 64b66b 128 Bit In............................................................................ 303
Aurora 64b66b 128 Bit Out......................................................................... 305
MGT In............................................................................................. .......... 307
MGT In Opto Ready.......................................................................... .......... 309
MGT Out.......................................................................................... .......... 310

I/O Functions of the Inter-FPGA Interface Framework 313

I‑FPGA In..................................................................................................... 314
I‑FPGA Out.................................................................................................. 318

I/O Functions of the FPGA1401Tp1 with Multi-I/O

Module Frameworks 323
ADC (Type A).................................................................................... .......... 325
ADC (Type B)............................................................................................... 326
Buffer In...................................................................................................... 328
Buffer64 In.................................................................................................. 329
Buffer Out................................................................................................... 331
Buffer64 Out............................................................................................... 333
DAC............................................................................................................ 335
Digital Crank/Cam Sensor................................................................. .......... 336
Digital In (Type A)........................................................................................ 338

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Digital In (Type B).............................................................................. .......... 340

Digital Out (Type A)..................................................................................... 341
Digital Out (Type B)........................................................................... .......... 343
Inductive Zero Voltage Detector................................................................... 345
Interrupt........................................................................................... .......... 346
LED Out...................................................................................................... 347
Register In................................................................................................... 347
Register64 In............................................................................................... 349
Register Out................................................................................................ 351
Register64 Out............................................................................................ 352
Sensor Supply................................................................................... .......... 354
Status In...................................................................................................... 355
UART (RS232)................................................................................... .......... 356
UART (RS422/485)............................................................................ .......... 361

I/O Functions of the FPGA1401Tp1 with Engine

Control I/O Module Framework 367
ADC (Type A).................................................................................... .......... 368
Buffer In...................................................................................................... 370
Buffer64 In.................................................................................................. 372
Buffer Out................................................................................................... 374
Buffer64 Out............................................................................................... 376
Digital Crank/Cam Sensor................................................................. .......... 378
Digital In (Type B).............................................................................. .......... 379
Digital Out (Type A)..................................................................................... 381
Digital Out (Type B)........................................................................... .......... 383
Inductive Zero Voltage Detector................................................................... 385
Interrupt........................................................................................... .......... 386
Knock Sensor.............................................................................................. 387
LED Out...................................................................................................... 388
Register In................................................................................................... 389
Register64 In............................................................................................... 391
Register Out................................................................................................ 393
Register64 Out............................................................................................ 394
Status In...................................................................................................... 396
Temperature................................................................................................ 397

I/O Functions of the FPGA1403Tp1 with Multi-I/O

Module Frameworks 399
ADC (Type A).................................................................................... .......... 400
ADC (Type B)............................................................................................... 402

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Contents

Buffer In...................................................................................................... 403

Buffer64 In.................................................................................................. 405
Buffer Out................................................................................................... 407
Buffer64 Out............................................................................................... 408
DAC............................................................................................................ 410
Digital Crank/Cam Sensor................................................................. .......... 411
Digital In (Type A)........................................................................................ 413
Digital In (Type B).............................................................................. .......... 415
Digital Out (Type A)..................................................................................... 417
Digital Out (Type B)........................................................................... .......... 418
Inductive Zero Voltage Detector................................................................... 420
Interrupt........................................................................................... .......... 421
LED Out...................................................................................................... 422
Register In................................................................................................... 423
Register64 In............................................................................................... 424
Register Out................................................................................................ 426
Register64 Out............................................................................................ 427
Sensor Supply................................................................................... .......... 429
Status In...................................................................................................... 430
UART (RS232)................................................................................... .......... 431
UART (RS422/485)............................................................................ .......... 436

I/O Functions of the FPGA1403Tp1 with Engine

Control I/O Module Framework 443
ADC (Type A).................................................................................... .......... 444
Buffer In...................................................................................................... 446
Buffer64 In.................................................................................................. 448
Buffer Out................................................................................................... 450
Buffer64 Out............................................................................................... 451
Digital Crank/Cam Sensor................................................................. .......... 453
Digital In (Type B).............................................................................. .......... 455
Digital Out (Type A)..................................................................................... 456
Digital Out (Type B)........................................................................... .......... 459
Inductive Zero Voltage Detector................................................................... 460
Interrupt........................................................................................... .......... 461
Knock Sensor.............................................................................................. 462
LED Out...................................................................................................... 464
Register In................................................................................................... 465
Register64 In............................................................................................... 466
Register Out................................................................................................ 468
Register64 Out............................................................................................ 469

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Status In...................................................................................................... 471

Temperature................................................................................................ 472

Index 475

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About This Reference

About This Reference

Content This reference provides detailed information about the I/O functions provided
by the FPGA handcode frameworks of your dSPACE installation. For example, it
contains descriptions of the parameters and ports of the available functions.

Audience profile It is assumed that you have good knowledge in:

§ Applying generally accepted FPGA design rules to ensure a stable and reliable
FPGA application.
§ The architectural structure of FPGAs (CLB architecture, slice flip-flops, memory
resources, DSP resources, clocking resources) with a verifiable experience on
digital designs (structural mapping, tool-flow knowledge, synthesis options,
timing analysis).
§ Modeling with Simulink®.
§ Using the AMD design tools for simulation and debugging.

Symbols dSPACE user documentation uses the following symbols:

Symbol Description
Indicates a hazardous situation that, if not avoided,
V DANGER
will result in death or serious injury.
Indicates a hazardous situation that, if not avoided,
V WARNING could result in death or serious injury.
Indicates a hazardous situation that, if not avoided,
V CAUTION could result in minor or moderate injury.
Indicates a hazard that, if not avoided, could result in
NOTICE
property damage.
Indicates important information that you should take
Note
into account to avoid malfunctions.
Indicates tips that can make your work easier.
Tip
Indicates a link that refers to a definition in the
glossary, which you can find at the end of the
document unless stated otherwise.

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May 2024 FPGA Programming Handcode Framework - FPGA Interface Reference
About This Reference

Symbol Description
Follows the document title in a link that refers to
another document.

Naming conventions dSPACE user documentation uses the following naming conventions:

%name% Names enclosed in percent signs refer to environment variables for

file and path names.

<> Angle brackets contain wildcard characters or placeholders for variable

file and path names, etc.

Special Windows folders Windows‑based software products use the following special folders:

Common Program Data folder A standard folder for application-specific

program data that is used by all users.
%PROGRAMDATA%\dSPACE\<InstallationGUID>\<ProductName>
or
%PROGRAMDATA%\dSPACE\<ProductName>\<VersionNumber>

Documents folder A standard folder for application‑specific files that are

used by the current user.
%USERPROFILE%\Documents\dSPACE\<ProductName>\<VersionNumber>

Local Program Data folder A standard folder for application-specific

program data that is used by the current user.
%USERPROFILE%\AppData\Local\dSPACE\<InstallationGUID>\
<ProductName>

Accessing dSPACE Help and After you install and decrypt Windows‑based dSPACE software, the
PDF files documentation for the installed products is available in dSPACE Help and as PDF
files.

dSPACE Help (local) You can open your local installation of dSPACE Help:
§ On its home page via Windows Start Menu
§ On specific content using context-sensitive help via F1

PDF files You can access PDF files via the icon in dSPACE Help. The PDF
opens on the first page.

dSPACE Help (Web) Independently of the software installation, you can

access the Web version of dSPACE Help at https://www.dspace.com/go/help.
To access the Web version, you must have a mydSPACE account.
For more information on the mydSPACE registration process, refer to
https://www.dspace.com/faq?097.

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FPGA Programming Handcode Framework - FPGA Interface Reference May 2024
General Information on the I/O Functions Available with FPGA Frameworks

General Information on the I/O Functions Available

with FPGA Frameworks

Introduction Overview of the I/O functions provided by the FPGA Programming Handcode
Framework.

Where to go from here Information in this section

Overview of the Frameworks Available for MicroLabBox.......................... 14

The DS1202 FPGA I/O Type 1 frameworks are the standard frameworks
supporting MicroLabBox. They provide access to analog and digital
signals, and to the internal bus buffers and registers.

Overview of the Frameworks Available for MicroLabBox II........................ 16

The DS1303 (KU15P) Multi-I/O Boardframework is the standard
framework supporting MicroLabBox II. It provides access to analog and
digital signals, and to the IOCNET buffers and registers.

Overview of the DS2655 FPGA Base Board Frameworks........................... 19

The frameworks comes with the DS2655 FPGA Base Board, providing
access to APU signals, and to the IOCNET buffers and registers.

Overview of the DS6601 FPGA Base Board Frameworks........................... 21

The framework comes with the DS6601 FPGA Base Board, providing
access to APU signals, and to the IOCNET buffers and registers.

Overview of the DS6602 FPGA Base Board Frameworks........................... 23

The framework comes with the DS6602 FPGA Base Board, providing
access to APU signals, and to the IOCNET buffers and registers.

Overview of the DS2655M1 I/O Module Framework................................ 25

The DS2655M1 I/O Module framework comes with the DS2655M1
Multi-I/O Module, providing access to analog and digital signals.

Overview of the DS2655M2 I/O Module Framework................................ 27

The DS2655M2 I/O Module framework comes with the DS2655M2
Digital I/O Module, providing access to digital signals.

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General Information on the I/O Functions Available with FPGA Frameworks

Overview of the DS6651 Multi-I/O Module Framework............................ 29

The DS6651 Multi-I/O Module framework comes with the DS6651 Multi-
I/O Module, providing access to digital signals.

Overview of the DS660X_MGT Framework.............................................. 31

The DS660X_MGT framework provides MGT communication for
DS6601/DS6602 FPGA Base Boards.

Overview of the Inter-FPGA Interface Framework..................................... 32

The Inter-FPGA Interface framework provides inter-FPGA communication
between SCALEXIO FPGA Base Boards.

Overview of the Frameworks Available for MicroAutoBox II

(FPGA1401Tp1)....................................................................................... 34
The FPGA1401Tp1 frameworks are the standard frameworks for
MicroAutoBox II with DS1552 or DS1552B1 Multi-I/O Module. The
frameworks provide access to analog and digital signals, and to the
intermodule-bus buffers and registers.

Overview of the Frameworks Available for MicroAutoBox III

(FPGA1403Tp1)....................................................................................... 37
The FPGA1403Tp1 frameworks are the standard frameworks for
MicroAutoBox III with DS1552 or DS1552B1 Multi-I/O Module. The
frameworks provide access to analog and digital signals, and to the
intermodule-bus buffers and registers.

Unsupported Features of the FPGA Programming Handcode

Framework.............................................................................................. 41
The blocks of the FPGA Programming Blockset provides more features
than the FPGA handcode frameworks.

Overview of the Frameworks Available for MicroLabBox

Introduction The DS1202 FPGA I/O Type 1 frameworks are the standard frameworks
supporting MicroLabBox. They provide access to analog and digital signals, and
to the internal bus buffers and registers.

Framework location Depending on the use case, there are two frameworks:
§ Framework to handcode a custom FPGA application without using the
standard I/O features:
<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\
DS1302_XC7K325T
§ Framework to handcode a custom FPGA application that additionally supports
the standard I/O features to use remaining I/O channels with the RTI
blocksets/Real-Time Libraries (RTLib) for MicroLabBox:
<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\
DS1302_XC7K325T_FLEXIBLEIO

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FPGA Programming Handcode Framework - FPGA Interface Reference May 2024
Overview of the Frameworks Available for MicroLabBox

The entire framework folder must be copied to your working folder

(see also Preparing Your Environment (FPGA Programming Handcode
Framework Guide )). The included handcode FPGA framework INI file
hc_fpga_framework_ini_DS1302.m must be adapted to your specific
framework configuration. You find the configuration options in this reference.

For each I/O function category a specific range of channels is reserved. With the
I/O function number, you can specify a specific I/O function and its corresponding
channel.

Functions for exchanging data The following I/O functions can be used to exchange data with the processor
with the processor application application.

Functions for exchanging data The following I/O functions can be used to exchange data with the I/O of
with the I/O module MicroLabBox's DS1302 board.

I/O Function Available Channels I/O Function Numbering

ADC (Class 1) 24 2 … 25
ADC (Class 2) 8 26 … 33
Digital InOut (Class 1) 48 5 … 52
DAC (Class 1) 16 53 … 68
Digital InOut (Class 2) 12 73 … 84

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General Information on the I/O Functions Available with FPGA Frameworks

I/O Function Purpose Available I/O Function

Channels Numbering
Proc App Status To get information on 1 34
the state of the processor
application.
LED Out To set the FPGA status LEDs 4 1…4
near the I/O connectors.
Buzzer To generate an acoustic signal. 1 85
UART (RS232) To implement communication 2 69 … 70
UART via the serial interface. 2 71 … 72
(RS422/485)
Resolver To get the rotor's position via 2 35 ... 36
a resolver sensor.

Parameters and ports For detailed information on the I/O functions and their parameters and ports,
refer to the function descriptions in I/O Functions of the DS1202 FPGA I/O Type 1
Framework on page 43. The parameter and port descriptions additionally
contain more descriptive names for a simple identification of the parameters and
ports. For example, Fct(<IOFunction_Number>).Parameter(1).Init / Binary point
position describes the Binary point position parameter of the I/O function.
The port definitions are required to specify the FPGA functionality in VHDL or
Verilog code. In your Vivado project, you must adapt the related cm file to
the required FPGA functionality. For further information, refer to Specifying the
FPGA Functionality (FPGA Programming Handcode Framework Guide ).

For each accessed port in the VHDL or Verilog code, you must configure the
corresponding I/O function in the handcode FPGA framework INI file. Most
of the I/O function parameters configure the function behavior. For further
information, refer to Specifying the FPGA I/O Interface (FPGA Programming
Handcode Framework Guide ).

I/O Functions of the DS1202 FPGA I/O Type 1 Framework......................................................... 43

Overview of the Frameworks Available for MicroLabBox II

Introduction The DS1303 (KU15P) Multi-I/O Board framework is the standard framework
supporting MicroLabBox II. It provides access to analog and digital signals, and to
the IOCNET buffers and registers.

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Overview of the Frameworks Available for MicroLabBox II

Framework location The framework is located in the following folder:

§ <RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\
DS1303_XCKU15P

The entire framework folder must be copied to your working folder,

refer to Preparing Your Environment (FPGA Programming Handcode
Framework Guide ). The included handcode FPGA framework INI file
hc_fpga_framework_ini_DS1303.m must be adapted to your specific
framework configuration. You find the configuration options in this reference.

For each I/O function category a specific range of channels is reserved. With the
I/O function number, you can specify a specific I/O function and its corresponding
channel.

Functions for exchanging data The following I/O functions can be used to exchange data with the processor
with the processor application application.

I/O Function Available Channels I/O Function Numbering

Register In 256 1 … 256
Register64 In1) 256 289 … 544
Buffer In 32 257 … 288
Buffer64 In1) 32 545 … 576
Register Out 256 1 … 256
Register64 Out1) 256 289 … 544
Buffer Out 32 257 … 288
Buffer64 Out1) 32 545 … 576
1) 64-bit fixed-point data types are converted to double, except the data type without
a binary point (binary point position = 0). Therefore, the fixed-point resolution of
fixed-point data types with a binary point (binary point position > 0) is restricted to
53 bits.

Functions for exchanging data The following I/O functions can be used to exchange data with the I/O of
with the I/O module MicroLabBox's DS1302 board.

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General Information on the I/O Functions Available with FPGA Frameworks

Additional I/O functions for The following I/O functions can be used for special purposes.
special purposes

I/O Function Purpose Available I/O Function

Channels Numbering
APU Master To distribute angle values over IOCNET for synchronizing 6 2…7
angle-based applications.
APU Slave To read angle values distributed by an APU Master over 6 4…9
IOCNET for synchronizing angle-based applications.
CN App Status To get information on the state of the processor 2 2
application.
Interrupt To implement interrupt handling. 8 1…8
IOCNET Global To read the number of hardware ticks. 1 3
Time
LED Out To write a digital signal that controls the USR LED 1 of the 4 1…4
MicroLabBox II.
Status In To get information on the state of the FPGA 1 1
programming sequence.

Parameters and ports For detailed information on the I/O functions and their parameters
and ports, refer to the function descriptions in I/O Functions of the
DS1303 (KU15P) Multi-I/O Board Framework on page 85. The parameter
and port descriptions additionally contain more descriptive names for
a simple identification of the parameters and ports. For example,
Fct(<IOFunction_Number>).Parameter(1).Init / Binary point position describes the
Binary point position parameter of the I/O function.

The port definitions are required to specify the FPGA functionality in VHDL or
Verilog code. In your Vivado project, you must adapt the related cm file to
the required FPGA functionality. For further information, refer to Specifying the
FPGA Functionality (FPGA Programming Handcode Framework Guide ).

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

References

I/O Functions of the DS1303 (KU15P) Multi-I/O Board Framework............................................. 85

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FPGA Programming Handcode Framework - FPGA Interface Reference May 2024
Overview of the DS2655 FPGA Base Board Frameworks

Overview of the DS2655 FPGA Base Board Frameworks

Introduction The frameworks comes with the DS2655 FPGA Base Board, providing access to
APU signals, and to the IOCNET buffers and registers.

Each variant of the DS2655 FPGA Base Board is supported by its own
framework:
§ DS2655 (7K160) FPGA Base Board framework
§ DS2655 (7K410) FPGA Base Board framework

Framework location The location of the frameworks depends on the used variant of the DS2655
FPGA Base Boards:
§ DS2655 (7K160) FPGA Base Board:
<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\
DS2655_XC7K160T
§ DS2655 (7K410) FPGA Base Board:
<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\
DS2655_XC7K410T

The entire framework folder must be copied to your working folder

(see also Preparing Your Environment (FPGA Programming Handcode
Framework Guide )). The included handcode FPGA framework INI file
hc_fpga_framework_ini_DS2655.m must be adapted to your specific
framework configuration. You find the configuration options in this reference.

Functions for exchanging data The following I/O functions can be used to exchange data with the processor
with the processor application application, either with 32 bit or with 64 bit data width.

I/O Function Available Channels I/O Function Numbering

Register In 256 1 … 256
Register64 In1) 256 289 … 544
Register Out 256 1 … 256
Register64 Out1) 256 289 … 544
Buffer In 32 257 … 288
Buffer64 In1) 32 545 … 576
Buffer Out 32 257 … 288
Buffer64 Out1) 32 545 … 576
1) 64-bit fixed-point data types are converted to double, except the data type without
a binary point (binary point position = 0). Therefore, the fixed-point resolution of
fixed-point data types with a binary point (binary point position > 0) is restricted to
53 bits.

For detailed information, refer to I/O Functions of the DS2655 FPGA Base Board
Framework on page 125.

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Additional I/O functions for The following I/O functions can be used for special purposes.
special purposes
I/O Function Purpose Available I/O Function
Channels Numbering
Interrupt To implement interrupt 8 1…8
handling.
Status In To get information on the 1 1
state of the FPGA programming
sequence.
CN App Status To get information on the state 1 2
of the controller application.
LED Out To set the LED on the board's 1 1
bracket.
IOCNET Global To implement angle-based 1 3
Timer applications.
APU Master 6 2…7
APU Slave 6 4…9
I-FPGA In To implement inter-FPGA 32 10 … 41
(IOCNET) communication between FPGA
I-FPGA64 In base boards via IOCNET. 32 42 … 73
(IOCNET)
I-FPGA Out 32 8 … 39
(IOCNET)
I-FPGA64 Out 32 40 … 71
(IOCNET)

Parameters and ports For detailed information on the I/O functions and their parameters and ports,
refer to the function descriptions in I/O Functions of the DS2655 FPGA Base
Board Framework on page 125. The parameter and port descriptions additionally
contain more descriptive names for a simple identification of the parameters and
ports. For example, Fct(<IOFunction_Number>).Parameter(1).Init / Binary point
position describes the Binary point position parameter of the I/O function.
The port definitions are required to specify the FPGA functionality in VHDL code.
In your Vivado project, you must adapt the related cm file to the required FPGA
functionality. For further information, refer to Specifying the FPGA Functionality
(FPGA Programming Handcode Framework Guide ).

For each accessed port in the VHDL code, you must configure the corresponding
I/O function in the handcode FPGA framework INI file. Most of the I/O function
parameters configure the function behavior. For further information, refer to
Specifying the FPGA I/O Interface (FPGA Programming Handcode Framework
Guide ).

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Overview of the DS6601 FPGA Base Board Frameworks

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

Overview of the DS6601 FPGA Base Board Frameworks

Introduction The DS6601 (KU035) FPGA Base Board framework comes with the DS6601
FPGA Base Board, providing access to APU signals, and to the IOCNET buffers
and registers.

Framework location The framework is located in the following folder:

§ <RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\
DS6601_XCKU035

The entire framework folder must be copied to your working folder

(see also Preparing Your Environment (FPGA Programming Handcode
Framework Guide )). The included handcode FPGA framework INI file
hc_fpga_framework_ini_DS6601_XCKU035.m must be adapted to your
specific framework configuration. You find the configuration options in this
reference.

Functions for exchanging data The following I/O functions can be used to exchange data with the processor
with the processor application application, either with 32 bit or with 64 bit data width.

I/O Function Available Channels I/O Function Numbering

For detailed information, refer to I/O Functions of the DS6601 FPGA Base Board
Framework on page 159.

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Additional I/O functions for The following I/O functions can be used for special purposes.
special purposes
I/O Function Purpose Available I/O Function
Channels Numbering
Interrupt To implement interrupt 16 1 … 16
handling.
Status In To get information on the state 1 1
of the FPGA programming
sequence.
CN App Status To get information on the state 1 2
of the controller application.
Watchdog To check if the processor 1 75
application is alive.
LED Out To set the LED on the board's 1 1
bracket.
IOCNET Global To implement angle-based 1 3
Timer applications.
APU Master 6 2…7
APU Slave 6 4…9
I-FPGA In To implement inter-FPGA 32 11 … 42
(IOCNET) communication between FPGA
I-FPGA64 In base boards via IOCNET. 32 43 … 74
(IOCNET)
I-FPGA Out 32 8 … 39
(IOCNET)
I-FPGA64 Out 32 40 … 71
(IOCNET)

Parameters and ports For detailed information on the I/O functions and their parameters and ports,
refer to the function descriptions in I/O Functions of the DS6601 FPGA Base
Board Framework on page 159. The parameter and port descriptions additionally
contain more descriptive names for a simple identification of the parameters and
ports. For example, Fct(<IOFunction_Number>).Parameter(1).Init / Binary point
position describes the Binary point position parameter of the I/O function.
The port definitions are required to specify the FPGA functionality in VHDL code.
In your Vivado project, you must adapt the related cm file to the required FPGA
functionality. For further information, refer to Specifying the FPGA Functionality
(FPGA Programming Handcode Framework Guide ).

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Overview of the DS6602 FPGA Base Board Frameworks

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

Overview of the DS6602 FPGA Base Board Frameworks

Introduction The DS6602 (KU15P) FPGA Base Board framework comes with the DS6602 FPGA
Base Board, providing access to APU signals, and to the IOCNET buffers and
registers.

Framework location The framework is located in the following folder:

§ <RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\
DS6602_XCKU15P

The entire framework folder must be copied to your working folder

(see also Preparing Your Environment (FPGA Programming Handcode
Framework Guide )). The included handcode FPGA framework INI file
hc_fpga_framework_ini_DS6602_XCKU15P.m must be adapted to your
specific framework configuration. You find the configuration options in this
reference.

Functions for exchanging data The following I/O functions can be used to exchange data with the processor
with the processor application application, either with 32 bit or with 64 bit data width.

I/O Function Available Channels I/O Function Numbering

For detailed information, refer to I/O Functions of the DS6602 FPGA Base Board
Framework on page 193.

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Additional I/O functions for The following I/O functions can be used for special purposes.
special purposes
I/O Function Purpose Available I/O Function
Channels Numbering
Interrupt To implement interrupt 16 1 … 16
handling.
Status In To get information on the state 1 1
of the FPGA programming
sequence.
CN App Status To get information on the state 1 2
of the controller application.
Watchdog To check if the processor 1 75
application is alive.
LED Out To set the LED on the board's 1 1
bracket.
IOCNET Global To implement angle-based 1 3
Timer applications.
APU Master 6 2…7
APU Slave 6 4…9
DDR4 32 Mode To provide read/write access to 1 8
1 the DDR4 RAM.
DDR4 32 Mode 1 9
2
DDR4 64 Mode 1 10
1
DDR4 64 Mode 1 11
2
I-FPGA In To implement inter-FPGA 32 11 … 42
(IOCNET) communication between FPGA
I-FPGA64 In base boards via IOCNET. 32 43 … 74
(IOCNET)
I-FPGA Out 32 12 … 43
(IOCNET)
I-FPGA64 Out 32 44 … 75
(IOCNET)

Parameters and ports For detailed information on the I/O functions and their parameters and ports,
refer to the function descriptions in I/O Functions of the DS6602 FPGA Base
Board Framework on page 193. The parameter and port descriptions additionally
contain more descriptive names for a simple identification of the parameters and
ports. For example, Fct(<IOFunction_Number>).Parameter(1).Init / Binary point
position describes the Binary point position parameter of the I/O function.
The port definitions are required to specify the FPGA functionality in VHDL code.
In your Vivado project, you must adapt the related cm file to the required FPGA

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Overview of the DS2655M1 I/O Module Framework

functionality. For further information, refer to Specifying the FPGA Functionality

(FPGA Programming Handcode Framework Guide ).

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

Overview of the DS2655M1 I/O Module Framework

Introduction The DS2655M1 I/O Module framework comes with the DS2655M1 Multi-I/O
Module, providing access to analog and digital signals.

Framework location The location of the frameworks depends on the used variant of the SCALEXIO
FPGA base board:
§ DS2655 (7K160) FPGA Base Board:
<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\
DS2655_XC7K160T
§ DS2655 (7K410) FPGA Base Board:
<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\
DS2655_XC7K410T
§ DS6601 FPGA Base Board:
<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\
DS6601_XCKU035
§ DS6602 FPGA Base Board:
<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\
DS6602_XCKU15P

The entire framework folder must be copied to your working folder

(see also Preparing Your Environment (FPGA Programming Handcode
Framework Guide )). The included handcode FPGA framework INI file
hc_fpga_framework_ini_<FPGA base board>.m must be adapted to your
specific framework configuration. You find the configuration options in this
reference.

Functions for exchanging data The DS2655M1 Multi-I/O Module is an I/O module for the SCALEXIO FPGA base
with the I/O module boards. A SCALEXIO FPGA Base Board and one or more I/O modules mounted

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General Information on the I/O Functions Available with FPGA Frameworks

together and connected via ribbon cables form an FPGA board in a SCALEXIO
system.

The following I/O functions can be used to exchange data with the I/O of the
DS2655M1 Multi-I/O Module. Because you can use up to five I/O modules,
you have to specify not only the I/O function number and the channel number
to configure a specific I/O function, but also the module number. The module
number is the number of the slot the I/O module is connected to.

I/O Function Available I/O Function Channel Module

Channels Numbering Numbering Numbering
Analog In 5 11 … 15 1 ... 5 1 ... 5
Analog Out 5 21 … 25 6 ... 10
Digital In 10 1 … 10 1 ... 10
Digital InOut 10 11 … 20 1 ... 10
Digital Out 10 1 … 10 1 ... 10

For detailed information, refer to I/O Functions of the DS2655M1 I/O Module
Framework on page 237.

Parameters and ports For detailed information on the I/O functions and their parameters and
ports, refer to the function descriptions in I/O Functions of the DS2655M1
I/O Module Framework on page 237. The parameter and port descriptions
additionally contain more descriptive names for a simple identification of the
parameters and ports. For example, IOProperties.In.Fct(<IOFunction_Number> +
ioInOffset<Module_number>).Parameter(3).Init / Input range describes the Input
Range parameter of the I/O function.

The port definitions are required to specify the FPGA functionality in VHDL code.
In your Vivado project, you must adapt the related cm file to the required FPGA
functionality. For further information, refer to Specifying the FPGA Functionality
(FPGA Programming Handcode Framework Guide ).

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

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Overview of the DS2655M2 I/O Module Framework

Overview of the DS2655M2 I/O Module Framework

Introduction The DS2655M2 I/O Module framework comes with the DS2655M2 Digital I/O
Module, providing access to digital signals.

The entire framework folder must be copied to your working folder

Note

To use DS2655M2 Digital I/O Modules, you must additionally copy files from
the RTL folder of the DS2655M2 I/O Module framework folder into your
project once and customize them. Refer to Configuring the FPGA Code
With the Specified I/O Interface (FPGA Programming Handcode Framework
Guide ).

Functions for exchanging data The DS2655M2 Digital I/O Module is an I/O module for the SCALEXIO FPGA base
with the I/O module boards. A SCALEXIO FPGA base board and one or more I/O modules mounted
together and connected via ribbon cables form an FPGA board in a SCALEXIO
system.

The following I/O functions can be used to exchange data with the I/O of the
DS2655M2 Digital I/O Module. Because you can use up to five I/O modules,
you have to specify not only the I/O function number and the channel number
to configure a specific I/O function, but also the module number. The module
number is the number of the slot the I/O module is connected to.

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I/O Function Available I/O Function Channel Numbering Module

Number of Numbering Numbering
I/O Functions
Digital In 32 1 … 32 1 ... 32 1 ... 5
Digital Out 32 1 … 32 1 … 32
Digital Out-Z 16 33 … 48 1-2, 3-4, ... , 31-32
RS232 Rx 8 33 … 40 2, 6, ... , 30
RS232 Tx 8 49 … 56 1, 5, ... , 29
RS485 Rx 8 41 … 48 1-2, 5-6, ... , 29-30
RS485 RxTx 8 65 … 72 1-3, 5-7, ... , 29-31
RS485 Tx 8 57 … 64 1-2, 5-6, ... , 29-30

The I/O functions of the DS2655M2 I/O Module framework share the 32 I/O
channels of the DS2655M2 Digital I/O Module. For details on the signal mapping
to optimize channel usage, refer to Signal Mapping of the DS2655M2 Digital I/O
Module (SCALEXIO Hardware Installation and Configuration ).

For detailed information, refer to I/O Functions of the DS2655M2 I/O Module
Framework on page 249.

Parameters and ports For detailed information on the I/O functions and their parameters and
ports, refer to the function descriptions in I/O Functions of the DS2655M2
I/O Module Framework on page 249. The parameter and port descriptions
additionally contain more descriptive names for a simple identification of the
parameters and ports. For example, IOProperties.In.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).Parameter(8).Init / Threshold init voltage describes
the Threshold init voltage parameter of the I/O function.

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

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Overview of the DS6651 Multi-I/O Module Framework

Overview of the DS6651 Multi-I/O Module Framework

Introduction The DS6651 Multi-I/O Module framework comes with the DS6651 Multi-I/O
Module, providing access to digital signals.

The entire framework folder must be copied to your working folder

Note

To use DS6651 Multi-I/O Modules, you must additionally copy files from
the RTL folder of the DS6651 Multi-I/O Module framework folder into your
project once and customize them. Refer to Configuring the FPGA Code
With the Specified I/O Interface (FPGA Programming Handcode Framework
Guide ).

Functions for exchanging data The DS6651 Multi-I/O Module is an I/O module for the SCALEXIO FPGA base
with the I/O module boards. A SCALEXIO FPGA base board and one or more I/O modules mounted
together and connected via ribbon cables form an FPGA board in a SCALEXIO
system.

The following I/O functions can be used to exchange data with the I/O of the
DS6651 Multi-I/O Module. Because you can use up to five I/O modules, you
have to specify not only the I/O function number and the channel number to
configure a specific I/O function, but also the module number. The module
number is the number of the slot the I/O module is connected to.

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I/O Function Available I/O Function Channel Numbering Module

Number of Numbering Numbering
I/O Functions
Analog In 4 25 … 28 23 … 26 1 ... 5
Analog In‑L 2 29, 30 27, 28
Analog Out 4 41 … 44 17 … 20
Analog Out‑T 2 45, 46 21, 22
Digital In Up to 16 1 … 16 1 … 16
Digital In/Out-Z Up to 4 25 … 28 1, 5, 9, 13
Digital Out Up to 16 1 … 16 1 … 16
Digital Out-Z Up to 8 17 … 24 1, 3, 5, … , 15
RS485 Rx Up to 8 17 … 24 1, 3, 5, … , 15
RS485 Rx/Tx Up to 4 37 … 40 1, 5, 9, 13
RS485 Tx Up to 8 29 … 36 1, 3, 5, … , 15
Trigger 2 47, 48 17, 18

The I/O functions of the DS6651 Multi-I/O Module framework share the digital
I/O channels that provide the digital I/O functionality. The DS6651 Multi-I/O
Module provides 16 digital I/O channels. Some I/O channels provide only specific
I/O functionalities, and some I/O functions use more than one I/O channel. These
channel dependencies and I/O channel sharing limit the number of I/O functions
that can be implemented.

For the data sheet of the DS6651 Multi-I/O Module, refer to DS6651 Multi-I/O
Module (SCALEXIO Hardware Installation and Configuration ).

For details on the signal mapping to optimize channel usage, refer to Supported
Digital Functions and Related I/O Channels (SCALEXIO Hardware Installation and
Configuration ).

For detailed information, refer to I/O Functions of the DS6651 Multi-I/O Module
Framework on page 269.

Parameters and ports For detailed information on the I/O functions and their parameters and
ports, refer to the function descriptions in I/O Functions of the DS6651 Multi-
I/O Module Framework on page 269. The parameter and port descriptions
additionally contain more descriptive names for a simple identification of the
parameters and ports. For example, IOProperties.In.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).Parameter(8).Init / Threshold init voltage describes
the Threshold init voltage parameter of the I/O function.

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Overview of the DS660X_MGT Framework

Specifying the FPGA I/O Interface (FPGA Programming Handcode Framework

Guide ).

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

Overview of the DS660X_MGT Framework

Framework location The location of the frameworks depends on the used variant of the SCALEXIO
FPGA base board:
§ DS6601 FPGA Base Board:
<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\
DS6601_XCKU035
§ DS6602 FPGA Base Board:
<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\
DS6602_XCKU15P

The entire framework folder must be copied to your working folder

Functions for MGT The following I/O functions can be used to exchange data via the MGT
communication communication bus.

I/O Function Available Number of I/O Function

Lanes Numbering
Aurora 64b66b In 4 1 ... 4
Aurora 64b66b Out 4 1 ... 4
Aurora 64b66b 128 Bit In 4 5…8
Aurora 64b66b 128 Bit Out 4 5…8
MGT In 1 9
MGT In Opto Ready 1 10
MGT Out 1 9

For more information on inter-FPGA communication, refer to Handcoding Inter-

FPGA Communication (FPGA Programming Handcode Framework Guide ).

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General Information on the I/O Functions Available with FPGA Frameworks

Parameters and ports For detailed information on the I/O functions and their parameters and
ports, refer to the function descriptions in I/O Functions of the DS660X_MGT
Framework on page 299. Additionally, the parameter and port descriptions
contain more descriptive names for a simple identification of the parameters
and ports. For example, hcfw.IOProperties.In.Fct(<ChannelNumber+8> +
ioInOffset(ioModuleNr)).HcCustomName / Channel name describes the Channel
name parameter of the I/O function.

The port definitions are required to specify the FPGA functionality in VHDL code.
In your Vivado project, you must adapt the related cm file to the required FPGA
functionality. For more information, refer to Specifying the FPGA Functionality
(FPGA Programming Handcode Framework Guide ).

For each accessed port in the VHDL code, you must configure the corresponding
I/O function in the handcode FPGA framework INI file. Most of the I/O function
parameters configure the function behavior. For more information, refer to
Specifying the FPGA I/O Interface (FPGA Programming Handcode Framework
Guide ).

Handcoding Inter-FPGA Communication (FPGA Programming Handcode Framework

Guide )

Overview of the Inter-FPGA Interface Framework

The entire framework folder must be copied to your working folder

(see also Preparing Your Environment (FPGA Programming Handcode
Framework Guide )). The included handcode FPGA framework INI file
hc_fpga_framework_ini_<FPGA base board>.m must be adapted to your

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Overview of the Inter-FPGA Interface Framework

specific framework configuration. You find the configuration options in this

reference.

Functions for inter-FPGA Inter-FPGA communication is a point-to-point connection between the I/O
communication module slots of the SCALEXIO FPGA base boards.

NOTICE

The improper assembly of inter-FPGA communication buses will

damage the FPGA boards
For inter-FPGA communication buses, special inter-FPGA communication
cables must be used. Other cables, such as the cables used for connecting
the I/O modules, will damage the FPGA boards. Furthermore, special rules
for attaching the FPGA boards must be observed to ensure proper bus
communication.
§ Use the SCLX_INT_FPGA_CAB1 inter-FPGA cables and observe the
enclosed documentation for assembling.
§ Do not connect FPGA boards via inter-FPGA cables if the FPGA boards are
connected to different processors via IOCNET.

The following I/O functions can be used. Because you can use up to five I/O
module slots, you have to specify the channel number to configure a specific
I/O function and the used I/O module slot. The module number represents the
number of the slot the I/O module is connected to.

I/O Function Available Number of Channel Module

I/O Functions Numbering Numbering
I‑FPGA In 8 1 ... 8 1 ... 5
I‑FPGA Out 8 1 ... 8

For more information on inter-FPGA communication, refer to Handcoding Inter-

FPGA Communication (FPGA Programming Handcode Framework Guide ).

Parameters and ports For detailed information on the I/O functions and their parameters and ports,
refer to the function descriptions in I/O Functions of the Inter-FPGA Interface
Framework on page 313. Additionally, the parameter and port descriptions
contain more descriptive names for a simple identification of the parameters
and ports. For example, hcfw.IOProperties.In.Fct(<ChannelNumber+8> +
ioInOffset(ioModuleNr)).HcCustomName / Channel name describes the Channel
name parameter of the I/O function.

The port definitions are required to specify the FPGA functionality in VHDL code.
In your Vivado project, you must adapt the related cm file to the required FPGA
functionality. For more information, refer to Specifying the FPGA Functionality
(FPGA Programming Handcode Framework Guide ).

For each accessed port in the VHDL code, you must configure the corresponding
I/O function in the handcode FPGA framework INI file. Most of the I/O function
parameters configure the function behavior. For more information, refer to
Specifying the FPGA I/O Interface (FPGA Programming Handcode Framework
Guide ).

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Handcoding Inter-FPGA Communication (FPGA Programming Handcode Framework

Guide )

Overview of the Frameworks Available for MicroAutoBox II (FPGA1401Tp1)

Introduction The FPGA1401Tp1 frameworks are the standard frameworks for MicroAutoBox II
1401/1511/1514 and MicroAutoBox II 1401/1513/1514 with one of the
following I/O modules:
§ DS1552 Multi-I/O Module
§ DS1552B1 Multi-I/O Module
§ DS1554 Engine Control I/O Module

The frameworks provide access to analog and digital signals, and to the
intermodule-bus buffers and registers.

Framework location Depending on the I/O module, there are three frameworks.

The frameworks are stored in the following folders:

§ MicroAutoBox II with DS1514 and DS1552 Multi-I/O Module
<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\
FPGA1401Tp1_DS1552_XC7K325T
§ MicroAutoBox II with DS1514 and DS1552B1 Multi-I/O Module
<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\
FPGA1401Tp1_DS1552B1_XC7K325T
§ MicroAutoBox II with DS1514 and DS1554 Engine Control I/O Module
<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\
FPGA1401Tp1_DS1554_XC7K325T

The entire framework folder must be copied to your working

folder (see also Preparing Your Environment (FPGA Programming
Handcode Framework Guide )). The included handcode FPGA
framework INI file hc_fpga_framework_ini_FPGA1401Tp1_DS1552.m,
hc_fpga_framework_ini_FPGA1401Tp1_DS1552B1.m, or
hc_fpga_framework_ini_FPGA1401Tp1_DS1554_XC7K325T.m must be
adapted to your specific framework configuration. You find the configuration
options in this reference.

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Overview of the Frameworks Available for MicroAutoBox II (FPGA1401Tp1)

Functions for exchanging data The following I/O functions can be used to exchange data with the processor
with the processor application application.

Refer to I/O Functions of the FPGA1401Tp1 with Multi-I/O Module Frameworks

on page 323 or I/O Functions of the FPGA1401Tp1 with Engine Control I/O
Module Framework on page 367.

Functions for exchanging data The following I/O functions can be used to exchange data with the I/O modules.
with the I/O module
DS1552 and DS1552B1 Multi-I/O Modules

I/O Function Available Channels I/O Function Numbering

Digital In (Type A) 16 2 … 17
Digital In (Type B) 8 18 … 25
Digital Out (Type A) 16 2 … 17
Digital Out (Type B) 8 18 … 25
ADC (Type A) 8 26 … 33
ADC (Type B) 16 34 … 49
DAC 4 26 … 29

Refer to I/O Functions of the FPGA1401Tp1 with Multi-I/O Module Frameworks

on page 323.

DS1554 Engine Control I/O Module

I/O Function Available Channels I/O Function Numbering

Digital In (Type B) 8 2…9
Digital Out (Type A) 40 2 … 41
Digital Out (Type B) 8 42 … 49
ADC (Type A) 14 10 … 23

Refer to I/O Functions of the FPGA1401Tp1 with Engine Control I/O Module
Framework on page 367.

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Additional I/O functions for The following I/O functions can be used for special purposes.
special purposes
DS1552 and DS1552B1 Multi-I/O Modules

I/O Function Purpose Available I/O Function

Channels Numbering
Interrupt To implement interrupt 8 1…8
handling.
Status In To get information on 1 1
the state of the FPGA
programming sequence.
LED Out To set the FPGA status LED 1 1
near the DS1514 ZIF I/O
connector.
Sensor Supply To provide a supply voltage. 1 30
UART (RS232) To implement communication 21) 31 … 32
UART via the serial interface. 21) 33 … 34
(RS422/485)
Digital To access digital camshaft 3 50 ... 52
Crank/Cam and crankshaft sensors.
Sensor
Inductive Zero To access inductive zero 1 53
Voltage Detector voltage detectors.
1) To use UART 2, your DS1552 has to be modified by dSPACE.
Refer to I/O Functions of the FPGA1401Tp1 with Multi-I/O Module Frameworks
on page 323.

DS1554 Engine Control I/O Module

I/O Function Purpose Available I/O Function

Channels Numbering
Interrupt To implement interrupt 8 1…8
handling.
Status In To get information on 1 1
the state of the FPGA
programming sequence.
LED Out To set the FPGA status LED 1 1
near the DS1514 ZIF I/O
connector.
Knock Sensor To access knock sensors. 4 24 ... 27
Digital To access digital camshaft 5 28 ... 32
Crank/Cam and crankshaft sensors.
Sensor
Inductive Zero To access inductive zero 1 33
Voltage Detector voltage detectors.
Temperature To access the FPGA die 1 34
temperature.

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Overview of the Frameworks Available for MicroAutoBox III (FPGA1403Tp1)

Refer to I/O Functions of the FPGA1401Tp1 with Engine Control I/O Module
Framework on page 367.

Parameters and ports For detailed information on the I/O functions and their parameters and ports,
refer to the function descriptions in I/O Functions of the FPGA1401Tp1
with Multi-I/O Module Frameworks on page 323 and I/O Functions of the
FPGA1401Tp1 with Engine Control I/O Module Framework on page 367.
The parameter and port descriptions additionally contain more descriptive
names for a simple identification of the parameters and ports. For example,
Fct(<IOFunction_Number>).Parameter(1).Init / Binary point position describes the
Binary point position parameter of the I/O function.

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

Overview of the Frameworks Available for MicroAutoBox III (FPGA1403Tp1)

Introduction The FPGA1403Tp1 frameworks are the standard frameworks for

MicroAutoBox III with DS1514 and one of the following I/O modules:
§ DS1552 Multi-I/O Module
§ DS1552B1 Multi-I/O Module
§ DS1554 Engine Control I/O Module

The frameworks provide access to analog and digital signals, and to the
intermodule-bus buffers and registers.

Framework location Depending on the I/O module, there are three frameworks.

The frameworks are stored in the following folders:

§ MicroAutoBox III with DS1552 Multi-I/O Module
<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\
FPGA1403Tp1_DS1552_XC7K325T

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General Information on the I/O Functions Available with FPGA Frameworks

§ MicroAutoBox III with DS1552B1 Multi-I/O Module

<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\
FPGA1403Tp1_DS1552B1_XC7K325T
§ MicroAutoBox III with DS1554 Engine Control I/O Module
<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\
FPGA1403Tp1_DS1554_XC7K325T

The entire framework folder must be copied to your working

folder (see also Preparing Your Environment (FPGA Programming
Handcode Framework Guide )). The included handcode FPGA
framework INI file hc_fpga_framework_ini_FPGA1403Tp1_DS1552.m,
hc_fpga_framework_ini_FPGA1403Tp1_DS1552B1.m, or
hc_fpga_framework_ini_FPGA1403Tp1_DS1554_XC7K325T.m must be
adapted to your specific framework configuration. You find the configuration
options in this reference.

Functions for exchanging data The following I/O functions can be used to exchange data with the processor
with the processor application application.

I/O Function Available Channels I/O Function Numbering

Refer to I/O Functions of the FPGA1403Tp1 with Multi-I/O Module Frameworks

on page 399 or I/O Functions of the FPGA1403Tp1 with Engine Control I/O
Module Framework on page 443.

Functions for exchanging data The following I/O functions can be used to exchange data with the I/O modules.
with the I/O module
DS1552 and DS1552B1 Multi-I/O Modules

I/O Function Available Channels I/O Function Numbering

Digital In (Type A) 16 2 … 17
Digital In (Type B) 8 18 … 25
Digital Out (Type A) 16 2 … 17
Digital Out (Type B) 8 18 … 25
ADC (Type A) 8 26 … 33

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Overview of the Frameworks Available for MicroAutoBox III (FPGA1403Tp1)

I/O Function Available Channels I/O Function Numbering

ADC (Type B) 16 34 … 49
DAC 4 26 … 29

Refer to I/O Functions of the FPGA1403Tp1 with Multi-I/O Module Frameworks

on page 399.

DS1554 Engine Control I/O Module

I/O Function Available Channels I/O Function Numbering

Digital In (Type B) 8 2…9
Digital Out (Type A) 40 2 … 41
Digital Out (Type B) 8 42 … 49
ADC (Type A) 14 10 … 23

Refer to I/O Functions of the FPGA1403Tp1 with Engine Control I/O Module
Framework on page 443.

Additional I/O functions for The following I/O functions can be used for special purposes.
special purposes
DS1552 and DS1552B1 Multi-I/O Modules

I/O Function Purpose Available I/O Function

Channels Numbering
Interrupt To implement interrupt 8 1…8
handling.
Status In To get information on 1 1
the state of the FPGA
programming sequence.
LED Out To set the FPGA status LED 1 1
near the DS1514 ZIF I/O
connector.
Sensor Supply To provide a supply voltage. 1 30
UART (RS232) To implement communication 21) 31 … 32
UART via the serial interface. 21) 33 … 34
(RS422/485)
Digital To access digital camshaft 3 50 ... 52
Crank/Cam and crankshaft sensors.
Sensor
Inductive Zero To access inductive zero 1 53
Voltage Detector voltage detectors.
1)
To use UART 2, your DS1552 has to be modified by dSPACE.
Refer to I/O Functions of the FPGA1403Tp1 with Multi-I/O Module Frameworks
on page 399.

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General Information on the I/O Functions Available with FPGA Frameworks

DS1554 Engine Control I/O Module

I/O Function Purpose Available I/O Function

Channels Numbering
Interrupt To implement interrupt 8 1…8
handling.
Status In To get information on 1 1
the state of the FPGA
programming sequence.
LED Out To set the FPGA status LED 1 1
near the DS1514 ZIF I/O
connector.
Knock Sensor To access knock sensors. 4 24 ... 27
Digital To access digital camshaft 5 28 ... 32
Crank/Cam and crankshaft sensors.
Sensor
Inductive Zero To access inductive zero 1 33
Voltage Detector voltage detectors.
Temperature To access the FPGA die 1 34
temperature.

Refer to I/O Functions of the FPGA1403Tp1 with Engine Control I/O Module
Framework on page 443.

Parameters and ports For detailed information on the I/O functions and their parameters and ports,
refer to the function descriptions in I/O Functions of the FPGA1403Tp1
with Multi-I/O Module Frameworks on page 399 and I/O Functions of the
FPGA1403Tp1 with Engine Control I/O Module Framework on page 443.
The parameter and port descriptions additionally contain more descriptive
names for a simple identification of the parameters and ports. For example,
Fct(<IOFunction_Number>).Parameter(1).Init / Binary point position describes the
Binary point position parameter of the I/O function.

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

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Unsupported Features of the FPGA Programming Handcode Framework

Unsupported Features of the FPGA Programming Handcode Framework

Introduction The FPGA Programming Handcode Framework does not support all features
that are provided by the FPGA Interface sublibrary of the FPGA Programming
Blockset.

Unsupported features The following FPGA features are exclusively provided by the FPGA Interface
blocks of the FPGA Programming Blockset:
§ FPGA Scope functionality to capture time sequences of FPGA signals.
FPGA Scope blocks can capture an FPGA signal with the time resolution of
the FPGA clock to display the signal in ControlDesk. The handcode framework
does not provide this feature.
§ FPGA signal tracing via FPGA variables that are automatically added to the
FPGA application during the build process.
§ Support of tunable FPGA constants that can be adjusted at run time.
§ FPGA test access and scaling to modify the I/O signals at run time.
§ Support of multiple FPGA clock domains.
The FPGA interface of the handcode framework must be used with the base
rate of the FPGA board. You can handcode FPGA subsystems with other clock
domains, but the handcode framework does not support you in handcoding
such subsystems.
§ Support of multicore processor applications.
A multicore processor application cannot access a handcoded FPGA
application from different processor cores. However, each processor core can
access its own FPGA board if the real-time hardware provides multiple FPGA
boards.
§ Support of scaling subsystems.
Scaling subsystems are used to preprocess or postprocess processor signals.
Scaling subsystems are part of the FPGA model, although they are executed
by the real-time processor. The handcode framework does not provide this
feature.
§ MGT support for MicroLabBox II.

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I/O Functions of the DS1202 FPGA I/O Type 1 Framework

I/O Functions of the DS1202 FPGA I/O Type 1

Framework

Introduction The DS1202 FPGA I/O Type 1 frameworks DS1302_XC7K325T and

DS1302_XC7K325T_FLEXIBLEIO provide the custom I/O functionality of
MicroLabBox.

Where to go from here Information in this section

ADC (Class 1).......................................................................................... 44

To read data from an analog input signal in the FPGA application using
the class 1 A/D conversion function.

ADC (Class 2).......................................................................................... 46

To read data from an analog input signal in the FPGA application using
the class 2 A/D conversion function.

Buffer In.................................................................................................. 47
To read data from an internal bus buffer with a data width of 32 bits.

Buffer64 In.............................................................................................. 49
To read data from an internal bus buffer with a data width of 64 bits.

Buffer Out............................................................................................... 50
To write data to an internal bus buffer with a data width of 32 bits.

Buffer64 Out........................................................................................... 52
To write data to an internal bus buffer with a data width of 64 bits.

Buzzer..................................................................................................... 54
To generate an acoustic signal.

DAC (Class 1).......................................................................................... 56

To write data to an analog output signal in the FPGA application using
the class 1 D/A conversion function.

Digital InOut (Class 1).............................................................................. 57

To read or write data to a digital I/O signal in the FPGA application using
the class 1 digital I/O function.

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I/O Functions of the DS1202 FPGA I/O Type 1 Framework

Digital InOut (Class 2).............................................................................. 60

To read or write data to a digital I/O signal in the FPGA application using
the class 2 digital I/O function.

Interrupt.................................................................................................. 62
To request a processor interrupt outside of the FPGA application.

LED Out................................................................................................... 62
To write a digital signal that controls the color of one FPGA status LED on
the board.

Proc App Status....................................................................................... 63

To read the status of application that is running on the computation
node.

Register In............................................................................................... 64
To read data from an internal bus register with a data width of 32 bits.

Register64 In........................................................................................... 66
To read data from an internal bus register with a data width of 64 bits.

Register Out............................................................................................ 68
To write data to an internal bus register with a data width of 32 bits.

Register64 Out........................................................................................ 69
To write data to an internal bus register with a data width of 64 bits.

Resolver................................................................................................... 71
To get the rotor's position via a resolver sensor in the FPGA application.

Status In.................................................................................................. 74
To read a digital signal that outputs the state of the FPGA initialization
sequence.

UART (RS232).......................................................................................... 74
To implement communication via serial interface for RS232 UART type.

UART (RS422/485)................................................................................... 79
To implement communication via serial interface for RS422/485 UART
type.

ADC (Class 1)

Purpose To read data from an analog input signal in the FPGA application using the class
1 A/D conversion function.

Description According to the number of physical connections available on MicroLabBox's

DS1302 board, you can select the ADC (Class 1) I/O functions. There are 24
differential analog input channels.

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ADC (Class 1)

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 2 … 25.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 23.

adctp1_<ChannelNumber>_value / Data Outputs the current results of an

analog input channel.
Data type: Fix_16_0
Range: ‑32767 … +32767 (‑10 V … +10 V)
Update rate: 1 Msps

adctp1_<ChannelNumber>_convert / Convert Triggers the sampling of the

A/D converter. When the value is set to 1 for at least one clock cycle, the ADC
starts the conversion. The port allows a precise definition of the starting point of
ADC sampling. The Busy outport signals the end of the conversion process.
Setting this value permanently to 1 results in continuous sampling.
Data type: UFix_1_0
Range: 0 or 1

adctp1_<ChannelNumber>_busy / Busy Outputs an end of conversion

signal if the conversion result is available. If the flag changes from 0 to 1, the
ADC data contains a new value. The flag is set to 0 for only one clock cycle.
Data type: UFix_1_0
Range: 0 or 1

I/O mapping The signals are available at the Analog In connector.

The channel numbers 00 … 23 corresponds to the channels 1 … 24.

MicroLabBox has static mapping between I/O signals and I/O pins. The signal
name is also printed on the housing of MicroLabBox. You have to consider only
the connector panel type.

For a detailed connector pinout, refer to:

§ Analog I/O A Connector (Sub-D) (MicroLabBox Hardware Installation and
Configuration )
§ Analog In and Analog Out Connectors (BNC) (MicroLabBox Hardware
Installation and Configuration )
§ Analog In Class 1 Connectors (Spring-Cage) (MicroLabBox Hardware
Installation and Configuration )

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For detailed information on the channel characteristics, refer to Analog Class 1

Inputs (MicroLabBox Hardware Installation and Configuration ).

ADC (Class 2)........................................................................................................................... 46

Overview of the Frameworks Available for MicroLabBox........................................................... 14

ADC (Class 2)

Purpose To read data from an analog input signal in the FPGA application using the
class 2 A/D conversion function.

Description According to the number of physical connections available on MicroLabBox's

DS1302 board, you can select the ADC (Class 2) I/O functions. There are 8
differential analog input channels.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 26 … 33.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 7.

adctp2_<ChannelNumber>_value / Data Outputs the current results of

analog input channel.
Data type: Fix_16_0
Range: ‑32767 … +32767 (‑10 V … +10 V)
Update rate: 10 Msps

I/O mapping The signals are available at the Analog In connector.

The channel numbers 0 … 7 corresponds to the channels 1 … 8.

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Buffer In

MicroLabBox has static mapping between I/O signals and I/O pins. The signal
name is also printed on the housing of MicroLabBox. You have to consider only
the connector panel type.

For a detailed connector pinout, refer to:

§ Analog I/O A Connector (Sub-D) (MicroLabBox Hardware Installation and
Configuration )
§ Analog In and Analog Out Connectors (BNC) (MicroLabBox Hardware
Installation and Configuration )
§ Analog In Class 2 Connectors (Spring-Cage) (MicroLabBox Hardware
Installation and Configuration )

For detailed information on the channel characteristics, refer to Analog Class 2

Inputs (MicroLabBox Hardware Installation and Configuration ).

ADC (Class 1)........................................................................................................................... 44

Overview of the Frameworks Available for MicroLabBox........................................................... 14

Buffer In

Purpose To read data from an internal bus buffer with a data width of 32 bits.

Description If you select Buffer as the access type, the data is read from an internal bus
buffer. 32 buffers are available. Each buffer has a variable buffer size of 1 up to
32768 elements. Each buffer element has a data width of 32 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 257 … 288.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(1).Init / Binary
point position (fraction width) Lets you specify the binary point position or
returns the fraction width of the Data outport depending on the format selected
in the Format setting (see below).
§ signed/unsigned
The values of the Data outport are in fixed-point format. You can specify the
binary point position of the 32-bit value in the range 0 … 32.
0 represents the lowest bit position, 32 the highest bit position.

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I/O Functions of the DS1202 FPGA I/O Type 1 Framework

§ floating-point
The values of the Data outport are in floating‑point format. The parameter
then provides the fraction width.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(2).Init /
Format Lets you specify the data format of the Data outport.
§ signed/unsigned
The values of the Data outport are in fixed‑point format with or without one
bit reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
§ floating‑point
The values of the Data outport are in floating‑point format.
The 32‑bit data value supports the single-precision floating‑point format with a
fraction width of 24, which complies with the IEEE 754 standard (single).
The fraction width is provided by the Binary point position (or fraction
width) setting.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(3).Init / Buffer
size Lets you specify the size of the buffer in the range 1 … 32768. The
maximum range of the Address inport depends on the buffer size.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmemf_<ChannelNumber>_count / Data Count Outputs the number of

elements in the current buffer. The maximum range depends on the specified
buffer size. You can use the value to define the valid range for the Address
inport of 0 … (Data Count ‑1).

xmemf_<ChannelNumber>_dout / Data Outputs a 32-bit data value to

be read from an internal bus buffer. The data format depends on the related
parameter settings.

xmemf_<ChannelNumber>_new_data / Data New Outputs a flag that

indicates the changes of the buffer status. If the flag changes from 0 to 1 and
then back to 0, the requested buffer contains new values and is ready to be
read. The flag is set to 1 only within one clock cycle.

xmemf_<ChannelNumber>_addr / Address Specifies an element in the

buffer you want to read. The block requires 1 clock cycle to update the value
of the Data outport according to the specified address. The maximum port
range depends on the specified buffer size. The valid port range depends on
the number of elements currently in the buffer (see Data Count outport). If
you request data from an address that is greater than the Data Count value,
the output of the Data outport is undefined. The first element of a buffer is
addressed by 0.

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Buffer64 In

The channel number can be specified in the range 00 … 31.

xmem64f_<ChannelNumber>_count / Data Count Outputs the number of

elements in the current buffer. The maximum range depends on the specified
buffer size. You can use the value to define the valid range for the Address
inport of 0 … (Data Count -1).

xmem64f_<ChannelNumber>_dout / Data Outputs a 64-bit data value to

be read from an internal bus buffer. The data format depends on the related
parameter settings.

xmem64f_<ChannelNumber>_new_data / Data New Outputs a flag that

xmem64f_<ChannelNumber>_addr / Address Specifies an element in the

The channel number can be specified in the range 00 … 31.

xmemp_<ChannelNumber>_din / Data Specifies a 32-bit data value to be

written to an internal bus buffer. The data format depends on the related
parameter settings.

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xmemp_<ChannelNumber>_write / Enable Specifies the current valid Data

port value.
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.

xmemp_<ChannelNumber>_finished / Ready Explicitly specifies the buffer

state as ready to send the buffer immediately, even if it is not completely filled.
The data values will be written to a new buffer in the next clock cycle. While
the port value is 1, transmission switches buffer in every clock cycle. The value
should therefore be set for one clock cycle only. If the buffer is completely filled,
it is automatically switched, and the data values are stored in a new buffer.
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready for sending, even if it is not completely filled.
The buffer is switched and the data values are accessible via the internal bus in
the next clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.

xmemp_<ChannelNumber>_overflow / Overflow Outputs a flag that

indicates that a buffer overflow occurred. An overflow occurs if the old buffer is
not read completely before a new buffer is ready to be read.
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.

The channel number can be specified in the range 00 … 31.

xmem64p_<ChannelNumber>_din / Data Specifies a 64-bit data value to

be written to an internal bus buffer. The data format depends on the related
parameter settings.

xmem64p_<ChannelNumber>_write / Enable Specifies the current valid

Data port value.
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.

xmem64p_<ChannelNumber>_finished / Ready Explicitly specifies the

buffer state as ready to send the buffer immediately, even if it is not completely

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I/O Functions of the DS1202 FPGA I/O Type 1 Framework

filled. The data values will be written to a new buffer in the next clock cycle.
While the port value is 1, transmission switches buffer in every clock cycle. The
value should therefore be set for one clock cycle only. If the buffer is completely
filled, it is automatically switched, and the data values are stored in a new buffer.
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready for sending, even if it is not completely filled.
The buffer is switched and the data values are accessible via the internal bus in
the next clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.

xmem64p_<ChannelNumber>_overflow / Overflow Outputs a flag that

Purpose To generate an acoustic signal.

Description You can add the Buzzer I/O function to your application to access the board's
buzzer.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number is 85.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

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Buzzer

buzzer_frequency / Frequency Specifies the period of the acoustic signal in

steps of 40 µs. You calculate the frequency with the following equation:
frequency [Hz] = 1 / period [s]
Data type: UFix8_0
Value range: 0 … 255
§ 0 : No acoustic signal
§ 1: 40 µs (25 kHz)
§ ...
§ 255: 10200 µs (98 Hz)

buzzer_beep_duration / Beep Duration Specifies the duration of one beep

of the acoustic signal in steps of 10 ms.
Data type: UFix8_0
Value range: 0 … 255
§ 0: No acoustic signal
§ 1 ... 254: 10 ms ... 2540 ms
§ 255: The beep is generated permanently

buzzer_pause_duration / Pause Duration Specifies the duration of a pause

between two beeps of the buzzer in steps of 10 ms.
Data type: UFix8_0
Value range: 0 … 255 (0 ms ... 2550 ms)

buzzer_beep_count / Beep Count Specifies the number of beeps to be

generated.
Data type: UFix8_0
Value range: 0 … 255
§ 0: No acoustic signal
§ 255: The number of beeps is infinite

buzzer_start / Start Starts the buzzer if the value is 1 for one clock cycle.
The started buzzer outputs the specified acoustic signal. New values of the
Frequency, Beep Duration, Pause Duration, and Beep Count ports take
effect immediately. For example: If you change the value of the Frequency port
to 0, the buzzer stops the generation of an acoustic signal immediately.
Data type: UFix1_0
Range: 0 or 1

Overview of the Frameworks Available for MicroLabBox........................................................... 14

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DAC (Class 1)

Purpose To write data to an analog output signal in the FPGA application using the class
1 D/A conversion function.

Description According to the number of physical connections available on MicroLabBox's

DS1302 board, you can select the DAC (Class 1) I/O functions. There are 16
single‑ended analog output channels.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 53 … 68.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 15.

dactp1_<ChannelNumber>_value / Data Outputs the current results of an

analog output channel.
Data type: Fix_16_0
Value range: ‑32767 … +32767 (‑10 V … +10 V)
Update rate: 2.78 Msps

dactp1_<ChannelNumber>_convert / Convert Triggers the sampling of the

D/A converter. When the value is set to 1 for at least one clock cycle, the DAC
starts the conversion. The port allows a precise definition of the starting point of
DAC sampling. The Busy outport signals the end of the conversion process.
Setting this value permanently to 1 results in continuous sampling.
Data type: UFix_1_0
Range: 0 or 1

dactp1_<ChannelNumber>_busy / Busy Outputs an end of conversion

signal if the conversion result is available. If the flag changes from 0 to 1, the
DAC data contains a new value. The flag is set to 1 for only one clock cycle.
Data type: UFix_1_0
Range: 0 or 1

I/O mapping The signals are available at the Analog Out connector.

The channel numbers 00 … 15 corresponds to the channels 1 … 16.

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Digital InOut (Class 1)

MicroLabBox has static mapping between I/O signals and I/O pins. The signal
name is also printed on the housing of MicroLabBox. You have to consider only
the connector panel type.

For a detailed connector pinout, refer to:

§ Analog I/O B Connector (Sub-D) (MicroLabBox Hardware Installation and
Configuration )
§ Analog In and Analog Out Connectors (BNC) (MicroLabBox Hardware
Installation and Configuration )
§ Analog Out Class 1 Connectors (Spring-Cage) (MicroLabBox Hardware
Installation and Configuration )

For detailed information on the channel characteristics, refer to Analog Class 1

Outputs (MicroLabBox Hardware Installation and Configuration ).

Overview of the Frameworks Available for MicroLabBox........................................................... 14

Digital InOut (Class 1)

Purpose To read or write data to a digital I/O signal in the FPGA application using the
class 1 digital I/O function.

Description According to the number of physical connections available on MicroLabBox's

DS1302 board, you can select the Digital InOut (Class 1) I/O functions. There
are 48 single‑ended digital I/O channels, which you can separately configure for
input or output.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 5 … 52.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(2).Init / Invert
values Lets you specify whether to invert the input and output values of the
digital channel.
§ 0: The values are not inverted.
§ 1: The values are inverted.

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IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Input
filter Lets you specify the minimum pulse length for detecting a valid input in
the range 0 … 10,000,000 ns.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(5).Init / High
supply Lets you specify the high level voltage for the digital outputs.
§ 0: 5 V
§ 1: 3.3 V
§ 2: 2.5 V

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(6).Init / Rising edge

delay Lets you specify the delay for the rising edge detection in the range
0 … 65500 ns.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 47.

diotp1_<ChannelNumber>_ena / Enable Controls the hardware output.

Data values if the channel is used as digital input:
§ 0: The Data In outport is disabled.
§ 1: The Data In outport outputs the current results of the digital input channel.
Data values if the channel is used as digital output:
§ 0: The hardware is set to High-Z.
§ 1: The hardware output reacts to the Data Out inport.
Data type: UFix_1_0

diotp1_<ChannelNumber>_dir / Direction Controls the direction of the

digital channel.
Data type: UFix_1_0
§ 0: The channel is used as digital input channel.
§ 1: The channel is used as digital output channel.

diotp1_<ChannelNumber>_in / Data In Outputs the current results of the

digital input channel.
Data type: UFix_1_0
§ 0: Input voltage falled below the threshold low voltage of 0.8 V.
§ 1: Input voltage exceeded the threshold high voltage of 2 V.
Update rate: 100 MHz

Note

The frequency that can be generated is much smaller than the update rate.
For information on the electrical characteristics of the DS1302 board, refer
to Digital Class 1 I/O (Bidirectional) (MicroLabBox Hardware Installation and
Configuration ).

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Digital InOut (Class 1)

diotp1_<ChannelNumber>_out / Data Out Outputs a signal in the

specified range.
If driven with 0, the hardware output is 0 V. If driven with 1, the hardware
output is set to the specified high supply voltage. The hardware output is
only driven if the Enable port is set to 1, otherwise the output is set to high
impedance (High-Z).
Data Type: UFix_1_0
Update rate: 100 MHz

Note

I/O mapping The signals are available at the Digital I/O connector.

The channel numbers 00 … 47 corresponds to the channels 1 … 48.

MicroLabBox has static mapping between I/O signals and I/O pins. The signal
name is also printed on the housing of MicroLabBox. You have to consider only
the connector panel type.

For a detailed connector pinout, refer to:

§ Digital I/O A Connector (Sub-D) (MicroLabBox Hardware Installation and
Configuration )
DIO1 ch 1 … DIO1 ch 32
§ Digital I/O B Connector (Sub-D) (MicroLabBox Hardware Installation and
Configuration )
DIO1 ch 33 … DIO1 ch 48
§ Digital I/O Class 1 Connectors (Spring-Cage) (MicroLabBox Hardware
Installation and Configuration )
DIO1 ch 1 … DIO1 ch 48

For detailed information on the channel characteristics, refer to:

§ Digital Class 1 I/O (Bidirectional) (MicroLabBox Hardware Installation and
Configuration )

Digital InOut (Class 2)............................................................................................................... 60

Overview of the Frameworks Available for MicroLabBox........................................................... 14

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Digital InOut (Class 2)

Purpose To read or write data to a digital I/O signal in the FPGA application using the
class 2 digital I/O functions.

Description According to the number of physical connections available on MicroLabBox's

DS1302 board, you can select the Digital InOut (Class 2) I/O functions. There
are 12 differential digital I/O channels, which you can separately configure for
input or output.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 73 … 84.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Input
filter Lets you specify the minimum pulse length for detecting a valid input in
the range 0 … 10,000,000 ns.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(6).Init / Rising edge

delay Lets you specify the delay for the rising edge detection in the range
0 … 65,500 ns.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 11.

diotp1_<ChannelNumber>_ena / Enable Controls the hardware output. If

set to 1, the hardware output reacts to the Data Out outport, otherwise it is set
to High-Z.
Data type: UFix_1_0

diotp1_<ChannelNumber>_dir / Direction Controls the direction of the

digital channel.
Data type: UFix_1_0
§ 0: The channel is used as digital input channel.
§ 1: The channel is used as digital output channel.

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Digital InOut (Class 2)

diotp1_<ChannelNumber>_in / Data In Outputs the current results of the

digital input channel.
Data type: UFix_1_0
§ 0: Input voltage falled below the threshold low voltage of 0.8 V.
§ 1: Input voltage exceeded the threshold high voltage of 2 V.
Update rate: 100 MHz

Note

The frequency that can be generated is much smaller than the update rate.
For information on the electrical characteristics of the DS1302 board, refer
to Digital Class 2 I/O (Bidirectional) (MicroLabBox Hardware Installation and
Configuration ).

diotp1_<ChannelNumber>_out / Data Out Outputs a signal in the

Note

I/O mapping The signals are available at the Digital I/O connector.

The channel numbers 00 … 11 corresponds to the channels 1 … 12.

MicroLabBox has static mapping between I/O signals and I/O pins. The signal
name is also printed on the housing of MicroLabBox. You have to consider only
the connector panel type.

For a detailed connector pinout, refer to:

§ Digital I/O B Connector (Sub-D) (MicroLabBox Hardware Installation and
Configuration )
§ Digital I/O Class 2 Connectors (Spring-Cage) (MicroLabBox Hardware
Installation and Configuration )

For detailed information on the channel characteristics, refer to:

§ Digital Class 2 I/O (Bidirectional) (MicroLabBox Hardware Installation and
Configuration )

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Digital InOut (Class 1)............................................................................................................... 57

Overview of the Frameworks Available for MicroLabBox........................................................... 14

Interrupt

Purpose To request a processor interrupt outside of the FPGA application.

Description MicroLabBox provides 32 interrupt lines. An interrupt is requested if the Int port
is set to 1 for at least one clock cycle. If you set the Int port to 0, the last
interrupt is not released but saved. An interrupt is edge-triggered.

Parameters The Interrupt I/O function can be used for up to 32 channels / interrupt lines.
You will find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 32.

IRQProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

usr_interrupt_<ChannelNumber> / Int Provides the interrupt request line.

§ 0 to 1: Interrupt is requested (edge-triggered).
§ 0: No interrupt is requested. Last requested interrupt is saved.

Overview of the Frameworks Available for MicroLabBox........................................................... 14

LED Out

Purpose To write a digital signal that controls the color of one FPGA status LED on the
board.

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Proc App Status

Description According to the number of physical connections available on MicroLabBox's

DS1302 board, you can select the LED Out I/O functions. There are 4 digital
output channels. For each FPGA status LED you can separately configure the RGB
color value.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 4.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

led_<ChannelNumber>_red / Red Specifies the red portion of the LED's

color value.
Data type: UFix8_0
Value range: 0 … 255

led_<ChannelNumber>_green / Green Specifies the green portion of the

LED's color value.
Data type: UFix8_0
Value range: 0 … 255

led_<ChannelNumber>_blue / Blue Specifies the blue portion of the LED's

color value.
Data type: UFix8_0
Value range: 0 … 255

Overview of the Frameworks Available for MicroLabBox........................................................... 14

Proc App Status

Purpose To read the status of application that is running on the computation node.

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Description There is one digital input channel that is used for the Proc App Status I/O
function.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 34.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

appl_run/ Processor Application Status Outputs the state of the application

that is running on the computation node.
Data type: UFix_1_0
§ 0: The application on the computation node is stopped.
§ 1: The application on the computation node is running.

Overview of the Frameworks Available for MicroLabBox........................................................... 14

Purpose To read data from an internal bus register with a data width of 32 bits.

Description If you select Register as the access type, the data is read from an internal bus
register. 256 registers are available with a data width of 32 bits each. The values
are transmitted element by element. If you want to access data from several
registers simultaneously, you can group these registers by specifying the same
group identifier for them.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 256.

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Register In

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(3).Init / Register
group ID Lets you specify a number in the range 1 … 63 to create
register groups. Registers that you specified with the same group ID are
sampled simultaneously within the FPGA application. The values therefore form a
consistent data group that is written to the internal bus.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 255.

xreg_<ChannelNumber>_dout / Data Outputs a 32-bit data value to be

read from an internal bus register. The data format depends on the related
parameter settings.

xreg_<ChannelNumber>_dout_wr / Data New Outputs a flag that

indicates the changes of the register status. If the flag changes from 0 to 1

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and then back to 0, the requested register contains a new value. The flag is set
to 1 only within one clock cycle.

Overview of the Frameworks Available for MicroLabBox........................................................... 14

Register64 In............................................................................................................................ 66

Register64 In

Purpose To read data from an internal bus register with a data width of 64 bits.

Description If you select Register64 as the access type, the data is read from an internal bus
register. 256 registers are available with a data width of 64 bits each. The values
are transmitted element by element. If you want to access data from several
registers simultaneously, you can group these registers by specifying the same
group identifier for them.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 289 … 544.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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Register64 In

PHSProperties.In.Fct(<IOFunction_Number>).Parameter(2).Init /
Format Lets you specify the data format of the Data outport.
§ signed/unsigned
The values of the Data outport are in fixed‑point format with or without one
bit reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
§ floating‑point
The values of the Data outport are in floating‑point format.
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is provided by the Binary point position (or fraction
width) setting.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 255.

xreg64_<ChannelNumber>_dout / Data Outputs a 64-bit data value to be

read from an internal bus register. The data format depends on the related
parameter settings.

xreg64_<ChannelNumber>_dout_wr / Data New Outputs a flag that

indicates the changes of the register status. If the flag changes from 0 to 1
and then back to 0, the requested register contains a new value. The flag is set
to 1 only within one clock cycle.

Overview of the Frameworks Available for MicroLabBox........................................................... 14

Register In................................................................................................................................ 64

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Purpose To write data to an internal bus register with a data width of 32 bits.

Description If you select Register as the access type, the data is written to an internal bus
register. 256 registers are available with a data width of 32 bits each. The values
are transmitted element by element. If you want to access data from several
registers simultaneously, you can group these registers by specifying the same
group identifier for them.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 256.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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Register64 Out

from the nternal bus sequentially and then provided to the FPGA application
simultaneously.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 255.

xreg_<ChannelNumber>_din / Data Specifies a 32-bit data value to be

written to an internal bus register. The data format depends on the related
parameter settings.

Overview of the Frameworks Available for MicroLabBox........................................................... 14

Register In................................................................................................................................ 64
Register64 Out......................................................................................................................... 69

Register64 Out

Purpose To write data to an internal bus register with a data width of 64 bits.

Description If you select Register64 as the access type, the data is written to an internal bus
register. 256 registers are available with a data width of 64 bits each. The values
are transmitted element by element. If you want to access data from several
registers simultaneously, you can group these registers by specifying the same
group identifier for them.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 289 … 544.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(1).Init / Binary
point position (or fraction width) Lets you specify the binary point position

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or returns the fraction width of the Data inport depending on the format
selected in the Format setting (see below).
§ signed/unsigned
The values of the Data inport are in fixed-point format. You can specify the
binary point position of the 64-bit value in the range 0 … 64.
0 represents the lowest bit position, 64 the highest bit position.
64-bit fixed-point data types are converted to double. Therefore, the fixed-
point resolution of fixed-point data types is restricted to 53 bits.
§ floating-point
The values of the Data inport are in floating‑point format. The parameter then
provides the fraction width.

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init /
Register64 group ID Lets you specify a number in the range 1 … 63 to
create register groups. Registers that you specified with the same group ID
are read from the nternal bus sequentially and then provided to the FPGA
application simultaneously.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 255.

xreg64_<ChannelNumber>_din / Data Specifies a 64-bit data value to be

written to an internal bus register. The data format depends on the related
parameter settings.

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Resolver

Overview of the Frameworks Available for MicroLabBox........................................................... 14

Register Out............................................................................................................................. 68
Register64 In............................................................................................................................ 66

Resolver

Purpose To get the rotor's position via a resolver sensor in the FPGA application.

Description According to the number of physical connections available on MicroLabBox's

DS1302 board, you can select the Resolver I/O functions. There are two resolver
input channels.

This I/O function is not taken into account if you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 35 … 36.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.In.Fct(<IOFunctionNumber>).Parameter(2).Init / Desired
excitation frequency Lets you specify the frequency of the sine signal to be
used for the excitation of the resolver rotor in the range 2,000 Hz … 20,000 Hz
in steps of 250 Hz.

IOProperties.In.Fct(<IOFunctionNumber>).Parameter(3).Init / Excitation
RMS voltage Lets you specify the voltage level of the excitation output
signal:
§ 0: 3.0 VRMS
§ 1: 7.0 VRMS
§ 2: 10.0 VRMS

IOProperties.In.Fct(<IOFunctionNumber>).Parameter(4).Init / Input RMS

voltage Lets you specify the voltage level of the sine and cosine input signals:
§ 0: 1.5 VRMS
§ 1: 3.5 VRMS
§ 2: 5.0 VRMS

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IOProperties.In.Fct(<IOFunctionNumber>).Parameter(5).Init / Maximum
speed Lets you specify the maximum speed to be measured in revolutions
per minute. By specifying the speed range, you set the related resolution.
§ 0: Specifies a maximum speed of 150,000 rpm and a resolution of 10 bits.
§ 1: Specifies a maximum speed of 60,000 rpm and a resolution of 12 bits.
§ 2: Specifies a maximum speed of 30,000 rpm and a resolution of 14 bits.
§ 3: Specifies a maximum speed of 7500 rpm and a resolution of 16 bits.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 1.

resolver_<ChannelNumber>_enable / Enable Enables the excitation

voltage:
§ 0: The resolver interface provides no excitation voltage.
§ 1: The resolver interface provides the excitation voltage that you set with the
Excitation RMS voltage parameter.
Data type: UFix_1_0
Data width: 1

resolver_<ChannelNumber>_mech_pos / Mechanical Position Outputs

the position of the resolver sensor as a 16-bit angle value. The 16-bit range
of 0 … +65535 corresponds to 0° ... (360 - 2-16)°.
Formula for angle calculation:
alpha[°] = Mechanical Position * 360°/216.
Data type: UFix_16_0
Range: 0 … +65535
Data width: 1

resolver_<ChannelNumber>_valid / Valid Outputs whether the angle

position and fault status that are provided by the resolver sensor are valid.
This port is used to evaluate whether the resolver interface is ready to receive
data from the input signals:
§ 0: The hardware cannot get data from the input signals. The current values are
not valid.
§ 1: Data values for the position and the fault status has been received. The
current values are valid.
Data type: UFix_1_0
Data width: 1

resolver_<ChannelNumber>_update / Update Outputs a flag that

indicates that a new position value or fault status is available.
A high level acknowledges the update. The flag is set high only within one clock
cycle.
Data type: UFix_1_0
Data width: 1

resolver_<ChannelNumber>_fault / Fault Outputs the fault status of the

resolver interface. The measured position might be valid only if no error is found.

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Resolver

Each bit in the 8‑bit value represents a specific fault if its value is 1:
§ Bit 0 (LSB): Configuration parity error
§ Bit 1: Phase lock
§ Bit 2: Velocity too high
§ Bit 3: Loss of tracking
§ Bit 4: Degradation of signal mismatch
§ Bit 5: Degradation of signal overrange
§ Bit 6: Inputs loss of signal
§ Bit 7: Inputs clipped
Data type: UFix_1_0
Data width: 8
For more information on the status information, refer to Resolver Interface
(MicroLabBox Features ).

resolver_<ChannelNumber>_err_rst / Reset Resets the fault status of the

resolver interface that is provided at the fault port to 0:
§ 0: No reset.
§ 1: Resets the fault status.
Data type: UFix_1_0
Data width: 1

I/O mapping The signals are available at the Resolver connector.

The channel numbers 0 … 1 correspond to the channels 1 … 2.

MicroLabBox has static mapping between I/O signals and I/O pins. The signal
name is also printed on the housing of MicroLabBox. You have to consider only
the connector panel type.

Each interface provides six signals:

§ 2 differential analog output signals for EXC and EXC
§ 4 differential analog input signals for SIN, SIN, COS and COS

For a detailed connector pinout, refer to:

§ Resolver Connectors (Sub-D) (MicroLabBox Hardware Installation and
Configuration )
§ Resolver Connectors (Spring-Cage) (MicroLabBox Hardware Installation and
Configuration )

For a detailed information on the channel characteristics, refer to Resolver

Interfaces (MicroLabBox Hardware Installation and Configuration ).

Resolver Interface (MicroLabBox Features )

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References

Overview of the Frameworks Available for MicroLabBox........................................................... 14

Status In

Purpose To read a digital signal that outputs the state of the FPGA initialization sequence.

Description The DS1302 framework provides one digital input channel for the Status In I/O
function.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number is to be specified with 1.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

init_done/ Init Done Outputs the state of the initialization sequence that is
started after programming the FPGA.
Data type: UFix_1_0
§ 0: Initialization sequence is in progress.
§ 1: Initialization sequence has finished.

Overview of the Frameworks Available for MicroLabBox........................................................... 14

UART (RS232)

Purpose To implement communication via serial interface for RS232 UART type.

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UART (RS232)

Description According to the number of physical connections available on MicroLabBox's

DS1302 board, you can select the UART (RS232) I/O function. There are two
channels for this function.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 69 … 70.

Most of the parameters are used for the UART (RS232) and UART (RS422/485)
I/O functions.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(1).Init / Baud
rate Lets you specify the baud rate of the UART in the range 50 … 1,000,000
baud (bits per second).
The baud rate depends on the parameters 2, 3 and 4, and can be calculated by
the following formula:
BaudRate = (10^8 · uart_x_dcm_m) / (4 · uart_x_dcm_d
· (uart_dcm_clk_divider+1))
With:

Variable Parameter Description

uart_x_dcm_m1) Parameter(2).Init Multiplier for the digital clock manager (DCM)
module in the range 2 … 255.
uart_x_dcm_d1) Parameter(3).Init Divisor for the digital clock manager (DCM)
module in the range 1 … 255.
uart_x_dcm_clk_divider1) Parameter(4).Init UART clock divider in the range 0 … 262,143.
1) x=1 for UART 1; x=2 for UART 2

Note

Limitations:
§ The maximum baud rate of 1,000,000 baud must not be exceeded.

Tip

You find the DS1302_uart_parameters.mat file in

<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\DS1302
_XC7K325T that you can open in MATLAB. It contains some calculated baud
rates and the percentage deviations to the supported baud rates according
to the parameters m, d and the clock divider.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(5).Init / Word
length Lets you specify the word length in the range 5 … 9 bit. The word

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length includes the number of data bits and the optional parity bit. Exceeding
bits in a message are ignored at the transmitter or cleared at the receiver.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(6).Init / Stop
bits Lets you specify the length of the stop bits in half of bits.

Stop Bits Parameter Value

1 2
1.5 3
2 4

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(7).Init / UART
type Lets you specify the UART type.

Value UART Type

0 RS232
1 RS422/485

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(8).Init /
Termination Lets you specify the termination state.

Note

For the RS232 UART type, the termination must be set to 0 (disconnected).

Value Termination State Description

0 Disconnected § The RXD/CTS and TXD/RTS signals are not
terminated.
1 Connected § Not allowed

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 1.

There is only one section in the file that is valid for both UART types.

uart_<ChannelNumber>_rd / Read Enable Specifies to start receiving a

value.
After three clock cycles, the value is available and can be read from the RX FIFO
buffer. The value remains valid until the next Read_Enable signal.
Before you read data from the RX FIFO buffer, you should check the
Read_Fifo_Empty signal not to be set. The Read_Fifo_Empty signal switches
one clock cycle after the RX FIFO value has been read.
Do not use the Read_Data_Count signal (Read_Data_Count < 0) to check the
RX FIFO buffer, because it requires one additional clock cycle to get the count
value.
You can read one value per FPGA clock cycle from the UART.

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UART (RS232)

uart_<ChannelNumber>_rd_data_count / Read Data Count Outputs the

number of new entries in the RX FIFO buffer.
Two clock cycles are required to return the number of entries.
If you only want to check whether a value is available in the RX FIFO buffer, use
the Read_Fifo_Empty signal instead of this.
Value range: 0 … 2047

uart_<ChannelNumber>_rd_fifo_empty / Read Fifo Empty Outputs the

status of the RX FIFO buffer.
If the status of the buffer is not empty, then you can start reading the data using
the Read_Enable signal.
The Read_Fifo_Empty signal switches one clock cycle after the FIFO value has
been read.
Do not use the Read_Data_Count signal to check the status of the buffer
(Read_Data_Count>0), because this requires one additional clock cycle before its
value is valid.
Range:
§ 0: The RX FIFO buffer is not empty.
§ 1: The RX FIFO buffer is empty.

uart_<ChannelNumber>_rd_data / Read Data Outputs the last read data

from the RX FIFO buffer.
The read_data is available after three clock cycles after the Read_Enable signal.
The return value is 0, if the data is read before anything has been received by the
RX hardware input.
Range: 0 … 511
The hardware input receives serial data for the UART RX FIFO buffer using
inverted voltage levels of ‑6 V (logical high) and +6 V (logical low).

uart_<ChannelNumber>_wr / Write Enable Specifies to start sending a

value.
The Write_Data value is written to the TX FIFO buffer, from which it is
automatically send to the TX output pin of the I/O connector using the specified
UART communication settings.
Write_Enable must be set to 1 for only one clock cycle.
Before you write data to the TX FIFO buffer, you should check the
Write_Fifo_Full signal not to be set. The Write_Fifo_Full signal switches one
clock cycle after the Write_Enable signal has been set.
Do not use the Write_Data_Count signal (Write_Data_Count < 2047) to check
the TX FIFO buffer, because it requires one additional clock cycle to get the count
value.
The hardware output port is driven with the values from the TX FIFO buffer. It
is synchronously running to the UART clock defined by the UART baud rate. The
hardware port has inverted voltage levels of ‑6 V (logical high) and +6 V (logical
low).

uart_<ChannelNumber>_wr_data_count / Write Data Count Outputs the

number of values in the TX FIFO buffer.
The values in the TX FIFO buffer has not been sent already.

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Do not use the Write_Data_Count signal to check the status of the buffer
(Write_Data_Count<2047), because this requires two clock cycles before its
value is valid, instead of one clock cycle when using the Write_Fifo_Full signal.
Range: 0 … 2047

uart_<ChannelNumber>_wr_fifo_full / Write Fifo Full Outputs the status

of the TX FIFO buffer.
You can use the signal to check the TX FIFO buffer before you start writing
data to the buffer. The Write_Fifo_Full signal switches one clock cycle after the
Write_Enable signal has been set.
Range:
§ 0: The TX FIFO buffer is not full.
§ 1: The TX FIFO buffer is full.

uart_<ChannelNumber>_wr_data / Write Data Specifies the value to be

send.
The Write_Data signal is transferred at each clock cycle with Write_Enable set
to 1.
Range: 0 … 511

uart_<ChannelNumber>_rts / RTS Specifies the Ready‑To‑Send (RTS) signal.

The RTS/CTS handshake is handled by the user, the RTS signal is just passed
through and adapted to the physical layer.
The hardware port is synchronously running to the UART clock defined by the
UART baud rate. The hardware port has voltage levels of +6 V (active, logical
high) and ‑6 V (inactive).

uart_<ChannelNumber>_cts / CTS Outputs the state of the Clear‑To‑Send

(CTS) hardware port.
RTS/CTS handshake is handled by the user. CTS is just passed through with
conversion to logical 1 and 0.
Range:
§ 0: CTS inactive
§ 1: CTS active
The CTS hardware port is synchronously running to the UART clock defined by
the UART baud rate. The hardware port has voltage levels of +6 V (active, logical
high) and ‑6 V (inactive).

I/O mapping The signals are available at the RS232 (422/485) connector.

MicroLabBox has static mapping between I/O signals and I/O pins. The signal
name is also printed on the housing of MicroLabBox. You have to consider only
the connector panel type.

For a detailed connector pinout, refer to:

§ RS232 (422/485) Connector (Sub-D) (MicroLabBox Hardware Installation and
Configuration )

For detailed information on the channel characteristics, refer to:

§ Communication Interfaces (MicroLabBox Hardware Installation and
Configuration )

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UART (RS422/485)

Overview of the Frameworks Available for MicroLabBox........................................................... 14

UART (RS422/485).................................................................................................................... 79

UART (RS422/485)

Purpose To implement communication via serial interface for RS422/485 UART type.

Description According to the number of physical connections available on MicroLabBox's

DS1302 board, you can select the I/O function UART (RS422/485). There are
two channels for this function.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 71 … 72.

Most of the parameters are used for the UART (RS232) and UART (RS422/485)
I/O functions.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(1).Init / Baud
rate Lets you specify the baud rate of the UART in the range
50 … 10,000,000 baud (bits per second).
The baud rate depends on the parameters 2, 3 and 4, and can be calculated by
the following formula:
BaudRate = (10^8 · uart_x_dcm_m) / (4 · uart_x_dcm_d · (uart_dcm_clk_divider+1))

With:

Variable Parameter Description

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Tip

You find the DS1302_uart_parameters.mat file in

<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\DS1302
_XC7K325T that you can open in MATLAB. It contains some calculated baud
rates and the percentaged deviations to the supported baud rates according
to the parameters m, d and the clock divider.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(5).Init / Word
length Lets you specify the word length in the range 5 … 9 bit. The word
length includes the number of data bits and the optional parity bit. Exceeding
bits in a message are ignored at the transmitter or cleared at the receiver.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(6).Init / Stop
bits Lets you specify the length of the stop bits in half of bits.

Stop Bits Parameter Value

1 2
1.5 3
2 4

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(7).Init / UART
mode Lets you specify the mode when using the RS422/485 UART type.

Value UART Mode

0 Full‑duplex mode
1 Half‑duplex mode

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(8).Init / UART
type Lets you specify the UART type.

Value UART Type

0 RS232
1 RS422/485

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(9).Init /
Termination Lets you specify the termination state.

Value Termination State Description

0 Disconnected § Full‑duplex mode:
RX‑/RX+ and TX‑/TX+ signals are not terminated.
§ Half‑duplex mode:
BM/BP signals are not terminated.
1 Connected § Full‑duplex mode:
RX‑/RX+ and TX‑/TX+ signals are terminated via
120 Ω resistors.
§ Half‑duplex mode:
BM/BP signal are terminated via a 120 Ω resistor.

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UART (RS422/485)

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 1.

There is only one section in the file that is valid for both UART types.

uart_<ChannelNumber>_rd / Read Enable Specifies to start receiving a

uart_<ChannelNumber>_rd_data_count / Read Data Count Outputs the

uart_<ChannelNumber>_rd_fifo_empty / Read Fifo Empty Outputs the

uart_<ChannelNumber>_rd_data / Read Data Outputs the last read data

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uart_<ChannelNumber>_wr / Write Enable Specifies to start sending a

uart_<ChannelNumber>_wr_data_count / Write Data Count Outputs the

number of values in the TX FIFO buffer.
The values in the TX FIFO buffer has not been sent already.
Do not use the Write_Data_Count signal to check the status of the buffer
(Write_Data_Count<2047), because this requires two clock cycles before its
value is valid, instead of one clock cycle when using the Write_Fifo_Full signal.
Range: 0 … 2047

uart_<ChannelNumber>_wr_fifo_full / Write Fifo Full Outputs the status

uart_<ChannelNumber>_wr_data / Write Data Specifies the value to be

send.
The Write_Data signal is transferred at each clock cycle with Write_Enable set
to 1.
Range: 0 … 511

uart_<Channel_Number>_driver_en / Driver Enable Specifies to enable

the output driver in the transceiver for data transmission.
If you use the UART (RS485/422) function in half-duplex mode, the output driver
must be disabled while receiving data.

I/O mapping The signals are available at the RS232 (422/485) connector.

MicroLabBox has static mapping between I/O signals and I/O pins. The signal
name is also printed on the housing of MicroLabBox. You have to consider only
the connector panel type.

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UART (RS422/485)

For a detailed connector pinout, refer to:

§ RS232 (422/485) Connector (Sub-D) (MicroLabBox Hardware Installation and
Configuration )

For detailed information on the channel characteristics, refer to:

§ Communication Interfaces (MicroLabBox Hardware Installation and
Configuration )

Overview of the Frameworks Available for MicroLabBox........................................................... 14

UART (RS232)........................................................................................................................... 74

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I/O Functions of the DS1202 FPGA I/O Type 1 Framework

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I/O Functions of the DS1303 (KU15P) Multi-I/O Board Framework

I/O Functions of the DS1303 (KU15P) Multi-I/O

Board Framework

Introduction The DS1303 (KU15P) Multi-I/O Board framework provides the custom I/O
functionality of the MicroLabBox II.

Where to go from here Information in this section

Analog In 23........................................................................................... 86
To read data from an analog input signal in the FPGA application.

Analog In 24........................................................................................... 88
To read data from an analog input signal in the FPGA application.

Analog In 25........................................................................................... 89
To read data from an analog input signal in the FPGA application.

Analog Out 19........................................................................................ 90

To output an analog voltage signal using the Analog Out 19 channel
type.

Analog Out 20........................................................................................ 92

To output an analog voltage signal using the Analog Out 20 channel
type.

APU Master............................................................................................. 93
To distribute angle values over IOCNET for synchronizing angle-based
applications.

APU Slave................................................................................................ 95
To read angle values distributed by an APU Master over IOCNET for
synchronizing angle-based applications.

Buffer In.................................................................................................. 97
To read data from an IOCNET buffer with a data width of 32 bits.

Buffer Out............................................................................................... 99
To write data to an IOCNET buffer with a data width of 32 bits.

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Buffer64 In............................................................................................ 101

To read data from an IOCNET buffer with a data width of 64 bits.

Buffer64 Out......................................................................................... 103

To write data to an IOCNET buffer with a data width of 64 bits.

CN App Status....................................................................................... 105

To read the status of application that is running on the computation
node.

Digital In/Out 14 (In).............................................................................. 106

To read data from a digital signal with the FPGA application.

Digital In/Out 14 (In/Out-Z).................................................................... 107

To read or write data to or from a digital signal in the FPGA application,
or to switch the output to a high-impedance state (tristate).

Digital In/Out 15.................................................................................... 110

To read/write digital data with the digital I/O interface.

Interrupt................................................................................................ 113
To request a processor interrupt outside of the FPGA application.

IOCNET Global Time.............................................................................. 113

To read the number of hardware ticks.

LED Out................................................................................................. 114

To write a digital signal that controls the USR LED 1 of the
MicroLabBox II.

Register In............................................................................................. 115

To read data from an IOCNET register with a data width of 32 bits.

Register Out.......................................................................................... 117

To write data to an IOCNET register with a data width of 32 bits.

Register64 In......................................................................................... 118

To read data from an IOCNET register with a data width of 64 bits.

Register64 Out...................................................................................... 120

To write data to an IOCNET register with a data width of 64 bits.

Status In................................................................................................ 122

To read a digital signal that outputs the state of the FPGA initialization
sequence.

Analog In 23

Purpose To measure an analog voltage signal using the Analog In 23 channel type.

Description The Analog In 23 I/O function lets you measure differential analog voltage
signals in the range ±10 V.

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Analog In 23

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 67 … 90.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Ports The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 023.

ds1303_ai23_<ChannelNumber>_data / Data Outputs the current results

of the A/D conversions on the current channel.
Data type: Fix_16_0
Range: ‑32,768 … +32,767
Update rate: 2 MS/s

ds1303_ai23_<ChannelNumber>_trigger / Convert Triggers the sampling

of the A/D converter. The port allows a precise definition of the starting point of
ADC sampling. The Data New port signals the end of the conversion process.
Data type: UFix_1_0
Data width: 1
Values
§ 0: No conversion.
§ Set to 1 for at least one clock cycle: The ADC starts the conversion.
§ Permanently set to 1: The ADC samples continuously.

ds1303_ai23_<ChannelNumber>_event / Data New Outputs an end of

conversion signal if the conversion result is available.
Data type: UFix_1_0
Range: 0 or 1
If the flag changes from 0 to 1, the ADC data contains a new value. The flag is
set to 1 for only one clock cycle.

I/O mapping For the I/O mapping, refer to Analog In 23 Characteristics (MicroLabBox II
Hardware Installation and Configuration ).

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

References

Overview of the Frameworks Available for MicroLabBox II......................................................... 16

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I/O Functions of the DS1303 (KU15P) Multi-I/O Board Framework

Analog In 24

Purpose To measure an analog voltage signal using the Analog In 24 channel type.

Description The Analog In 24 I/O function lets you measure differential analog voltage
signals in the range ±1 V or ±10 V.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 61 … 66.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.In.Fct(<IOFunctionNumber>).Parameter(2).Init / Input
range Lets you specify the input voltage range that can be converted from
analog to digital for the chosen ADC channel:
§ 0: The input voltage range is ±10 V.
§ 1: The input voltage range is ±1 V.
Input voltages outside the specified range are saturated.
This electrical interface setting can be changed in ConfigurationDesk.

Ports The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 005.

ds1303_ai24_<ChannelNumber>_data / Data Outputs the current results

of the A/D conversions on the current channel.
Data type: Fix_16_0
Range: ‑32,768 … +32,767
Update rate: 5 MS/s

ds1303_ai24_<ChannelNumber>_trigger / Convert Triggers the sampling

ds1303_ai24_<ChannelNumber>_event / Data New Outputs an end of

conversion signal if the conversion result is available.
Data type: UFix_1_0

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Analog In 25

Range: 0 or 1
If the flag changes from 0 to 1, the ADC data contains a new value. The flag is
set to 1 for only one clock cycle.

I/O mapping For the I/O mapping, refer to Analog In 24 Characteristics (MicroLabBox II
Hardware Installation and Configuration ).

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

References

Overview of the Frameworks Available for MicroLabBox II......................................................... 16

Analog In 25

Purpose To measure an analog voltage signal using the Analog In 25 channel type.

Description The Analog In 25 I/O function lets you measure differential analog voltage
signals in the range ±1 V or ±10 V.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 59 … 60.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Ports The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 001.

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ds1303_ai25_<ChannelNumber>_data / Data Outputs the current results

of the A/D conversions on the current channel.
Data type: Fix_16_0
Range: ‑32,768 … +32,767
Update rate: 5 MS/s

ds1303_ai25_<ChannelNumber>_trigger / Convert Triggers the sampling

ds1303_ai25_<ChannelNumber>_event / Data New Outputs an end of

I/O mapping For the I/O mapping, refer to Analog In 25 Characteristics (MicroLabBox II
Hardware Installation and Configuration ).

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

References

Overview of the Frameworks Available for MicroLabBox II......................................................... 16

Analog Out 19

Purpose To output an analog voltage signal using the Analog Out 19 channel type.

Description The Analog Out 19 I/O function lets you generate differential analog voltage
signals with ground sense in the range ±10 V.

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Analog Out 19

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 70 … 84.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 013.

ds1303_ao19_<ChannelNumber>_data / Data Generates a voltage signal

in the specified range.
Data type: Fix_16_0
Data width: 1
Value range: ‑32,768 … +32,767
Update rate: 2.5 MS/s

ds1303_ao19_<ChannelNumber>_trigger / Enable Lets you enable on-

demand conversion of the Data port value. When a new value can be converted,
the Ready port outputs 1.
Note: If you connect the Ready port directly to the Enable port, the analog
output channel works in the same way as in a free-running mode.
Data Type: UFix_1_0
Data width: 1

ds1303_ao19_<ChannelNumber>_event / Ready Indicates that the

channel is ready to be updated.
Data type: UFix_1_0
Data width: 1
Update rate: 2.5 MS/s

I/O mapping For the I/O mapping, refer to Analog Out 19 Characteristics (MicroLabBox II
Hardware Installation and Configuration ).

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

References

Overview of the Frameworks Available for MicroLabBox II......................................................... 16

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Analog Out 20

Purpose To output an analog voltage signal using the Analog Out 20 channel type.

Description The Analog Out 20 I/O function lets you generate a differential signal with
ground sense (±10 V DC) or a transformer-coupled signal (±20 V AC).

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 68 … 69.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(2).Init / Noise
amplitude Lets you enable a pseudo-random noise that is added to the
generated output signal.
Value range: 0 … 65,535 (216-1)
Resulting noise amplitude: 0 V … 10 V (direct output) or 0 V … 20 V
(transformer-coupled output)
Set the noise amplitude to 0 to disable the noise generation.
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(6).Init /
Transformer Lets you switch between the direct output and the transformer-
coupled output.
§ 0: Direct output with a voltage range of ±10 V DC.
§ 1: Transformer-coupled output with a voltage range of ±20 V AC.
This electrical interface setting can be changed in ConfigurationDesk.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 001.

ds1303_ao20_<ChannelNumber>_data / Data Generates a voltage signal

in the specified range.
Data type: Fix_16_0
Data width: 1
Value range: ‑32,768 … +32,767
Update rate: 5 MS/s

ds1303_ao20_<ChannelNumber>_trigger / Enable Lets you enable on-

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APU Master

Data Type: UFix_1_0

Data width: 1

ds1303_ao20_<ChannelNumber>_event / Ready Indicates that the

channel is ready to be updated.
Data type: UFix_1_0
Data width: 1
Update rate: 5 MS/s

I/O mapping For the I/O mapping, refer to Analog Out 20 Characteristics (MicroLabBox II
Hardware Installation and Configuration ).

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

References

Overview of the Frameworks Available for MicroLabBox II......................................................... 16

APU Master

Purpose To distribute angle values over IOCNET for synchronizing angle-based

applications.

Description According to the number of physical connections available on the

MicroLabBox II, you can select the APU Master I/O functions. There are six
digital output channels.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 2 … 7.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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§ 2: The Angle range property of the FPGA custom function block in

ConfigurationDesk lets you set the angle range of the APU. The default value
is 720°.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(2).Init / Initial
position Lets you set the initial APU master position in degree.
§ Value range: -1440° ... +1440°

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 01 … 06.

iocnet_glob_master_angle<ChannelNumber>_ctr / Phi Read HD For

internal use only.

iocnet_glob_master_angle<ChannelNumber>_pos / Phi Read Outputs

the angle counter value of the APU that the APU Master writes to the APU
bus. The step size of the angle counter is approximately 0.011°. The step size is
independent from the angle range.
Formula for angle calculation: alpha[°] = Phi Read * 720°/216
The value range depends on the settings of the Angle Range:
§ 360° angle range: 0 ... 32,767 (215-1)
§ 720° angle range: 0 ... 65,535 (216-1)
Data type: UFix_16_0
Data width: 1
APU bus clock cycle: 8 ns
Range exceeding is not possible.

iocnet_glob_master_angle<ChannelNumber>_rev / Rev Read Specifies

the 37 bit total revolution (rev) value for the APU bus.
The APU bus clock cycle is 8 ns. The 37 Bit range is -236 … 236 - 1.
Data type: Double
Data width: 1
Range exceeding is not possible.

iocnet_glob_master_angle<ChannelNumber>_vel / Delta Phi For internal

use only.

iocnet_glob_master_angle<ChannelNumber>_en / Delta Phi Enable For

internal use only.

iocnet_glob_master_angle<ChannelNumber>_busy / Busy Specifies

whether APU master is busy to set the last velocity value. If Busy is 1 (high),
new velocity values cannot be set.
Busy stays active for at least 10 µs depending on the IOCNET structure..

iocnet_glob_master_angle<ChannelNumber>_res / Angle
Range Specifies the angle value range of Phi Read.
§ 0: 720° angle range
§ 1: 360° angle range

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APU Slave

iocnet_glob_master_angle<ChannelNumber>_upd_vel_deg_sec /
Velocity Specifies a velocity value in degree/second to be applied as APU
Master speed.
The value will be applied if Set Velocity is 1 (high) and Busy is 0 (low).
Data type: Fix_32_10
Data width: 1
Value range: -1,200,000 °/s ... +1,200,000 °/s
Range exceeding is not possible. The port is saturated at the higher or lower
limit.

iocnet_glob_master_angle<ChannelNumber>_upd_trig / Set
Velocity Specifies the actual value of Velocity as new velocity value. The new
value is set only if Set Velocity is 1 (high) and Busy is 0 (low).
Notes on updating velocity values:
§ Setting the velocity values at very short intervals (e.g. every 80 ns) leads to high
data traffic on IOCNET.
High data traffic might freeze your MicroLabBox II.
§ Setting a new velocity value before the last setting is executed overwrites the
last setting.
To distribute and execute a new velocity value takes about 10 µs. If the APU
master always sets new velocity values before the last value is executed, the
velocity value will never change.

I/O mapping No external connection to the I/O connector of the board.

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

References

Overview of the Frameworks Available for MicroLabBox II......................................................... 16

APU Slave

Purpose To read angle values distributed by an APU Master over IOCNET for synchronizing
angle-based applications.

Description According to the number of physical connections available on the

MicroLabBox II, you can select the APU Slave I/O functions. There are six digital
input channels.

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Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 4 … 9.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.In.Fct(<IOFunctionNumber>).Parameter(11).Init Lets you

inherit the angle range of the APU bus or specify a local angle range
independent from the APU bus:
§ 0: 720° angle range.
§ 1: 360° angle range.
§ 2: The angle range is inherited from the APU bus.
The following table shows you the possible combinations of angle range
settings.

APU Bus Slave APU Resulting Angle Range of the Slave

Setting Setting APU
360° 2 (Inherit) 360°
720° 720°
360° 1 (360°) 360°
0 (720°) 720° 1)
720° 1 (360°) 360° 2)
0 (720°) 720°
1) Two engine cycles are required to run through the 720 ° angle range. If you simulate a
four-stroke piston engine, for example, the angle values of the function block are not
clearly related to the camshaft position.
2)
One engine cycle runs twice through the 360° angle range.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 01 … 06.

iocnet_glob_angle<ChannelNumber>_pos / Phi Read Outputs the angle

value that APU Slave reads from the APU bus. The angle value is independent
from the angle range of the APU bus.
Formula for angle calculation: alpha[°] = Phi Read * 720°/216
The value range depends on the angle range of the APU bus:
§ 360° angle range: 0 ... 32,767 (215-1)
§ 720° angle range: 0 ... 65,535 (216-1)
Data type: UFix_16_0
Data width: 1
APU bus clock cycle: 8 ns
Range exceeding is not possible.

iocnet_glob_angle<ChannelNumber>_rev / Rev Read Outputs the 37 bit

total revolution (rev) value for the APU bus.

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The APU bus clock cycle is 8 ns. The 37 bit range is -236 … 236 - 1.
Data type: Double
Data width: 1
Range exceeding is not possible.

iocnet_glob_angle<ChannelNumber>_ctr / Phi Read HD For internal use

only.

iocnet_glob_angle<ChannelNumber>_vel / Delta Phi For internal use

only.

iocnet_glob_angle<ChannelNumber>_en / Delta Phi Enable For internal

use only.

iocnet_glob_angle<ChannelNumber>_res / Angle Range Outputs a flag

whether the angle range of the APU bus is 360° or 720°. The angle range has
been sent by an I/O board in the hardware system specified as APU master.
Data type: Double
Data width: 1
§ 0: The angle range is 720°.
§ 1: The angle range is 360°.

I/O mapping No external connection to the I/O connector of the board.

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

References

Overview of the Frameworks Available for MicroLabBox II......................................................... 16

Buffer In

Purpose To read data from an IOCNET buffer with a data width of 32 bits.

Description If you select Buffer as the access type, the data is read from an IOCNET buffer.
32 buffers are available. Each buffer has a variable buffer size of 1 up to 32,768
elements. Each buffer element has a data width of 32 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

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The I/O function number can be specified in the range 257 … 288.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmemf_<ChannelNumber>_count / Data Count Outputs the number of

elements in the current buffer. The maximum range depends on the specified
buffer size. You can use the value to define the valid range for the Address
inport of 0 … (Data Count ‑1).

xmemf_<ChannelNumber>_dout / Data Outputs a 32-bit data value to be

read from an IOCNET buffer. The data format depends on the related parameter
settings.

xmemf_<ChannelNumber>_new_data / Data New Outputs a flag that

indicates the changes of the buffer status. If the flag changes from 0 to 1 and

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then back to 0, the requested buffer contains new values and is ready to be
read. The flag is set to 1 only within one clock cycle.

xmemf_<ChannelNumber>_addr / Address Specifies an element in the

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

References

Overview of the Frameworks Available for MicroLabBox II......................................................... 16

Buffer Out

Purpose To write data to an IOCNET buffer with a data width of 32 bits.

Description If you select Buffer as the access type, the data is written to an IOCNET buffer.
32 buffers are available. Each buffer has a variable buffer size of 1 up to 32,768
elements. Each buffer element has a data width of 32 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 257 … 288.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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§ floating-point
The values of the Data inport are in floating‑point format. The parameter then
provides the fraction width.

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Buffer
size Lets you specify the size of the buffer in the range 1 … 32768.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmemp_<ChannelNumber>_din / Data Specifies a 32-bit data value to be

written to an IOCNET buffer. The data format depends on the related parameter
settings.

xmemp_<ChannelNumber>_write / Enable Specifies the current valid Data

port value.
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.

xmemp_<ChannelNumber>_finished / Ready Explicitly specifies the buffer

state as ready to send the buffer immediately, even if it is not completely filled.
The data values will be written to a new buffer in the next clock cycle. While
the port value is 1, transmission switches buffer in every clock cycle. The value
should therefore be set for one clock cycle only. If the buffer is completely filled,
it is automatically switched, and the data values are stored in a new buffer.
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready for sending, even if it is not completely filled.
The buffer is switched and the data values are accessible via the IOCNET in the
next clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.

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Buffer64 In

xmemp_<ChannelNumber>_overflow / Overflow Outputs a flag that

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

References

Overview of the Frameworks Available for MicroLabBox II......................................................... 16

Buffer64 In

Purpose To read data from an IOCNET buffer with a data width of 64 bits.

Description If you select Buffer64 as the access type, the data is read from an IOCNET
buffer. 32 buffers are available. Each buffer has a variable buffer size of 1 up to
32,768 elements. Each buffer element has a data width of 64 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 545 … 576.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(1).Init / Binary
point position (or fraction width) Lets you specify the binary point position
or returns the fraction width of the Data outport depending on the format
selected in the Format setting (see below).
§ signed/unsigned
The values of the Data outport are in fixed-point format. You can specify the
binary point position of the 64-bit value in the range 0 … 64.
0 represents the lowest bit position, 64 the highest bit position.
64-bit fixed-point data types are converted to double, except the data
type without a binary point (binary point position = 0). Therefore, the fixed-
point resolution of fixed-point data types with a binary point (binary point
position > 0) is restricted to 53 bits.

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§ floating-point
The values of the Data outport are in floating‑point format. The parameter
then provides the fraction width.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(2).Init /
Format Lets you specify the data format of the Data outport.
§ signed/unsigned
The values of the Data outport are in fixed‑point format with or without one
bit reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
§ floating‑point
The values of the Data outport are in floating‑point format.
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is provided by the Binary point position (or fraction
width) setting.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmem64f_<ChannelNumber>_count / Data Count Outputs the number of

elements in the current buffer. The maximum range depends on the specified
buffer size. You can use the value to define the valid range for the Address
inport of 0 … (Data Count -1).

xmem64f_<ChannelNumber>_dout / Data Outputs a 64-bit data value to

be read from an IOCNET buffer. The data format depends on the related
parameter settings.

xmem64f_<ChannelNumber>_new_data / Data New Outputs a flag that

xmem64f_<ChannelNumber>_addr / Address Specifies an element in the

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Buffer64 Out

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

References

Overview of the Frameworks Available for MicroLabBox II......................................................... 16

Buffer64 Out

Purpose To write data to an IOCNET buffer with a data width of 64 bits.

Description If you select Buffer64 as the access type, the data is written to an IOCNET
buffer. 32 buffers are available. Each buffer has a variable buffer size of 1 up to
32,768 elements. Each buffer element has a data width of 64 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 545 … 576.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(1).Init / Binary
point position (or fraction width) Lets you specify the binary point position
or returns the fraction width of the Data inport depending on the format
selected in the Format setting (see below).
§ signed/unsigned
The values of the Data inport are in fixed-point format. You can specify the
binary point position of the 64-bit value in the range 0 … 64.
0 represents the lowest bit position, 64 the highest bit position.
64-bit fixed-point data types are converted to double, except the data
type without a binary point (binary point position = 0). Therefore, the fixed-
point resolution of fixed-point data types with a binary point (binary point
position > 0) is restricted to 53 bits.
§ floating-point
The values of the Data inport are in floating‑point format. The parameter then
provides the fraction width.

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PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Buffer
size Lets you specify the size of the buffer in the range 1 … 32768.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmem64p_<ChannelNumber>_din / Data Specifies a 64-bit data value to

be written to an IOCNET buffer. The data format depends on the related
parameter settings.

xmem64p_<ChannelNumber>_write / Enable Specifies the current valid

Data port value.
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.

xmem64p_<ChannelNumber>_finished / Ready Explicitly specifies the

buffer state as ready to send the buffer immediately, even if it is not completely
filled. The data values will be written to a new buffer in the next clock cycle.
While the port value is 1, transmission switches buffer in every clock cycle. The
value should therefore be set for one clock cycle only. If the buffer is completely
filled, it is automatically switched, and the data values are stored in a new buffer.
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready for sending, even if it is not completely filled.
The buffer is switched and the data values are accessible via the IOCNET in the
next clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.

xmem64p_<ChannelNumber>_overflow / Overflow Outputs a flag that

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CN App Status

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

References

Overview of the Frameworks Available for MicroLabBox II......................................................... 16

CN App Status

Purpose To read the status of application that is running on the computation node.

Description There is one digital input channel that is used for the CN App Status I/O
function.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 2.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

iocnet_appl_status/ CN Application Status Outputs the state of the

processor application.
Data type: UFix_1_0
§ 0: The processor application is stopped.
§ 1: The processor application is running.

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

References

Overview of the Frameworks Available for MicroLabBox II......................................................... 16

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Digital In/Out 14 (In)

Purpose To read data from a digital signal with the FPGA application.

Description The Digital In/Out 14 (In) I/O function lets you measure ground-based digital
signals.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 11 … 58.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(4).Init / Invert
values Lets you select whether to invert the input and output values of the
digital channel.
§ 0: The Data port does not invert the values: A logical 1 represents a low-high
transition of the physical signal.
§ 1: The Data port inverts the values: A logical 1 represents a high-low transition
of the physical signal.
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(7).Init / Threshold
voltage Lets you specify the threshold level for the current digital channel.
If the input signal is below this level, a logical 0 is detected, otherwise a logical 1.
Value range: 0 ... 255 (-100 mV ... 12,288 mV).

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(9).Init / Disable
filter Lets you disable the input filter:
§ 1: The input filter is disabled.
§ 0: The input filter is enabled.
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(11).Init / Input
filter Lets you specify the minimum pulse length for detecting a valid input in
the range 0 ns … 1,250,000 ns in steps of 8 ns.
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(13).Init / Rising
edge delay Lets you specify whether to use a delay for the rising edge
detection. The delay can be specified in the range 0 … 50,000 ns in steps of
8 ns.
This electrical interface setting can be changed in ConfigurationDesk.

Ports You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

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Digital In/Out 14 (In/Out-Z)

The channel number can be specified in the range 000 …. 047

ds1303_dio14_<ChannelNumber>_lvl_in / DigIn Outputs the current

results of the digital input channel.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Input voltage of the channel is below the threshold voltage of a high-low
transition.
§ 1: Input voltage of the channel is higher than or equal to the threshold voltage
of a low-high transition.
Threshold level: Set by the Threshold init voltage parameter.
Update rate: FPGA clock frequency

ds1303_dio14_<ChannelNumber>_dir / Direction Lets you enable the

measurement of of the input channel.
Data type: UFix_1_0
Data width: 1
Values:
§ 1: The measurement is enabled.
§ 0: The measurement is disabled.

I/O mapping For the I/O mapping, refer to Digital In/Out 14 Characteristics (MicroLabBox II
Hardware Installation and Configuration ).

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

References

Overview of the Frameworks Available for MicroLabBox II......................................................... 16

Digital In/Out 14 (In/Out-Z)

Purpose To read or write data to or from a digital signal in the FPGA application, or to
switch the output to a high-impedance state (tristate).

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Description The Digital In/Out 14 (In/Out-Z) I/O function lets you access bidirectional
channels to measure or generate ground-based digital signals.

Note

If you use the same digital channel for the input and the output, the
maximum input voltage for the digital input channel is equal to the
specified high supply, and the applicable threshold voltage is lower than
the specified high supply.
To use the maximum input voltage range, you have to use Digital
In/Out 14 (In) I/O function.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 8 … 55.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(6).Init / Output
Mode Lets you select the output mode.
§ 1: Low-side switch
Lets you actively drive the output to GND to output a low-level signal.
An external load to the high supply voltage is required to output a high-level
signal.
§ 2: High-side switch
Lets you actively drive the output to the high supply voltage to output a
high-level signal.
An external load to GND is necessary to output a low-level signal.
§ 3: Push-pull
Lets you drive the output between the high supply voltage and GND.
An external load is not required.
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(9).Init / Threshold
voltage Lets you specify the threshold level for the current digital channel.
If the input signal is below this level, a logical 0 is detected, otherwise a logical 1.
Value range: 0 ... 255 (-100 mV ... 12,288 mV).

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IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(11).Init / Disable
filter Lets you disable the input filter:
§ 1: The input filter is disabled.
§ 0: The input filter is enabled.
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(13).Init / Input
filter Lets you specify the minimum pulse length for detecting a valid input in
the range 0 ns … 1,250,000 ns in steps of 8 ns.
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(15).Init / Rising
edge delay Lets you specify whether to use a delay for the rising edge
detection. The delay can be specified in the range 0 … 50,000 ns in steps of
8 ns.
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(17).Init / High
supply Lets you specify the high supply voltage that determines the high-level
voltage for the high‑side switch.
§ 0: 3.3 V
§ 1: 5 V
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(19).Init / Drive
Config Lets you specify the high supply voltage that determines the high-level
voltage for the high‑side switch.
§ 0: 3.3 V
§ 1: 5 V
This electrical interface setting can be changed in ConfigurationDesk.

Ports You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 …. 047

ds1303_dio14_<ChannelNumber>_lvl_in / DigIn Outputs the current

ds1303_dio14_<ChannelNumber>_lvl_out / DigOut Outputs a signal in

the specified range if the Direction port is set to 1.
To set the voltage level, use the High Supply parameter.

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Data Type: UFix_1_0

Data width: 1
If driven with 0, the hardware outputs a low-level signal. If driven with 1, the
hardware outputs a high-level signal.
Update rate: FPGA clock frequency
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit
by using only the lowest bit.

ds1303_dio14_<ChannelNumber>_dir / Direction Enables the output of

data values and disables the high-impedance state.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The output is set to the high-impedance state.
§ 1: The output is enabled and outputs the data values of the DigOut port.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit
by using only the lowest bit.

I/O mapping For the I/O mapping, refer to Digital In/Out 14 Characteristics (MicroLabBox II
Hardware Installation and Configuration ).

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

References

Overview of the Frameworks Available for MicroLabBox II......................................................... 16

Digital In/Out 15

Purpose To read/write digital data to the bidirectional interface of the Digital In/Out 15
channel type.

Description The Digital In/Out 15 I/O function lets you access bidirectional channels to
measure or generate differential digital signals.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 56 … 67.

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Digital In/Out 15

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(2).Init / Invert
values Lets you select whether to invert the input and output values of the
digital channel.
§ 0: The Data port does not invert the values: A logical 1 represents a low-high
transition of the physical signal.
§ 1: The Data port inverts the values: A logical 1 represents a high-low transition
of the physical signal.
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(4).Init /
Termination Lets you select whether to invert the input and output values
of the digital channel.
§ 0: The Data port does not invert the values: A logical 1 represents a low-high
transition of the physical signal.
§ 1: The Data port inverts the values: A logical 1 represents a high-low transition
of the physical signal.
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(6).Init / Disable
filter Lets you disable the input filter:
§ 1: The input filter is disabled.
§ 0: The input filter is enabled.
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(8).Init / Input
filter Lets you specify the minimum pulse length for detecting a valid input in
the range 0 ns … 1,250,000 ns in steps of 8 ns.
This electrical interface setting can be changed in ConfigurationDesk.

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 …. 011

ds1303_dio15_<ChannelNumber>_lvl_in / DigIn Outputs the current

ds1303_dio15_<ChannelNumber>_lvl_out / DigOut Outputs a signal in

the specified range if the Direction port is set to 1.
Data Type: UFix_1_0

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ds1303_dio15_<ChannelNumber>_dir / Direction Enables the output of

I/O mapping The following I/O mapping is relevant if you use the DS2655M1 I/O Module
framework for the bidirectional digital I/O channels. The signals are available at
the female 50-pin Sub-D I/O connector of the respective MicroLabBox II Multi-I/O
Module (x = 1 … 5)..

Outport I/O Function Channel Connector Signal

Number Number Pin
Data 11 1 2 Digital In/Out 15 - Ch: 1 [Mod: x]
12 2 19 Digital In/Out 15 - Ch: 2 [Mod: x]
13 3 36 Digital In/Out 15 - Ch: 3 [Mod: x]
14 4 4 Digital In/Out 15 - Ch: 4 [Mod: x]
15 5 21 Digital In/Out 15 - Ch: 5 [Mod: x]
16 6 6 Digital In/Out 15 - Ch: 6 [Mod: x]
17 7 23 Digital In/Out 15 - Ch: 7 [Mod: x]
18 8 40 Digital In/Out 15 - Ch: 8 [Mod: x]
19 9 8 Digital In/Out 15 - Ch: 9 [Mod: x]
20 10 25 Digital In/Out 15 - Ch: 10 [Mod: x]

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

References

Overview of the Frameworks Available for MicroLabBox II......................................................... 16

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Interrupt

Interrupt

Purpose To request a processor interrupt outside of the FPGA application.

Description MicroLabBox II provides 8 interrupt lines. An interrupt is requested if the Int port
is set to 1 for at least one clock cycle. If you set the Int port to 0, the last
interrupt is not released but saved. An interrupt is edge-triggered.

Parameters The Interrupt I/O function can be used for up to 8 channels / interrupt lines.
You will find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 8.

IRQProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 7.

usr_<ChannelNumber>_interrupt / Int Provides the interrupt request line.

§ 0 to 1: Interrupt is requested (edge-triggered).
§ 0: No interrupt is requested. Last requested interrupt is saved.

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

References

Overview of the Frameworks Available for MicroLabBox II......................................................... 16

IOCNET Global Time

Purpose To read the number of hardware ticks.

Description There is one digital input channel that is used for the IOCNET Global Time I/O
function.

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Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 3.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

iocnet_glob_time/ IOCNET Global Time Outputs the number of hardware

ticks that occurred since the MicroLabBox II was powered on.
Data type: UFix_56_0
Tick step-width: 8.5 ns

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

References

Overview of the Frameworks Available for MicroLabBox II......................................................... 16

LED Out

Purpose To write a digital signal that controls the USR LED 1 of the MicroLabBox II.

Description There is one digital output channel that is used for the LED Out I/O function.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 1.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

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Register In

There is no channel number to be specified.

led_out / LED Out Controls the LED on the board.

Data type: UFix_1_0
§ 0: The LED outputs status information for custom FPGA applications. Refer
to LED States of the MicroLabBox II (MicroLabBox II Hardware Installation and
Configuration ).
§ 1: LED lights orange.

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

References

Overview of the Frameworks Available for MicroLabBox II......................................................... 16

Purpose To read data from an IOCNET register with a data width of 32 bits.

Description If you select Register as the access type, the data is read from an IOCNET
register. 256 registers are available with a data width of 32 bits each. The values
are transmitted element by element. If you want to access data from several
registers simultaneously, you can group these registers by specifying the same
group identifier for them.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 256.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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§ floating-point
The values of the Data outport are in floating‑point format. The parameter
then provides the fraction width.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(3).Init / Register
group ID Lets you specify a number in the range 1 … 63 to create
register groups. Registers that you specified with the same group ID are
sampled simultaneously within the FPGA application. The values therefore form a
consistent data group that is written to the IOCNET bus.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 255.

xreg_<ChannelNumber>_dout / Data Outputs a 32-bit data value to be

read from an IOCNET register. The data format depends on the related
parameter settings.

xreg_<ChannelNumber>_dout_wr / Data New Outputs a flag that

indicates the changes of the register status. If the flag changes from 0 to 1
and then back to 0, the requested register contains a new value. The flag is set
to 1 only within one clock cycle.

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

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Register Out

References

Overview of the Frameworks Available for MicroLabBox II......................................................... 16

Purpose To write data to an IOCNET register with a data width of 32 bits.

Description If you select Register as the access type, the data is written to an IOCNET
register. 256 registers are available with a data width of 32 bits each. The values
are transmitted element by element. If you want to access data from several
registers simultaneously, you can group these registers by specifying the same
group identifier for them.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 256.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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The fraction width is provided by the Binary point position (or fraction
width) setting.

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Register
group ID Lets you specify a number in the range 1 … 63 to create
register groups. Registers that you specified with the same group ID are read
from the IOCNET bus sequentially and then provided to the FPGA application
simultaneously.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 255.

xreg_<ChannelNumber>_din / Data Specifies a 32-bit data value to be

written to an IOCNET register. The data format depends on the related
parameter settings.

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

References

Overview of the Frameworks Available for MicroLabBox II......................................................... 16

Register64 In

Purpose To read data from an IOCNET register with a data width of 64 bits.

Description If you select Register64 as the access type, the data is read from an IOCNET
register. 256 registers are available with a data width of 64 bits each. The values
are transmitted element by element. If you want to access data from several
registers simultaneously, you can group these registers by specifying the same
group identifier for them.

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Register64 In

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 289 … 544.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(1).Init / Binary
point position (or fraction width) Lets you specify the binary point position
or returns the fraction width of the Data outport depending on the format
selected in the Format setting (see below).
§ signed/unsigned
The values of the Data outport are in fixed-point format. You can specify the
binary point position of the 64-bit value in the range 0 … 64.
0 represents the lowest bit position, 64 the highest bit position.
64-bit fixed-point data types are converted to double, except the data
type without a binary point (binary point position = 0). Therefore, the fixed-
point resolution of fixed-point data types with a binary point (binary point
position > 0) is restricted to 53 bits.
§ floating-point
The values of the Data outport are in floating‑point format. The parameter
then provides the fraction width.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(3).Init / Register
group ID Lets you specify a number in the range 1 … 63 to create
register groups. Registers that you specified with the same group ID are
sampled simultaneously within the FPGA application. The values therefore form a
consistent data group that is written to the IOCNET bus.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

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Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 255.

xreg64_<ChannelNumber>_dout / Data Outputs a 64-bit data value to

be read from an IOCNET register. The data format depends on the related
parameter settings.

xreg64_<ChannelNumber>_dout_wr / Data New Outputs a flag that

indicates the changes of the register status. If the flag changes from 0 to 1
and then back to 0, the requested register contains a new value. The flag is set
to 1 only within one clock cycle.

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

References

Overview of the Frameworks Available for MicroLabBox II......................................................... 16

Register64 Out

Purpose To write data to an IOCNET register with a data width of 64 bits.

Description If you select Register64 as the access type, the data is written to an IOCNET
register. 256 registers are available with a data width of 64 bits each. The values
are transmitted element by element. If you want to access data from several
registers simultaneously, you can group these registers by specifying the same
group identifier for them.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 289 … 544.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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Register64 Out

§ signed/unsigned
The values of the Data inport are in fixed-point format. You can specify the
binary point position of the 64-bit value in the range 0 … 64.
0 represents the lowest bit position, 64 the highest bit position.
64-bit fixed-point data types are converted to double, except the data
type without a binary point (binary point position = 0). Therefore, the fixed-
point resolution of fixed-point data types with a binary point (binary point
position > 0) is restricted to 53 bits.
§ floating-point
The values of the Data inport are in floating‑point format. The parameter then
provides the fraction width.

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init /
Register64 group ID Lets you specify a number in the range 1 … 63 to
create register groups. Registers that you specified with the same group ID
are read from the IOCNET bus sequentially and then provided to the FPGA
application simultaneously.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 255.

xreg64_<ChannelNumber>_din / Data Specifies a 64-bit data value to

be written to an IOCNET register. The data format depends on the related
parameter settings.

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Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

References

Overview of the Frameworks Available for MicroLabBox II......................................................... 16

Status In

Purpose To read a digital signal that outputs the state of the FPGA initialization sequence.

Description The DS1303 (KU15P) Multi-I/O Board framework provides one digital input
channel for the Status In I/O function.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number is to be specified with 1.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

Detailed Instructions on the Handcode Workflow (FPGA Programming Handcode

Framework Guide )

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Status In

References

Overview of the Frameworks Available for MicroLabBox II......................................................... 16

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I/O Functions of the DS2655 FPGA Base Board Framework

I/O Functions of the DS2655 FPGA Base Board

Framework

Introduction The following frameworks of the DS2655 FPGA Base Boards provide the
standard I/O functionality of the boards:
§ DS2655 (7K160) FPGA Base Board framework
§ DS2655 (7K410) FPGA Base Board framework

Where to go from here Information in this section

APU Master........................................................................................... 127

To distribute angle values over IOCNET for synchronizing angle-based
applications.

APU Slave.............................................................................................. 129

To read angle values distributed by an APU Master over IOCNET for
synchronizing angle-based applications.

Buffer In................................................................................................ 131

To read data from an IOCNET buffer with a data width of 32 bits.

Buffer64 In............................................................................................ 133

To read data from an IOCNET buffer with a data width of 64 bits.

Buffer Out............................................................................................. 135

To write data to an IOCNET buffer with a data width of 32 bits.

Buffer64 Out......................................................................................... 137

To write data to an IOCNET buffer with a data width of 64 bits.

CN App Status....................................................................................... 140

To read the status of application that is running on the computation
node.

I-FPGA In (IOCNET)................................................................................ 141

To read a 32-bit raw data value from an IOCNET buffer.

I-FPGA64 In (IOCNET)............................................................................ 142

To read a 64-bit raw data value from an IOCNET buffer.

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I-FPGA Out (IOCNET)............................................................................. 144

To write a 32-bit raw data value to an IOCNET buffer.

I-FPGA64 Out (IOCNET)......................................................................... 146

To write a 64-bit raw data value to an IOCNET buffer.

Interrupt................................................................................................ 148
To request a processor interrupt outside of the FPGA application.

IOCNET Global Time.............................................................................. 149

To read the number of hardware ticks.

LED Out................................................................................................. 149

To write a digital signal that controls the LED on the board.

Register In............................................................................................. 150

To read data from an IOCNET register with a data width of 32 bits.

Register64 In......................................................................................... 152

To read data from an IOCNET register with a data width of 64 bits.

Register Out.......................................................................................... 154

To write data to an IOCNET register with a data width of 32 bits.

Register64 Out...................................................................................... 155

To write data to an IOCNET register with a data width of 64 bits.

Status In................................................................................................ 157

To read a digital signal that outputs the state of the FPGA initialization
sequence.

Information in other sections

Other frameworks that provide access to the FPGA functionality

of a SCALEXIO system:
I/O Functions of the DS2655M1 I/O Module Framework........................ 237
The DS2655M1 I/O Module framework provides analog and digital I/O
functionality of SCALEXIO FPGA base board with at least one DS2655M1
Multi-I/O Module.

I/O Functions of the DS2655M2 I/O Module Framework........................ 249

The DS2655M2 I/O Module framework provides digital I/O functionality
of a SCALEXIO FPGA base board with at least one DS2655M2 Digital I/O
Module.

I/O Functions of the DS6651 Multi-I/O Module Framework.................... 269

The DS6651 Multi-I/O Module framework provides analog and digital I/O
functionality of a SCALEXIO FPGA base board with at least one DS6651
Multi-I/O Module.

I/O Functions of the Inter-FPGA Interface Framework............................. 313

The Inter-FPGA Interface framework provides access to the I/O module
slots of a SCALEXIO FPGA base board to implement an inter-FPGA
communication bus.

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APU Master

APU Master

Purpose To distribute angle values over IOCNET for synchronizing angle-based

applications.

Description According to the number of physical connections available on the DS2655 FPGA
Base Board, you can select the APU Master I/O functions. There are six digital
output channels.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 2 … 7.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(1).Init / Angle
range Lets you specify the angle value range of the Phi Read port.
§ 0: The angle range is 720° and cannot be changed in ConfigurationDesk.
§ 1: The angle range is 360° and cannot be changed in ConfigurationDesk.
§ 2: The Angle range property of the FPGA custom function block in
ConfigurationDesk lets you set the angle range of the APU. The default value
is 720°.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(2).Init / Initial
position Lets you set the initial APU master position in degree.
§ Value range: -1440° ... +1440°

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 01 … 06.

iocnet_glob_master_angle<ChannelNumber>_ctr / Phi Read HD For

internal use only.

iocnet_glob_master_angle<ChannelNumber>_pos / Phi Read Outputs

the angle counter value of the APU that the APU Master writes to the APU
bus. The step size of the angle counter is approximately 0.011°. The step size is
independent from the angle range.
Formula for angle calculation: alpha[°] = Phi Read * 720°/216
The value range depends on the settings of the Angle Range:
§ 360° angle range: 0 ... 32767 (215-1)
§ 720° angle range: 0 ... 65535 (216-1)
Data type: UFix_16_0
Data width: 1
APU bus clock cycle: 8 ns

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Range exceeding is not possible.

iocnet_glob_master_angle<ChannelNumber>_rev / Rev Read Specifies

the 37 bit total revolution (rev) value for the APU bus.
The APU bus clock cycle is 8 ns. The 37 Bit range is -236 … 236 - 1.
Data type: Double
Data width: 1
Range exceeding is not possible.

iocnet_glob_master_angle<ChannelNumber>_vel / Delta Phi For internal

use only.

iocnet_glob_master_angle<ChannelNumber>_en / Delta Phi Enable For

internal use only.

iocnet_glob_master_angle<ChannelNumber>_busy / Busy Specifies

whether APU master is busy to set the last velocity value. If Busy is 1 (high),
new velocity values cannot be set.
Busy stays active for at least 10 µs depending on the IOCNET structure..

iocnet_glob_master_angle<ChannelNumber>_res / Angle
Range Specifies the angle value range of Phi Read.
§ 0: 720° angle range
§ 1: 360° angle range

iocnet_glob_master_angle<ChannelNumber>_upd_trig / Set
Velocity Specifies the actual value of Velocity as new velocity value. The new
value is set only if Set Velocity is 1 (high) and Busy is 0 (low).
Notes on updating velocity values:
§ Setting the velocity values at very short intervals (e.g. every 80 ns) leads to high
data traffic on IOCNET.
High data traffic might freeze your SCALEXIO system.
§ Setting a new velocity value before the last setting is executed overwrites the
last setting.
To distribute and execute a new velocity value takes about 10 µs. If the APU
master always sets new velocity values before the last value is executed, the
velocity value will never change.

I/O mapping No external connection to the I/O connector of the board.

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APU Slave

Overview of the DS2655 FPGA Base Board Frameworks............................................................ 19

APU Slave

Purpose To read angle values distributed by an APU Master over IOCNET for synchronizing
angle-based applications.

Description According to the number of physical connections available on the DS2655 FPGA
Base Board, you can select the APU Slave I/O functions. There are six digital
input channels.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 4 … 9.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.In.Fct(<IOFunctionNumber>).Parameter(11).Init Lets you

APU Bus Slave APU Resulting Angle Range of the Slave

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Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 01 … 06.

iocnet_glob_angle<ChannelNumber>_pos / Phi Read Outputs the angle

value that APU Slave reads from the APU bus. The angle value is independent
from the angle range of the APU bus.
Formula for angle calculation: alpha[°] = Phi Read * 720°/216
The value range depends on the angle range of the APU bus:
§ 360° angle range: 0 ... 32767 (215-1)
§ 720° angle range: 0 ... 65535 (216-1)
Data type: UFix_16_0
Data width: 1
APU bus clock cycle: 8 ns
Range exceeding is not possible.

iocnet_glob_angle<ChannelNumber>_rev / Rev Read Outputs the 37 bit

total revolution (rev) value for the APU bus.
The APU bus clock cycle is 8 ns. The 37 Bit range is -236 … 236 - 1.
Data type: Double
Data width: 1
Range exceeding is not possible.

iocnet_glob_angle<ChannelNumber>_ctr / Phi Read HD For internal use

only.

iocnet_glob_angle<ChannelNumber>_vel / Delta Phi For internal use

only.

iocnet_glob_angle<ChannelNumber>_en / Delta Phi Enable For internal

use only.

iocnet_glob_angle<ChannelNumber>_res / Angle Range Outputs a flag

I/O mapping No external connection to the I/O connector of the board.

Overview of the DS2655 FPGA Base Board Frameworks............................................................ 19

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Buffer In

Buffer In

Purpose To read data from an IOCNET buffer with a data width of 32 bits.

Description If you select Buffer as the access type, the data is read from an IOCNET buffer.
32 buffers are available. Each buffer has a variable buffer size of 1 up to 32768
elements. Each buffer element has a data width of 32 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 257 … 288.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(1).Init / Binary
point position Lets you specify the binary point position or returns the
fraction width of the Data outport depending on the format selected in the
Format setting (see below).
§ signed/unsigned
The values of the Data outport are in fixed-point format. You can specify the
binary point position of the 32-bit value in the range 0 … 32.
0 represents the lowest bit position, 32 the highest bit position.
§ floating-point
The values of the Data outport are in floating‑point format. The parameter
then provides the fraction width.

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Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmemf_<ChannelNumber>_count / Data Count Outputs the number of

elements in the current buffer. The maximum range depends on the specified
buffer size. You can use the value to define the valid range for the Address
inport of 0 … (Data Count -1).

xmemf_<ChannelNumber>_dout / Data Outputs a 32-bit data value to be

read from an IOCNET buffer. The data format depends on the related parameter
settings.

xmemf_<ChannelNumber>_addr / Address Specifies an element in the

xmemf_<ChannelNumber>_new_data / Data New Outputs a flag that

xmemf_<ChannelNumber>_read_req / Read Request Outputs a flag that

indicates that a data transmission is requested via IOCNET. With Buffer In port
Read Request and the Buffer Out port Send Acknowledge you can trigger a
processor synchronous data exchange.
A data transmission is always requested at the beginning of a task, before the
processor model is computed. Each time a new data transmission is requested
by the Buffer Out port Send Acknowledge, the Buffer In port Read Request
must explicitly acknowledge the Data values for transmission within one task
period. To send current data you can delay the transmission. After a new data
transmission is requested, you write the current data values to the buffer. Then
you must acknowledge the new data for transmission.
Usable only if Enable Read_Req and Send_Ack ports for explicit data
transmit value is enabled in the FPGA framework INI file.
§ 0: No data transmission is requested.
§ 1: A data transmission is requested. This value is set for one clock cycle.
A data transmission request that is not acknowledged by the Buffer Out port
Send Acknowledge leads to task overrun in the processor application. A task
overrun will be logged as an I/O error in the Message Viewer of the SCALEXIO
web interface. The FPGA buffer that caused the task overrun will also be logged.
For details on acknowledging a data transmission with Send Acknowledge,
refer to Buffer Out on page 135.

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Buffer64 In

Overview of the DS2655 FPGA Base Board Frameworks............................................................ 19

Buffer64 In

Purpose To read data from an IOCNET buffer with a data width of 64 bits.

Description If you select Buffer64 as the access type, the data is read from an IOCNET
buffer. 32 buffers are available. Each buffer has a variable buffer size of 1 up to
32768 elements. Each buffer element has a data width of 64 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 545 … 576.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(1).Init / Binary
point position (or fraction width) Lets you specify the binary point position
or returns the fraction width of the Data outport depending on the format
selected in the Format setting (see below).
§ signed/unsigned
The values of the Data outport are in fixed-point format. You can specify the
binary point position of the 64-bit value in the range 0 … 64.
0 represents the lowest bit position, 64 the highest bit position.
64-bit fixed-point data types are converted to double, except the data
type without a binary point (binary point position = 0). Therefore, the fixed-
point resolution of fixed-point data types with a binary point (binary point
position > 0) is restricted to 53 bits.
§ floating-point
The values of the Data outport are in floating‑point format. The parameter
then provides the fraction width.

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Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmem64f_<ChannelNumber>_count / Data Count Outputs the number of

elements in the current buffer. The maximum range depends on the specified
buffer size. You can use the value to define the valid range for the Address
inport of 0 … (Data Count -1).

xmem64f_<ChannelNumber>_dout / Data Outputs a 64-bit data value to

be read from an IOCNET buffer. The data format depends on the related
parameter settings.

xmem64f_<ChannelNumber>_addr / Address Specifies an element in the

xmem64f_<ChannelNumber>_new_data / Data New Outputs a flag that

xmem64f_<ChannelNumber>_read_req / Read Request Outputs a flag

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Buffer Out

Usable only if Enable Read_Req and Send_Ack ports for explicit data
transmit value is enabled in the FPGA framework INI file.
§ 0: No data transmission is requested.
§ 1: A data transmission is requested. This value is set for one clock cycle.
A data transmission request that is not acknowledged by the Buffer Out port
Send Acknowledge leads to task overrun in the processor application. A task
overrun will be logged as an I/O error in the Message Viewer of the SCALEXIO
web interface. The FPGA buffer that caused the task overrun will also be logged.
For details on acknowledging a data transmission with Send Acknowledge,
refer to Buffer64 Out on page 137.

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Buffer Out

Purpose To write data to an IOCNET buffer with a data width of 32 bits.

Description If you select Buffer as the access type, the data is written to an IOCNET buffer.
32 buffers are available. Each buffer has a variable buffer size of 1 up to 32768
elements. Each buffer element has a data width of 32 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 129 … 160.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(1).Init / Binary
point position Lets you specify the binary point position or returns the
fraction width of the Data inport depending on the format selected in the
Format setting (see below).
§ signed/unsigned
The values of the Data inport are in fixed-point format. You can specify the
binary point position of the 32 bit value in the range 0 … 32.
0 represents the lowest bit position, 32 the highest bit position.
§ floating-point
The values of the Data inport are in floating‑point format. The parameter then
provides the fraction width.

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PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Buffer
size Lets you specify the size of the buffer in the range 1 ... 32768.

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(9).Init / Enable
Read_Req and Send_Ack ports for explicit data transmit value Lets
you enable the Buffer In port Read Request and the Buffer Out port Send
Acknowledge. With Read Request and Send Acknowledge you can trigger a
processor synchronous data exchange.
§ 0: The ports are disabled. Each data request will instantly be acknowledged.
§ 1: The ports are enabled. Each data request must be acknowledged by your
handcode.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmemp_<ChannelNumber>_din / Data Specifies a 32-bit data value to be

written to an IOCNET buffer. The data format depends on the related parameter
settings.

xmemp_<ChannelNumber>_write / Enable Specifies the current valid Data

port value.
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.

xmemp_<ChannelNumber>_finished / Ready Explicitly specifies the buffer

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The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.

xmemp_<ChannelNumber>_overflow / Overflow Outputs a flag that

xmemp_<ChannelNumber>_send_ack / Send Acknowledge Triggers a

data transmission to IOCNET. With the Buffer Out port Send Acknowledge and
the Buffer In port Read Request you can trigger a processor synchronous data
exchange.
A data transmission is always requested at the beginning of a task, before the
processor model is computed. Each time a new data transmission is requested
by the Buffer Out port Send Acknowledge, the Buffer In port Read Request
must explicitly acknowledge the Data values for transmission within one task
period. To send current data you can delay the transmission. After a new data
transmission is requested, you write the current data values to the buffer. Then
you must acknowledge the new data for transmission.
Usable only if Enable Read_Req and Send_Ack ports for explicit data
transmit value is enabled in the FPGA framework INI file.
§ 0: No data transmission is acknowledged..
§ 1: A data transmission is acknowledged and the current data values will be
transmitted via IOCNET.
A data transmission request that is not acknowledged by the Buffer Out port
Send Acknowledge leads to task overrun in the processor application. A task
overrun will be logged as an I/O error in the Message Viewer of the SCALEXIO
web interface. The FPGA buffer that caused the task overrun will also be logged.
For details on the port Read Request, refer to Buffer In on page 131.

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Buffer64 Out

Purpose To write data to an IOCNET buffer with a data width of 64 bits.

Description If you select Buffer64 as the access type, the data is written to an IOCNET
buffer. 32 buffers are available. Each buffer has a variable buffer size of 1 up to
32768 elements. Each buffer element has a data width of 64 bits.

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Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 545 … 576.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(1).Init / Binary
point position (or fraction width) Lets you specify the binary point position
or returns the fraction width of the Data inport depending on the format
selected in the Format setting (see below).
§ signed/unsigned
The values of the Data inport are in fixed-point format. You can specify the
binary point position of the 64-bit value in the range 0 … 64.
0 represents the lowest bit position, 64 the highest bit position.
64-bit fixed-point data types are converted to double, except the data
type without a binary point (binary point position = 0). Therefore, the fixed-
point resolution of fixed-point data types with a binary point (binary point
position > 0) is restricted to 53 bits.
§ floating-point
The values of the Data inport are in floating‑point format. The parameter then
provides the fraction width.

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Buffer
size Lets you specify the size of the buffer in the range 1 … 32768.

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Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmem64p_<ChannelNumber>_din / Data Specifies a 64-bit data value to

be written to an IOCNET buffer. The data format depends on the related
parameter settings.

xmem64p_<ChannelNumber>_write / Enable Specifies the current valid

Data port value.
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.

xmem64p_<ChannelNumber>_finished / Ready Explicitly specifies the

buffer state as ready to send the buffer immediately, even if it is not completely
filled. The data values will be written to a new buffer in the next clock cycle.
While the port value is 1, transmission switches buffer in every clock cycle. The
value should therefore be set for one clock cycle only. If the buffer is completely
filled, it is automatically switched, and the data values are stored in a new buffer.
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready for sending, even if it is not completely filled.
The buffer is switched and the data values are accessible via IOCNET bus in the
next clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.

xmem64p_<ChannelNumber>_overflow / Overflow Outputs a flag that

xmem64p_<ChannelNumber>_send_ack / Send Acknowledge Triggers a

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overrun will be logged as an I/O error in the Message Viewer of the SCALEXIO
web interface. The FPGA buffer that caused the task overrun will also be logged.
For details on the port Read Request, refer to Buffer64 In on page 133.

Overview of the DS2655 FPGA Base Board Frameworks............................................................ 19

CN App Status

Purpose To read the status of application that is running on the computation node.

Description There is one digital input channel that is used for the CN App Status I/O
function.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 2.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

iocnet_appl_status/ CN Application Status Outputs the state of the

application that is running on the computation node.
Data type: UFix_1_0
§ 0: The application on the computation node is stopped.
§ 1: The application on the computation node is running.

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I-FPGA In (IOCNET)

I-FPGA In (IOCNET)

Purpose To read a 32-bit raw data value from an IOCNET buffer.

Description You can select I-FPGA In (IOCNET) I/O functions to implement an inter-FPGA
communication between FPGA base boards. There are 32 channels.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 10 … 41.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

hcfw.PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(1).Init / Buffer
size Lets you specify the size of the IOCNET buffer in the range 1 … 1024.
The maximum range of the Address inport depends on the buffer size.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 32-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

Note

You can transfer any data type with a bit width of up to 32 Bit via
inter-FPGA over IOCNET. To do this, you can reinterpret the data type
to UFix_32_0 and vice versa. Reinterpreting data types does not cost any
hardware or latency.
The range can be exceeded for the Data outport. The outport's value is
then cast to UFix_32_0.

xmemf_inter_<ChannelNumber>_addr / Address Specifies a data value in

the IOCNET buffer to be read. The block requires one clock cycle to update the
value of the Data outport with the data value of the specified address.
Data type: UFix_16_0
Data width: 1

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The maximum address range depends on the Buffer size parameter. The address
range with valid data values can be derived from the value of the Data Count
port.

xmemf_inter_<ChannelNumber>_count / Data Count Outputs the

number of elements in the current IOCNET buffer. You can use the value to
define the valid range for the Address port from 0 to (Data Count -1).
Data type: UFix_16_0
Data width: 1
The maximum value range depends on the Buffer size parameter.

xmemf_inter_<ChannelNumber>_dout / Data Outputs a 32-bit raw data

value from the specified address of the IOCNET buffer.
Data type: UFix_32_0
Data width: 1

xmemf_inter_<ChannelNumber>_new_data / Data New Outputs a flag

that indicates the update of the Data port.
Data type: UFix_1_0
Data width: 1
If the flag changes from 0 to 1 and then to 0 again, the requested buffer
contains new values and is ready to be read. The flag is set to 1 within only one
clock cycle.

I/O mapping No external connection to the I/O connector of the board.

Overview of the DS2655 FPGA Base Board Frameworks............................................................ 19

I-FPGA64 In (IOCNET)

Purpose To read a 64-bit raw data value from an IOCNET buffer.

Description According to the number of physical connections available on the DS2655 FPGA
Base Board, you can select the I-FPGA64 In (IOCNET) I/O functions. There are
32 channels.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 42 … 73.

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IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

hcfw.PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(1).Init / Buffer
size Lets you specify the size of the IOCNET buffer in the range 1 … 512. The
maximum range of the Address inport depends on the buffer size.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64 bits in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

Note

You can transfer any data type with a bit width of up to 64 Bit via
inter-FPGA over IOCNET. To do this, you can reinterpret the data type
to UFix_64_0 and vice versa. Reinterpreting data types does not cost any
hardware or latency.
The range can be exceeded for the Data outport. The outport's value is
then cast to UFix_64_0.

xmem64f_inter_<ChannelNumber>_addr / Address Specifies a data value

in the IOCNET buffer to be read. The block requires one clock cycle to update the
value of the Data outport with the data value of the specified address.
Data type: UFix_16_0
Data width: 1
The maximum address range depends on the Buffer size parameter. The address
range with valid data values can be derived from the value of the Data Count
port.

xmem64f_inter_<ChannelNumber>_count / Data Count Outputs the

xmem64f_inter_<ChannelNumber>_dout / Data Outputs a 64-bit raw

data value from the specified address of the IOCNET buffer.
Data type: UFix_64_0
Data width: 1

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xmem64f_inter_<ChannelNumber>_new_data / Data New Outputs a flag

I/O mapping No external connection to the I/O connector of the board.

Overview of the DS2655 FPGA Base Board Frameworks............................................................ 19

I-FPGA Out (IOCNET)

Purpose To write a 32-bit raw data value to an IOCNET buffer.

Description You can select I-FPGA Out (IOCNET) I/O functions to implement an inter-FPGA
communication between FPGA base boards. There are 32 channels.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 8 … 39.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

hcfw.PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(1).Init / Buffer
size Lets you specify the size of the IOCNET buffer in the range 1 … 1024.

Note

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

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The channel number can be specified in the range 00 … 31.

Note

You can transfer any data type with a bit width of up to 32 Bit via
inter-FPGA over IOCNET. To do this, you can reinterpret the data type
to UFix_32_0 and vice versa. Reinterpreting data types does not cost any
hardware or latency.
The range of the Data inport can be exceeded. The value of the inport is
then cast to the raw data format UFix_32_0.

xmemp_inter_<ChannelNumber>_din / Data Specifies a 32-bit raw data

value to be written to an IOCNET buffer.
Data type: UFix_32_0
Data width: 1

xmemp_inter_<ChannelNumber>_strobe / Enable Specifies the current

valid Data port value.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The Data value to be written is not stored in the IOCNET buffer.
§ 1: The Data value to be written is stored in the IOCNET buffer. The value of
the current clock cycle is used.

xmemp_inter_<ChannelNumber>_finished / Ready Explicitly specifies the

buffer state as ready to send immediately, even if the buffer is not completely
filled. The data values are written to a new buffer in the following clock cycle.
While the port value is 1, the buffer switches every clock cycle. You are therefore
recommended to set the value for only one clock cycle. If the buffer is completely
filled, it is automatically switched, and the data values are stored in a new buffer.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready to send, even if it is not completely filled.
The ready flag must be set no later than the last data value, otherwise the
buffer switches twice.

xmemp_inter_<ChannelNumber>_write / Send Triggers a data

transmission via IOCNET.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Data values are not acknowledged for transmission.
§ 1: Current Data values are acknowledged and will be transmitted via IOCNET.

xmemp_inter_<ChannelNumber>_overflow / Overflow Outputs a flag

that indicates that a buffer overflow occurred. An overflow occurs when the new
buffer is triggered for transmission and the old buffer was not sent completely.
Data type: UFix_1_0

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Data width: 1
Values:
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.

I/O mapping No external connection to the I/O connector of the board.

Overview of the DS2655 FPGA Base Board Frameworks............................................................ 19

I-FPGA64 Out (IOCNET)

Purpose To write a 64-bit raw data value to an IOCNET buffer.

Description You can select I-FPGA64 Out (IOCNET) I/O functions to implement an inter-
FPGA communication between FPGA base boards. There are 32 channels.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 40 … 71.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

hcfw.PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(1).Init / Buffer
size Lets you specify the size of the IOCNET buffer in the range 1 … 512.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64 bits in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

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I-FPGA64 Out (IOCNET)

The channel number can be specified in the range 00 … 31.

Note

You can transfer any data type with a bit width of up to 64 Bit via
inter-FPGA over IOCNET. To do this, you can reinterpret the data type
to UFix_64_0 and vice versa. Reinterpreting data types does not cost any
hardware or latency.
The range of the Data inport can be exceeded. The value of the inport is
then cast to the raw data format UFix_64_0.

xmem64p_inter_<ChannelNumber>_din / Data Specifies a 64-bit raw data

value to be written to an IOCNET buffer.
Data type: UFix_64_0
Data width: 1

xmem64p_inter_<ChannelNumber>_strobe / Enable Specifies the current

xmem64p_inter_<ChannelNumber>_finished / Ready Explicitly specifies

the buffer state as ready to send immediately, even if the buffer is not
completely filled. The data values are written to a new buffer in the following
clock cycle. While the port value is 1, the buffer switches every clock cycle. You
are therefore recommended to set the value for only one clock cycle. If the buffer
is completely filled, it is automatically switched, and the data values are stored in
a new buffer.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready to send, even if it is not completely filled.
The ready flag must be set no later than the last data value, otherwise the
buffer switches twice.

xmem64p_inter_<ChannelNumber>_write / Send Triggers a data

xmem64p_inter_<ChannelNumber>_overflow / Overflow Outputs a flag

that indicates that a buffer overflow occurred. An overflow occurs when the new
buffer is triggered for transmission and the old buffer was not sent completely.

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Data type: UFix_1_0

Data width: 1
Values:
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.

I/O mapping No external connection to the I/O connector of the board.

Overview of the DS2655 FPGA Base Board Frameworks............................................................ 19

Interrupt

Purpose To request a processor interrupt outside of the FPGA application.

Description The DS2655 FPGA Base Board provides 8 interrupt lines. An interrupt is
requested if the Int port is set to 1 for at least one clock cycle. If you set
the Int port to 0, the last interrupt is not released but saved. An interrupt is
edge-triggered.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 8.

IRQProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 7.

usr_<ChannelNumber>_interrupt / Int Provides the interrupt request line.

§ 0 to 1: Interrupt is requested (edge-triggered).
§ 0: No interrupt is requested. Last requested interrupt is saved.

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IOCNET Global Time

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IOCNET Global Time

Purpose To read the number of hardware ticks.

Description There is one digital input channel that is used for the IOCNET Global Time I/O
function.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 3.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

iocnet_glob_time/ IOCNET Global Time Outputs the number of hardware

ticks that occurred since the SCALEXIO system power was switched to on. If you
use a multiprocessor system, the value is set to zero each time an application is
reloaded and restarted.
Data type: UFix_56_0
Tick step-width: 8.5 ns

Overview of the DS2655 FPGA Base Board Frameworks............................................................ 19

LED Out

Purpose To write a digital signal that controls the LED on the board.

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Description There is one digital output channel that is used for the LED Out I/O function.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 1.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

led_out / LED Out Controls the LED on the board.

Data type: UFix_1_0
§ 0: LED lights green.
§ 1: LED lights orange.

Overview of the DS2655 FPGA Base Board Frameworks............................................................ 19

Purpose To read data from an IOCNET register with a data width of 32 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 256.

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Register In

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(3).Init / Register
group ID Lets you specify a number in the range 1 … 63 to create
register groups. Registers that you specified with the same group ID are
sampled simultaneously within the FPGA application. The values therefore form a
consistent data group that is written to the IOCNET bus.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 255.

xreg_<ChannelNumber>_dout / Data Outputs a 32-bit data value to be

read from an IOCNET register. The data format depends on the related
parameter settings.

xreg_<ChannelNumber>_dout_wr / Data New Outputs a flag that

indicates the changes of the register status. If the flag changes from 0 to 1

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and then back to 0, the requested register contains a new value. The flag is set
to 1 only within one clock cycle.

Overview of the DS2655 FPGA Base Board Frameworks............................................................ 19

Register64 In

Purpose To read data from an IOCNET register with a data width of 64 bits.

Description If you select Register as the access type, the data is read from an IOCNET
register. 256 registers are available with a data width of 64 bits each. The values
are transmitted element by element. If you want to access data from several
registers simultaneously, you can group these registers by specifying the same
group identifier for them.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 289 … 544.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(1).Init / Binary
point position (or fraction width) Lets you specify the binary point position
or returns the fraction width of the Data outport depending on the format
selected in the Format setting (see below).
§ signed/unsigned
The values of the Data outport are in fixed-point format. You can specify the
binary point position of the 64-bit value in the range 0 … 64.
0 represents the lowest bit position, 64 the highest bit position.
64-bit fixed-point data types are converted to double, except the data
type without a binary point (binary point position = 0). Therefore, the fixed-
point resolution of fixed-point data types with a binary point (binary point
position > 0) is restricted to 53 bits.
§ floating-point
The values of the Data outport are in floating‑point format. The parameter
then provides the fraction width.

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PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(2).Init /
Format Lets you specify the data format of the Data outport.
§ signed/unsigned
The values of the Data outport are in fixed‑point format with or without one
bit reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
§ floating‑point
The values of the Data outport are in floating‑point format.
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is provided by the Binary point position (or fraction
width) setting.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(3).Init / Register
group ID Lets you specify a number in the range 1 … 63 to create
register groups. Registers that you specified with the same group ID are
sampled simultaneously within the FPGA application. The values therefore form a
consistent data group that is written to the IOCNET bus.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 255.

xreg64_<ChannelNumber>_dout / Data Outputs a 64-bit data value to

be read from an IOCNET register. The data format depends on the related
parameter settings.

xreg64_<ChannelNumber>_dout_wr / Data New Outputs a flag that

indicates the changes of the register status. If the flag changes from 0 to 1
and then back to 0, the requested register contains a new value. The flag is set
to 1 only within one clock cycle.

Overview of the DS2655 FPGA Base Board Frameworks............................................................ 19

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Purpose To write data to an IOCNET register with a data width of 32 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 256.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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Register64 Out

from the IOCNET bus sequentially and then provided to the FPGA application
simultaneously.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 255.

xreg_<ChannelNumber>_din / Data Specifies a 32-bit data value to be

written to an IOCNET register. The data format depends on the related
parameter settings.

Overview of the DS2655 FPGA Base Board Frameworks............................................................ 19

Register64 Out

Purpose To write data to an IOCNET register with a data width of 64 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 289 … 544.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init /
Register64 group ID Lets you specify a number in the range 1 … 63 to
create register groups. Registers that you specified with the same group ID
are read from the IOCNET bus sequentially and then provided to the FPGA
application simultaneously.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 255.

xreg64_<ChannelNumber>_din / Data Specifies a 64-bit data value to

be written to an IOCNET register. The data format depends on the related
parameter settings.

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Status In

Overview of the DS2655 FPGA Base Board Frameworks............................................................ 19

Status In

Purpose To read a digital signal that outputs the state of the FPGA initialization sequence.

Description There is one digital input channel that is used for the Status In I/O function.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 1.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

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I/O Functions of the DS6601 FPGA Base Board Framework

I/O Functions of the DS6601 FPGA Base Board

Framework

Introduction The DS6601 (KU035) FPGA Base Board framework of the DS6601 FPGA Base
Board provides the standard I/O functionality of the board.

Where to go from here Information in this section

APU Master........................................................................................... 161

To distribute angle values over IOCNET for synchronizing angle-based
applications.

APU Slave.............................................................................................. 163

To read angle values distributed by an APU Master over IOCNET for
synchronizing angle-based applications.

Buffer In................................................................................................ 165

To read data from an IOCNET buffer with a data width of 32 bits.

Buffer64 In............................................................................................ 167

To read data from an IOCNET buffer with a data width of 64 bits.

Buffer Out............................................................................................. 169

To write data to an IOCNET buffer with a data width of 32 bits.

Buffer64 Out......................................................................................... 171

To write data to an IOCNET buffer with a data width of 64 bits.

CN App Status....................................................................................... 174

To read the status of application that is running on the computation
node.

I-FPGA In (IOCNET)................................................................................ 175

To read a 32-bit raw data value from an IOCNET buffer.

I-FPGA64 In (IOCNET)............................................................................ 176

To read a 64-bit raw data value from an IOCNET buffer.

I-FPGA Out (IOCNET)............................................................................. 178

To write a 32-bit raw data value to an IOCNET buffer.

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I-FPGA64 Out (IOCNET)......................................................................... 180

To write a 64-bit raw data value to an IOCNET buffer.

Interrupt................................................................................................ 182
To request a processor interrupt outside of the FPGA application.

IOCNET Global Time.............................................................................. 183

To read the number of hardware ticks.

LED Out................................................................................................. 183

To write a digital signal that controls the LED on the board.

Register In............................................................................................. 184

To read data from an IOCNET register with a data width of 32 bits.

Register64 In......................................................................................... 186

To read data from an IOCNET register with a data width of 64 bits.

Register Out.......................................................................................... 188

To write data to an IOCNET register with a data width of 32 bits.

Register64 Out...................................................................................... 189

To write data to an IOCNET register with a data width of 64 bits.

Status In................................................................................................ 191

To read a digital signal that outputs the state of the FPGA initialization
sequence.

Watchdog............................................................................................. 191
To check if the processor application is alive.

Information in other sections

Other frameworks that provide access to the FPGA functionality

I/O Functions of the DS2655M2 I/O Module Framework........................ 249

The DS2655M2 I/O Module framework provides digital I/O functionality
of a SCALEXIO FPGA base board with at least one DS2655M2 Digital I/O
Module.

I/O Functions of the DS6651 Multi-I/O Module Framework.................... 269

The DS6651 Multi-I/O Module framework provides analog and digital I/O
functionality of a SCALEXIO FPGA base board with at least one DS6651
Multi-I/O Module.

I/O Functions of the Inter-FPGA Interface Framework............................. 313

The Inter-FPGA Interface framework provides access to the I/O module
slots of a SCALEXIO FPGA base board to implement an inter-FPGA
communication bus.

I/O Functions of the DS660X_MGT Framework...................................... 299

The DS660X_MGT framework provides access to an MGT module.

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APU Master

APU Master

Purpose To distribute angle values over IOCNET for synchronizing angle-based

applications.

Description According to the number of physical connections available on the DS6601 FPGA
Base Board, you can select the APU Master I/O functions. There are six digital
output channels.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 2 … 7.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(2).Init / Initial
position Lets you set the initial APU master position in degree.
§ Value range: -1440° ... +1440°

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 01 … 06.

iocnet_glob_master_angle<ChannelNumber>_ctr / Phi Read HD For

internal use only.

iocnet_glob_master_angle<ChannelNumber>_pos / Phi Read Outputs

the angle counter value of the APU that the APU Master writes to the APU
bus. The step size of the angle counter is approximately 0.011°. The step size is
independent from the angle range.
Formula for angle calculation: alpha[°] = Phi Read * 720°/216
The value range depends on the settings of the Angle Range:
§ 360° angle range: 0 ... 32767 (215-1)
§ 720° angle range: 0 ... 65535 (216-1)
Data type: UFix_16_0
Data width: 1
APU bus clock cycle: 8 ns

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Range exceeding is not possible.

iocnet_glob_master_angle<ChannelNumber>_rev / Rev Read Specifies

the 37 bit total revolution (rev) value for the APU bus.
The APU bus clock cycle is 8 ns. The 37 Bit range is -236 … 236 - 1.
Data type: Double
Data width: 1
Range exceeding is not possible.

iocnet_glob_master_angle<ChannelNumber>_vel / Delta Phi For internal

use only.

iocnet_glob_master_angle<ChannelNumber>_en / Delta Phi Enable For

internal use only.

iocnet_glob_master_angle<ChannelNumber>_busy / Busy Specifies

whether APU master is busy to set the last velocity value. If Busy is 1 (high),
new velocity values cannot be set.
Busy stays active for at least 10 µs depending on the IOCNET structure..

iocnet_glob_master_angle<ChannelNumber>_res / Angle
Range Specifies the angle value range of Phi Read.
§ 0: 720° angle range
§ 1: 360° angle range

iocnet_glob_master_angle<ChannelNumber>_upd_trig / Set
Velocity Specifies the actual value of Velocity as new velocity value. The new
value is set only if Set Velocity is 1 (high) and Busy is 0 (low).
Notes on updating velocity values:
§ Setting the velocity values at very short intervals (e.g. every 80 ns) leads to high
data traffic on IOCNET.
High data traffic might freeze your SCALEXIO system.
§ Setting a new velocity value before the last setting is executed overwrites the
last setting.
To distribute and execute a new velocity value takes about 10 µs. If the APU
master always sets new velocity values before the last value is executed, the
velocity value will never change.

I/O mapping No external connection to the I/O connector of the board.

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APU Slave

Overview of the DS6601 FPGA Base Board Frameworks............................................................ 21

APU Slave

Purpose To read angle values distributed by an APU Master over IOCNET for synchronizing
angle-based applications.

Description According to the number of physical connections available on the DS6601 FPGA
Base Board, you can select the APU Slave I/O functions. There are six digital
input channels.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 4 … 9.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.In.Fct(<IOFunctionNumber>).Parameter(11).Init Lets you

APU Bus Slave APU Resulting Angle Range of the Slave

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Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 01 … 06.

iocnet_glob_angle<ChannelNumber>_pos / Phi Read Outputs the angle

value that APU Slave reads from the APU bus. The angle value is independent
from the angle range of the APU bus.
Formula for angle calculation: alpha[°] = Phi Read * 720°/216
The value range depends on the angle range of the APU bus:
§ 360° angle range: 0 ... 32767 (215-1)
§ 720° angle range: 0 ... 65535 (216-1)
Data type: UFix_16_0
Data width: 1
APU bus clock cycle: 8 ns
Range exceeding is not possible.

iocnet_glob_angle<ChannelNumber>_rev / Rev Read Outputs the 37 bit

total revolution (rev) value for the APU bus.
The APU bus clock cycle is 8 ns. The 37 Bit range is -236 … 236 - 1.
Data type: Double
Data width: 1
Range exceeding is not possible.

iocnet_glob_angle<ChannelNumber>_ctr / Phi Read HD For internal use

only.

iocnet_glob_angle<ChannelNumber>_vel / Delta Phi For internal use

only.

iocnet_glob_angle<ChannelNumber>_en / Delta Phi Enable For internal

use only.

iocnet_glob_angle<ChannelNumber>_res / Angle Range Outputs a flag

I/O mapping No external connection to the I/O connector of the board.

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Buffer In

Buffer In

Purpose To read data from an IOCNET buffer with a data width of 32 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 257 … 288.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmemf_<ChannelNumber>_count / Data Count Outputs the number of

elements in the current buffer. The maximum range depends on the specified
buffer size. You can use the value to define the valid range for the Address
inport of 0 … (Data Count -1).

xmemf_<ChannelNumber>_dout / Data Outputs a 32-bit data value to be

read from an IOCNET buffer. The data format depends on the related parameter
settings.

xmemf_<ChannelNumber>_addr / Address Specifies an element in the

xmemf_<ChannelNumber>_new_data / Data New Outputs a flag that

xmemf_<ChannelNumber>_read_req / Read Request Outputs a flag that

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Buffer64 In

Overview of the DS6601 FPGA Base Board Frameworks............................................................ 21

Buffer64 In

Purpose To read data from an IOCNET buffer with a data width of 64 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 545 … 576.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(1).Init / Binary
point position (or fraction width) Lets you specify the binary point position
or returns the fraction width of the Data outport depending on the format
selected in the Format setting (see below).
§ signed/unsigned
The values of the Data outport are in fixed-point format. You can specify the
binary point position of the 64-bit value in the range 0 … 64.
0 represents the lowest bit position, 64 the highest bit position.
64-bit fixed-point data types are converted to double, except the data
type without a binary point (binary point position = 0). Therefore, the fixed-
point resolution of fixed-point data types with a binary point (binary point
position > 0) is restricted to 53 bits.
§ floating-point
The values of the Data outport are in floating‑point format. The parameter
then provides the fraction width.

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Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmem64f_<ChannelNumber>_count / Data Count Outputs the number of

elements in the current buffer. The maximum range depends on the specified
buffer size. You can use the value to define the valid range for the Address
inport of 0 … (Data Count -1).

xmem64f_<ChannelNumber>_dout / Data Outputs a 64-bit data value to

be read from an IOCNET buffer. The data format depends on the related
parameter settings.

xmem64f_<ChannelNumber>_addr / Address Specifies an element in the

xmem64f_<ChannelNumber>_new_data / Data New Outputs a flag that

xmem64f_<ChannelNumber>_read_req / Read Request Outputs a flag

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Buffer Out

Overview of the DS6601 FPGA Base Board Frameworks............................................................ 21

Buffer Out

Purpose To write data to an IOCNET buffer with a data width of 32 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 129 … 160.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Buffer
size Lets you specify the size of the buffer in the range 1 ... 32768.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmemp_<ChannelNumber>_din / Data Specifies a 32-bit data value to be

written to an IOCNET buffer. The data format depends on the related parameter
settings.

xmemp_<ChannelNumber>_write / Enable Specifies the current valid Data

port value.
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.

xmemp_<ChannelNumber>_finished / Ready Explicitly specifies the buffer

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Buffer64 Out

The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.

xmemp_<ChannelNumber>_overflow / Overflow Outputs a flag that

xmemp_<ChannelNumber>_send_ack / Send Acknowledge Triggers a

Overview of the DS6601 FPGA Base Board Frameworks............................................................ 21

Buffer64 Out

Purpose To write data to an IOCNET buffer with a data width of 64 bits.

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Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 545 … 576.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(1).Init / Binary
point position (or fraction width) Lets you specify the binary point position
or returns the fraction width of the Data inport depending on the format
selected in the Format setting (see below).
§ signed/unsigned
The values of the Data inport are in fixed-point format. You can specify the
binary point position of the 64-bit value in the range 0 … 64.
0 represents the lowest bit position, 64 the highest bit position.
64-bit fixed-point data types are converted to double, except the data
type without a binary point (binary point position = 0). Therefore, the fixed-
point resolution of fixed-point data types with a binary point (binary point
position > 0) is restricted to 53 bits.
§ floating-point
The values of the Data inport are in floating‑point format. The parameter then
provides the fraction width.

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Buffer
size Lets you specify the size of the buffer in the range 1 … 32768.

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Buffer64 Out

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmem64p_<ChannelNumber>_din / Data Specifies a 64-bit data value to

be written to an IOCNET buffer. The data format depends on the related
parameter settings.

xmem64p_<ChannelNumber>_write / Enable Specifies the current valid

Data port value.
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.

xmem64p_<ChannelNumber>_finished / Ready Explicitly specifies the

buffer state as ready to send the buffer immediately, even if it is not completely
filled. The data values will be written to a new buffer in the next clock cycle.
While the port value is 1, transmission switches buffer in every clock cycle. The
value should therefore be set for one clock cycle only. If the buffer is completely
filled, it is automatically switched, and the data values are stored in a new buffer.
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready for sending, even if it is not completely filled.
The buffer is switched and the data values are accessible via IOCNET bus in the
next clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.

xmem64p_<ChannelNumber>_overflow / Overflow Outputs a flag that

xmem64p_<ChannelNumber>_send_ack / Send Acknowledge Triggers a

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Overview of the DS6601 FPGA Base Board Frameworks............................................................ 21

CN App Status

Purpose To read the status of application that is running on the computation node.

Description There is one digital input channel that is used for the CN App Status I/O
function.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 2.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

iocnet_appl_status/ CN Application Status Outputs the state of the

application that is running on the computation node.
Data type: UFix_1_0
§ 0: The application on the computation node is stopped.
§ 1: The application on the computation node is running.

Overview of the DS6601 FPGA Base Board Frameworks............................................................ 21

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I-FPGA In (IOCNET)

I-FPGA In (IOCNET)

Purpose To read a 32-bit raw data value from an IOCNET buffer.

Description You can select I-FPGA In (IOCNET) I/O functions to implement an inter-FPGA
communication between FPGA base boards. There are 32 channels.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 11 … 42.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Note

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

Note

xmemf_inter_<ChannelNumber>_addr / Address Specifies a data value in

the IOCNET buffer to be read. The block requires one clock cycle to update the
value of the Data outport with the data value of the specified address.
Data type: UFix_16_0
Data width: 1

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The maximum address range depends on the Buffer size parameter. The address
range with valid data values can be derived from the value of the Data Count
port.

xmemf_inter_<ChannelNumber>_count / Data Count Outputs the

xmemf_inter_<ChannelNumber>_dout / Data Outputs a 32-bit raw data

value from the specified address of the IOCNET buffer.
Data type: UFix_32_0
Data width: 1

xmemf_inter_<ChannelNumber>_new_data / Data New Outputs a flag

I/O mapping No external connection to the I/O connector of the board.

Overview of the DS6601 FPGA Base Board Frameworks............................................................ 21

I-FPGA64 In (IOCNET)

Purpose To read a 64-bit raw data value from an IOCNET buffer.

Description According to the number of physical connections available on the DS6601 FPGA
Base Board, you can select the I-FPGA64 In (IOCNET) I/O functions. There are
32 channels.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 43 … 74.

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I-FPGA64 In (IOCNET)

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64 bits in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

Note

xmem64f_inter_<ChannelNumber>_addr / Address Specifies a data value

xmem64f_inter_<ChannelNumber>_count / Data Count Outputs the

xmem64f_inter_<ChannelNumber>_dout / Data Outputs a 64-bit raw

data value from the specified address of the IOCNET buffer.
Data type: UFix_64_0
Data width: 1

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xmem64f_inter_<ChannelNumber>_new_data / Data New Outputs a flag

I/O mapping No external connection to the I/O connector of the board.

Overview of the DS6601 FPGA Base Board Frameworks............................................................ 21

I-FPGA Out (IOCNET)

Purpose To write a 32-bit raw data value to an IOCNET buffer.

Description You can select I-FPGA Out (IOCNET) I/O functions to implement an inter-FPGA
communication between FPGA base boards. There are 32 channels.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 8 … 39.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

hcfw.PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(1).Init / Buffer
size Lets you specify the size of the IOCNET buffer in the range 1 … 1024.

Note

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

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I-FPGA Out (IOCNET)

The channel number can be specified in the range 00 … 31.

Note

You can transfer any data type with a bit width of up to 32 Bit via
inter-FPGA over IOCNET. To do this, you can reinterpret the data type
to UFix_32_0 and vice versa. Reinterpreting data types does not cost any
hardware or latency.
The range of the Data inport can be exceeded. The value of the inport is
then cast to the raw data format UFix_32_0.

xmemp_inter_<ChannelNumber>_din / Data Specifies a 32-bit raw data

value to be written to an IOCNET buffer.
Data type: UFix_32_0
Data width: 1

xmemp_inter_<ChannelNumber>_strobe / Enable Specifies the current

xmemp_inter_<ChannelNumber>_finished / Ready Explicitly specifies the

xmemp_inter_<ChannelNumber>_write / Send Triggers a data

xmemp_inter_<ChannelNumber>_overflow / Overflow Outputs a flag

that indicates that a buffer overflow occurred. An overflow occurs when the new
buffer is triggered for transmission and the old buffer was not sent completely.
Data type: UFix_1_0

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Data width: 1
Values:
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.

I/O mapping No external connection to the I/O connector of the board.

Overview of the DS6601 FPGA Base Board Frameworks............................................................ 21

I-FPGA64 Out (IOCNET)

Purpose To write a 64-bit raw data value to an IOCNET buffer.

Description You can select I-FPGA64 Out (IOCNET) I/O functions to implement an inter-
FPGA communication between FPGA base boards. There are 32 channels.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 40 … 71.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

hcfw.PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(1).Init / Buffer
size Lets you specify the size of the IOCNET buffer in the range 1 … 512.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64 bits in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

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I-FPGA64 Out (IOCNET)

The channel number can be specified in the range 00 … 31.

Note

You can transfer any data type with a bit width of up to 64 Bit via
inter-FPGA over IOCNET. To do this, you can reinterpret the data type
to UFix_64_0 and vice versa. Reinterpreting data types does not cost any
hardware or latency.
The range of the Data inport can be exceeded. The value of the inport is
then cast to the raw data format UFix_64_0.

xmem64p_inter_<ChannelNumber>_din / Data Specifies a 64-bit raw data

value to be written to an IOCNET buffer.
Data type: UFix_64_0
Data width: 1

xmem64p_inter_<ChannelNumber>_strobe / Enable Specifies the current

xmem64p_inter_<ChannelNumber>_finished / Ready Explicitly specifies

xmem64p_inter_<ChannelNumber>_write / Send Triggers a data

xmem64p_inter_<ChannelNumber>_overflow / Overflow Outputs a flag

that indicates that a buffer overflow occurred. An overflow occurs when the new
buffer is triggered for transmission and the old buffer was not sent completely.

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Data type: UFix_1_0

Data width: 1
Values:
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.

I/O mapping No external connection to the I/O connector of the board.

Overview of the DS6601 FPGA Base Board Frameworks............................................................ 21

Interrupt

Purpose To request a processor interrupt outside of the FPGA application.

Description The DS6601 FPGA Base Board provides 16 interrupt lines. An interrupt is
requested if the Int port is set to 1 for at least one clock cycle. If you set
the Int port to 0, the last interrupt is not released but saved. An interrupt is
edge-triggered.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 16.

IRQProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 15.

usr_<ChannelNumber>_interrupt / Int Provides the interrupt request line.

§ 0 to 1: Interrupt is requested (edge-triggered).
§ 0: No interrupt is requested. Last requested interrupt is saved.

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IOCNET Global Time

Overview of the DS6601 FPGA Base Board Frameworks............................................................ 21

IOCNET Global Time

Purpose To read the number of hardware ticks.

Description There is one digital input channel that is used for the IOCNET Global Time I/O
function.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 3.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

iocnet_glob_time/ IOCNET Global Time Outputs the number of hardware

Overview of the DS6601 FPGA Base Board Frameworks............................................................ 21

LED Out

Purpose To write a digital signal that controls the LED on the board.

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Description There is one digital output channel that is used for the LED Out I/O function.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 1.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

led_out / LED Out Controls the LED on the board.

Data type: UFix_1_0
§ 0: LED lights green.
§ 1: LED lights orange.

Overview of the DS6601 FPGA Base Board Frameworks............................................................ 21

Purpose To read data from an IOCNET register with a data width of 32 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 256.

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Register In

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(3).Init / Register
group ID Lets you specify a number in the range 1 … 63 to create
register groups. Registers that you specified with the same group ID are
sampled simultaneously within the FPGA application. The values therefore form a
consistent data group that is written to the IOCNET bus.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 255.

xreg_<ChannelNumber>_dout / Data Outputs a 32-bit data value to be

read from an IOCNET register. The data format depends on the related
parameter settings.

xreg_<ChannelNumber>_dout_wr / Data New Outputs a flag that

indicates the changes of the register status. If the flag changes from 0 to 1

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and then back to 0, the requested register contains a new value. The flag is set
to 1 only within one clock cycle.

Overview of the DS6601 FPGA Base Board Frameworks............................................................ 21

Register64 In

Purpose To read data from an IOCNET register with a data width of 64 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 289 … 544.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(1).Init / Binary
point position (or fraction width) Lets you specify the binary point position
or returns the fraction width of the Data outport depending on the format
selected in the Format setting (see below).
§ signed/unsigned
The values of the Data outport are in fixed-point format. You can specify the
binary point position of the 64-bit value in the range 0 … 64.
0 represents the lowest bit position, 64 the highest bit position.
64-bit fixed-point data types are converted to double, except the data
type without a binary point (binary point position = 0). Therefore, the fixed-
point resolution of fixed-point data types with a binary point (binary point
position > 0) is restricted to 53 bits.
§ floating-point
The values of the Data outport are in floating‑point format. The parameter
then provides the fraction width.

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Register64 In

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(2).Init /
Format Lets you specify the data format of the Data outport.
§ signed/unsigned
The values of the Data outport are in fixed‑point format with or without one
bit reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
§ floating‑point
The values of the Data outport are in floating‑point format.
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is provided by the Binary point position (or fraction
width) setting.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(3).Init / Register
group ID Lets you specify a number in the range 1 … 63 to create
register groups. Registers that you specified with the same group ID are
sampled simultaneously within the FPGA application. The values therefore form a
consistent data group that is written to the IOCNET bus.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 255.

xreg64_<ChannelNumber>_dout / Data Outputs a 64-bit data value to

be read from an IOCNET register. The data format depends on the related
parameter settings.

xreg64_<ChannelNumber>_dout_wr / Data New Outputs a flag that

indicates the changes of the register status. If the flag changes from 0 to 1
and then back to 0, the requested register contains a new value. The flag is set
to 1 only within one clock cycle.

Overview of the DS6601 FPGA Base Board Frameworks............................................................ 21

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Purpose To write data to an IOCNET register with a data width of 32 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 256.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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Register64 Out

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 255.

xreg_<ChannelNumber>_din / Data Specifies a 32-bit data value to be

written to an IOCNET register. The data format depends on the related
parameter settings.

Overview of the DS6601 FPGA Base Board Frameworks............................................................ 21

Register64 Out

Purpose To write data to an IOCNET register with a data width of 64 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 289 … 544.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init /
Register64 group ID Lets you specify a number in the range 1 … 63 to
create register groups. Registers that you specified with the same group ID
are read from the IOCNET bus sequentially and then provided to the FPGA
application simultaneously.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 255.

xreg64_<ChannelNumber>_din / Data Specifies a 64-bit data value to

be written to an IOCNET register. The data format depends on the related
parameter settings.

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Status In

Overview of the DS6601 FPGA Base Board Frameworks............................................................ 21

Status In

Purpose To read a digital signal that outputs the state of the FPGA initialization sequence.

Description There is one digital input channel that is used for the Status In I/O function.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 1.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

Overview of the DS6601 FPGA Base Board Frameworks............................................................ 21

Watchdog

Purpose To check if the processor application is alive.

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Description There is one digital input channel that is used for the Watchdog I/O function.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 75.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

status / Status Outputs a flag that indicates that the processor application
transmits a keep-alive signal within the specified timeout.
§ 0: The watchdog timer expires without a keep-alive signal being transmitted to
the FPGA application.
§ 1: The processor application is alive.
Data type: UFix_1_0

Overview of the DS6601 FPGA Base Board Frameworks............................................................ 21

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I/O Functions of the DS6602 FPGA Base Board Framework

I/O Functions of the DS6602 FPGA Base Board

Framework

Introduction The DS6602 (KU15P) FPGA Base Board framework of the DS6602 FPGA Base
Board provides the standard I/O functionality of the board.

Note

If you use a DS6602 FPGA Base Board, the build process issues a critical
warning about a specific timing requirement.
For more information, refer to Problems and Their Solutions (FPGA
Programming Handcode Framework Guide ).

Where to go from here Information in this section

APU Master........................................................................................... 195

To distribute angle values over IOCNET for synchronizing angle-based
applications.

APU Slave.............................................................................................. 197

To read angle values distributed by an APU Master over IOCNET for
synchronizing angle-based applications.

Buffer In................................................................................................ 199

To read data from an IOCNET buffer with a data width of 32 bits.

Buffer64 In............................................................................................ 201

To read data from an IOCNET buffer with a data width of 64 bits.

Buffer Out............................................................................................. 203

To write data to an IOCNET buffer with a data width of 32 bits.

Buffer64 Out......................................................................................... 206

To write data to an IOCNET buffer with a data width of 64 bits.

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CN App Status....................................................................................... 208

To read the status of application that is running on the computation
node.

DDR4 32 Mode 1.................................................................................. 209

To provide 32-bit read/write access to the DDR4 RAM using the memory
access mode 1.

DDR4 32 Mode 2.................................................................................. 211

To provide 32-bit read/write access to the DDR4 RAM using the memory
access mode 2.

DDR4 64 Mode 1.................................................................................. 214

To provide 64-bit read/write access to the DDR4 RAM using the memory
access mode 1.

DDR4 64 Mode 2.................................................................................. 216

To provide 64-bit read/write access to the DDR4 RAM using the memory
access mode 2.

I-FPGA In (IOCNET)................................................................................ 218

To read a 32-bit raw data value from an IOCNET buffer.

I-FPGA64 In (IOCNET)............................................................................ 220

To read a 64-bit raw data value from an IOCNET buffer.

I-FPGA Out (IOCNET)............................................................................. 222

To write a 32-bit raw data value to an IOCNET buffer.

I-FPGA64 Out (IOCNET)......................................................................... 224

To write a 64-bit raw data value to an IOCNET buffer.

Interrupt................................................................................................ 226
To request a processor interrupt outside of the FPGA application.

IOCNET Global Time.............................................................................. 227

To read the number of hardware ticks.

LED Out................................................................................................. 227

To write a digital signal that controls the LED on the board.

Register In............................................................................................. 228

To read data from an IOCNET register with a data width of 32 bits.

Register64 In......................................................................................... 230

To read data from an IOCNET register with a data width of 64 bits.

Register Out.......................................................................................... 232

To write data to an IOCNET register with a data width of 32 bits.

Register64 Out...................................................................................... 233

To write data to an IOCNET register with a data width of 64 bits.

Status In................................................................................................ 235

To read a digital signal that outputs the state of the FPGA initialization
sequence.

Watchdog............................................................................................. 235
To check if the processor application is alive.

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APU Master

Information in other sections

Other frameworks that provide access to the FPGA functionality

I/O Functions of the DS2655M2 I/O Module Framework........................ 249

The DS2655M2 I/O Module framework provides digital I/O functionality
of a SCALEXIO FPGA base board with at least one DS2655M2 Digital I/O
Module.

I/O Functions of the DS6651 Multi-I/O Module Framework.................... 269

The DS6651 Multi-I/O Module framework provides analog and digital I/O
functionality of a SCALEXIO FPGA base board with at least one DS6651
Multi-I/O Module.

I/O Functions of the Inter-FPGA Interface Framework............................. 313

The Inter-FPGA Interface framework provides access to the I/O module
slots of a SCALEXIO FPGA base board to implement an inter-FPGA
communication bus.

I/O Functions of the DS660X_MGT Framework...................................... 299

The DS660X_MGT framework provides access to an MGT module.

APU Master

Purpose To distribute angle values over IOCNET for synchronizing angle-based

applications.

Description According to the number of physical connections available on the DS6602 FPGA
Base Board, you can select the APU Master I/O functions. There are six digital
output channels.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 2 … 7.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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§ 2: The Angle range property of the FPGA custom function block in

ConfigurationDesk lets you set the angle range of the APU. The default value
is 720°.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(2).Init / Initial
position Lets you set the initial APU master position in degree.
§ Value range: -1440° ... +1440°

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 01 … 06.

iocnet_glob_master_angle<ChannelNumber>_ctr / Phi Read HD For

internal use only.

iocnet_glob_master_angle<ChannelNumber>_pos / Phi Read Outputs

the angle counter value of the APU that the APU Master writes to the APU
bus. The step size of the angle counter is approximately 0.011°. The step size is
independent from the angle range.
Formula for angle calculation: alpha[°] = Phi Read * 720°/216
The value range depends on the settings of the Angle Range:
§ 360° angle range: 0 ... 32767 (215-1)
§ 720° angle range: 0 ... 65535 (216-1)
Data type: UFix_16_0
Data width: 1
APU bus clock cycle: 8 ns
Range exceeding is not possible.

iocnet_glob_master_angle<ChannelNumber>_rev / Rev Read Specifies

the 37 bit total revolution (rev) value for the APU bus.
The APU bus clock cycle is 8 ns. The 37 Bit range is -236 … 236 - 1.
Data type: Double
Data width: 1
Range exceeding is not possible.

iocnet_glob_master_angle<ChannelNumber>_vel / Delta Phi For internal

use only.

iocnet_glob_master_angle<ChannelNumber>_en / Delta Phi Enable For

internal use only.

iocnet_glob_master_angle<ChannelNumber>_busy / Busy Specifies

whether APU master is busy to set the last velocity value. If Busy is 1 (high),
new velocity values cannot be set.
Busy stays active for at least 10 µs depending on the IOCNET structure..

iocnet_glob_master_angle<ChannelNumber>_res / Angle
Range Specifies the angle value range of Phi Read.
§ 0: 720° angle range
§ 1: 360° angle range

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APU Slave

iocnet_glob_master_angle<ChannelNumber>_upd_trig / Set
Velocity Specifies the actual value of Velocity as new velocity value. The new
value is set only if Set Velocity is 1 (high) and Busy is 0 (low).
Notes on updating velocity values:
§ Setting the velocity values at very short intervals (e.g. every 80 ns) leads to high
data traffic on IOCNET.
High data traffic might freeze your SCALEXIO system.
§ Setting a new velocity value before the last setting is executed overwrites the
last setting.
To distribute and execute a new velocity value takes about 10 µs. If the APU
master always sets new velocity values before the last value is executed, the
velocity value will never change.

I/O mapping No external connection to the I/O connector of the board.

Overview of the DS6602 FPGA Base Board Frameworks............................................................ 23

APU Slave

Purpose To read angle values distributed by an APU Master over IOCNET for synchronizing
angle-based applications.

Description According to the number of physical connections available on the DS6601 FPGA
Base Board, you can select the APU Slave I/O functions. There are six digital
input channels.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 4 … 9.

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IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.In.Fct(<IOFunctionNumber>).Parameter(11).Init Lets you

APU Bus Slave APU Resulting Angle Range of the Slave

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 01 … 06.

iocnet_glob_angle<ChannelNumber>_pos / Phi Read Outputs the angle

value that APU Slave reads from the APU bus. The angle value is independent
from the angle range of the APU bus.
Formula for angle calculation: alpha[°] = Phi Read * 720°/216
The value range depends on the angle range of the APU bus:
§ 360° angle range: 0 ... 32767 (215-1)
§ 720° angle range: 0 ... 65535 (216-1)
Data type: UFix_16_0
Data width: 1
APU bus clock cycle: 8 ns
Range exceeding is not possible.

iocnet_glob_angle<ChannelNumber>_rev / Rev Read Outputs the 37 bit

total revolution (rev) value for the APU bus.
The APU bus clock cycle is 8 ns. The 37 Bit range is -236 … 236 - 1.
Data type: Double
Data width: 1
Range exceeding is not possible.

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Buffer In

iocnet_glob_angle<ChannelNumber>_ctr / Phi Read HD For internal use

only.

iocnet_glob_angle<ChannelNumber>_vel / Delta Phi For internal use

only.

iocnet_glob_angle<ChannelNumber>_en / Delta Phi Enable For internal

use only.

iocnet_glob_angle<ChannelNumber>_res / Angle Range Outputs a flag

I/O mapping No external connection to the I/O connector of the board.

Overview of the DS6602 FPGA Base Board Frameworks............................................................ 23

Buffer In

Purpose To read data from an IOCNET buffer with a data width of 32 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 257 … 288.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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§ signed/unsigned
The values of the Data outport are in fixed-point format. You can specify the
binary point position of the 32-bit value in the range 0 … 32.
0 represents the lowest bit position, 32 the highest bit position.
§ floating-point
The values of the Data outport are in floating‑point format. The parameter
then provides the fraction width.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmemf_<ChannelNumber>_count / Data Count Outputs the number of

elements in the current buffer. The maximum range depends on the specified
buffer size. You can use the value to define the valid range for the Address
inport of 0 … (Data Count -1).

xmemf_<ChannelNumber>_dout / Data Outputs a 32-bit data value to be

read from an IOCNET buffer. The data format depends on the related parameter
settings.

xmemf_<ChannelNumber>_addr / Address Specifies an element in the

xmemf_<ChannelNumber>_new_data / Data New Outputs a flag that

indicates the changes of the buffer status. If the flag changes from 0 to 1 and

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Buffer64 In

then back to 0, the requested buffer contains new values and is ready to be
read. The flag is set to 1 only within one clock cycle.

xmemf_<ChannelNumber>_read_req / Read Request Outputs a flag that

Overview of the DS6602 FPGA Base Board Frameworks............................................................ 23

Buffer64 In

Purpose To read data from an IOCNET buffer with a data width of 64 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 545 … 576.

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PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(1).Init / Binary
point position (or fraction width) Lets you specify the binary point position
or returns the fraction width of the Data outport depending on the format
selected in the Format setting (see below).
§ signed/unsigned
The values of the Data outport are in fixed-point format. You can specify the
binary point position of the 64-bit value in the range 0 … 64.
0 represents the lowest bit position, 64 the highest bit position.
64-bit fixed-point data types are converted to double, except the data
type without a binary point (binary point position = 0). Therefore, the fixed-
point resolution of fixed-point data types with a binary point (binary point
position > 0) is restricted to 53 bits.
§ floating-point
The values of the Data outport are in floating‑point format. The parameter
then provides the fraction width.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(2).Init /
Format Lets you specify the data format of the Data outport.
§ signed/unsigned
The values of the Data outport are in fixed‑point format with or without one
bit reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
§ floating‑point
The values of the Data outport are in floating‑point format.
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is provided by the Binary point position (or fraction
width) setting.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmem64f_<ChannelNumber>_count / Data Count Outputs the number of

elements in the current buffer. The maximum range depends on the specified
buffer size. You can use the value to define the valid range for the Address
inport of 0 … (Data Count -1).

xmem64f_<ChannelNumber>_dout / Data Outputs a 64-bit data value to

be read from an IOCNET buffer. The data format depends on the related
parameter settings.

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xmem64f_<ChannelNumber>_addr / Address Specifies an element in the

xmem64f_<ChannelNumber>_new_data / Data New Outputs a flag that

xmem64f_<ChannelNumber>_read_req / Read Request Outputs a flag

that indicates that a data transmission is requested via IOCNET. With Buffer
In port Read Request and the Buffer Out port Send Acknowledge you can
trigger a processor synchronous data exchange.
A data transmission is always requested at the beginning of a task, before the
processor model is computed. Each time a new data transmission is requested
by the Buffer Out port Send Acknowledge, the Buffer In port Read Request
must explicitly acknowledge the Data values for transmission within one task
period. To send current data you can delay the transmission. After a new data
transmission is requested, you write the current data values to the buffer. Then
you must acknowledge the new data for transmission.
Usable only if Enable Read_Req and Send_Ack ports for explicit data
transmit value is enabled in the FPGA framework INI file.
§ 0: No data transmission is requested.
§ 1: A data transmission is requested. This value is set for one clock cycle.
A data transmission request that is not acknowledged by the Buffer Out port
Send Acknowledge leads to task overrun in the processor application. A task
overrun will be logged as an I/O error in the Message Viewer of the SCALEXIO
web interface. The FPGA buffer that caused the task overrun will also be logged.
For details on acknowledging a data transmission with Send Acknowledge,
refer to Buffer64 Out on page 206.

Overview of the DS6602 FPGA Base Board Frameworks............................................................ 23

Buffer Out

Purpose To write data to an IOCNET buffer with a data width of 32 bits.

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Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 129 … 160.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Buffer
size Lets you specify the size of the buffer in the range 1 ... 32768.

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Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmemp_<ChannelNumber>_din / Data Specifies a 32-bit data value to be

written to an IOCNET buffer. The data format depends on the related parameter
settings.

xmemp_<ChannelNumber>_write / Enable Specifies the current valid Data

port value.
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.

xmemp_<ChannelNumber>_finished / Ready Explicitly specifies the buffer

state as ready to send the buffer immediately, even if it is not completely filled.
The data values will be written to a new buffer in the next clock cycle. While
the port value is 1, transmission switches buffer in every clock cycle. The value
should therefore be set for one clock cycle only. If the buffer is completely filled,
it is automatically switched, and the data values are stored in a new buffer.
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready for sending, even if it is not completely filled.
The buffer is switched and the data values are accessible via IOCNET in the
next clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.

xmemp_<ChannelNumber>_overflow / Overflow Outputs a flag that

xmemp_<ChannelNumber>_send_ack / Send Acknowledge Triggers a

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Overview of the DS6602 FPGA Base Board Frameworks............................................................ 23

Buffer64 Out

Purpose To write data to an IOCNET buffer with a data width of 64 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 545 … 576.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(1).Init / Binary
point position (or fraction width) Lets you specify the binary point position
or returns the fraction width of the Data inport depending on the format
selected in the Format setting (see below).
§ signed/unsigned
The values of the Data inport are in fixed-point format. You can specify the
binary point position of the 64-bit value in the range 0 … 64.
0 represents the lowest bit position, 64 the highest bit position.
64-bit fixed-point data types are converted to double, except the data
type without a binary point (binary point position = 0). Therefore, the fixed-
point resolution of fixed-point data types with a binary point (binary point
position > 0) is restricted to 53 bits.
§ floating-point
The values of the Data inport are in floating‑point format. The parameter then
provides the fraction width.

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PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Buffer
size Lets you specify the size of the buffer in the range 1 … 32768.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmem64p_<ChannelNumber>_din / Data Specifies a 64-bit data value to

be written to an IOCNET buffer. The data format depends on the related
parameter settings.

xmem64p_<ChannelNumber>_write / Enable Specifies the current valid

Data port value.
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.

xmem64p_<ChannelNumber>_finished / Ready Explicitly specifies the

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The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.

xmem64p_<ChannelNumber>_overflow / Overflow Outputs a flag that

xmem64p_<ChannelNumber>_send_ack / Send Acknowledge Triggers a

Overview of the DS6602 FPGA Base Board Frameworks............................................................ 23

CN App Status

Purpose To read the status of application that is running on the computation node.

Description There is one digital input channel that is used for the CN App Status I/O
function.

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Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 2.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

iocnet_appl_status/ CN Application Status Outputs the state of the

application that is running on the computation node.
Data type: UFix_1_0
§ 0: The application on the computation node is stopped.
§ 1: The application on the computation node is running.

Overview of the DS6602 FPGA Base Board Frameworks............................................................ 23

DDR4 32 Mode 1

Purpose To provide 32-bit read/write access to the DDR4 RAM using the memory access
mode 1.

Description The DS6602 FPGA Base Board provides a 4 GB DDR4 RAM that can be used by
the FPGA application.

The RAM interface always handles 512 bits at once. Therefore, the FPGA
application can read/write 16 x 32 bits data or 8 x 64 bits data within one
memory access.

You can select different I/O functions to access the DDR4 RAM:
§ DDR4 32 Mode 1 and DDR4 64 Mode 1 to read/write 32/64-bit values with
one memory address. These I/O types use the memory access mode 1.
§ DDR4 32 Mode 2 and DDR4 64 Mode 2 to read/write 32/64-bit values with
two memory addresses. These I/O types use the memory access mode 2.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

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The I/O function number is 8.

hcfw.IOProperties.Out.Fct(8).HcCustomName / Channel name Lets you

specify a custom name for the specified channel.

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

ddr4_init_done / Init Done Outputs a flag that indicates that the RAM is
initialized with specified data values. For more information, refer to Initializing
the DDR4 RAM of the DS6602 (FPGA Programming Handcode Framework
Guide ).
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The RAM is not initialized.
§ 1: The RAM is initialized.

ddr4_init_fail / Init Failed Outputs a flag that the initializing of the RAM
with initial values failed.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The RAM is not initialized or no failure occurs.
§ 1: A failure occurs during the initialization of the RAM.

ddr4_busy_flag / Busy Inport to read a flag that indicates the state of the
DDR4 RAM:
§ 0: The DDR4 module is ready for new read/write operations.
§ 1: The DDR4 module is busy.
Data type: UFix_1_0

ddr4_data_en / Enable Outport to enable the RAM access:

§ 1: Data values are written to the RAM or read from the RAM.
§ 0: No read/write access.
Data type: UFix_1_0

ddr4_direction / Direction Outport to control the direction of data access:

§ 0: Write access
§ 1: Read access
Data type: UFix_1_0

ddr4_address_block_1 / Address Outport to specify the first element in

the RAM for the read/write access. The memory is addressed 512 bit-wise to
read/write 16 x 32-bit data values with the same address.
Data type: UFix_26_0
Value range: 0 … 67,108,863 (226-1)
Data width: 1

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ddr4_rd_data_valid_block_1 / Data valid Inport to read a flag that

indicates that the data values of the Data Read ports are valid:
§ 0: The values are not valid.
§ 1: The values are valid. This value is set for one clock cycle. The data values
must be read by the FPAG application within the same clock cycle.
Data type: UFix_1_0

ddr4_data_<PortNumber>_wr_32_block_1 / Data Write Outport to

specify a 32-bit data value to be written to the RAM. 16 ports specify 16 data
values. The Address port specifies the memory address to write the data values.
Data type: UFix_32_0
Data width: 1 per port

ddr4_data_<PortNumber>_rd_32_block_1 / Data Read Inport to read a

32-bit data value from the RAM. 16 ports output 16 data values. The Address
port specifies the memory address to read the data values.
Data type: UFix_32_0
Data width: 1 per port

I/O mapping No external connection to the I/O connector of the board.

Overview of Inter-FPGA Communication (FPGA Programming Handcode Framework

Guide )

DDR4 32 Mode 2

Purpose To provide 32-bit read/write access to the DDR4 RAM using the memory access
mode 2.

Description The DS6602 FPGA Base Board provides a 4 GB DDR4 RAM that can be used by
the FPGA application.

The RAM interface always handles 512 bits at once. Therefore, the FPGA
application can read/write 16 x 32 bits data or 8 x 64 bits data within one
memory access.

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Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number is 9.

hcfw.IOProperties.Out.Fct(8).HcCustomName / Channel name Lets you

specify a custom name for the specified channel.

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

ddr4_busy_flag / Busy Inport to read a flag that indicates the state of the
DDR4 RAM:
§ 0: The DDR4 module is ready for new read/write operations.
§ 1: The DDR4 module is busy.
Data type: UFix_1_0

ddr4_data_en / Enable Outport to enable the RAM access:

§ 1: Data values are written to the RAM or read from the RAM.
§ 0: No read/write access.
Data type: UFix_1_0

ddr4_direction / Direction Outport to control the direction of data access:

§ 0: Write access
§ 1: Read access
Data type: UFix_1_0

ddr4_address_1_block_3 / Address A Outport to specify the first element in

the RAM for the read/write access of the Data Write A/Data Read A ports. The
memory is addressed 256 bit-wise to read/write 8 x 32-bit data values with the
same address.
Data type: UFix_27_0

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Value range: 0 … 134,217,727 (227-1)

Data width: 1

ddr4_address_2_block_3 / Address B Outport to specify the first element in

the RAM for the read/write access of the Data Write B/Data Read B ports. The
memory is addressed 256 bit-wise to read/write 8 x 32-bit data values with the
same address.
Data type: UFix_27_0
Value range: 0 … 134,217,727 (227-1)
Data width: 1

ddr4_rd_data_valid_1_block_3 / Data valid A Inport to read a flag that

indicates that the data values of the Data Read A ports are valid:
§ 0: The values are not valid.
§ 1: The values are valid. This value is set for one clock cycle. The data values
must be written within the same clock cycle.
Data type: UFix_1_0

ddr4_rd_data_valid_2_block_3 / Data valid B Inport to read a flag that

indicates that the data values of the Data Read B ports are valid:
§ 0: The values are not valid.
§ 1: The values are valid. This value is set for one clock cycle. The data values
must be written within the same clock cycle.
Data type: UFix_1_0

ddr4_data_1_<PortNumber>_wr_32_block_3 / Data Write A Outport to

specify a 32-bit data value to be written to the RAM. 8 ports specify 8 data
values at the same time.
The Address A port specifies the memory address to write the data values.
Data type: UFix_32_0
Data width: 1 per port

ddr4_data_2_<PortNumber>_wr_32_block_3 / Data Write B Outport to

specify a 32-bit data value to be written to the RAM. 8 ports specify 8 data
values at the same time.
The Address B port specifies the memory address to write the data values.
Data type: UFix_32_0
Data width: 1 per port

ddr4_data_1_<PortNumber>_rd_32_block_3 / Data Read A Inport to read

a 32-bit data value from the RAM. 8 ports output 8 data values at the same
time. The Address A port specifies the memory address to read the data values.
Data type: UFix_32_0
Data width: 1 per port

ddr4_data_2_<PortNumber>_rd_32_block_3 / Data Read B Inport to read

a 32-bit data value from the RAM. 8 ports output 8 data values at the same
time. The Address B port specifies the memory address to read the data values.
Data type: UFix_32_0
Data width: 1 per port

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I/O mapping No external connection to the I/O connector of the board.

Overview of Inter-FPGA Communication (FPGA Programming Handcode Framework

Guide )

DDR4 64 Mode 1

Purpose To provide 64-bit read/write access to the DDR4 RAM using the memory access
mode 1.

Description The DS6602 FPGA Base Board provides a 4 GB DDR4 RAM that can be used by
the FPGA application.

The RAM interface always handles 512 bits at once. Therefore, the FPGA
application can read/write 16 x 32 bits data or 8 x 64 bits data within one
memory access.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number is 10.

hcfw.IOProperties.Out.Fct(8).HcCustomName / Channel name Lets you

specify a custom name for the specified channel.

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

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Values:
§ 0: The RAM is not initialized.
§ 1: The RAM is initialized.

ddr4_busy_flag / Busy Inport to read a flag that indicates the state of the
DDR4 RAM:
§ 0: The DDR4 module is ready for new read/write operations.
§ 1: The DDR4 module is busy.
Data type: UFix_1_0

ddr4_data_en / Enable Outport to enable the RAM access:

§ 1: Data values are written to the RAM or read from the RAM.
§ 0: No read/write access.
Data type: UFix_1_0

ddr4_direction / Direction Outport to control the direction of data access:

§ 0: Write access
§ 1: Read access
Data type: UFix_1_0

ddr4_address_block_2 / Address Outport to specify the first element in

the RAM for the read/write access. The memory is addressed 512 bit-wise to
read/write 8 x 64-bit data values with the same address.
Data type: UFix_26_0
Value range: 0 … 67,108,863 (226-1)
Data width: 1

ddr4_rd_data_valid_block_2 / Data valid Inport to read a flag that

ddr4_data_<PortNumber>_wr_64_block_2 / Data Write Outport to

specify a 64-bit data value to be written to the RAM. 8 ports specify 8 data
values. The Address port specifies the memory address to write the data values.
Data type: UFix_64_0
Data width: 1 per port

ddr4_data_<PortNumber>_rd_64_block_2 / Data Read Inport to read a

64-bit data value from the RAM. 8 ports output 8 data values. The Address port
specifies the memory address to read the data values.

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Data type: UFix_64_0

Data width: 1 per port

I/O mapping No external connection to the I/O connector of the board.

Overview of Inter-FPGA Communication (FPGA Programming Handcode Framework

Guide )

DDR4 64 Mode 2

Purpose To provide 64-bit read/write access to the DDR4 RAM using the memory access
mode 2.

Description The DS6602 FPGA Base Board provides a 4 GB DDR4 RAM that can be used by
the FPGA application.

The RAM interface always handles 512 bits at once. Therefore, the FPGA
application can read/write 16 x 32 bits data or 8 x 64 bits data within one
memory access.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number is 11.

hcfw.IOProperties.Out.Fct(8).HcCustomName / Channel name Lets you

specify a custom name for the specified channel.

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

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Data type: UFix_1_0

Data width: 1
Values:
§ 0: The RAM is not initialized.
§ 1: The RAM is initialized.

ddr4_busy_flag / Busy Inport to read a flag that indicates the state of the
DDR4 RAM:
§ 0: The DDR4 module is ready for new read/write operations.
§ 1: The DDR4 module is busy.
Data type: UFix_1_0

ddr4_data_en / Enable Outport to enable the RAM access:

§ 1: Data values are written to the RAM or read from the RAM.
§ 0: No read/write access.
Data type: UFix_1_0

ddr4_direction / Direction Outport to control the direction of data access:

§ 0: Write access
§ 1: Read access
Data type: UFix_1_0

ddr4_address_1_block_4 / Address A Outport to specify the first element in

the RAM for the read/write access of the Data Write A/Data Read A ports. The
memory is addressed 256 bit-wise to read/write 4 x 64-bit data values with the
same address.
Data type: UFix_27_0
Value range: 0 … 134,217,727 (227-1)
Data width: 1

ddr4_address_2_block_4 / Address B Outport to specify the first element in

the RAM for the read/write access of the Data Write B/Data Read B ports. The
memory is addressed 256 bit-wise to read/write 4 x 64-bit data values with the
same address.
Data type: UFix_27_0
Value range: 0 … 134,217,727 (227-1)
Data width: 1

ddr4_rd_data_valid_1_block_4 / Data valid A Inport to read a flag that

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Data type: UFix_1_0

ddr4_rd_data_valid_2_block_4 / Data valid B Inport to read a flag that

ddr4_data_1_<PortNumber>_wr_64_block_4 / Data Write A Outport to

specify a 64-bit data value to be written to the RAM. 4 ports specify 4 data
values at the same time.
The Address A port specifies the memory address to write the data values.
Data type: UFix_64_0
Data width: 1 per port

ddr4_data_2_<PortNumber>_wr_64_block_4 / Data Write B Outport to

specify a 64-bit data value to be written to the RAM. 4 ports specify 4 data
values at the same time.
The Address B port specifies the memory address to write the data values.
Data type: UFix_64_0
Data width: 1 per port

ddr4_data_1_<PortNumber>_rd_64_block_4 / Data Read A Inport to read

a 64-bit data value from the RAM. 4 ports output 4 data values at the same
time. The Address A port specifies the memory address to read the data values.
Data type: UFix_64_0
Data width: 1 per port

ddr4_data_2_<PortNumber>_rd_64_block_4 / Data Read B Inport to read

a 64-bit data value from the RAM. 4 ports output 4 data values at the same
time. The Address B port specifies the memory address to read the data values.
Data type: UFix_64_0
Data width: 1 per port

I/O mapping No external connection to the I/O connector of the board.

Overview of Inter-FPGA Communication (FPGA Programming Handcode Framework

Guide )

I-FPGA In (IOCNET)

Purpose To read a 32-bit raw data value from an IOCNET buffer.

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I-FPGA In (IOCNET)

Description You can select I-FPGA In (IOCNET) I/O functions to implement an inter-FPGA
communication between FPGA base boards. There are 32 channels.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 11 … 42.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Note

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

Note

xmemf_inter_<ChannelNumber>_addr / Address Specifies a data value in

the IOCNET buffer to be read. The block requires one clock cycle to update the
value of the Data outport with the data value of the specified address.
Data type: UFix_16_0
Data width: 1
The maximum address range depends on the Buffer size parameter. The address
range with valid data values can be derived from the value of the Data Count
port.

xmemf_inter_<ChannelNumber>_count / Data Count Outputs the

number of elements in the current IOCNET buffer. You can use the value to
define the valid range for the Address port from 0 to (Data Count -1).
Data type: UFix_16_0

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Data width: 1
The maximum value range depends on the Buffer size parameter.

xmemf_inter_<ChannelNumber>_dout / Data Outputs a 32-bit raw data

value from the specified address of the IOCNET buffer.
Data type: UFix_32_0
Data width: 1

xmemf_inter_<ChannelNumber>_new_data / Data New Outputs a flag

I/O mapping No external connection to the I/O connector of the board.

Overview of the DS6602 FPGA Base Board Frameworks............................................................ 23

I-FPGA64 In (IOCNET)

Purpose To read a 64-bit raw data value from an IOCNET buffer.

Description According to the number of physical connections available on the DS6602 FPGA
Base Board, you can select the I-FPGA64 In (IOCNET) I/O functions. There are
32 channels.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 43 … 74.

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I-FPGA64 In (IOCNET)

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64 bits in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

Note

xmem64f_inter_<ChannelNumber>_addr / Address Specifies a data value

xmem64f_inter_<ChannelNumber>_count / Data Count Outputs the

xmem64f_inter_<ChannelNumber>_dout / Data Outputs a 64-bit raw

data value from the specified address of the IOCNET buffer.
Data type: UFix_64_0
Data width: 1

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xmem64f_inter_<ChannelNumber>_new_data / Data New Outputs a flag

I/O mapping No external connection to the I/O connector of the board.

Overview of the DS6602 FPGA Base Board Frameworks............................................................ 23

I-FPGA Out (IOCNET)

Purpose To write a 32-bit raw data value to an IOCNET buffer.

Description You can select I-FPGA Out (IOCNET) I/O functions to implement an inter-FPGA
communication between FPGA base boards. There are 32 channels.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 12 … 43.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

hcfw.PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(1).Init / Buffer
size Lets you specify the size of the IOCNET buffer in the range 1 … 1024.

Note

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

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I-FPGA Out (IOCNET)

The channel number can be specified in the range 00 … 31.

Note

You can transfer any data type with a bit width of up to 32 Bit via
inter-FPGA over IOCNET. To do this, you can reinterpret the data type
to UFix_32_0 and vice versa. Reinterpreting data types does not cost any
hardware or latency.
The range of the Data inport can be exceeded. The value of the inport is
then cast to the raw data format UFix_32_0.

xmemp_inter_<ChannelNumber>_din / Data Specifies a 32-bit raw data

value to be written to an IOCNET buffer.
Data type: UFix_32_0
Data width: 1

xmemp_inter_<ChannelNumber>_strobe / Enable Specifies the current

xmemp_inter_<ChannelNumber>_finished / Ready Explicitly specifies the

xmemp_inter_<ChannelNumber>_write / Send Triggers a data

xmemp_inter_<ChannelNumber>_overflow / Overflow Outputs a flag

that indicates that a buffer overflow occurred. An overflow occurs when the new
buffer is triggered for transmission and the old buffer was not sent completely.
Data type: UFix_1_0

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Data width: 1
Values:
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.

I/O mapping No external connection to the I/O connector of the board.

Overview of the DS6602 FPGA Base Board Frameworks............................................................ 23

I-FPGA64 Out (IOCNET)

Purpose To write a 64-bit raw data value to an IOCNET buffer.

Description You can select I-FPGA64 Out (IOCNET) I/O functions to implement an inter-
FPGA communication between FPGA base boards. There are 32 channels.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 44 … 75.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

hcfw.PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(1).Init / Buffer
size Lets you specify the size of the IOCNET buffer in the range 1 … 512.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64 bits in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

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I-FPGA64 Out (IOCNET)

The channel number can be specified in the range 00 … 31.

Note

You can transfer any data type with a bit width of up to 64 Bit via
inter-FPGA over IOCNET. To do this, you can reinterpret the data type
to UFix_64_0 and vice versa. Reinterpreting data types does not cost any
hardware or latency.
The range of the Data inport can be exceeded. The value of the inport is
then cast to the raw data format UFix_64_0.

xmem64p_inter_<ChannelNumber>_din / Data Specifies a 64-bit raw data

value to be written to an IOCNET buffer.
Data type: UFix_64_0
Data width: 1

xmem64p_inter_<ChannelNumber>_strobe / Enable Specifies the current

xmem64p_inter_<ChannelNumber>_finished / Ready Explicitly specifies

xmem64p_inter_<ChannelNumber>_write / Send Triggers a data

xmem64p_inter_<ChannelNumber>_overflow / Overflow Outputs a flag

that indicates that a buffer overflow occurred. An overflow occurs when the new
buffer is triggered for transmission and the old buffer was not sent completely.

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Data type: UFix_1_0

Data width: 1
Values:
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.

I/O mapping No external connection to the I/O connector of the board.

Overview of the DS6602 FPGA Base Board Frameworks............................................................ 23

Interrupt

Purpose To request a processor interrupt outside of the FPGA application.

Description The DS6602 FPGA Base Board provides 16 interrupt lines. An interrupt is
requested if the Int port is set to 1 for at least one clock cycle. If you set
the Int port to 0, the last interrupt is not released but saved. An interrupt is
edge-triggered.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 16.

IRQProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 15.

usr_<ChannelNumber>_interrupt / Int Provides the interrupt request line.

§ 0 to 1: Interrupt is requested (edge-triggered).
§ 0: No interrupt is requested. Last requested interrupt is saved.

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IOCNET Global Time

Overview of the DS6602 FPGA Base Board Frameworks............................................................ 23

IOCNET Global Time

Purpose To read the number of hardware ticks.

Description There is one digital input channel that is used for the IOCNET Global Time I/O
function.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 3.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

iocnet_glob_time/ IOCNET Global Time Outputs the number of hardware

Overview of the DS6602 FPGA Base Board Frameworks............................................................ 23

LED Out

Purpose To write a digital signal that controls the LED on the board.

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Description There is one digital output channel that is used for the LED Out I/O function.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 1.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

led_out / LED Out Controls the LED on the board.

Data type: UFix_1_0
§ 0: LED lights green.
§ 1: LED lights orange.

Overview of the DS6602 FPGA Base Board Frameworks............................................................ 23

Purpose To read data from an IOCNET register with a data width of 32 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 256.

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Register In

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(3).Init / Register
group ID Lets you specify a number in the range 1 … 63 to create
register groups. Registers that you specified with the same group ID are
sampled simultaneously within the FPGA application. The values therefore form a
consistent data group that is written to the IOCNET bus.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 255.

xreg_<ChannelNumber>_dout / Data Outputs a 32-bit data value to be

read from an IOCNET register. The data format depends on the related
parameter settings.

xreg_<ChannelNumber>_dout_wr / Data New Outputs a flag that

indicates the changes of the register status. If the flag changes from 0 to 1

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and then back to 0, the requested register contains a new value. The flag is set
to 1 only within one clock cycle.

Overview of the DS6602 FPGA Base Board Frameworks............................................................ 23

Register64 In

Purpose To read data from an IOCNET register with a data width of 64 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 289 … 544.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(1).Init / Binary
point position (or fraction width) Lets you specify the binary point position
or returns the fraction width of the Data outport depending on the format
selected in the Format setting (see below).
§ signed/unsigned
The values of the Data outport are in fixed-point format. You can specify the
binary point position of the 64-bit value in the range 0 … 64.
0 represents the lowest bit position, 64 the highest bit position.
64-bit fixed-point data types are converted to double, except the data
type without a binary point (binary point position = 0). Therefore, the fixed-
point resolution of fixed-point data types with a binary point (binary point
position > 0) is restricted to 53 bits.
§ floating-point
The values of the Data outport are in floating‑point format. The parameter
then provides the fraction width.

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Register64 In

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(2).Init /
Format Lets you specify the data format of the Data outport.
§ signed/unsigned
The values of the Data outport are in fixed‑point format with or without one
bit reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
§ floating‑point
The values of the Data outport are in floating‑point format.
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is provided by the Binary point position (or fraction
width) setting.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(3).Init / Register
group ID Lets you specify a number in the range 1 … 63 to create
register groups. Registers that you specified with the same group ID are
sampled simultaneously within the FPGA application. The values therefore form a
consistent data group that is written to the IOCNET bus.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 255.

xreg64_<ChannelNumber>_dout / Data Outputs a 64-bit data value to

be read from an IOCNET register. The data format depends on the related
parameter settings.

xreg64_<ChannelNumber>_dout_wr / Data New Outputs a flag that

indicates the changes of the register status. If the flag changes from 0 to 1
and then back to 0, the requested register contains a new value. The flag is set
to 1 only within one clock cycle.

Overview of the DS6602 FPGA Base Board Frameworks............................................................ 23

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Purpose To write data to an IOCNET register with a data width of 32 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 256.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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Register64 Out

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 255.

xreg_<ChannelNumber>_din / Data Specifies a 32-bit data value to be

written to an IOCNET register. The data format depends on the related
parameter settings.

Overview of the DS6602 FPGA Base Board Frameworks............................................................ 23

Register64 Out

Purpose To write data to an IOCNET register with a data width of 64 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 289 … 544.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init /
Register64 group ID Lets you specify a number in the range 1 … 63 to
create register groups. Registers that you specified with the same group ID
are read from the IOCNET bus sequentially and then provided to the FPGA
application simultaneously.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 255.

xreg64_<ChannelNumber>_din / Data Specifies a 64-bit data value to

be written to an IOCNET register. The data format depends on the related
parameter settings.

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Status In

Overview of the DS6602 FPGA Base Board Frameworks............................................................ 23

Status In

Purpose To read a digital signal that outputs the state of the FPGA initialization sequence.

Description There is one digital input channel that is used for the Status In I/O function.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 1.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

Overview of the DS6602 FPGA Base Board Frameworks............................................................ 23

Watchdog

Purpose To check if the processor application is alive.

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Description There is one digital input channel that is used for the Watchdog I/O function.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 75.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

iocnet_appl_term_status / Status Outputs a flag that indicates that the

processor application transmits a keep-alive signal within the specified timeout.
§ 0: The watchdog timer expires without a keep-alive signal being transmitted to
the FPGA application.
§ 1: The processor application is alive.
Data type: UFix_1_0

Overview of the DS6602 FPGA Base Board Frameworks............................................................ 23

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I/O Functions of the DS2655M1 I/O Module Framework

I/O Functions of the DS2655M1 I/O Module

Framework

Introduction The DS2655M1 I/O Module framework provides analog and digital I/O
functionality of SCALEXIO FPGA base board with at least one DS2655M1 Multi-
I/O Module.

Where to go from here Information in this section

Analog In.............................................................................................. 238

To read data from an analog input signal in the FPGA application.

Analog Out........................................................................................... 240

To write data to a analog output signal in the FPGA application.

Digital In................................................................................................ 242

To read data from a digital input signal in the FPGA application.

Digital InOut.......................................................................................... 243

To read/write data to a digital output signal in the FPGA application.

Digital Out............................................................................................. 246

To write data to a digital output signal in the FPGA application.

Information in other sections

Other frameworks that provide access to the FPGA functionality

of a SCALEXIO system:
I/O Functions of the DS2655 FPGA Base Board Framework.................... 125
The frameworks of the DS2655 FPGA Base Boards provide the standard
I/O functionality of the boards.

I/O Functions of the DS6601 FPGA Base Board Framework.................... 159

The DS6601 (KU035) FPGA Base Board framework of the DS6601 FPGA
Base Board provides the standard I/O functionality of the board.

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I/O Functions of the DS6602 FPGA Base Board Framework.................... 193

The DS6602 (KU15P) FPGA Base Board framework of the DS6602 FPGA
Base Board provides the standard I/O functionality of the board.

I/O Functions of the DS2655M2 I/O Module Framework........................ 249

The DS2655M2 I/O Module framework provides digital I/O functionality
of a SCALEXIO FPGA base board with at least one DS2655M2 Digital I/O
Module.

I/O Functions of the DS6651 Multi-I/O Module Framework.................... 269

The DS6651 Multi-I/O Module framework provides analog and digital I/O
functionality of a SCALEXIO FPGA base board with at least one DS6651
Multi-I/O Module.

I/O Functions of the Inter-FPGA Interface Framework............................. 313

The Inter-FPGA Interface framework provides access to the I/O module
slots of a SCALEXIO FPGA base board to implement an inter-FPGA
communication bus.

Analog In

Purpose To read data from an analog input signal in the FPGA application.

Description According to the number of physical connections available on the DS2655M1

Multi-I/O Module, you can select the Analog In I/O functions. There are five
analog input channels.

The module number can be specified in the range 1 … 5.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 11 … 15.

IOProperties.In.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).HcCustomName / Channel name Lets you
specify a custom name for the specified channel.

IOProperties.In.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).Parameter(3).Init / Input range Lets you
select the input range for all analog input channels.
§ 0: -30 V … +30 V
§ 1: -5 V … +5 V
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.In.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).Parameter(5).Init / Scaling Lets you select

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Analog In

the scaling of the output data. If you select mV, the valid output port range
corresponds to the specified input range in mV (-5000 … +5000 mV or
-30000 … +30000 mV). If you select the unscaled Bit value, the valid output
port range is -8192 … +8191, independently from the specified input range.
§ 0: mV
§ 1: Bit

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The channel number can be specified in the range 6 … 10.

m<ModuleNumber>_rx<ChannelNumber>_data00 / Data Outputs the

current results of analog input channel.
Data type: UFix_16_0
Update rate: 4 Msps

m<ModuleNumber>_rx<ChannelNumber>_ready_pulse / Data
New Outputs a flag that indicates the current status of the Data port.
The port is set to 1 for one clock cycle if the Data port provides new values.
New measured values from analog input channels of the same I/O module
are always provided synchronously. If analog inputs are read from different I/O
modules, the measured values are provided either synchronously or offset by two
clock cycles (16 ns). However, the sample time of the analog measurements is
synchronous on different I/O modules except for 8 ns.
If synchronous measured values from analog inputs of different I/O modules
are required, you can implement a logic to wait with the further processing of
analog values until the Data New ports flag new data within two clock cycles.
Data type: UFix_1_0
§ 0: No new values are available at the Data port.
§ 1: New values are available at the Data port.

m<Module_number>_tx<Channel_number>_data00 / Enable Controls

the data port. If set to 1 the ADC is in freerun mode.
Data type: UFix_1_0

I/O mapping The following I/O mapping is relevant if you use the DS2655M1 I/O Module
framework for analog input channels. The signals are available at the female
50-pin Sub-D I/O connector of the respective DS2655M1 Multi-I/O Module (x =
1 … 5).

Outport I/O Function Channel Number1) Channel Type Channel2) Connector Pin Signal
Number
Data 11 6 Analog In 3 11 10 Analog In - Ch: 11 [Mod: x]
12 7 12 27 Analog In - Ch: 12 [Mod: x]
13 8 13 44 Analog In - Ch: 13 [Mod: x]

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Outport I/O Function Channel Number1) Channel Type Channel2) Connector Pin Signal
Number
14 9 14 12 Analog In - Ch: 14 [Mod: x]
15 10 15 29 Analog In - Ch: 15 [Mod: x]
1) Setting in the handcode framework.
2) Hardware channel displayed in the Platform Manager, for example.

Configuring the Basic Functionality (FPGA) (ConfigurationDesk I/O Function

Implementation Guide )

References

Overview of the DS2655M1 I/O Module Framework................................................................. 25

Analog Out

Purpose To write data to a analog output signal in the FPGA application.

Description According to the number of physical connections available on the DS2655M1

Multi-I/O Module, you can select the Analog Out I/O functions. There are five
analog output channels.

The module number can be specified in the range 1 … 5.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 21 … 25.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).HcCustomName / Channel name Lets
you specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(5).Init / Scaling Lets you select
the scaling of the input data. If you select mV, the valid input port range is
‑10000 … +10000 mV. If you select the unscaled Bit value, the valid input port
range is ‑8192 … +8191 (14-bit D/A converter).
§ 0: mV
§ 1: Bit

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Analog Out

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The channel number can be specified in the range 1 … 5.

Note

The TX channels 1 … 5 are also used by the Digital InOut functions.

§ If you want to use the analog out channels with an optimal timing
behavior, do not use the related Digital InOut functions at a time.

m<ModuleNumber>_tx<ChannelNumber>_data00_14_0_14_0i /
Data Outputs a voltage signal in the specified range.
Data type: UFix_15_0
Update rate: 7.8125 Msps

m<ModuleNumber>_tx<ChannelNumber>_data00_16_0_16_0i /
Enable Controls the data port. If set to 1 the DAC is in freerun mode.
Data type: UFix_1_0

I/O mapping The following I/O mapping is relevant if you use the DS2655M1 I/O Module
framework for analog output channels. The signals are available at the female
50-pin Sub-D I/O connector of the respective DS2655M1 Multi-I/O Module (x =
1 … 5).

Outport I/O Function Channel Number1) Channel Type Channel2) Connector Pin Signal
Number
Data 21 1 Analog Out 5 16 14 Analog Out - Ch: 16 [Mod: x]
22 2 17 31 Analog Out - Ch: 17 [Mod: x]
23 3 18 48 Analog Out - Ch: 18 [Mod: x]
24 4 19 16 Analog Out - Ch: 19 [Mod: x]
25 5 20 33 Analog Out - Ch: 20 [Mod: x]
1) Setting in the handcode framework.
2) Hardware channel displayed in the Platform Manager, for example.

Configuring the Basic Functionality (FPGA) (ConfigurationDesk I/O Function

Implementation Guide )

References

Overview of the DS2655M1 I/O Module Framework................................................................. 25

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Digital In

Purpose To read data from a digital input signal in the FPGA application.

Description According to the number of physical connections available on the DS2655M1

Multi-I/O Module, you can select the Digital In I/O functions. There are 10 digital
input channels.

The module number can be specified in the range 1 … 5.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 10.

IOProperties.In.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).HcCustomName / Channel name Lets you
specify a custom name for the specified channel.

IOProperties.In.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).Parameter(4).Init / Threshold init
voltage Specifies the initial voltage value that is used for the threshold in
mV.
Data type: UFix_14_0
Range: 0 mV … 10500 mV in 100 mV steps
Update rate: 125 MHz
This electrical interface setting can be changed in ConfigurationDesk.

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The channel number can be specified in the range 1 … 10.

m<ModuleNumber>_rx<ChannelNumber>_trigger00 / Data Outputs the

current results of digital input channel.
§ 0: Input voltage of the channel is below the threshold voltage of a high-low
transition.
§ 1: Input voltage of the channel is higher than or equal to the threshold voltage
of a low-high transition.
Data type: UFix_1_0
Update rate: 125 MHz

I/O mapping The following I/O mapping is relevant if you use the DS2655M1 I/O Module
framework for digital input channels. The signals are available at the female
50-pin Sub-D I/O connector of the respective DS2655M1 Multi-I/O Module (x =
1 … 5).

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Digital InOut

Outport I/O Function Number Channel Number1) Channel Type Channel2) Connector Pin Signal
Data 1 1 Digital In/Out 2 1 2 Digital In - Ch: 1 [Mod: x]
2 2 2 19 Digital In - Ch: 2 [Mod: x]
3 3 3 36 Digital In - Ch: 3 [Mod: x]
4 4 4 4 Digital In - Ch: 4 [Mod: x]
5 5 5 21 Digital In - Ch: 5 [Mod: x]
6 6 6 6 Digital In - Ch: 6 [Mod: x]
7 7 7 23 Digital In - Ch: 7 [Mod: x]
8 8 8 40 Digital In - Ch: 8 [Mod: x]
9 9 9 8 Digital In - Ch: 9 [Mod: x]
10 10 10 25 Digital In - Ch: 10 [Mod: x]
1) Setting in the handcode framework.
2) Hardware channel displayed in the Platform Manager, for example.

Configuring the Basic Functionality (FPGA) (ConfigurationDesk I/O Function

Implementation Guide )

References

Overview of the DS2655M1 I/O Module Framework................................................................. 25

Digital InOut

Purpose To read/write data to a digital output signal in the FPGA application. The Data
direction port lets you specify the data direction during run time.

Description According to the number of physical connections available on the DS2655M1

Multi-I/O Module, you can select the Digital InOut I/O functions. There are 10
bidirectional digital channels.

The module number can be specified in the range 1 … 5.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 11 … 20.

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IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).HcCustomName / Channel name Lets
you specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(4).Init / Output
mode Specifies the output mode.
§ 1: LowSide switch
To drive loads which are connected to VCC.
§ 2: HighSide switch
To drive loads which are connected to GND.
§ 3: Push/Pull
To switch the signal between two different potentials (for example, VCC and
GND).
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(6).Init / Drive config Lets you
enable/disable the termination of the signal line by a serial resistor.
§ 0: 68 Ohm terminated
The signal line is terminated with 68 Ω.
§ 1: The termination is disabled.
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(8).Init / High supply Lets you
select the voltage for the high side switch.
§ 0: 5 V
§ 1: 3.3 V
This electrical interface setting can be changed in ConfigurationDesk.

Note

If you use a Digital InOut channel, the applicable threshold voltage for the
digital input channel is less than or equal to the specified high supply.
To apply the maximum input voltage range, you have to use a Digital In
channel.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(10).Init / Digital In threshold
init voltage Lets you set the initial threshold voltage for a digital input signal
in the range of 0 mV … 10500 mV in steps of 100 mV. This electrical interface
setting can be changed in ConfigurationDesk.

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The channel number can be specified in the range 1 … 10.

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Digital InOut

m<ModuleNumber>_tx<ChannelNumber>_data01_0_0_1_1i / Data
direction Specifies the direction of the digital signal.
§ 0: Digital in
§ 1: Digital out
Data type: UFix_1_0
Update rate: 125 MHz

m<ModuleNumber>_rx<ChannelNumber>_trigger00 / Inport:
Data Outputs the current results of digital input channel.
§ 0: Input voltage of the channel is below the threshold voltage of a high-low
transition.
§ 1: Input voltage of the channel is higher than or equal to the threshold voltage
of a low-high transition.
Data type: UFix_1_0
Update rate: 125 MHz

m<ModuleNumber>_tx<ChannelNumber>_data01_0_0_0_0i / Outport:
Data Outputs a signal in the specified range. If driven with 0, the hardware
output is 0 V. If driven with 1, the hardware output is 3.3 V or 5 V according to
the specified high supply voltage.
Data type: UFix_1_0
Update rate: 15.625 MHz

Outport I/O Function Channel Channel Type Channel2) Connector Pin Signal
Number Number1)
Data 11 1 Digital In/Out 2 1 2 Digital InOut - Ch: 1 [Mod: x]
12 2 2 19 Digital InOut - Ch: 2 [Mod: x]
13 3 3 36 Digital InOut - Ch: 3 [Mod: x]
14 4 4 4 Digital InOut - Ch: 4 [Mod: x]
15 5 5 21 Digital InOut - Ch: 5 [Mod: x]
16 6 6 6 Digital InOut - Ch: 6 [Mod: x]
17 7 7 23 Digital InOut - Ch: 7 [Mod: x]
18 8 8 40 Digital InOut - Ch: 8 [Mod: x]
19 9 9 8 Digital InOut - Ch: 9 [Mod: x]
20 10 10 25 Digital InOut - Ch: 10 [Mod: x]
1) Setting in the handcode framework.
2) Hardware channel displayed in the Platform Manager, for example.

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I/O Functions of the DS2655M1 I/O Module Framework

Configuring the Basic Functionality (FPGA) (ConfigurationDesk I/O Function

Implementation Guide )

References

Overview of the DS2655M1 I/O Module Framework................................................................. 25

Digital Out

Purpose To write data to a digital output signal in the FPGA application.

Description According to the number of physical connections available on the DS2655M1

Multi-I/O Module, you can select the Digital Out I/O functions. There are 10
digital output channels.

The module number can be specified in the range 1 … 5.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 10.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).HcCustomName / Channel name Lets
you specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(3).Init / Output
mode Specifies the output mode.
§ 17: LowSide switch
To drive loads that are connected to VCC.
§ 18: HighSide switch
To drive loads that are connected to GND.
§ 19: Push/Pull
To switch the signal between two different potentials (for example, VCC and
GND).
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(5).Init / Drive config Lets you
enable/disable the termination of the signal line by a serial resistor.
§ 0: The signal line is terminated with 68 Ω.
§ 1: The termination is disabled.

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Digital Out

This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(7).Init / High supply Lets you
select the voltage for the high side switch.
§ 0: 5 V
§ 1: 3.3 V
This electrical interface setting can be changed in ConfigurationDesk.

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The channel number can be specified in the range 1 … 10.

m<ModuleNumber>_tx<ChannelNumber>_trigger00 / Data Outputs a

signal in the specified range. If driven with 0, the hardware output is 0 V. If
driven with 1, the hardware output is 3.3 V or 5 V according to the specified
high supply voltage.
Data type: UFix_1_0
Update rate: 125 MHz

I/O mapping The following I/O mapping is relevant if you use the DS2655M1 I/O Module
framework for digital output channels. The signals are available at the female
50-pin Sub-D I/O connector of the respective DS2655M1 Multi-I/O Module (x =
1 … 5).

Outport I/O Function Channel Number1) Channel Type Channel2) Connector Pin Signal
Number
Data 1 1 Digital In/Out 2 1 2 Digital Out - Ch: 1 [Mod: x]
2 2 2 19 Digital Out - Ch: 2 [Mod: x]
3 3 3 36 Digital Out - Ch: 3 [Mod: x]
4 4 4 4 Digital Out - Ch: 4 [Mod: x]
5 5 5 21 Digital Out - Ch: 5 [Mod: x]
6 6 6 6 Digital Out - Ch: 6 [Mod: x]
7 7 7 23 Digital Out - Ch: 7 [Mod: x]
8 8 8 40 Digital Out - Ch: 8 [Mod: x]
9 9 9 8 Digital Out - Ch: 9 [Mod: x]
10 10 10 25 Digital Out - Ch: 10 [Mod: x]
1) Setting in the handcode framework.
2) Hardware channel displayed in the Platform Manager, for example.

Configuring the Basic Functionality (FPGA) (ConfigurationDesk I/O Function

Implementation Guide )

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I/O Functions of the DS2655M1 I/O Module Framework

References

Overview of the DS2655M1 I/O Module Framework................................................................. 25

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I/O Functions of the DS2655M2 I/O Module Framework

I/O Functions of the DS2655M2 I/O Module

Framework

Introduction The DS2655M2 I/O Module framework provides digital I/O functionality of a
SCALEXIO FPGA base board with at least one DS2655M2 Digital I/O Module.

Where to go from here Information in this section

Digital In................................................................................................ 250

To read data from a digital input signal in the FPGA application.

Digital Out............................................................................................. 253

To write data to a digital output signal in the FPGA application.

Digital Out-Z.......................................................................................... 255

To write data to a digital output signal in the FPGA application or to
switch the output to a high-impedance state (tri-state).

RS232 Rx............................................................................................... 258

To receive data values from a RS232 network.

RS232 Tx............................................................................................... 259

To transmit data values to a RS232 network.

RS485 Rx............................................................................................... 261

To receive data values from a RS485 network in simplex mode.

RS485 RxTx........................................................................................... 263

To implement communication via a RS485 network in half-duplex mode.

RS485 Tx............................................................................................... 265

To transmit data values to a RS485 network in simplex mode.

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Information in other sections

Other frameworks that provide access to the FPGA functionality

of a SCALEXIO system:
I/O Functions of the DS2655 FPGA Base Board Framework.................... 125
The frameworks of the DS2655 FPGA Base Boards provide the standard
I/O functionality of the boards.

I/O Functions of the DS6601 FPGA Base Board Framework.................... 159

The DS6601 (KU035) FPGA Base Board framework of the DS6601 FPGA
Base Board provides the standard I/O functionality of the board.

I/O Functions of the DS6602 FPGA Base Board Framework.................... 193

The DS6602 (KU15P) FPGA Base Board framework of the DS6602 FPGA
Base Board provides the standard I/O functionality of the board.

I/O Functions of the DS2655M1 I/O Module Framework........................ 237

The DS2655M1 I/O Module framework provides analog and digital I/O
functionality of SCALEXIO FPGA base board with at least one DS2655M1
Multi-I/O Module.

I/O Functions of the DS6651 Multi-I/O Module Framework.................... 269

The DS6651 Multi-I/O Module framework provides analog and digital I/O
functionality of a SCALEXIO FPGA base board with at least one DS6651
Multi-I/O Module.

I/O Functions of the Inter-FPGA Interface Framework............................. 313

The Inter-FPGA Interface framework provides access to the I/O module
slots of a SCALEXIO FPGA base board to implement an inter-FPGA
communication bus.

Digital In

Purpose To read data from a digital input signal in the FPGA application.

Description According to the number of physical connections available on the DS2655M2

Digital I/O Module, you can select the Digital In I/O functions. There are up to
32 digital input channels.

The module number can be specified in the range 1 … 5.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 32.

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Digital In

IOProperties.In.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).HcCustomName / Channel name Lets you
specify a custom name for the specified channel.

IOProperties.In.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).Parameter(9).Init / Threshold init
voltage Specifies the initial voltage value that is used for the threshold in
mV.
Data type: UFix_14_0
Range: 0 mV … 10500 mV in 100 mV steps
Update rate: 125 MHz
This electrical interface setting can be changed in ConfigurationDesk.

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The channel number can be specified in the range 1 … 32.

m<ModuleNumber>_io2raw_<ChannelNumber>_
<ChannelNumber>_<ChannelNumber>_<ChannelNumber>i /
Data Outputs the current results of digital input channel.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Input voltage of the channel is below the threshold voltage of a high-low
transition.
§ 1: Input voltage of the channel is higher than or equal to the threshold voltage
of a low-high transition.
Update rate: 125 MHz
For information on the electrical characteristics of the DS2655M2 Digital I/O
Module, refer to Data Sheet of the DS2655M2 Digital I/O Module (SCALEXIO
Hardware Installation and Configuration ).

I/O mapping The following I/O mapping is relevant if you use the DS2655M2 I/O Module
framework for Digital In channels. The signals are available at the female 50-pin
Sub-D I/O connector of the respective DS2655M2 Digital I/O Module.

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I/O Functions of the DS2655M2 I/O Module Framework

Configuring the Basic Functionality (FPGA) (ConfigurationDesk I/O Function

Implementation Guide )

References

Overview of the DS2655M2 I/O Module Framework................................................................. 27

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Digital Out

Digital Out

Purpose To write data to a digital output signal in the FPGA application.

Description According to the number of physical connections available on the DS2655M2

Digital I/O Module, you can select the Digital Out I/O functions. There are up to
32 digital output channels.

The module number can be specified in the range 1 … 5.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 32.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).HcCustomName / Channel name Lets
you specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(7).Init / Output
mode Specifies the output mode.
§ 5: LowSide switch
To drive loads which are connected to VCC.
§ 6: HighSide switch
To drive loads which are connected to GND.
§ 7: Push/Pull
To switch the signal between two different potentials (for example, VCC and
GND).
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(9).Init / Drive config Lets you
enable/disable the termination of the signal line by a serial resistor.
§ 0: The signal line is terminated with 68 Ω.
§ 1: The termination is disabled.
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(11).Init / High supply Lets you
select the voltage for the high side switch.
§ 0: 5 V
§ 1: 3.3 V
This electrical interface setting can be changed in ConfigurationDesk.

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

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The channel number can be specified in the range 1 … 32.

m<ModuleNumber>_raw2io_<ChannelNumber>_
<ChannelNumber>_<ChannelNumber>_<ChannelNumber>i /
Data Outputs a signal in the specified range.
To set the voltage level, use the High supply.
Data Type: UFix_1_0
Data width: 1
If driven with 0, the hardware outputs a low-level signal. If driven with 1, the
hardware outputs a high-level signal.
Update rate: 125 MHz
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit
by using only the lowest bit.

Note

The frequency that can be generated is smaller than the update rate.
For information on the electrical characteristics of the DS2655M2 Digital
I/O Module, refer to Data Sheet of the DS2655M2 Digital I/O Module
(SCALEXIO Hardware Installation and Configuration ).

I/O mapping The following I/O mapping is relevant if you use the DS2655M2 I/O Module
framework for digital output channels. The signals are available at the female
50-pin Sub-D I/O connector of the respective DS2655M2 Digital I/O Module.

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Digital Out-Z

Configuring the Basic Functionality (FPGA) (ConfigurationDesk I/O Function

Implementation Guide )

References

Overview of the DS2655M2 I/O Module Framework................................................................. 27

Digital Out-Z

Purpose To write data to a digital output signal in the FPGA application or to switch the
output to a high-impedance state (tri-state).

Description According to the number of physical connections available on the DS2655M2

Digital I/O Module, you can select the Digital Out-Z I/O functions. There are up
to 16 digital output channels.

The module number can be specified in the range 1 … 5.

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Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 33 … 48.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).HcCustomName / Channel name Lets
you specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(14).Init / Drive config Lets
you enable/disable the termination of the signal line by a serial resistor.
§ 0: The signal line is terminated with 68 Ω.
§ 1: The termination is disabled.
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(16).Init / High supply Lets you
select the voltage for the high side switch.
§ 0: 5 V
§ 1: 3.3 V
This electrical interface setting can be changed in ConfigurationDesk.

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The channel number can be specified in the range 1, 3, 5, … ,31.

m<ModuleNumber>_raw2io_<ChannelNumber>_
<ChannelNumber>_<ChannelNumber>_<ChannelNumber>i /
Data Outputs a signal in the specified range if the Enable port is set to 1.
To set the voltage level, use the High Supply parameter .
Data Type: UFix_1_0
Data width: 1
If driven with 0, the hardware outputs a low-level signal. If driven with 1, the
hardware outputs a high-level signal.
Update rate: 125 MHz
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit
by using only the lowest bit.

Note

m<ModuleNumber>_raw2io_<ChannelNumber+1>_
<ChannelNumber+1>_<ChannelNumber+1>_ <ChannelNumber+1>i /

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Digital Out-Z

Enable Enables the output of data values and disables the high-impedance
state.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The output is set to the high-impedance state.
§ 1: The output is enabled and outputs the data values of the Data inport.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit
by using only the lowest bit.

Inport Channel Type Channel Connector Pin Signal

Data Digital In/Out 4 1 18 Dig Out-Z (Ch. 1-2)
2 2 Do not use
Digital In/Out 2 3 35 Dig Out-Z (Ch. 3-4)
4 19 Do not use
Digital In/Out 4 5 20 Dig Out-Z (Ch. 5-6)
6 4 Do not use
Digital In/Out 2 7 37 Dig Out-Z (Ch. 7-8)
8 21 Do not use
Digital In/Out 4 9 22 Dig Out-Z (Ch. 9-10)
10 6 Do not use
Digital In/Out 2 11 39 Dig Out-Z (Ch. 11-12)
12 23 Do not use
Digital In/Out 4 13 24 Dig Out-Z (Ch. 13-14)
14 8 Do not use
Digital In/Out 2 15 41 Dig Out-Z (Ch. 15-16)
16 25 Do not use
Digital In/Out 4 17 26 Dig Out-Z (Ch. 17-18)
18 10 Do not use
Digital In/Out 2 19 43 Dig Out-Z (Ch. 19-20)
20 27 Do not use
Digital In/Out 4 21 28 Dig Out-Z (Ch. 21-22)
22 12 Do not use
Digital In/Out 2 23 45 Dig Out-Z (Ch. 23-24)
24 29 Do not use
Digital In/Out 4 25 30 Dig Out-Z (Ch. 25-26)
26 14 Do not use
Digital In/Out 2 27 47 Dig Out-Z (Ch. 27-28)

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Inport Channel Type Channel Connector Pin Signal

28 31 Do not use
Digital In/Out 4 29 32 Dig Out-Z (Ch. 29-30)
30 16 Do not use
Digital In/Out 2 31 49 Dig Out-Z (Ch. 31-32)
32 33 Do not use

Configuring the Basic Functionality (FPGA) (ConfigurationDesk I/O Function

Implementation Guide )

References

Overview of the DS2655M2 I/O Module Framework................................................................. 27

RS232 Rx

Purpose To receive data values from a RS232 network.

Description According to the number of physical connections available on the DS2655M2

Digital I/O Module, you can select the RS232 Rx I/O functions. There are up to 8
channels.

The module number can be specified in the range 1 … 5.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 33 … 40.

IOProperties.In.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).HcCustomName / Channel name Lets you
specify a custom name for the specified channel.

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

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RS232 Tx

The channel number can be specified in the range 2, 6, 10, … ,30.

m<ModuleNumber>_io2raw_<ChannelNumber>_
<ChannelNumber>_<ChannelNumber>_<ChannelNumber>i /
Data Outputs the data received from the RS232 network.
Data type: UFix_1_0
Data width: 1
Range:
§ 0: The input voltage level is positive (≥ 0 V).
§ 1: The input voltage level is negative (< 0 V).
For information on the electrical characteristics of the DS2655M2 Digital I/O
Module, refer to Data Sheet of the DS2655M2 Digital I/O Module (SCALEXIO
Hardware Installation and Configuration ).

I/O mapping The following I/O mapping is relevant if you use the DS2655M2 I/O Module
framework for RS232 Rx channels. The signals are available at the female 50-pin
Sub-D I/O connector of the respective DS2655M2 Digital I/O Module.

Overview of the DS2655M2 I/O Module Framework................................................................. 27

RS232 Tx

Purpose To transmit data values to a RS232 network.

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Description According to the number of physical connections available on the DS2655M2

Digital I/O Module, you can select the RS232 Tx I/O functions. There are up to 8
channels.

The module number can be specified in the range 1 … 5.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 49 … 56.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).HcCustomName / Channel name Lets you
specify a custom name for the specified channel.

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The channel number can be specified in the range 1 … 32.

m<ModuleNumber>_raw2io_<ChannelNumber>_
<ChannelNumber>_<ChannelNumber>_<ChannelNumber>i /
Data Outputs the data to be send to the RS232 Tx channel.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The output voltage level is +5.5 V.
§ 1: The output voltage level is –5.5 V.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit
by using only the lowest bit.
For information on the electrical characteristics of the DS2655M2 Digital I/O
Module, refer to Data Sheet of the DS2655M2 Digital I/O Module (SCALEXIO
Hardware Installation and Configuration ).

Outport Channel Type Channel Connector Pin Signal

Data Digital In/Out 4 1 18 TX (Ch. 1)
5 20 TX (Ch. 5)
9 22 TX (Ch. 9)
13 24 TX (Ch. 13)
17 26 TX (Ch. 17)
21 28 TX (Ch. 21)

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RS485 Rx

Outport Channel Type Channel Connector Pin Signal

25 30 TX (Ch. 25)
29 32 TX (Ch. 29)

Overview of the DS2655M2 I/O Module Framework................................................................. 27

RS485 Rx

Purpose To receive data values from a RS485 network in simplex mode.

Description According to the number of physical connections available on the DS2655M2

Digital I/O Module, you can select the RS485 Rx I/O functions. There are up to 8
channels.

The module number can be specified in the range 1 … 5.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 41 … 48.

IOProperties.In.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).HcCustomName / Channel name Lets you
specify a custom name for the specified channel.

IOProperties.In.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(7).Init / RS485
Termination Lets you enable/disable the termination of the signal line by a
serial resistor.
§ 0: The termination is disabled.
§ 1: The signal line is terminated by an internal 120 Ω resistor.
This electrical interface setting can be changed in ConfigurationDesk.

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The channel number can be specified in the range 1, 5, 9, ... , 29.

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m<ModuleNumber>_io2raw_<ChannelNumber>_
<ChannelNumber>_<ChannelNumber>_<ChannelNumber>i /
Data Outputs the data received from the RS485 network.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The input voltage level is negative (< 0 V).
§ 1: The input voltage level is positive (≥ 0 V).

I/O mapping The following I/O mapping is relevant if you use the DS2655M2 I/O Module
framework for RS485 Rx channels. The signals are available at the female 50-pin
Sub-D I/O connector of the respective DS2655M2 Digital I/O Module.

Configuring the Basic Functionality (FPGA) (ConfigurationDesk I/O Function

Implementation Guide )

References

Overview of the DS2655M2 I/O Module Framework................................................................. 27

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RS485 RxTx

RS485 RxTx

Purpose To implement communication via a RS485 network in half-duplex mode.

Description According to the number of physical connections available on the DS2655M2

Digital I/O Module, you can select the RS485 RxTx I/O functions. There are up to
8 channels.

The module number can be specified in the range 1 … 5.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 41 … 48.

IOProperties.In.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).HcCustomName / Channel name Lets you
specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(17).Init / RS485
Termination Lets you enable/disable the termination of the signal line by a
serial resistor.
§ 0: The termination is disabled.
§ 1: The signal line is terminated by an internal 120 Ω resistor.
This electrical interface setting can be changed in ConfigurationDesk.

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The channel number can be specified in the range 1, 5, 9, … , 29.

m<ModuleNumber+1>_raw2io_<ChannelNumber+1>_
<ChannelNumber+1>_<ChannelNumber+1>_ <ChannelNumber+1>i /
Tx Data Outputs the data to be send to the RS485 network if the Tx Enable
port is set to 1.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The output voltage level is –5.5 V.
§ 1: The output voltage level is +5.5 V.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit
by using only the lowest bit.

m<ModuleNumber>_raw2io_<ChannelNumber+2>_
<ChannelNumber+2>_<ChannelNumber+2>_ <ChannelNumber+2>i /
Tx Enable Enables the output of data values to the RS485 network and
disables the high-impedance state.

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Data type: UFix_1_0

Data width: 1
Values:
§ 0: The output is set to the high-impedance state (tri-state). The Rx Data
outport can output received data from the RS485 network.
§ 1: The output is enabled and transmits the data values of the Tx Data inport.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit
by using only the lowest bit.

m<ModuleNumber>_io2raw_<ChannelNumber>_
<ChannelNumber>_<ChannelNumber>_<ChannelNumber>i /
Rx Data Outputs the data that is received from the RS485 network if the
Tx Enable inport is set to 0.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The input voltage level is negative (< 0 V).
§ 1: The input voltage level is positive (≥ 0 V).

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RS485 Tx

Port Channel Type Channel Connector Pin Signal

26 14 RxTx+ (Ch. 25-27)
Digital In/Out 2 27 47 Do not use
Digital In/Out 4 29 32 RxTx– (Ch. 29-31)
30 16 RxTx+ (Ch. 29-31)
Digital In/Out 2 31 49 Do not use
1) The RS485 RxTx network is a half-duplex network.

Configuring the Basic Functionality (FPGA) (ConfigurationDesk I/O Function

Implementation Guide )

References

Overview of the DS2655M2 I/O Module Framework................................................................. 27

RS485 Tx

Purpose To transmit data values to a RS485 network in simplex mode.

Description According to the number of physical connections available on the DS2655M2

Digital I/O Module, you can select the RS485 Tx I/O functions. There are up to 8
channels.

The module number can be specified in the range 1 … 5.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 57 … 64.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).HcCustomName / Channel name Lets you
specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(14).Init / RS485

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Termination Lets you enable/disable the termination of the signal line by a

serial resistor.
§ 0: The termination is disabled.
§ 1: The signal line is terminated by an internal 120 Ω resistor.
This electrical interface setting can be changed in ConfigurationDesk.

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The channel number can be specified in the range 1, 5, 9, … , 29.

m<ModuleNumber>_raw2io_<ChannelNumber>_
<ChannelNumber>_<ChannelNumber>_<ChannelNumber>i /
Data Outputs the data to the RS485 network if the Enable port is set to 1.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The output voltage level is –5.5 V.
§ 1: The output voltage level is +5.5 V.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit
by using only the lowest bit.

m<ModuleNumber>_raw2io_<ChannelNumber+1>_
<ChannelNumber+1>_<ChannelNumber+1>_ <ChannelNumber+1>i /
Data Enables the output of data values to the RS485 network.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The output is disabled.
The output voltage level is 0 V. The output does not support an high-
impedance state (tri-state).
§ 1: The output is enabled and transmits the data values of the Data inport.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit
by using only the lowest bit.

Outport Channel Type Channel Connector Pin Signal

Data Digital In/Out 4 1 18 Tx– (1-2)
2 2 Tx+ (1-2)
5 20 Tx– (5-6)
6 4 Tx+ (5-6)
9 22 Tx– (9-10)
10 6 Tx+ (9-10)

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RS485 Tx

Configuring the Basic Functionality (FPGA) (ConfigurationDesk I/O Function

Implementation Guide )

References

Overview of the DS2655M2 I/O Module Framework................................................................. 27

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I/O Functions of the DS6651 Multi-I/O Module Framework

I/O Functions of the DS6651 Multi-I/O Module

Framework

Introduction The DS6651 Multi-I/O Module framework provides analog and digital I/O
functionality of a SCALEXIO FPGA base board with at least one DS6651 Multi-I/O
Module.

Where to go from here Information in this section

Analog In.............................................................................................. 270

To read data from an analog input signal in the FPGA application.

Analog In-L............................................................................................ 273

To measure data of the 16-bit A/D converter.

Analog Out........................................................................................... 276

To write data to an analog output signal in the FPGA application.

Analog Out-T........................................................................................ 278

To write data to an analog output signal in the FPGA application.

Digital In................................................................................................ 279

To read data from a digital input signal in the FPGA application.

Digital In/Out-Z...................................................................................... 281

To read or write data to or from a digital signal in the FPGA application,
or to switch the output to a high-impedance state (tristate).

Digital Out............................................................................................. 284

To write data to a digital output signal in the FPGA application.

Digital Out-Z.......................................................................................... 287

To write data to a digital output signal in the FPGA application or to
switch the output to a high-impedance state (tristate).

RS485 Rx............................................................................................... 289

To implement communication via a RS485 network in simplex mode.

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RS485 Rx/Tx.......................................................................................... 291

To implement communication via a RS485 network in half-duplex mode.

RS485 Tx............................................................................................... 294

To implement communication via a RS485 network in simplex mode.

Trigger................................................................................................... 296
To trigger the analog measurement.

Information in other sections

Other frameworks that provide access to the FPGA functionality

of a SCALEXIO system:
I/O Functions of the DS2655 FPGA Base Board Framework.................... 125
The frameworks of the DS2655 FPGA Base Boards provide the standard
I/O functionality of the boards.

I/O Functions of the DS6601 FPGA Base Board Framework.................... 159

The DS6601 (KU035) FPGA Base Board framework of the DS6601 FPGA
Base Board provides the standard I/O functionality of the board.

I/O Functions of the DS6602 FPGA Base Board Framework.................... 193

The DS6602 (KU15P) FPGA Base Board framework of the DS6602 FPGA
Base Board provides the standard I/O functionality of the board.

I/O Functions of the DS2655M1 I/O Module Framework........................ 237

The DS2655M1 I/O Module framework provides analog and digital I/O
functionality of SCALEXIO FPGA base board with at least one DS2655M1
Multi-I/O Module.

I/O Functions of the DS2655M2 I/O Module Framework........................ 249

The DS2655M2 I/O Module framework provides digital I/O functionality
of a SCALEXIO FPGA base board with at least one DS2655M2 Digital I/O
Module.

I/O Functions of the Inter-FPGA Interface Framework............................. 313

The Inter-FPGA Interface framework provides access to the I/O module
slots of a SCALEXIO FPGA base board to implement an inter-FPGA
communication bus.

Analog In

Purpose To read data from an analog input signal in the FPGA application.

Description According to the number of physical connections available on the DS6651 Multi-
I/O Module, you can select the Analog In I/O functions. There are four channels.

The module number can be specified in the range 1 … 5.

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Analog In

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 25 … 28.

IOProperties.In.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).HcCustomName / Channel name Lets you
specify a custom name for the specified channel.

IOProperties.In.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).Parameter(2).Init / Input range Lets you
select the input voltage range that can be converted from analog to digital for
the chosen ADC channel.
§ 0: ‑60 V ... +60 V
§ 1: ‑10 V ... +10 V
§ 2: ‑5 V ... +5 V
§ 3: ‑1 V ... +1 V
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.In.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).Parameter(4).Init / Scaling Lets you select
whether the I/O function scales the measuring results of the A/D converter to
mV.
§ 0: mV
To output the measuring results in mV.
The valid value range corresponds to the settings of the Input range
parameter in mV.
The default data type is Fix_22_5 to provide the precision of the A/D converter
when using the ±1 V input voltage range.
§ 1: Bit
To output the raw measuring results as a signed Bit value.
Value range: -32,768 … +32,767.
Data type: Fix_22_5

Tip

If you select Bit, you can reduce the complexity of the logic by using only
16 bits of the raw measurement result due to the 16-bit resolution of the
A/D converter.

IOProperties.In.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).Parameter(6).Init / Trigger mode Lets you
select the trigger mode and source for sampling the analog input voltage.
§ 15: Free running
The ADC samples the input voltage with a fixed sample period that is set by
the Sample period parameter.
§ 258: Trigger 1
The ADC samples the input voltage with each trigger impulse provided by a
Trigger I/O function. Refer to Trigger on page 296.

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§ 274: Trigger 2
The ADC samples the input voltage with each trigger impulse provided by a
Trigger I/O function. Refer to Trigger on page 296.
§ Digital In:
§ 16 · (x-1) + 2: Digital In, <x>, rising edge, 8 ns filter
§ 16 · (x-1) + 1026: Digital In, <x>, rising edge, no filter
§ 16 · (x-1) + 1538: Digital In, <x>, falling edge, 8 ns filter
§ 16 · (x-1) + 514: Digital In, <x>, falling edge, no filter
The selected digital input channel triggers the sampling of the analog input
signal:
§ <x>: Indicates the channel number of the digital input channel.
§ Rising edge: A 0 to 1 transition of a digital input signal triggers the ADC.
§ Falling edge: A 1 to 0 transition of a digital input signal triggers the ADC.
§ 8 ns filter: The digital signal is filtered by a digital low-pass filter with a time
constant of 8 ns.

IOProperties.In.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).Parameter(8).Init / Sample period Lets you
specify the sample period of the ADC in the free running mode.
Sample period = nselected · 8 ns
With the value range 25 ≤ nselected ≤ 3,750,000,000.
The resulting sample period is in the range 200 ns ... 30 s.

Ports You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The channel number can be specified in the range 23 … 26.

m<ModuleNumber>_rx<ChannelNumber>_data00 / Data Outputs the

measured values of the 16-bit A/D converter.
Data type: Fix_22_5
Data width: 1
Value range: Depends on the setting of the Scaling parameter.

m<ModuleNumber>_rx<ChannelNumber>_ready_pulse / Data
New Outputs a flag that indicates the current status of the Data port.
New measured values from analog input channels of the same I/O module
are always provided synchronously. If analog inputs are read from different I/O
modules, the measured values are provided either synchronously or offset by two
clock cycles (16 ns). However, the sample time of the analog measurements is
synchronous on different I/O modules except for 8 ns.
If synchronous measured values from analog inputs of different I/O modules
are required, you can implement a logic to wait with the further processing of
analog values until the Data New ports flag new data within two clock cycles.
Data type: UFix_1_0
Data width: 1

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Analog In-L

Values:
§ 0: No new value is available at the Data port.
§ 1: A new valid value is available at the Data port.
The port is set to 1 only for one clock cycle.

I/O mapping The following I/O mapping is relevant if you use the DS6651 Multi-I/O Module
framework for analog input channels. The signals are available at the female
50-pin Sub-D I/O connector of the respective DS6651 Multi-I/O Module (x =
1 … 5).

Outport I/O Function Number Channel Type Channel Connector Pin Signal
Data 25 Analog In 18 23 29 Analog In - Ch: 23 [Mod: x]
26 24 14 Analog In - Ch: 24 [Mod: x]
27 25 31 Analog In - Ch: 25 [Mod: x]
28 26 48 Analog In - Ch: 26 [Mod: x]

Configuring the Basic Functionality (FPGA) (ConfigurationDesk I/O Function

Implementation Guide )

References

Overview of the DS6651 Multi-I/O Module Framework............................................................. 29

Analog In-L

Purpose To measure data of the 16-bit A/D converter.

Description According to the number of physical connections available on the DS6651

Multi-I/O Module, you can select the Analog In-L I/O functions. There are two
channels.

The module number can be specified in the range 1 … 5.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 29 … 30.

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IOProperties.In.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).HcCustomName / Channel name Lets you
specify a custom name for the specified channel.

Tip

If you select Bit, you can reduce the complexity of the logic by using only
16 bits of the raw measurement result due to the 16-bit resolution of the
A/D converter.

IOProperties.In.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).Parameter(6).Init / Load Config Lets you
enable a 220 Ω resistor between the analog signal and the signal reference.
§ 0: Disabled
§ 1: 220 Ohm

IOProperties.In.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).Parameter(8).Init / Trigger mode Lets you
select the trigger mode and source for sampling the analog input voltage.
§ 15: Free running
The ADC samples the input voltage with a fixed sample period that is set by
the Sample period parameter.
§ 258: Trigger 1
The ADC samples the input voltage with each trigger impulse provided by a
Trigger I/O function. Refer to Trigger on page 296.

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Analog In-L

IOProperties.In.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).Parameter(10).Init / Sample period Lets
you specify the sample period of the ADC in the free running mode.
Sample period = nselected · 8 ns
With the value range 25 ≤ nselected ≤ 3,750,000,000.
The resulting sample period is in the range 200 ns ... 30 s.

Ports You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The channel number can be specified in the range 27 … 28.

m<ModuleNumber>_rx<ChannelNumber>_data00 / Data Outputs the

measured values of the 16-bit A/D converter.
Data type: Fix_22_5
Data width: 1
Value range: Depends on the setting of the Scaling parameter.

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Values:
§ 0: No new value is available at the Data port.
§ 1: A new valid value is available at the Data port.
The port is set to 1 only for one clock cycle.

Outport I/O Function Number Channel Type Channel Connector Pin Signal
Data 29 Analog In 19 27 16 Analog In-L - Ch: 27 [Mod: x]
30 28 33 Analog In-L - Ch: 28 [Mod: x]

Configuring the Basic Functionality (FPGA) (ConfigurationDesk I/O Function

Implementation Guide )

References

Overview of the DS6651 Multi-I/O Module Framework............................................................. 29

Analog Out

Purpose To write data to an analog output signal in the FPGA application.

Description According to the number of physical connections available on the DS6651

Multi-I/O Module, you can select the Analog Out I/O functions. There are four
channels.

The module number can be specified in the range 1 … 5.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 41 … 44.

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Analog Out

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).HcCustomName / Channel name Lets
you specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(5).Init / Scaling Lets you select
the scaling of the input data.
§ 0: mV
The valid input port range is ‑10,000 … +10,000 mV.
§ 1: Bit
The valid input port range is -32,768 … +32,776 (16-bit converter).

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The channel number can be specified in the range 17 … 20.

m<ModuleNumber>_tx<ChannelNumber>_data00_17_0_17_0i /
Data Outputs a voltage signal in the specified range.
Data type: Fix_18_2
Data width: 1
Update rate: 10.417 MS/s

I/O mapping The following I/O mapping is relevant if you use the DS6651 Multi-I/O Module
framework for analog output channels. The signals are available at the female
50-pin Sub-D I/O connector of the respective DS6651 Multi-I/O Module (x =
1 … 5).

Outport I/O Function Number Channel Type Channel Connector Pin Signal
Data 41 Analog Out 15 17 8 Analog Out - Ch: 17 [Mod: x]
42 18 25 Analog Out - Ch: 18 [Mod: x]
43 19 10 Analog Out - Ch: 19 [Mod: x]
44 20 27 Analog Out - Ch: 20 [Mod: x]

Configuring the Basic Functionality (FPGA) (ConfigurationDesk I/O Function

Implementation Guide )

References

Overview of the DS6651 Multi-I/O Module Framework............................................................. 29

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Analog Out-T

Purpose To write data to an analog output signal in the FPGA application.

Description According to the number of physical connections available on the DS6651 Multi-
I/O Module, you can select the Analog Out-T I/O functions. There are two
channels.

The module number can be specified in the range 1 … 5.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 45 … 46.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).HcCustomName / Channel name Lets
you specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(5).Init / Scaling Lets you select
the scaling of the input data.
§ 0: mV
The valid input port range corresponds to the settings of the Mode parameter.
§ 1: Bit
The valid input port range is -32,768 … +32,776 (16-bit converter).

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(7).Init / Mode Lets you select
the converter mode of the analog output channel.
§ 0: ±10 VDC
The DA converter directly outputs the voltage signal without using a
transformer. The output voltage range is ‑10 VDC … +10 VDC.
§ 1: ±20 V transformer coupled AC
The DA converter outputs the voltage signal via a transformer. The output
voltage range is ‑20 VAC … +20 VAC.

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The channel number can be specified in the range 21 … 22.

m<ModuleNumber>_tx<ChannelNumber>_data00_17_0_17_0i /
Data Outputs a voltage signal in the specified range.
Data type: Fix_18_2
Data width: 1
Update rate: 10.417 MS/s

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Digital In

Outport I/O Function Number Channel Type Channel Connector Pin Signal
Data 45 Analog Out 16 21 44 Analog Out‑T - Ch: 21 [Mod: x]
46 22 12 Analog Out‑T - Ch: 22 [Mod: x]

Configuring the Basic Functionality (FPGA) (ConfigurationDesk I/O Function

Implementation Guide )

References

Overview of the DS6651 Multi-I/O Module Framework............................................................. 29

Digital In

Purpose To read data from a digital input signal in the FPGA application.

Description According to the number of physical connections available on the DS6651 Multi-
I/O Module, you can select the Digital In I/O functions. There are up to 16
channels.

The module number can be specified in the range 1 … 5.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 16.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).HcCustomName / Channel name Lets
you specify a custom name for the specified channel.

IOProperties.In.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).Parameter(8).Init / Threshold init
voltage Lets you specify the voltage value that is used for the threshold in
mV.
Range: 0 mV ... 12,000 mV in 100 mV steps.
This electrical interface setting can be changed in ConfigurationDesk.

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Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The channel number can be specified in the range 1 … 16.

m<ModuleNumber>_rx<ChannelNumber>_trigger00 / Data Outputs the

current results of the digital input channel.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Input voltage of the channel is below the threshold voltage of a high-low
transition.
§ 1: Input voltage of the channel is higher than or equal to the threshold voltage
of a low-high transition.
Update rate: FPGA clock frequency

I/O mapping The following I/O mapping is relevant if you use the DS6651 Multi-I/O Module
framework for digital I/O channels. The signals are available at the female 50-pin
Sub-D I/O connector of the respective DS6651 Multi-I/O Module (x = 1 … 5).

Outport I/O Function Number Channel Type Channel Connector Pin Signal
Data 1 Digital In/Out 11 1 18 Digital In - Ch: 1 [Mod: x]
2 2 2 Digital In - Ch: 2 [Mod: x]
3 3 35 Digital In - Ch: 3 [Mod: x]
4 4 19 Digital In - Ch: 4 [Mod: x]
5 5 3 Digital In - Ch: 5 [Mod: x]
6 6 36 Digital In - Ch: 6 [Mod: x]
7 7 20 Digital In - Ch: 7 [Mod: x]
8 8 4 Digital In - Ch: 8 [Mod: x]
9 9 37 Digital In - Ch: 9 [Mod: x]
10 10 21 Digital In - Ch: 10 [Mod: x]
11 11 22 Digital In - Ch: 11 [Mod: x]
12 12 6 Digital In - Ch: 12 [Mod: x]
13 13 39 Digital In - Ch: 13 [Mod: x]
14 14 23 Digital In - Ch: 14 [Mod: x]
15 15 7 Digital In - Ch: 15 [Mod: x]
16 16 40 Digital In - Ch: 16 [Mod: x]

Configuring the Basic Functionality (FPGA) (ConfigurationDesk I/O Function

Implementation Guide )

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Digital In/Out-Z

References

Overview of the DS6651 Multi-I/O Module Framework............................................................. 29

Digital In/Out-Z

Purpose To read or write data to or from a digital signal in the FPGA application, or to
switch the output to a high-impedance state (tristate).

Description According to the number of physical connections available on the DS6651 Multi-
I/O Module, you can select the Digital In/Out-Z I/O functions. There are up to
four channels.

The module number can be specified in the range 1 … 5.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 4.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).HcCustomName / Channel name Lets
you specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(6).Init / Output Mode Lets
you select the output mode.
§ 49: Low-side switch
Lets you actively drive the output to GND to output a low-level signal.
An external load to VCC is required to output a high-level signal.
§ 50: High-side switch
Lets you actively drive the output to VCC to output a high-level signal.
An external load to GND is necessary to output a low-level signal.
§ 51: Push-pull
Lets you drive the output between VCC and GND.
An external load is not required.
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(8).Init / Drive Config Lets you
enable/disable the termination of the signal line by an internal resistor.
§ 1: Direct Drive
Lets you directly drive the I/O signal. The internal termination resistor is
disabled.

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§ 0: 68 Ohm Terminated
Lets you terminate the I/O signal with an internal 68 Ω resistor.
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(10).Init / High Supply Lets
you select the VCC voltage that determines the high-level voltage for the
high‑side switch.
§ 0: 5 V
§ 1: 3.3 V
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(14).Init / Threshold init
voltage Lets you specify the voltage value that is used for the threshold in
mV.
Range: 0 mV ... 12,000 mV in 100 mV steps.
This electrical interface setting can be changed in ConfigurationDesk.

Ports You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The channel number can be specified in the range 1, 5, 9, 13.

m<ModuleNumber>_rx<ChannelNumber>_trigger00 / Data In Outputs

the current results of the digital input channel.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Input voltage of the channel is below the threshold voltage of a high-low
transition.
§ 1: Input voltage of the channel is higher than or equal to the threshold voltage
of a low-high transition.
Update rate: FPGA clock frequency
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit
by using only the lowest bit.

Note

Asynchronous input data might lead to metastable register states because

input data is synchronized only by a single register stage. Further
synchronization techniques might be necessary.

m<ModuleNumber>_tx<ChannelNumber>_trigger00 / Data Out Outputs

a signal in the specified range if the Enable port is set to 1.
To set the voltage level, use the High supply parameter.
Data Type: UFix_1_0
Data width: 1

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Digital In/Out-Z

If driven with 0, the hardware outputs a low-level signal. If driven with 1, the
hardware outputs a high-level signal.
Update rate:
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit
by using only the lowest bit.

Note

The frequency that can be generated is smaller than the update rate.
For information on the electrical characteristics of the DS6651 Multi-I/O
Module, refer to Data Sheet of the DS6651 Multi-I/O Module (SCALEXIO
Hardware Installation and Configuration ).

m<ModuleNumber>_tx<ChannelNumber>_trigger00 / Enable Enables

the output of data values and disables the high-impedance state.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The output is set to the high-impedance state.
§ 1: The output is enabled and outputs the data values of the Data inport.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit
by using only the lowest bit.

Ports I/O Function Channel Channel Type Channel2) Connector Pin Signal
Number Number1)
Data In and 1 1 Digital In/Out 11 1 18 Digital In/Out-Z - Ch: 1-3
Data Out [Mod: x]
2 2 Do not use
3 35 Do not use
4 19 Usable by other I/O
functions
2 5 5 3 Digital In/Out-Z - Ch: 5-7
[Mod: x]
6 36 Do not use
7 20 Do not use
8 4 Usable by other I/O
functions
3 9 9 37 Digital In/Out-Z - Ch: 9-11
[Mod: x]
10 21 Do not use
11 22 Do not use
12 6 Usable by other I/O
functions

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Ports I/O Function Channel Channel Type Channel2) Connector Pin Signal
Number Number1)
4 13 13 39 Digital In/Out-Z - Ch: 13-15
[Mod: x]
14 23 Do not use
15 7 Do not use
16 40 Usable by other I/O
functions
1) Setting in the handcode framework.
2) Hardware channel displayed in the Platform Manager, for example.

Configuring the Basic Functionality (FPGA) (ConfigurationDesk I/O Function

Implementation Guide )

References

Overview of the DS6651 Multi-I/O Module Framework............................................................. 29

Digital Out

Purpose To write data to a digital output signal in the FPGA application.

Description According to the number of physical connections available on the DS6651 Multi-
I/O Module, you can select the Digital Out I/O functions. There are up to 16
channels.

The module number can be specified in the range 1 … 5.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 16.

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Digital Out

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).HcCustomName / Channel name Lets
you specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(4).Init / Output Mode Lets
you select the output mode.
§ 17: Low-side switch
Lets you actively drive the output to GND to output a low-level signal.
An external load to VCC is required to output a high-level signal.
§ 18: High-side switch
Lets you actively drive the output to VCC to output a high-level signal.
An external load to GND is necessary to output a low-level signal.
§ 19: Push-pull
Lets you drive the output between VCC and GND.
An external load is not required.
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(6).Init / Drive Config Lets you
enable/disable the termination of the signal line by an internal resistor.
§ 1: Direct Drive
Lets you directly drive the I/O signal. The internal termination resistor is
disabled.
§ 0: 68 Ohm Terminated
Lets you terminate the I/O signal with an internal 68 Ω resistor.
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(8).Init / High Supply Lets you
select the VCC voltage that determines the high-level voltage for the high‑side
switch.
§ 0: 5 V
§ 1: 3.3 V
This electrical interface setting can be changed in ConfigurationDesk.

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The channel number can be specified in the range 1 … 16.

m<ModuleNumber>_tx<ChannelNumber>_trigger00 / Data Outputs a

signal in the specified range.
To set the voltage level, use the High supply parameter.
Data Type: UFix_1_0
Data width: 1
If driven with 0, the hardware outputs a low-level signal. If driven with 1, the
hardware outputs a high-level signal.
Update rate: FPGA clock frequency

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Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit
by using only the lowest bit.

Note

Outport I/O Function Number Channel Type Channel Connector Pin Signal
Data 1 Digital In/Out 11 1 18 Digital Out - Ch: 1 [Mod: x]
2 2 2 Digital Out - Ch: 2 [Mod: x]
3 3 35 Digital Out - Ch: 3 [Mod: x]
4 4 19 Digital Out - Ch: 4 [Mod: x]
5 5 3 Digital Out - Ch: 5 [Mod: x]
6 6 36 Digital Out - Ch: 6 [Mod: x]
7 7 20 Digital Out - Ch: 7 [Mod: x]
8 8 4 Digital Out - Ch: 8 [Mod: x]
9 9 37 Digital Out - Ch: 9 [Mod: x]
10 10 21 Digital Out - Ch: 10 [Mod: x]
11 11 22 Digital Out - Ch: 11 [Mod: x]
12 12 6 Digital Out - Ch: 12 [Mod: x]
13 13 39 Digital Out - Ch: 13 [Mod: x]
14 14 23 Digital Out - Ch: 14 [Mod: x]
15 15 7 Digital Out - Ch: 15 [Mod: x]
16 16 40 Digital Out - Ch: 16 [Mod: x]

Configuring the Basic Functionality (FPGA) (ConfigurationDesk I/O Function

Implementation Guide )

References

Overview of the DS6651 Multi-I/O Module Framework............................................................. 29

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Digital Out-Z

Digital Out-Z

Purpose To write data to a digital output signal in the FPGA application or to switch the
output to a high-impedance state (tristate).

Description According to the number of physical connections available on the DS6651 Multi-
I/O Module, you can select the Digital Out-Z I/O functions. There are up to 8
channels.

The module number can be specified in the range 1 … 5.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 17 … 24.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).HcCustomName / Channel name Lets
you specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(5).Init / Output Mode Lets
you select the output mode.
§ 33: Low-side switch
Lets you actively drive the output to GND to output a low-level signal.
An external load to VCC is required to output a high-level signal.
§ 34: High-side switch
Lets you actively drive the output to VCC to output a high-level signal.
An external load to GND is necessary to output a low-level signal.
§ 35: Push-pull
Lets you drive the output between VCC and GND.
An external load is not required.
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(7).Init / Drive Config Lets you
enable/disable the termination of the signal line by an internal resistor.
§ 1: Direct Drive
Lets you directly drive the I/O signal. The internal termination resistor is
disabled.
§ 0: 68 Ohm Terminated
Lets you terminate the I/O signal with an internal 68 Ω resistor.
This electrical interface setting can be changed in ConfigurationDesk.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(9).Init / High Supply Lets you

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select the VCC voltage that determines the high-level voltage for the high‑side
switch.
§ 0: 5 V
§ 1: 3.3 V
This electrical interface setting can be changed in ConfigurationDesk.

Ports You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The channel number can be specified in the range 1, 3, 5, … 15.

m<ModuleNumber>_tx<ChannelNumber>_trigger00 / Data Outputs a

Note

m<ModuleNumber>_tx<ChannelNumber>_trigger00 / Enable Enables

the output of data values and disables the high-impedance state.
Data Type: UFix_1_0
Data width: 1
Values:
§ 0: The output is set to the high-impedance state.
§ 1: The output is enabled and outputs the data values of the Data inport.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit
by using only the lowest bit.

Outport I/O Function Channel Channel Type Channel2) Connector Pin Signal
Number Number1)
Data 17 1 Digital In/Out 11 1 18 Digital Out-Z - Ch: 1-2 [Mod: x]
2 2 Do not connect

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RS485 Rx

Outport I/O Function Channel Channel Type Channel2) Connector Pin Signal
Number Number1)
18 3 3 35 Digital Out-Z - Ch: 3-4 [Mod: x]
4 19 Do not connect
19 5 5 3 Digital Out-Z - Ch: 5-6 [Mod: x]
6 36 Do not connect
20 7 7 20 Digital Out-Z - Ch: 7-8 [Mod: x]
8 4 Do not connect
21 9 9 37 Digital Out-Z - Ch: 9-10 [Mod: x]
10 21 Do not connect
22 11 11 22 Digital Out-Z - Ch: 11-12 [Mod: x]
12 6 Do not connect
23 13 13 39 Digital Out-Z - Ch: 13-14 [Mod: x]
14 23 Do not connect
24 15 15 7 Digital Out-Z - Ch: 15-16 [Mod: x]
16 40 Do not connect
1) Setting in the handcode framework.
2) Hardware channel displayed in the Platform Manager, for example.

Configuring the Basic Functionality (FPGA) (ConfigurationDesk I/O Function

Implementation Guide )

References

Overview of the DS6651 Multi-I/O Module Framework............................................................. 29

RS485 Rx

Purpose To implement communication via a RS485 network in simplex mode.

Description According to the number of physical connections available on the DS6651 Multi-
I/O Module, you can select the RS485 Rx I/O functions. There are up to 8
channels.

The module number can be specified in the range 1 … 5.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

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The I/O function number can be specified in the range 17 … 24.

IOProperties.In.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).HcCustomName / Channel name Lets you
specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(8).Init / RS485
Termination Lets you enable an internal termination between the signal
lines. The setting can be overwritten by the RS485 termination ports.
§ 0: Open
The signal lines are not terminated.
§ 1: Terminated
An internal 120 Ω/5 nF RC termination terminates the signal lines.
This electrical interface setting can be changed in ConfigurationDesk.

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The channel number can be specified in the range 1, 3, 5, … 15.

m<ModuleNumber>_rx<ChannelNumber>_trigger00 / RX Data Outputs

the data received from the RS485 network.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The input voltage level is negative (< 0 V).
§ 1: The input voltage level is positive (≥ 0 V).

Outport I/O Function Number Channel1) Channel Type Channel2) Connector Pin Signal
Data 17 1 Digital In/Out 11 1 18 RS485 Rx- - Ch: 1-2 [Mod: x]
2 2 RS485 Rx+ - Ch: 1-2 [Mod: x]
18 3 3 35 RS485 Rx- - Ch: 3-4 [Mod: x]
4 19 RS485 Rx+ - Ch: 3-4 [Mod: x]
19 5 5 3 RS485 Rx- - Ch: 5-6 [Mod: x]
6 36 RS485 Rx+ - Ch: 5-6 [Mod: x]
20 7 7 20 RS485 Rx- - Ch: 7-8 [Mod: x]
8 4 RS485 Rx+ - Ch: 7-8 [Mod: x]
21 9 9 37 RS485 Rx- - Ch: 9-10 [Mod: x]
10 21 RS485 Rx+ - Ch: 9-10 [Mod: x]
22 11 11 22 RS485 Rx- - Ch: 11-12 [Mod: x]
12 6 RS485 Rx+ - Ch: 11-12 [Mod: x]
23 13 13 39 RS485 Rx- - Ch: 13-14 [Mod: x]

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RS485 Rx/Tx

Outport I/O Function Number Channel1) Channel Type Channel2) Connector Pin Signal
14 23 RS485 Rx+ - Ch: 13-14 [Mod: x]
24 15 15 7 RS485 Rx- - Ch: 15-16 [Mod: x]
16 40 RS485 Rx+ - Ch: 15-16 [Mod: x]
1) Setting in the handcode framework.
2) Hardware channel displayed in the Platform Manager, for example.

Configuring the Basic Functionality (FPGA) (ConfigurationDesk I/O Function

Implementation Guide )

References

Overview of the DS6651 Multi-I/O Module Framework............................................................. 29

RS485 Rx/Tx

Purpose To implement communication via a RS485 network in half-duplex mode.

Description According to the number of physical connections available on the DS6651 Multi-
I/O Module, you can select the RS485 Rx/Tx I/O functions. There are up to four
channels.

The module number can be specified in the range 1 … 5.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 37 … 40.

IOProperties.In.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).HcCustomName / Channel name Lets you
specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(10).Init / High supply Lets you
select the differential output voltage.
§ 0: 5 V
§ 1: 3.3 V

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(16).Init / RS485

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Termination Lets you enable an internal termination between the signal

lines. The setting can be overwritten by the RS485 termination ports.
§ 0: Open
The signal lines are not terminated.
§ 1: Terminated
An internal 120 Ω/5 nF RC termination terminates the signal lines.
This electrical interface setting can be changed in ConfigurationDesk.

Ports You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The channel number can be specified in the range 1, 5, 9, 13.

m<ModuleNumber>_rx<ChannelNumber>_trigger00 / RX Data Outputs

the data that is received from the RS485 network if the Tx Enable inport is set
to 0.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The input voltage level is negative (< 0 V).
§ 1: The input voltage level is positive (≥ 0 V).

m<ModuleNumber>_tx<ChannelNumber>_trigger00 / Tx Data Outputs

the data to be send to the RS485 network if the Tx Enable port is set to 1.
The differential output voltage level depends on the setting of the High Supply
parameter.
Data Type: UFix_1_0
Data width: 1
Values:
§ 0: The output voltage level is low.
§ 1: The output voltage level is high.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit
by using only the lowest bit.

m<ModuleNumber>_tx<ChannelNumber>_trigger00 / Tx Enable Enables

the output of data values to the RS485 network and disables the high-
impedance state.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The output is set to the high-impedance state (tristate). The Rx Data
outport can output received data from the RS485 network.
§ 1: The output is enabled and transmits the data values of the Tx Data inport.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit
by using only the lowest bit.

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RS485 Rx/Tx

Ports I/O Function Channel Channel Type Channel2) Connector Pin Signal
Number Number1)
Rx Data and 37 1 Digital In/Out 11 1 18 RS485 RxTx- - Ch: 1-3 [Mod:
Tx Data x]
2 2 RS485 RxTx+ - Ch: 1-3 [Mod:
x]
3 35 Do not connect
4 19 Usable by other I/O functions
38 5 5 3 RS485 RxTx- - Ch: 5-7 [Mod:
x]
6 36 RS485 RxTx+ - Ch: 5-7 [Mod:
x]
7 20 Do not connect
8 4 Usable by other I/O functions
39 9 9 37 RS485 RxTx- - Ch: 9-11
[Mod: x]
10 21 RS485 RxTx+ - Ch: 9-11
[Mod: x]
11 22 Do not connect
12 6 Usable by other I/O functions
40 13 13 39 RS485 RxTx- - Ch: 13-15
[Mod: x]
14 23 RS485 RxTx+ - Ch: 13-15
[Mod: x]
15 7 Do not connect
16 40 Usable by other I/O functions
1) Setting in the handcode framework.
2) Hardware channel displayed in the Platform Manager, for example.

Configuring the Basic Functionality (FPGA) (ConfigurationDesk I/O Function

Implementation Guide )

References

Overview of the DS6651 Multi-I/O Module Framework............................................................. 29

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RS485 Tx

Purpose To implement communication via a RS485 network in simplex mode.

Description According to the number of physical connections available on the DS6651 Multi-
I/O Module, you can select the RS485 Tx I/O functions. There are up to 8
channels.

The module number can be specified in the range 1 … 5.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 29 … 36.

IOProperties.In.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).HcCustomName / Channel name Lets you
specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(9).Init / High supply Lets you
select the differential output voltage.
§ 0: 5 V
§ 1: 3.3 V

IOProperties.Out.Fct(<IOFunctionNumber> +
ioOutOffset<ModuleNumber>).Parameter(15).Init / RS485
Termination Lets you enable an internal termination between the signal
lines. The setting can be overwritten by the RS485 termination ports.
§ 0: Open
The signal lines are not terminated.
§ 1: Terminated
An internal 120 Ω/5 nF RC termination terminates the signal lines.
This electrical interface setting can be changed in ConfigurationDesk.

Ports You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The channel number can be specified in the range 1, 3, 5, … 15.

m<ModuleNumber>_tx<ChannelNumber>_trigger00 / Data Outputs the

data to the RS485 network if the Enable port is set to 1.
The differential output voltage level depends on the setting of the High Supply
parameter.
Data Type: UFix_1_0
Data width: 1

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RS485 Tx

Values:
§ 0: The output voltage level is low.
§ 1: The output voltage level is high.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit
by using only the lowest bit.

m<ModuleNumber>_tx<ChannelNumber>_trigger00 / Enable Enables

the output of data values to the RS485 network.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The output is disabled.
The output voltage level is 0 V. The output does not support an high-
impedance state (tri-state).
§ 1: The output is enabled and transmits the data values of the Data inport.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit
by using only the lowest bit.

Outport I/O Function Channel Channel Type Channel2) Connector Pin Signal
Number Number1)
Data 29 1 Digital In/Out 11 1 18 RS485 Tx- - Ch: 1-2 [Mod: x]
2 2 RS485 Tx+ - Ch: 1-2 [Mod: x]
30 3 3 35 RS485 Tx- - Ch: 3-4 [Mod: x]
4 19 RS485 Tx+ - Ch: 3-4 [Mod: x]
31 5 5 3 RS485 Tx- - Ch: 5-6 [Mod: x]
6 36 RS485 Tx+ - Ch: 5-6 [Mod: x]
32 7 7 20 RS485 Tx- - Ch: 7-8 [Mod: x]
8 4 RS485 Tx+ - Ch: 7-8 [Mod: x]
33 9 9 37 RS485 Tx- - Ch: 9-10 [Mod: x]
10 21 RS485 Tx+ - Ch: 9-10 [Mod: x]
34 11 11 22 RS485 Tx- - Ch: 11-12 [Mod: x]
12 6 RS485 Tx+ - Ch: 11-12 [Mod: x]
35 13 13 39 RS485 Tx- - Ch: 13-14 [Mod: x]
14 23 RS485 Tx+ - Ch: 13-14 [Mod: x]
36 15 15 7 RS485 Tx- - Ch: 15-16 [Mod: x]
16 40 RS485 Tx+ - Ch: 15-16 [Mod: x]
1) Setting in the handcode framework.
2) Hardware channel displayed in the Platform Manager, for example.

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Configuring the Basic Functionality (FPGA) (ConfigurationDesk I/O Function

Implementation Guide )

References

Overview of the DS6651 Multi-I/O Module Framework............................................................. 29

Trigger

Purpose To trigger the analog measurement.

Description According to the number of physical connections available on the DS6651 Multi-
I/O Module, you can select the Trigger I/O functions. There are two channels.

The module number can be specified in the range 1 … 5.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 47 … 48.

IOProperties.In.Fct(<IOFunctionNumber> +
ioInOffset<ModuleNumber>).HcCustomName / Channel name Lets you
specify a custom name for the specified channel.

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The channel number can be specified in the range 17 … 18.

m<ModuleNumber>_tx<ChannelNumber>_trigger00 / Enable Lets you

trigger the analog measurement of the DS6651 Multi-I/O Module.
Data type: UFix_1_0
Data width: 1
A transition from 0 to 1 provides a trigger impulse that can be used by the
Analog In/Analog In-L I/O functions. Refer to Analog In on page 270 and
Analog In-L on page 273.

I/O mapping No external connection.

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Trigger

Configuring the Basic Functionality (FPGA) (ConfigurationDesk I/O Function

Implementation Guide )

References

Overview of the DS6651 Multi-I/O Module Framework............................................................. 29

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I/O Functions of the DS660X_MGT Framework

I/O Functions of the DS660X_MGT Framework

Introduction The DS660X_MGT framework provides access to an MGT module. An MGT

module can be installed to the following SCALEXIO FPGA base boards:
§ DS6601 FPGA Base Board
§ DS6602 FPGA Base Board

Where to go from here Information in this section

Aurora 64b66b In.................................................................................. 300

To provide read access to the installed MGT module.

Aurora 64b66b Out............................................................................... 302

To provide write access to the installed MGT module.

Aurora 64b66b 128 Bit In...................................................................... 303

To provide 128-bit-based read access to the installed MGT module.

Aurora 64b66b 128 Bit Out................................................................... 305

To provide 128-bit-based write access to the installed MGT module.

MGT In.................................................................................................. 307

To provide the information about the connection between the GTH
transceivers and the MGT module and to specify the reference clock
frequency.

MGT In Opto Ready............................................................................... 309

To indicate whether the MGT module is ready for data exchange.

MGT Out............................................................................................... 310

To provide the information about the connection between the GTH
transceivers and the MGT module.

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Aurora 64b66b In

Purpose To provide read access to the installed MGT module.

Description The DS6601 and DS6602 FPGA Base Boards provide an MGT module slot to
install an MGT Module. The Aurora 64b66b In I/O function lets you configure
read access to the MGT communication.

This I/O function is not considered when you generate the processor interface
model.

Used communication protocol setting The I/O function uses the Aurora
64B/66B protocol with the following settings:
§ Transceiver: GTH
§ Line Rate: 10.3125 Gbps
§ Dataflow Mode: Duplex
§ Interface: Framing
§ Flow Control: NFC
§ USER K: off
§ Little Endian Support: off
§ CRC: off
For more information on the protocol, refer to https://docs.xilinx.com/r/en-
US/pg074-aurora-64b66b.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file of the FPGA base board.

The I/O function number can be specified in the range 1 … 4.

The used module slot is 1 (mgtModuleNr = 1).

hcfw.IOProperties.In.Fct(<IOFunctionNumber> + mgtInOffset
(1)).HcCustomName / Channel name Lets you specify a custom name for
the specified channel.

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The lane number can be specified in the range 1 … 4.

mgt_lane<LaneNumber>_rx_data / Data Inport to read a 64-bit data value

from the MGT communication bus.
User data transfer rate: Max. 8 Gbit/s (125 MHz FPGA clock, 64 bits)
MGT latency (latency between sender and receiver via an optical loopback):
§ With maximum data rate: 456 ns
§ Single words: Max. 472 ns, typ. 384 ns

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Aurora 64b66b In

If you implement inter-FPGA communication via MGT modules, clock drifts can
result in additional latencies. Refer to Implementing Inter-FPGA Communication
via MGT Modules (FPGA Programming Handcode Framework Guide ).
Data type: U_Fix64_0
Data width: 1

mgt_lane<LaneNumber>_rx_valid / Data New Inport to indicate whether

a new data value was received by the MGT module.
If the MGT module contains a new value, the flag changes from 0 to 1 for one
clock cycle:
§ 0: No new data available.
§ 1: New data available.
Data type: U_Fix1_0
Data width: 1

mgt_lane<LaneNumber>_rx_ready / Ready Outport to specify that the

communication channel is ready to read new data. Use this port to prevent a
data overflow.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The communication channel is not ready.
§ 1: New data can be read.

mgt_user_clk_156 Inport to provide the reference clock of the MGT

(156.25 MHz). Use this port to implement parts of your FPGA application
synchronous with the clock frequency of the MGT module, i.e. with
156.25 MHz.
Working with synchronous frequencies has the following benefits:
§ Less latency because there is no clock transition between the clock frequencies
of the FPGA and the MGT module.
§ No need for clock compensation due to drifting clocks. The Aurora protocol
automatically synchronizes the different clocks.
Data type: UFix_1_0
Data width: 1

I/O mapping The MGT communication bus uses the MPO connector of the FPGA Base Board.

Overview of Inter-FPGA Communication (FPGA Programming Handcode Framework

Guide )

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Aurora 64b66b Out

Purpose To provide write access to the installed MGT module.

Description The DS6601 and DS6602 FPGA Base Boards provide an MGT module slot to
install an MGT Module. The Aurora 64b66b Out I/O function lets you configure
write access to the MGT communication.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file of the FPGA base board.

The I/O function number can be specified in the range 1 … 4.

The used module slot is 1 (mgtModuleNr = 1).

hcfw.IOProperties.Out.Fct(<IOFunctionNumber> + mgtOutOffset
(1)).HcCustomName / Channel name Lets you specify a custom name for
the specified channel.

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The lane number can be specified in the range 1 … 4.

mgt_lane<LaneNumber>_tx_valid / Enable Outport to enable the write

access to the MGT communication bus:
§ 0: No write access.
§ 1: The Data port value of the current clock cycle is written on the MGT
communication bus.
Data type: UFix_1_0
Data width: 1

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Aurora 64b66b 128 Bit In

mgt_lane<LaneNumber>_tx_data / Data Outport to write a 64-bit data

value to the MGT communication bus.
User data transfer rate: Max. 8 Gbit/s (125 MHz FPGA clock, 64 bits)
MGT latency (latency between sender and receiver via an optical loopback):
§ With maximum data rate: 456 ns
§ Single words: Max. 472 ns, typ. 384 ns
If you implement inter-FPGA communication via MGT modules, clock drifts can
result in additional latencies. Refer to Implementing Inter-FPGA Communication
via MGT Modules (FPGA Programming Handcode Framework Guide ).
Data type: U_Fix64_0
Data width: 1

mgt_lane<LaneNumber>_tx_ready / Ready Inport to read a flag that

indicates that the MGT module is ready to write new data on the MGT
communication bus:
§ 0: The MGT module is busy.
§ 1: New data values can be written to the MGT communication bus.
Data type: UFix_1_0
Data width: 1

I/O mapping The MGT communication bus uses the MPO connector of the FPGA Base Board.

Overview of Inter-FPGA Communication (FPGA Programming Handcode Framework

Guide )

Aurora 64b66b 128 Bit In

Purpose To provide 128-bit-based read access to the installed MGT module.

Description The DS6601 and DS6602 FPGA Base Boards provide an MGT module slot to
install an MGT Module. The Aurora 64b66b 128 Bit In I/O function lets you
configure read access to the MGT communication.

This I/O function is not considered when you generate the processor interface
model.

Used communication protocol setting The I/O function uses the Aurora
64B/66B protocol with the following settings:
§ Transceiver: GTH
§ Line Rate: 10.3125 Gbps
§ Dataflow Mode: Duplex

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§ Interface: Framing
§ Flow Control: NFC
§ USER K: off
§ Little Endian Support: off
§ CRC: off
For more information on the protocol, refer to https://docs.xilinx.com/r/en-
US/pg074-aurora-64b66b.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file of the FPGA base board.

The I/O function number can be specified in the range 5 … 8.

The used module slot is 1 (mgtModuleNr = 1).

hcfw.IOProperties.In.Fct(<IOFunctionNumber> + mgtInOffset
(1)).HcCustomName / Channel name Lets you specify a custom name for
the specified channel.

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The lane number can be specified in the range 1 … 4.

mgt_lane<LaneNumber>_rx_data / Data Inport to read a 128-bit data

value from the MGT communication bus.
User data transfer rate: Max. 10.3125 Gbit/s, limited by the MGT module.
MGT latency (Latency between sender and receiver via an optical loopback):
§ With maximum data rate: Max. 6.272 µs, typ. 6.192 µs
The latency increases, because the TX-FIFO buffer becomes full when the data
stream fills the buffer with 16 Gbit/s (128 bits at 125 MHz).
§ Single words: Max. 472 ns, typ. 384 ns
If you implement inter-FPGA communication via MGT modules, clock drifts can
result in additional latencies. Refer to Implementing Inter-FPGA Communication
via MGT Modules (FPGA Programming Handcode Framework Guide ).
Data type: UFix_128_0
Data width: 1

mgt_lane<LaneNumber>_rx_valid / Data New Inport to indicate whether

mgt_lane<LaneNumber>_rx_ready / Ready Outport to specify that the

communication channel is ready to read new data. Use this port to prevent a
data overflow.

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Aurora 64b66b 128 Bit Out

Data type: UFix_1_0

Data width: 1
Values:
§ 0: The communication channel is not ready.
§ 1: New data can be read.

mgt_user_clk_156 Inport to provide the reference clock of the MGT

I/O mapping The MGT communication bus uses the MPO connector of the FPGA Base Board.

Overview of Inter-FPGA Communication (FPGA Programming Handcode Framework

Guide )

Aurora 64b66b 128 Bit Out

Purpose To provide 128-bit-based write access to the installed MGT module.

Description The DS6601 and DS6602 FPGA Base Boards provide an MGT module slot to
install an MGT Module. The Aurora 64b66b 128 Bit Out I/O function lets you
configure write access to the MGT communication.

This I/O function is not considered when you generate the processor interface
model.

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§ USER K: off
§ Little Endian Support: off
§ CRC: off
For more information on the protocol, refer to https://docs.xilinx.com/r/en-
US/pg074-aurora-64b66b.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file of the FPGA base board.

The I/O function number can be specified in the range 5 … 8.

The used module slot is 1 (mgtModuleNr = 1).

hcfw.IOProperties.Out.Fct(<IOFunctionNumber> + mgtOutOffset
(1)).HcCustomName / Channel name Lets you specify a custom name for
the specified channel.

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

The lane number can be specified in the range 1 … 4.

mgt_lane<LaneNumber>_tx_valid / Enable Outport to enable the write

access to the MGT communication bus:
§ 0: No write access.
§ 1: The Data port value of the current clock cycle is written on the MGT
communication bus.
Data type: UFix_1_0
Data width: 1

mgt_lane<LaneNumber>_tx_data / Data Outport to write a 128-bit data

value to the MGT communication bus.
User data transfer rate: Max. 10.3125 Gbit/s, limited by the MGT module.
MGT latency (latency between sender and receiver via an optical loopback):
§ With maximum data rate: Max. 6.272 µs, typ. 6.192 µs
The latency increases, because the TX-FIFO buffer becomes full when the data
stream fills the buffer with 16 Gbit/s (128 bits at 125 MHz).
§ Single words: Max. 472 ns, typ. 384 ns
If you implement inter-FPGA communication via MGT modules, clock drifts can
result in additional latencies. Refer to Implementing Inter-FPGA Communication
via MGT Modules (FPGA Programming Handcode Framework Guide ).
Data type: UFix_128_0
Data width: 1

mgt_lane<LaneNumber>_tx_ready / Ready Inport to read a flag that

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Data width: 1

I/O mapping The MGT communication bus uses the MPO connector of the FPGA Base Board.

Overview of Inter-FPGA Communication (FPGA Programming Handcode Framework

Guide )

MGT In

Purpose To provide the information about the connection between the GTH transceivers
and the MGT module and to specify the reference clock frequency.

Description The DS6601 and DS6602 FPGA Base Boards provide an MGT module slot to
install an MGT Module. The MGT In I/O function provides the information about
the connection between the GTH transceivers and the MGT module and lets you
specify the reference clock frequency.

The information is required for customer-specific protocol blocks that configure

the GTH transceivers. A GTH transceiver is a configurable transceiver of the AMD
UltraScale FPGA architecture.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file of the FPGA base board.

The I/O function number is 9.

The used module slot is 1 (mgtModuleNr = 1).

hcfw.IOProperties.In.Fct(<IOFunctionNumber> + mgtInOffset
(1)).HcCustomName / Channel name Lets you specify a custom name for
the specified channel.

hcfw.IOProperties.In.Fct(<IOFunctionNumber> + mgtInOffset
(1)).Parameter((<IOFunctionNumber> + 1)).Init / MGT reference clock
frequency Lets you specify the reference clock frequency that is used to
generate the MGT clock frequency.
The reference clock frequency depends on the protocol type, transfer rate, and
internal scaling factors. In many cases, the reference clock frequency for the
MGT module of the FPGA base board is 156.25 MHz.
For more information, refer to DS6601, DS6602: Coding a Customized MGT
Protocol (FPGA Programming Handcode Framework Guide ).

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Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

mgt_clk_p / CLK_P Provides the MGT reference clock frequency.

The port represents the differential signal of an internal clock. The port must be
connected to a function that provides the configuration for the GTH transceivers.
The reference frequency is specified by the MGT reference clock frequency
parameter.
Data type: UFix_1_0
Data width: 1

mgt_clk_n / CLK_N Provides the MGT reference clock frequency.

mgt_rx_p / RX_P Reads the raw data from the MGT module.
The port represents the differential output signals of the MGT module. The port
must be connected to a function that provides the configurations for the GTH
transceiver.
Data type: UFix_4_0
Each bit represents the output of one MGT channel.
Data width: 1
Update rate: Clock frequency of the GTH transceivers.

mgt_rx_n / RX_N Reads the raw data from the MGT module.
The port represents the differential output signals of the MGT module. The port
must be connected to a function that provides the configurations for the GTH
transceiver.
Data type: UFix_4_0
Each bit represents the output of one MGT channel.
Data width: 1
Update rate: Clock frequency of the GTH transceivers.

I/O mapping The MGT communication bus uses the MPO connector of the FPGA Base Board.

Overview of Inter-FPGA Communication (FPGA Programming Handcode Framework

Guide )

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MGT In Opto Ready

MGT In Opto Ready

Purpose To indicate whether the MGT module is ready for data exchange.

Description The DS6601 and DS6602 FPGA Base Boards provide an MGT module slot to
install an MGT Module. The MGT In Opto Ready I/O function lets you indicate
whether the MGT module is ready for data exchange.

If you are using a clock domain for MGT communication that is synchronous to
the GTH transceivers, you must use the MGT In Opto Ready I/O function in a
clock domain at the base rate of the FPGA.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file of the FPGA base board.

The I/O function number is 10.

The used module slot is 1 (mgtModuleNr = 1).

hcfw.IOProperties.In.Fct(<IOFunctionNumber> + mgtInOffset
(1)).HcCustomName / Channel name Lets you specify a custom name for
the specified channel.

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

mgt_opto_transceiver_ready / Opto_Ready Outport to indicate whether

the MGT module is ready for data exchange. The port changes to 1 during the
initialization phase, i.e. before the CN APP Status I/O function changes from
stop to running.
Data type: UFix_1_0
Data width: 1
If the MGT module is ready, the flag changes from 0 to 1:
§ 0: The MGT module is not ready.
§ 1: The MGT module is ready.

I/O mapping The MGT communication bus uses the MPO connector of the FPGA Base Board.

Overview of Inter-FPGA Communication (FPGA Programming Handcode Framework

Guide )

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MGT Out

Purpose To provide the information about the connection between the GTH transceivers
and the MGT module.

Description The DS6601 and DS6602 FPGA Base Boards provide an MGT module slot to
install an MGT Module. The MGT Out I/O function provides the information
about the connection between the GTH transceivers and the MGT module.

The information is required for customer-specific protocol blocks that configure

the GTH transceivers. A GTH transceiver is a configurable transceiver of the AMD
UltraScale FPGA architecture.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file of the FPGA base board.

The I/O function number is 9.

The used module slot is 1 (mgtModuleNr = 1).

hcfw.IOProperties.In.Fct(<IOFunctionNumber> + mgtInOffset
(1)).HcCustomName / Channel name Lets you specify a custom name for
the specified channel.

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

mgt_tx_p / TX_P Writes data to the MGT module.

The port represents the differential signals of the GTH transceivers that are
connected to the MGT module. The port must be connected to a function that
provides the configuration for the GTH transceivers.
Data type: UFix_4_0
Data width: 1
Each bit represents the input for one MGT channel.
Update rate: MGT reference clock frequency
The MGT reference clock frequency parameter of the MGT In I/O function
lets you specify the reference frequency that is used to generate the MGT clock
frequency. Refer to MGT In on page 307.

mgt_tx_n / TX_N Writes data to the MGT module.

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MGT Out

The MGT reference clock frequency parameter of the MGT In I/O function
lets you specify the reference frequency that is used to generate the MGT clock
frequency. Refer to MGT In on page 307.

I/O mapping The MGT communication bus uses the MPO connector of the FPGA Base Board.

Overview of Inter-FPGA Communication (FPGA Programming Handcode Framework

Guide )

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I/O Functions of the Inter-FPGA Interface Framework

I/O Functions of the Inter-FPGA Interface

Framework

Introduction The Inter-FPGA Interface framework provides access to the I/O module slots of a
SCALEXIO FPGA base board to implement an inter-FPGA communication bus.

Where to go from here Information in this section

I‑FPGA In............................................................................................... 314

To provide read access to the inter-FPGA communication bus with bus
synchronization.

I‑FPGA Out............................................................................................ 318

To provide write access to the inter-FPGA communication bus with bus
synchronization.

Information in other sections

Details on implementing an inter-FPGA communication bus:

Handcoding Inter-FPGA Communication (FPGA Programming
Handcode Framework Guide )
The SCALEXIO FPGA base boards support inter‑FPGA communication.

Other frameworks that provide access to the FPGA functionality

of a SCALEXIO system:
I/O Functions of the DS2655 FPGA Base Board Framework.................... 125
The frameworks of the DS2655 FPGA Base Boards provide the standard
I/O functionality of the boards.

I/O Functions of the DS6601 FPGA Base Board Framework.................... 159

The DS6601 (KU035) FPGA Base Board framework of the DS6601 FPGA
Base Board provides the standard I/O functionality of the board.

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I/O Functions of the DS6602 FPGA Base Board Framework.................... 193

The DS6602 (KU15P) FPGA Base Board framework of the DS6602 FPGA
Base Board provides the standard I/O functionality of the board.

I/O Functions of the DS2655M1 I/O Module Framework........................ 237

The DS2655M1 I/O Module framework provides analog and digital I/O
functionality of SCALEXIO FPGA base board with at least one DS2655M1
Multi-I/O Module.

I/O Functions of the DS2655M2 I/O Module Framework........................ 249

The DS2655M2 I/O Module framework provides digital I/O functionality
of a SCALEXIO FPGA base board with at least one DS2655M2 Digital I/O
Module.

I/O Functions of the DS6651 Multi-I/O Module Framework.................... 269

The DS6651 Multi-I/O Module framework provides analog and digital I/O
functionality of a SCALEXIO FPGA base board with at least one DS6651
Multi-I/O Module.

I‑FPGA In

Purpose To provide read access to the inter-FPGA communication bus with bus
synchronization.

Description With the Inter-FPGA Interface framework, you can use I/O module slots of
a SCALEXIO FPGA base board as inter-FPGA interfaces. The module number
represents the used I/O module slot of the FPGA board.

The I‑FPGA In I/O functions let you configure up to eight subbuses with bus
synchronization.

A previously configured communication channel is no more available for other

I‑FPGA I/O functions, such as I‑FPGA Out. In total, you can use up to eight input
and output channels.
This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

ioModuleNr Lets you set the used I/O module slot to configure the following
I/O functions. Value range: 1 ... 5

hcfw.IOProperties.In.Fct(<ChannelNumber> +
ioInOffset(ioModuleNr)).HcCustomName / Channel name Lets you
specify a custom name for the specified channel. The channel number reflects
one of eight configurable subbuses.

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I-FPGA In

hcfw.IOProperties.In.Fct(<ChannelNumber> +
ioInOffset(ioModuleNr)).Parameter(startparam).Init / Mode You have to
specify only the channel number. The channel number reflects one of eight
configurable subbuses. To use the I-FPGA In function, the mode must be set
to 2 or 4. Mode 4 is the recommended mode. Mode 2 is an expert mode
that you schould use only if you have enough experience of configuring buses
and knowledge of checking the correctness of the configured transmission with
regard to the observed signal integrity at the applicable temperature range.
Possible modes for the inter-FPGA interface:
§ 0: Unused
§ 1: Write access to the inter-FPGA interface with a lower latency (2 clock
cycles), but the bits are not synchronous (expert mode).
§ 2: Read access to the inter-FPGA interface with a lower latency (2 clock cycles),
but the bits are not synchronous (expert mode).
§ 3: Write access to the inter-FPGA interface with bus synchronization.
§ 4: Read access to the inter-FPGA interface with bus synchronization.

hcfw.IOProperties.In.Fct(<ChannelNumber> +
ioInOffset(ioModuleNr)).Parameter(startparam+2).Init / Startbit Lets you
specify the bit with which the transmission data starts in the range 0 … 27. The
channel number reflects one of eight configurable subbuses.

Note

If you send and receive data with the same inter-FPGA interface, you have
to consider limitations on the bit ranges for the subbuses. Refer to How
to Determine the Bit Ranges for Inter-FPGA Subbuses Between SCALEXIO
FPGA Base Boards (FPGA Programming Handcode Framework Guide ).

hcfw.IOProperties.In.Fct(<ChannelNumber> +
ioInOffset(ioModuleNr)).Parameter(startparam+4).Init / Endbit Lets you
specify the bit with which the transmission data ends in the range 0 … 27. The
channel number reflects one of eight configurable subbuses.
The range of the end bit is to be adapted to the specified start bit. It is not
allowed to specify an end bit less than the corresponding start bit.
For each subbus with bus synchronization, one bit is to be reserved
for synchronization. The maximum data width of a subbus is therefore
Endbit ‑ Startbit.

Note

hcfw.IOProperties.In.Fct(<ChannelNumber> +
ioInOffset(ioModuleNr)).Parameter(startparam+7).Init / Bit length Lets
you specify the bit length used for the transmission in the range 3 … 128 cycles.
The parameter effects only synchronized buses. The channel number reflects one
of eight configurable subbuses.

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The default value is 6 cycles.

Usable only for inter-FPGA communication buses with bus synchronization.

Note

You should change these values only if you have enough experience
of configuring buses and knowledge of checking the correctness of the
configured transmission with regard to the observed signal integrity at the
applicable temperature range.
The default values for the bit length, clock, and filter depth have been
tested by dSPACE.

A reference value for the bit length depends on the specified filter depth and can
be calculated by 2 + 2 · FilterDepthIn.

hcfw.IOProperties.In.Fct(<ChannelNumber> +
ioInOffset(ioModuleNr)).Parameter(startparam+9).Init / Clock Lets you
specify the clock frequency used for the inter‑FPGA communication. The
parameter effects only synchronized buses. The channel number reflects one of
eight configurable subbuses.
Usable only for inter-FPGA communication buses with bus synchronization.
Possible values:
§ 1: 125 MHz
§ 2: 250 MHz
The default value is 1 (125 MHz).

Note

hcfw.IOProperties.In.Fct(<ChannelNumber> +
ioInOffset(ioModuleNr)).Parameter(startparam+11).Init / Filter
depth Lets you specify a spike filter with the specified length to reduce
transmission errors in the range 0 … 32 cycles. The parameter effects only
synchronized buses. The channel number reflects one of eight configurable
subbuses.
Usable only for inter-FPGA communication buses with bus synchronization.

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I-FPGA In

The default value is 2 cycles.

Note

hcfw.IOProperties.In.Fct(<ChannelNumber> +
ioInOffset(ioModuleNr)).Parameter(startparam+12).Init / Add internal
pipeline register to relax timing Lets you enable an additional internal
pipeline to relax timing especially for 250 MHz communication if a FPGA build
process were otherwise not possible. The parameter effects only synchronized
buses. The channel number reflects one of eight configurable subbuses.
Usable only for inter-FPGA communication buses with bus synchronization.
§ 0: Off (default)
§ 1: On

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

m<ModuleNumber>_intercom_<ChannelNumber>_data_in / Data Reads

data from the inter‑FPGA communication bus. The module number reflects the
used I/O module slot. The channel number reflects one of eight configurable
subbuses.. Bits which exceed the configured bus width are discarded. For each
configured subbus one bit is automatically reserved for synchronization.
Data width: 1
Value range: 0 ... 227-1

m<ModuleNumber>_intercom_<ChannelNumber>_data_new / Data
New Indicates whether new data was written to the Data register. The
module number reflects the used I/O module slot. The channel number reflects
one of eight configurable subbuses.
If the Data register contains new values, the flag changes from 0 to 1 for one
clock cycle. If the transmission failed, the error counter increases.
Usable only for inter-FPGA communication buses with bus synchronization.
Data width: 1
§ 0: No new data available in the Data register. Either the transmission is not yet
finished, or the transmission failed (see Errors outport).
§ 1: New data available in the Data register.

m<ModuleNumber>_intercom_<ChannelNumber>_errors /
Errors Outputs the number of transmission errors. The counter is reset only at
FPGA application start. If the range exceeds, the counter restarts with 0.
The module number reflects the used I/O module slot. The channel number
reflects one of eight configurable subbuses.
Usable only for inter-FPGA communication buses with bus synchronization.

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Data width: 1
Value range: 0 ... 232-1

m<ModuleNumber>_intercom_<ChannelNumber>_reset_error / Errors
Reset Resets the Errors output. The module number reflects the used I/O
module slot. The channel number reflects one of eight configurable subbuses.
Usable only for inter-FPGA communication buses with bus synchronization.
The I-FPGA In Errors counter potentially increases until the FPGA Base Board with
the corresponding I-FPGA Out interface starts working.
§ 0: Not used
§ 1: Error output is reset
Data type: UFix1_0
Value range: 0 ... 1

I/O mapping No external connection to the I/O connector of the board. The SCALEXIO FPGA
base board uses its I/O module slots inside the SCALEXIO system for inter-FPGA
communication.

Overview of Inter-FPGA Communication (FPGA Programming Handcode Framework

Guide )

I‑FPGA Out

Purpose To provide write access to the inter-FPGA communication bus with bus
synchronization.

The I‑FPGA Out I/O functions let you configure up to eight subbuses with bus
synchronization.

A previously configured communication channel is no more available for other

I‑FPGA I/O functions, such as I‑FPGA In. In total, you can use up to eight input
and output channels.
This I/O function is not considered when you generate the processor interface
model.

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I-FPGA Out

Avoiding hardware damage NOTICE

An incorrect configuration might damage the electrical interface.

If you configure both ends of an inter-FPGA connection bus to write on the
bus, the connection results in a short circuit. This short circuit might damage
the electrical interface of the used I/O module slots. In multiprocessor
applications, an incorrect configuration cannot be detected automatically
to beware hardware damage.
§ Make sure that the counterpart interface on the other FPGA board uses
the same Startbit and Endbit to read the data. Refer to Overview of
Inter-FPGA Communication (FPGA Programming Handcode Framework
Guide ).

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

ioModuleNr Lets you set the used I/O module slot to configure the following
I/O functions. Value range: 1 ... 5

hcfw.IOProperties.Out.Fct(<ChannelNumber> +
ioOutOffset(ioModuleNr)).HcCustomName / Channel name Lets you
specify a custom name for the specified channel. The channel number reflects
one of eight configurable subbuses.

hcfw.IOProperties.Out.Fct(<ChannelNumber> +
ioOutOffset(ioModuleNr)).Parameter(startparam).Init / Mode You have
to specify only the channel number. The channel number reflects one of eight
configurable subbuses. To use the I-FPGA Out function, the mode must be set
to 1 or 3. Mode 3 is the recommended mode. Mode 1 is an expert mode
that you schould use only if you have enough experience of configuring buses
and knowledge of checking the correctness of the configured transmission with
regard to the observed signal integrity at the applicable temperature range.
Possible modes for the inter-FPGA interface:
§ 0: Unused
§ 1: Write access to the inter-FPGA interface with a lower latency (2 clock
cycles), but the bits are not synchronous (expert mode).
§ 2: Read access to the inter-FPGA interface with a lower latency (2 clock cycles),
but the bits are not synchronous (expert mode).
§ 3: Write access to the inter-FPGA interface with bus synchronization.
§ 4: Read access to the inter-FPGA interface with bus synchronization.

hcfw.IOProperties.Out.Fct(<ChannelNumber> +
ioOutOffset(ioModuleNr)).Parameter(startparam+2).Init / Startbit Lets

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you specify the bit with which the transmission data starts in the range 0 …
27. The channel number reflects one of eight configurable subbuses.

Note

hcfw.IOProperties.Out.Fct(<ChannelNumber> +
ioOutOffset(ioModuleNr)).Parameter(startparam+4).Init / Endbit Lets
you specify the bit with which the transmission data ends in the range 0 …
27. The channel number reflects one of eight configurable subbuses.
The range of the end bit is to be adapted to the specified start bit. It is not
allowed to specify an end bit less than the corresponding start bit.
For each subbus with bus synchronization, one bit is to be reserved
for synchronization. The maximum data width of a subbus is therefore
Endbit ‑ Startbit.

Note

hcfw.IOProperties.Out.Fct(<ChannelNumber> +
ioOutOffset(ioModuleNr)).Parameter(startparam+7).Init / Bit
length Lets you specify the bit length used for the transmission in the range
3 … 128 cycles. The parameter effects only synchronized buses. The channel
number reflects one of eight configurable subbuses.
The default value is 6 cycles.
Usable only for inter-FPGA communication buses with bus synchronization.

Note

A reference value for the bit length depends on the specified filter depth of the
related I‑FPGA In, and can be calculated by 2 + 2 · FilterDepthIn.

hcfw.IOProperties.Out.Fct(<ChannelNumber> +
ioOutOffset(ioModuleNr)).Parameter(startparam+9).Init / Clock Lets you
specify the clock frequency used for the inter‑FPGA communication. The
parameter effects only synchronized buses. The channel number reflects one of
eight configurable subbuses.

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Usable only for inter-FPGA communication buses with bus synchronization.

Possible values:
§ 1: 125 MHz
§ 2: 250 MHz
The default value is 1 (125 MHz).

Note

Port You must add the following signals of the I/O function to the port definition of
the custom module entity cm.

m<ModuleNumber>_intercom_<ChannelNumber>_data_out / Data
Out Outputs the data to be written to the inter‑FPGA communication bus.
The channel number reflects one of eight configurable bus segments. The
module number reflects the used I/O module slot. The channel number reflects
one of eight configurable subbuses. Bits which exceed the configured bus width
are discarded. For each configured subbus one bit is automatically reserved for
synchronization.
Data width: 1
Value range: 0 ... 227-1

m<ModuleNumber>_intercom_<ChannelNumber>_data_sent_v / Data
Sent Outputs the data already transmitted to the inter‑FPGA communication
bus. The module number reflects the used I/O module slot. The channel number
reflects one of eight configurable subbuses.
Usable only for inter-FPGA communication buses with bus synchronization.
Data width: 1
Value range: 0 ... 227-1

m<ModuleNumber>_intercom_<ChannelNumber>_ready /
Ready Signals the clock cycle in which the data to be transmitted is sampled.
The port is available only for synchronized buses.
The port is high for one clock cycle with the periodicity of the bit length.
Usable only for inter-FPGA communication buses with bus synchronization.
Data width: 1

I/O mapping No external connection to the I/O connector of the board. The SCALEXIO FPGA
base board uses its I/O module slots inside the SCALEXIO system for inter-FPGA
communication.

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Overview of Inter-FPGA Communication (FPGA Programming Handcode Framework

Guide )

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I/O Functions of the FPGA1401Tp1 with Multi-I/O Module Frameworks

I/O Functions of the FPGA1401Tp1 with Multi-I/O

Module Frameworks

Introduction The FPGA1401Tp1 frameworks provide the standard I/O functionality of

MicroAutoBox II with DS1552 (FPGA1401Tp1_DS1552_XC7K325T) or with
DS1552B1 Multi-I/O Module (FPGA1401Tp1_DS1552B1_XC7K325T).

Where to go from here Information in this section

ADC (Type A)......................................................................................... 325

To read data from an analog input signal in the FPGA application using
the Type A conversion function.

ADC (Type B)......................................................................................... 326

To read data from an analog input signal in the FPGA application using
the Type B conversion function.

Buffer In................................................................................................ 328

To read data from an intermodule-bus buffer with a data width of
32 bits.

Buffer64 In............................................................................................ 329

To read data from an intermodule-bus buffer with a data width of
64 bits.

Buffer Out............................................................................................. 331

To write data to an intermodule-bus buffer with a data width of 32 bits.

Buffer64 Out......................................................................................... 333

To write data to an intermodule-bus buffer with a data width of 64 bits.

DAC...................................................................................................... 335
To write data to an analog output signal in the FPGA application.

Digital Crank/Cam Sensor...................................................................... 336

To provide bit-wise read access to digital camshaft and crankshaft
sensors.

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Digital In (Type A).................................................................................. 338

To read data from a digital input signal in the FPGA application using a
digital input channel.

Digital In (Type B)................................................................................... 340

To read data from a digital input signal in the FPGA application using a
digital bidirectional channel.

Digital Out (Type A)............................................................................... 341

To write data to a digital output signal in the FPGA application using a
digital output channel.

Digital Out (Type B)................................................................................ 343

To write data to a digital output signal in the FPGA application using a
digital bidirectional channel.

Inductive Zero Voltage Detector............................................................. 345

To provide read access to an inductive zero voltage detector.

Interrupt................................................................................................ 346
To request a processor interrupt outside of the FPGA application.

LED Out................................................................................................. 347

To write a digital signal that controls the FPGA status LED near the
DS1514 ZIF I/O connector.

Register In............................................................................................. 347

To read data from an intermodule-bus register with a data width of
32 bits.

Register64 In......................................................................................... 349

To read data from an intermodule-bus register with a data width of
64 bits.

Register Out.......................................................................................... 351

To write data to an intermodule-bus register with a data width of 32 bits.

Register64 Out...................................................................................... 352

To write data to an intermodule-bus register with a data width of 64 bits.

Sensor Supply........................................................................................ 354

To provide a supply voltage at a connected sensor.

Status In................................................................................................ 355

To read digital signals that outputs state information, e.g.: state of the
FPGA initialization sequence or the FPGA die temperature.

UART (RS232)........................................................................................ 356

To implement communication via serial interface for RS232 UART type.

UART (RS422/485)................................................................................. 361

To implement communication via serial interface for RS422/485 UART
type.

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ADC (Type A)

ADC (Type A)

Purpose To read data from an analog input signal in the FPGA application using the Type
A conversion function.

Description According to the number of physical connections available on the DS1552 Multi-
I/O Module, you can select the ADC (Type A) I/O functions. There are eight
analog input channels.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 26 … 33.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 7.

hq_adc_<ChannelNumber>_data / Data Outputs the current results of the

A/D conversions on the current channel.
Range: 0 … +65535
Update rate: 1 Msps

hq_adc_<ChannelNumber>_soc / Start of conversion Lets you trigger the

start of an A/D conversion on the specified channel. When the value is set to
1 for at least one clock cycle, the ADC starts the conversion. The port allows a
precise definition of the starting point of ADC sampling. The Data_eoc outport
signals the end of the conversion process.
Setting this value permanently to 1 results in continuous sampling.

hq_adc_<ChannelNumber>_eoc / End of conversion Outputs an end of

conversion signal if the conversion result is available on the specified channel. If
the flag changes from 0 to 1, the ADC data contains a new value. The flag is set
to 1 for only one clock cycle.

I/O mapping The following I/O mapping is relevant if you use a FPGA1401Tp1 framework
for analog input channels using the Type A conversion function. The signals are
available at the DS1514 ZIF I/O connector.

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ADC (Type B).......................................................................................................................... 326

DAC....................................................................................................................................... 335
Overview of the Frameworks Available for MicroAutoBox II (FPGA1401Tp1)............................. 34

ADC (Type B)

Purpose To read data from an analog input signal in the FPGA application using the Type
B conversion function.

Description According to the number of physical connections available on the DS1552 Multi-
I/O Module, you can select the ADC (Type B) I/O functions. There are 16 analog
output channels.

This I/O function is not considered when you generate the processor interface
model.

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ADC (Type B)

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 34 … 49.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 15.

lq_adc_<ChannelNumber>_data / Data Outputs the current results of the

A/D conversions on the current channel in the range ‑32768 … +32767.
Update rate: 0.2 Msps

I/O mapping The following I/O mapping is relevant if you use a FPGA1401Tp1 framework
for analog input channels using the Type B conversion function. The signals are
available at the DS1514 ZIF I/O connector.

ADC (Type A).......................................................................................................................... 325

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Buffer In

Purpose To read data from an intermodule-bus buffer with a data width of 32 bits.

Description If you select Buffer as the access type, the data is read from an intermodule-bus
buffer. 32 buffers are available. Each buffer has a variable buffer size of 1 up to
32768 elements. Each buffer element has a data width of 32 bits.

If you generate the processor interface model for this FPGA I/O function,
a PROC_XDATA_WRITE_BL block is added to the processor model with the
configured data formats.

Parameters The I/O function number can be specified in the range 129 … 160.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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Buffer64 In

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmemf_<ChannelNumber>_count / Data Count Outputs the number of

elements in the current buffer. The maximum range depends on the specified
buffer size. You can use the value to define the valid range for the Address
inport of 0 … (Data Count -1).

xmemf_<ChannelNumber>_dout / Data Outputs a 32-bit data value to be

read from an intermodule-bus buffer. The data format depends on the related
parameter settings.

xmemf_<ChannelNumber>_new_data / Data New Outputs a flag that

xmemf_<ChannelNumber>_addr / Address Specifies an element in the

Buffer Out.............................................................................................................................. 331

Overview of the Frameworks Available for MicroAutoBox II (FPGA1401Tp1)............................. 34
Register In.............................................................................................................................. 347

Buffer64 In

Purpose To read data from an intermodule-bus buffer with a data width of 64 bits.

Description If you select Buffer64 as the access type, the data is read from an intermodule-
bus buffer. 32 buffers are available. Each buffer has a variable buffer size of 1 up
to 32768 elements. Each buffer element has a data width of 64 bits.

If you generate the processor interface model for this FPGA I/O function,
a PROC_XDATA_WRITE_BL block is added to the processor model with the
configured data formats.

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Parameters The I/O function number can be specified in the range 289 … 320.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(2).Init /
Format Lets you specify the data format of the Data outport.
§ signed/unsigned
The values of the Data outport are in fixed‑point format with or without one
bit reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
§ floating‑point
The values of the Data outport are in floating‑point format.
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is provided by the Binary point position (or fraction
width) setting.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmemf64_<ChannelNumber>_count / Data Count Outputs the number of

elements in the current buffer. The maximum range depends on the specified
buffer size. You can use the value to define the valid range for the Address
inport of 0 … (Data Count -1).

xmemf64_<ChannelNumber>_dout / Data Outputs a 64-bit data value to

be read from an intermodule-bus buffer. The data format depends on the related
parameter settings.

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Buffer Out

xmemf64_<ChannelNumber>_new_data / Data New Outputs a flag that

xmemf64_<ChannelNumber>_addr / Address Specifies an element in the

Buffer64 Out.......................................................................................................................... 333

Overview of the Frameworks Available for MicroAutoBox II (FPGA1401Tp1)............................. 34
Register64 In.......................................................................................................................... 349

Buffer Out

Purpose To write data to an intermodule-bus buffer with a data width of 32 bits.

Description If you select Buffer as the access type, the data is written to an intermodule-bus
buffer. 32 buffers are available. Each buffer has a variable buffer size of 1 up to
32768 elements. Each buffer element has a data width of 32 bits.

If you generate the processor interface model for this FPGA I/O function,
a PROC_XDATA_READ_BL block is added to the processor model with the
configured data formats.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 129 … 160.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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§ signed/unsigned
The values of the Data inport are in fixed-point format. You can specify the
binary point position of the 32 bit value in the range 0 … 32.
0 represents the lowest bit position, 32 the highest bit position.
§ floating-point
The values of the Data inport are in floating‑point format. The parameter then
provides the fraction width.

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Buffer
size Lets you specify the size of the buffer in the range 1 … 32768.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmemp_<ChannelNumber>_din / Data Specifies a 32-bit data value to be

written to an intermodule-bus buffer. The data format depends on the related
parameter settings.

xmemp_<ChannelNumber>_write / Enable Specifies the current valid Data

port value.
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.

xmemp_<ChannelNumber>_finished / Ready Explicitly specifies the buffer

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Buffer64 Out

The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.

xmemp_<ChannelNumber>_overflow / Overflow Outputs a flag that

Buffer In................................................................................................................................. 328

Overview of the Frameworks Available for MicroAutoBox II (FPGA1401Tp1)............................. 34
Register Out........................................................................................................................... 351

Buffer64 Out

Purpose To write data to an intermodule-bus buffer with a data width of 64 bits.

Description If you select Buffer64 as the access type, the data is written to an intermodule-
bus buffer. 32 buffers are available. Each buffer has a variable buffer size of 1 up
to 32768 elements. Each buffer element has a data width of 64 bits.

If you generate the processor interface model for this FPGA I/O function,
a PROC_XDATA_READ_BL block is added to the processor model with the
configured data formats.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 289 ... 320.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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§ floating-point
The values of the Data inport are in floating‑point format. The parameter then
provides the fraction width.

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Buffer
size Lets you specify the size of the buffer in the range 1 … 32768.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmemp64_<ChannelNumber>_din / Data Specifies a 64-bit data value to

be written to an intermodule-bus buffer. The data format depends on the related
parameter settings.

xmemp64_<ChannelNumber>_write / Enable Specifies the current valid

Data port value.
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.

xmemp64_<ChannelNumber>_finished / Ready Explicitly specifies the

buffer state as ready to send the buffer immediately, even if it is not completely
filled. The data values will be written to a new buffer in the next clock cycle.
While the port value is 1, transmission switches buffer in every clock cycle. The
value should therefore be set for one clock cycle only. If the buffer is completely
filled, it is automatically switched, and the data values are stored in a new buffer.
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready for sending, even if it is not completely filled.
The buffer is switched and the data values are accessible via intermodule bus
in the next clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.

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DAC

xmemp64_<ChannelNumber>_overflow / Overflow Outputs a flag that

Buffer64 In............................................................................................................................. 329

Overview of the Frameworks Available for MicroAutoBox II (FPGA1401Tp1)............................. 34
Register64 Out....................................................................................................................... 352

DAC

Purpose To write data to an analog output signal in the FPGA application.

Description According to the number of physical connections available on the DS1552 Multi-
I/O Module, you can select the DAC I/O functions. There are four analog output
channels.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 26 … 29.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 3.

dac<ChannelNumber>_data / Data Outputs a signal in the range 0

… +65535.
Range exceeding is possible and will be saturated to the minimum or maximum
value.
Hardware update rate: 2.1 Msps (if the values are updated at a higher FPGA
model rate, intermediate values are not updated by the DAC).

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I/O mapping The following I/O mapping is relevant if you use a FPGA1401Tp1 framework
for analog output channels. The signals are available at the DS1514 ZIF I/O
connector.

Inport Channel Connector Pin Signal

Data 1 c2 AnalogOut ch 1
2 c3 AnalogOut ch 2
3 c4 AnalogOut ch 3
4 c5 AnalogOut ch 4

ADC (Type A).......................................................................................................................... 325

ADC (Type B).......................................................................................................................... 326
Overview of the Frameworks Available for MicroAutoBox II (FPGA1401Tp1)............................. 34

Digital Crank/Cam Sensor

Purpose To provide bit-wise read access to digital camshaft and crankshaft sensors. Each
channel is 1 bit wide.

Description According to the number of physical connections available on the DS1552 Multi-
I/O Module, you can select the Digital Crank/Cam Sensor I/O functions. There
are three input channels.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 50 … 52.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.In.Fct(<IOFunctionNumber>).Parameter(1).Init / Low
threshold voltage To set the low threshold level for the selected digital input

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Digital Crank/Cam Sensor

channel. Below this level a logical 0 is detected, above this level a logical 1 is
detected, if the high threshold voltage was crossed before.
§ Range:
‑40000 mV … +40000 mV
§ Resolution:
20 mV
§ Default:
1000 mV

IOProperties.In.Fct(<IOFunctionNumber>).Parameter(2).Init / High
threshold voltage To set the high threshold level for the selected digital
input channel. The logical 1 is output, if this level is crossed and stays 1 until the
signal falls below the low threshold level.
§ Range:
‑40000 mV … +40000 mV
§ Resolution:
100 mV
§ Default:
1000 mV

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 2.

cam_<ChannelNumber> / Data Data type: UFix_1_0

§ 0: The input signal is lower than the Low threshold voltage parameter.
§ 1: The input signal is higher than the High threshold voltage parameter.
Update rate: 80 MHz

I/O mapping The following I/O mapping is relevant if you use a FPGA1401Tp1 framework for
analog input channels. Depending on the MicroAutoBox variant the signals are
available at the DS1514 ZIF I/O connector.

Outport Channel Connector Pin Signal

Data 1 R3 CrankCam+ ch 1
R4 CrankCam– ch 1
2 B3 CrankCam+ ch 2
B4 CrankCam– ch 2
3 A3 CrankCam+ ch 3
A4 CrankCam– ch 3

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Overview of the Frameworks Available for MicroAutoBox II (FPGA1401Tp1)............................. 34

Digital In (Type A)

Purpose To read data from a digital input signal in the FPGA application using a digital
input channel.

Description According to the number of physical connections available on the DS1552 Multi-
I/O Module, you can select the Digital In (Type A) I/O functions. There are 16
digital input channels.

The threshold level is fix:

§ 3.6 V for low-high transition
§ 1.2 V for high-low transition

Note

If you use the same digital channel for the input and the output, the I/O
driver is internally set to InOut mode. As a consequence, the maximum
input voltage for the digital input channel is equal to the specified high
supply, and the applicable threshold voltage is lower than the specified high
supply.
To use the maximum input voltage range, you have to use a digital channel
only as the input.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 2 … 17.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 15.

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Digital In (Type A)

dig_<ChannelNumber>_in / Data Outputs the current results of digital

input channel.
§ 0: Input voltage of the channel is below the threshold voltage of a high-low
transition.
§ 1: Input voltage of the channel is higher than or equal to the threshold voltage
of a low-high transition.
Update rate: 80 MHz

Note

§ The frequency that can be detected is much smaller than the update rate.
For information on the electrical characteristics of the DS1552 Multi‑I/O
Module, refer to Digital Inputs (MicroAutoBox II Hardware Reference ).
§ Asynchronous input data might lead to metastable register states. Further
synchronization techniques might be necessary.

I/O mapping The following I/O mapping is relevant if you use a FPGA1401Tp1 framework for
digital input channels. The signals are available at the DS1514 ZIF I/O connector.

Digital In (Type B).................................................................................................................... 340

Digital Out (Type A)................................................................................................................ 341
Overview of the Frameworks Available for MicroAutoBox II (FPGA1401Tp1)............................. 34

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Digital In (Type B)

Purpose To read data from a digital input signal in the FPGA application by using a digital
bidirectional channel.

Description According to the number of physical connections available on the DS1552 Multi-
I/O Module, you can select the Digital In (Type B) I/O functions. There are eight
digital input channels.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 18 … 25.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.In.Fct(<IOFunctionNumber>).Parameter(1).Init / Threshold
voltage Lets you specify the threshold level for the current digital channel
in the range 1000 mV … 7500 mV in steps of 100 mV. If the input signal is
below this level, a logical 0 is detected, otherwise a logical 1.
§ 1000: 1000 mV threshold level
§ …
§ 7500: 7500 mV threshold level

Note

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 07.

bidir_<ChannelNumber>_in / Data Outputs the current results of digital

input channel.
§ 0: Input voltage of the channel is below the specified threshold voltage.
§ 1: Input voltage of the channel is higher than or equal to the specified
threshold voltage.

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Digital Out (Type A)

Update rate: 80 MHz

Note

§ The frequency that can be detected is much smaller than the update
rate. For information on the electrical characteristics of the DS1552 Multi-
I/O Module, refer to Digital I/O (Bidirectional) (MicroAutoBox II Hardware
Reference ).
§ Asynchronous input data might lead to metastable register states. Further
synchronization techniques might be necessary.

I/O mapping The following I/O mapping is relevant if you use a FPGA1401Tp1 framework
for digital bidirectional channels. The signals are available at the DS1514 ZIF I/O
connector.

You can use the same digital channel for input and output signals.

Digital In (Type A)................................................................................................................... 338

Digital Out (Type B)................................................................................................................. 343
Overview of the Frameworks Available for MicroAutoBox II (FPGA1401Tp1)............................. 34

Digital Out (Type A)

Purpose To write data to a digital output signal in the FPGA application using a digital
output channel.

Description According to the number of physical connections available on the DS1552 Multi-
I/O Module, you can select the Digital Out (Type A) I/O functions. There are 16
digital output channels.

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The voltage range for the high side switch for all digital output channels is in the
range 0 V … 45 V.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 2 … 17.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 15.

dig_<ChannelNumber>_out / Data Outputs a signal in the specified range.

If driven with 0, the hardware output is 0 V. If driven with 1, the hardware
output is set to the specified high supply voltage (VDRIVE). The hardware output
is only driven if the Enable port is set to 1, otherwise the output is set to high
impedance (High‑Z).
Update rate: 80 MHz

Note

The frequency that can be generated is much smaller than the update rate.
For information on the electrical characteristics of the DS1552 Multi-I/O
Module, refer to Digital Outputs (MicroAutoBox II Hardware Reference ).

dig_<ChannelNumber>_oe / Enable Controls the hardware output. If set to

1, the hardware output reacts to the Data outport, otherwise it is set to High‑Z.

I/O mapping The following I/O mapping is relevant if you use a FPGA1401Tp1 framework
for digital output channels. The signals are available at the DS1514 ZIF I/O
connector.

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Digital Out (Type B)

Digital In (Type A)................................................................................................................... 338

Digital Out (Type B)

Purpose To write data to a digital output signal in the FPGA application by using a digital
bidirectional channel.

Description According to the number of physical connections available on the DS1514 Multi-
I/O Module, you can select the Digital Out (Type B) I/O functions. There are
eight digital output channels.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 18 … 25.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.Out.Fct(18).Parameter(1).Init / High supply Lets you select

the voltage for the high side switch for all digital output channels.
§ 0: 3.3 V
§ 1: 5 V

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Note

You can specify the high supply voltage value only globally for all digital
output channels.
The I/O function number must be specified as 18.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 07.

bidir_<ChannelNumber>_out / Data Outputs a signal in the specified

range. If driven with 0, the hardware output is 0 V. If driven with 1, the hardware
output is 3.3 V or 5 V according to the specified high supply voltage. The
hardware output is only driven if the Enable port is set to 1, otherwise the
output is set to high impedance (High‑Z).
Update rate: 80 MHz

Note

The frequency that can be generated is smaller than the update rate.
For information on the electrical characteristics of the DS1552 Multi-I/O
Module, refer to Digital I/O (Bidirectional) (MicroAutoBox II Hardware
Reference ).

bidir_<ChannelNumber>_oe / Enable Controls the hardware output. If set

to 1, the hardware output reacts to the Data outport, otherwise it is set to
High‑Z.

I/O mapping The following I/O mapping is relevant if you use a FPGA1401Tp1 framework
for digital bidirectional channels. The signals are available at the DS1514 ZIF I/O
connector.

You can use the same digital channel for input and output signals.

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Inductive Zero Voltage Detector

Digital In (Type B).................................................................................................................... 340

Inductive Zero Voltage Detector

Purpose To provide read access to an inductive zero voltage detector.

Description The FPGA1401Tp1 frameworks provide one channel for the Inductive Zero
Voltage Detector I/O function.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 53.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

crank / Data To detect the zero crossing points of the analog signals. If a zero
crossing from positive to negative is detected, the output signal is 1 for 1 clock
cycle.
Data type: UFix_1_0
§ 0: No zero crossing.
§ 1: Zero crossing is detected.
Update rate: 80 MHz

I/O mapping The following I/O mapping is relevant if you use a FPGA1401Tp1 framework for
analog input channels. The signals are available at the DS1514 ZIF I/O connector.

Outport Connector Pin Signal

Data P3 ZeroDetection+
P4 ZeroDetection–

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Overview of the Frameworks Available for MicroAutoBox II (FPGA1401Tp1)............................. 34

Interrupt

Purpose To request a processor interrupt outside of the FPGA application.

Description The FPGA1401Tp1 frameworks provide 8 interrupt lines. An interrupt is

requested if the Int port is set to 1 for at least one clock cycle. If you set
the Int port to 0, the last interrupt is not released but saved. An interrupt is
edge-triggered.

If you generate the processor interface model for this FPGA I/O function, a
PROC_INT_BL block is added to the processor model with the configured data
formats.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 8.

IRQProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 7.

usr_<ChannelNumber>_interrupt / Int Provides the interrupt request line.

§ 0 to 1: Interrupt is requested (edge-triggered).
§ 0: No interrupt is requested. Last requested interrupt is saved.

Overview of the Frameworks Available for MicroAutoBox II (FPGA1401Tp1)............................. 34

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LED Out

LED Out

Purpose To write a digital signal that controls the FPGA status LED.

You can find the FPGA status LED near the DS1514 ZIF I/O connector.

Description The FPGA1401Tp1 frameworks provide one channel for the LED Out I/O
function.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 1.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

led_out / Data Controls the Status LED on the board's bracket.

§ 0: LED lights green.
§ 1: LED lights orange.

Overview of the Frameworks Available for MicroAutoBox II (FPGA1401Tp1)............................. 34

Purpose To read data from an intermodule-bus register with a data width of 32 bits.

Description If you select Register as the access type, the data is read from an intermodule-
bus register. 128 registers are available with a data width of 32 bits each. The
values are transmitted element by element. If you want to access data from
several registers simultaneously, you can group these registers by specifying the
same group identifier for them.

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If you generate the processor interface model for this FPGA I/O function,
a PROC_XDATA_WRITE_BL block is added to the processor model with the
configured data formats.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 128.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(3).Init / Register
group ID Lets you specify a number in the range 1 … 63 to create
register groups. Registers that you specified with the same group ID are
sampled simultaneously within the FPGA application. The values therefore form a
consistent data group that is written to the intermodule bus.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

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Register64 In

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 127.

xreg_<ChannelNumber>_dout / Data Outputs a 32-bit data value to be

read from an intermodule-bus register. The data format depends on the related
parameter settings.

xreg_<ChannelNumber>_dout_wr / Data New Outputs a flag that

indicates the changes of the register status. If the flag changes from 0 to 1
and then back to 0, the requested register contains a new value. The flag is set
to 1 only within one clock cycle.

Buffer In................................................................................................................................. 328

Register64 In

Purpose To read data from an intermodule-bus register with a data width of 64 bits.

Description If you select Register64 as the access type, the data is read from an
intermodule-bus register. 128 registers are available with a data width of 64 bits
each. The values are transmitted element by element. If you want to access data
from several registers simultaneously, you can group these registers by specifying
the same group identifier for them.

If you generate the processor interface model for this FPGA I/O function,
a PROC_XDATA_WRITE_BL block is added to the processor model with the
configured data formats.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 161 … 288.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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§ signed/unsigned
The values of the Data outport are in fixed-point format. You can specify the
binary point position of the 64-bit value in the range 0 … 64.
0 represents the lowest bit position, 64 the highest bit position.
64-bit fixed-point data types are converted to double. Therefore, the fixed-
point resolution of fixed-point data types is restricted to 53 bits.
§ floating-point
The values of the Data outport are in floating‑point format. The parameter
then provides the fraction width.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(2).Init /
Format Lets you specify the data format of the Data outport.
§ signed/unsigned
The values of the Data outport are in fixed‑point format with or without one
bit reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
§ floating‑point
The values of the Data outport are in floating‑point format.
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is provided by the Binary point position (or fraction
width) setting.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(3).Init / Register
group ID Lets you specify a number in the range 1 … 63 to create
register groups. Registers that you specified with the same group ID are
sampled simultaneously within the FPGA application. The values therefore form a
consistent data group that is written to the intermodule bus.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 127.

xreg64_<ChannelNumber>_dout / Data Outputs a 64-bit data value to be

read from an intermodule-bus register. The data format depends on the related
parameter settings.

xreg64_<ChannelNumber>_dout_wr / Data New Outputs a flag that

indicates the changes of the register status. If the flag changes from 0 to 1
and then back to 0, the requested register contains a new value. The flag is set
to 1 only within one clock cycle.

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Register Out

Buffer64 In............................................................................................................................. 329

Purpose To write data to an intermodule-bus register with a data width of 32 bits.

Description If you select Register as the access type, the data is written to an intermodule-
bus register. 128 registers are available with a data width of 32 bits each. The
values are transmitted element by element. If you want to access data from
several registers simultaneously, you can group these registers by specifying the
same group identifier for them.

If you generate the processor interface model for this FPGA I/O function,
a PROC_XDATA_READ_BL block is added to the processor model with the
configured data formats.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 128.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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You can specify the binary point position in the Binary point position (or
fraction width) setting.
§ floating‑point
The values of the Data inport are in floating‑point format.
The 32‑bit data value supports the single-precision floating‑point format with a
fraction width of 24, which complies with the IEEE 754 standard (single).
The fraction width is provided by the Binary point position (or fraction
width) setting.

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Register
group ID Lets you specify a number in the range 1 … 63 to create register
groups. Registers that you specified with the same group ID are read from
the intermodule bus sequentially and then provided to the FPGA application
simultaneously.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 127.

xreg_<ChannelNumber>_din / Data Specifies a 32-bit data value to be

written to an intermodule-bus register. The data format depends on the related
parameter settings.

Buffer Out.............................................................................................................................. 331

Register64 Out

Purpose To write data to an intermodule-bus register with a data width of 64 bits.

Description If you select Register64 as the access type, the data is written to an
intermodule-bus register. 128 registers are available with a data width of 64 bits
each. The values are transmitted element by element. If you want to access data
from several registers simultaneously, you can group these registers by specifying
the same group identifier for them.

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Register64 Out

If you generate the processor interface model for this FPGA I/O function,
a PROC_XDATA_READ_BL block is added to the processor model with the
configured data formats.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 161 … 288.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Register
group ID Lets you specify a number in the range 1 … 63 to create register
groups. Registers that you specified with the same group ID are read from
the intermodule bus sequentially and then provided to the FPGA application
simultaneously.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

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Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 127.

xreg64_<ChannelNumber>_din / Data Specifies a 64-bit data value to be

written to an intermodule-bus register. The data format depends on the related
parameter settings.

Buffer64 Out.......................................................................................................................... 333

Sensor Supply

Purpose To provide a supply voltage, for example, for a connected sensor, in the range
2000 mV … 20000 mV in steps of 100 mV.

Description The FPGA1401Tp1 frameworks provide one channel for the Sensor Supply I/O
function.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 30.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(1).Init / Supply
voltage Lets you specify the supply voltage a connected sensor is to be driven
with in the range 2000 mV … 20000 mV in steps of 100 mV.

Port There is no port to be specified.

I/O mapping The following I/O mapping is relevant if you use a FPGA1401Tp1 framework for
for sensor supply. The signals are available at the DS1514 ZIF I/O connector.

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Status In

Outport Channel Connector Pin Signal

Sim_Data 1 b6 VS-
c6 VS+

Overview of the Frameworks Available for MicroAutoBox II (FPGA1401Tp1)............................. 34

Status In

Purpose To read digital signals that outputs state information, e.g.: state of the FPGA
initialization sequence or the FPGA die temperature.

Description The FPGA1401Tp1 framework provides one channel for the Status In I/O
function.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 1.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

init_done/ Init Done Outputs the state of the initialization sequence that is
started after programming the FPGA.
§ 0: Initialization sequence is in progress.
§ 1: Initialization sequence has finished.

temperature / Temperature Outputs the raw value of the FPGA's die

temperature measurement. Use the 12 MSB bits to calculate the die
temperature.
Equation to calculate the die temperature:
Temperature [°C] = (float)(Temperature[hex] & 0xFFF0) ·
503.975 / 65536 - 273.15
Data type: UFix_16_0
Data width: 1

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Value range: 0 ... 65536

high_temp / High Outputs a flag if the FPGA's die temperature exceeds

105 °C.
To reset the flag, the die temperature must fall below 85 °C.
Data type: UFix_1_0
§ 0: Die temperature does not exceed 105 °C.
§ 1: Die temperature exceeds 105 °C.

Note

A high ambient temperature and an FPGA application with a very high

FPGA utilization and/or toggle rate increase the FPGA die temperature
(internal chip temperature). If the die temperature exceeds 105 °C, the
FPGA might work incorrectly.
You can decrease the temperature by reducing the FPGA's toggle rate (e.g.,
by using clock enable) or by reducing the utilization of the FPGA resources.
If the die temperature exceeds 125 °C, the FPGA resets itself. The reset
stays active until the die temperature falls below 85 °C and you restart
MicroAutoBox II or reload the user application.

Overview of the Frameworks Available for MicroAutoBox II (FPGA1401Tp1)............................. 34

UART (RS232)

Purpose To implement communication via serial interface for RS232 UART type.

Description According to the number of physical connections available on the DS1552 Multi-
I/O Module, you can select the UART (RS232) I/O functions. There are two
interfaces.

Note

UART 1 can be used without modification. To use UART 2, your DS1552 has
to be modified by dSPACE.

This I/O function is not considered when you generate the processor interface
model.

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UART (RS232)

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 31 … 32.

Most of the parameters are used for the UART (RS232) and UART (RS422/485)
I/O functions.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(1).Init / Baud
rate Lets you specify the baud rate of the UART in the range 50 … 1,000,000
baud (bits per second).
The baud rate depends on the parameters 2, 3, 4 and the FPGA board, and can
be calculated by the following formula:
BaudRate = (10^8 · uart_x_dcm_m) / (2 · uart_x_dcm_d
· (uart_dcm_clk_divider+1))
With:

Variable Parameter Description

Note

Limitations:
§ The maximum baud rate of 1,000,000 baud must not be exceeded.
§ The output frequency of the digital clock manager (DCM) module should
be between 40 MHz and 160 MHz:
fDCM = 200 MHz · uart_x_dcm_m / uart_x_dcm_d

Tip

In the framework folder you find a MATLAB file that provides some
calculated baud rates and the percentage deviations to the supported baud
rates according to the parameters m, d and the clock divider.
§ Framework folder:
<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\FPGA
1401Tp1_<Multi_I/O_Module_type>_<FPGA_type>
§ MATLAB file name: FPGA1401Tp1_XC7K325T_uart_parameters.mat

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IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(6).Init / Stop
bits Lets you specify the length of the stop bits in half of bits.

Stop Bits Parameter Value

1 2
1.5 3
2 4

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(7).Init / UART
type Lets you specify the UART type.

Value UART Type

0 RS232
1 RS422/485

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(8).Init /
Termination Lets you specify the termination state.

Note

For the RS232 UART type, the termination must be set to 0 (disconnected).

Value Termination State Description

0 Disconnected § The RX/CTS and TX/RTS signals are not terminated.
1 Connected § Not allowed

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 1.

uart_<ChannelNumber>_rd / Read Enable Specifies to start receiving a

uart_<ChannelNumber>_rd_data_count / Read Data Count Outputs the

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UART (RS232)

uart_<ChannelNumber>_rd_fifo_empty / Read Fifo Empty Outputs the

uart_<ChannelNumber>_rd_data / Read Data Outputs the last read data

uart_<ChannelNumber>_wr / Write Enable Specifies to start sending a

value.
The Write_Data value is written to the TX FIFO buffer, from which it is
automatically send to the TX output pin of the I/O connector using the specified
UART communication settings.
Write_Enable must be set to 1 for only one clock cycle.
Before you write data to the TX FIFO buffer, you should check the
Write_Fifo_Full signal not to be set. The Write_Fifo_Full signal switches one
clock cycle after the Write_Enable signal has been set.
Do not use the Write_Data_Count signal (Write_Data_Count < 2047) to check
the TX FIFO buffer, because it requires one additional clock cycle to get the count
value.
The hardware output port is driven with the values from the TX FIFO buffer. It
is synchronously running to the UART clock defined by the UART baudrate. The
hardware port has inverted voltage levels of ‑6 V (logical high) and +6 V (logical
low).

uart_<ChannelNumber>_wr_data_count / Write Data Count Outputs the

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uart_<ChannelNumber>_wr_fifo_full / Write Fifo Full Outputs the status

uart_<ChannelNumber>_wr_data / Write Data Specifies the value to be

send.
The Write_Data signal is transferred at each clock cycle with Write_Enable set
to 1.
Range: 0 … 511

uart_<ChannelNumber>_rts / RTS Specifies the Ready‑To‑Send (RTS) signal.

The RTS/CTS handshake is handled by the user, the RTS signal is just passed
through and adapted to the physical layer.
The hardware port is synchronously running to the UART clock defined by the
UART baudrate. The hardware port has voltage levels of +6 V (active, logical
high) and ‑6 V (inactive).

uart_<ChannelNumber>_cts / CTS Outputs the state of the Clear‑To‑Send

(CTS) hardware port.
RTS/CTS handshake is handled by the user. CTS is just passed through with
conversion to logical 1 and 0.
Range:
§ 0: CTS inactive
§ 1: CTS active
The CTS hardware port is synchronously running to the UART clock defined by
the UART baudrate. The hardware port has voltage levels of +6 V (active, logical
high) and ‑6 V (inactive).

I/O mapping The following I/O mapping is relevant if you use a FPGA1401Tp1 framework for
serial communication using the UART (RS232) function. The signals are available
at the DS1514 ZIF I/O connector.

Inport Connector Pin Signal

UART 1 (RS232)
Write_Data a5 TX1
RTS a6 RTS1
Read_Data b5 RX1
CTS a4 CTS1
UART 2 (RS232)1)
Write_Data Z5 TX2
RTS Z6 RTS2

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UART (RS422/485)

Inport Connector Pin Signal

Read_Data Z3 RX2
CTS Z4 CTS2
1) To use UART 2, your DS1552 has to be modified by dSPACE.

Overview of the Frameworks Available for MicroAutoBox II (FPGA1401Tp1)............................. 34

UART (RS422/485).................................................................................................................. 361

UART (RS422/485)

Purpose To implement communication via serial interface for RS422/485 UART type.

Description According to the number of physical connections available on the DS1552 Multi-
I/O Module, you can select the UART (RS422/485) I/O functions. There are two
interfaces.

Note

UART 1 can be used without modification. To use UART 2, your DS1552 has
to be modified by dSPACE.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 33 … 34.

Most of the parameters are used for the UART (RS232) and UART (RS422/485)
I/O functions.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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With:

Variable Parameter Description

Tip

In the framework folder you find a MATLAB file providing some calculated
baud rates and the percentage deviations to the supported baud rates
according to the parameters m, d and the clock divider.
§ Framework folder:
<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\FPGA
1401Tp1_<Multi_I/O_Module_type>_<FPGA_type>
§ MATLAB file name: FPGA1401Tp1_XC7K325T_uart_parameters.mat

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(6).Init / Stop
bits Lets you specify the length of the stop bits in half of bits.

Stop Bits Parameter Value

1 2
1.5 3
2 4

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(7).Init / UART
mode Lets you specify the mode when using the RS422/485 UART type.

Value UART Mode

0 Full‑duplex mode
1 Half‑duplex mode

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(8).Init / UART
type Lets you specify the UART type.

Value UART Type

0 RS232
1 RS422/485

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UART (RS422/485)

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(9).Init /
Termination Lets you specify the termination state.

Value Termination State Description

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 1.

uart_<ChannelNumber>_rd / Read Enable Specifies to start receiving a

uart_<ChannelNumber>_rd_data_count / Read Data Count Outputs the

uart_<ChannelNumber>_rd_fifo_empty / Read Fifo Empty Outputs the

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Range:
§ 0: The RX FIFO buffer is not empty.
§ 1: The RX FIFO buffer is empty.

uart_<ChannelNumber>_rd_data / Read Data Outputs the last read data

uart_<ChannelNumber>_wr / Write Enable Specifies to start sending a

uart_<ChannelNumber>_wr_data_count / Write Data Count Outputs the

uart_<ChannelNumber>_wr_fifo_full / Write Fifo Full Outputs the status

uart_<ChannelNumber>_wr_data / Write Data Specifies the value to be

send.
The Write_Data signal is transferred at each clock cycle with Write_Enable set
to 1.

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UART (RS422/485)

Range: 0 … 511

uart_<ChannelNumber>_driver_en / Driver Enable Specifies to enable the

output driver in the transceiver for data transmission.
If you use the UART (RS485/422) function in half-duplex mode, the output driver
must be disabled while receiving data.

I/O mapping The following I/O mapping is relevant if you use a FPGA1401Tp1 framework
for serial communication using the UART (RS422/485) function. The signals are
available at the DS1514 ZIF I/O connector. The mapping differs when using the
UART (RS422/485) in full-duplex or half-duplex mode.

Full-duplex mode:

Inport Connector Pin Signal

UART 1 (RS422/485)
Write_Data a5 TX‑1
a6 TX+1
Read_Data b5 RX‑1
a4 RX+1
UART 2 (RS422/485)1)
Write_Data Z5 TX‑2
Z6 TX+2
Read_Data Z3 RX‑2
Z4 RX+2
1) To use UART 2, your DS1552 has to be modified by dSPACE.

Half-duplex mode:

Inport Connector Pin Signal

UART 1 (RS422/485)
Write_Data a5 BM1 (RX‑1/TX‑1)
a6 BP1 (RX+1/TX+1)
Read_Data b5 ‑1)
a4 ‑1)
UART 2 (RS422/485)2)
Write_Data Z5 BM2 (RX‑2/TX‑2)
Z6 BP2 (RX+2/TX+2)
Read_Data Z3 ‑1)
Z4 ‑1)
1)
Do not connect, TX signals are available via BM and BP signals.
2) To use UART 2, your DS1552 has to be modified by dSPACE.

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UART (RS232)......................................................................................................................... 356

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I/O Functions of the FPGA1401Tp1 with Engine Control I/O Module Framework

I/O Functions of the FPGA1401Tp1 with Engine

Control I/O Module Framework

Introduction The FPGA1401Tp1 (7K325) with Engine Control I/O Module (DS1554) provides
the I/O functionality of MicroAutoBox II with a DS1554 Engine Control I/O
Module.

Where to go from here Information in this section

ADC (Type A)......................................................................................... 368

To read data from an analog input signal in the FPGA application using
the Type A conversion function.

Buffer In................................................................................................ 370

To read data from an intermodule-bus buffer with a data width of
32 bits.

Buffer64 In............................................................................................ 372

To read data from an intermodule-bus buffer with a data width of
64 bits.

Buffer Out............................................................................................. 374

To write data to an intermodule-bus buffer with a data width of 32 bits.

Buffer64 Out......................................................................................... 376

To write data to an intermodule-bus buffer with a data width of 64 bits.

Digital Crank/Cam Sensor...................................................................... 378

To provide bit-wise read access to digital camshaft and crankshaft
sensors.

Digital In (Type B)................................................................................... 379

To read data from a digital input signal in the FPGA application using a
digital bidirectional channel.

Digital Out (Type A)............................................................................... 381

To write data to a digital output signal in the FPGA application using a
digital output channel.

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Digital Out (Type B)................................................................................ 383

To write data to a digital output signal in the FPGA application using a
digital bidirectional channel.

Inductive Zero Voltage Detector............................................................. 385

To provide read access to an inductive zero voltage detector.

Interrupt................................................................................................ 386
To request a processor interrupt outside of the FPGA application.

Knock Sensor........................................................................................ 387

To read data from a knock sensor in the FPGA application.

LED Out................................................................................................. 388

To write a digital signal that controls the FPGA status LED near the
DS1514 ZIF I/O connector.

Register In............................................................................................. 389

To read data from an intermodule-bus register with a data width of
32 bits.

Register64 In......................................................................................... 391

To read data from an intermodule-bus register with a data width of
64 bits.

Register Out.......................................................................................... 393

To write data to an intermodule-bus register with a data width of 32 bits.

Register64 Out...................................................................................... 394

To write data to an intermodule-bus register with a data width of 64 bits.

Status In................................................................................................ 396

To read digital signals that outputs state information, e.g.: state of the
FPGA initialization sequence.

Temperature.......................................................................................... 397
To read the FPGA die temperature.

ADC (Type A)

Purpose To read data from an analog input signal in the FPGA application by using the
Type A conversion function.

Description According to the number of physical connections available on the DS1554

Engine Control I/O Module, you can select the ADC (Type A) I/O functions.
There are 14 analog input channels.

This I/O function is not considered when you generate the processor interface
model.

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ADC (Type A)

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 10 … 23.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 13.

hq_adc_<ChannelNumber>_data / Data Outputs the current results of the

A/D conversions on the current channel.
Data type: UFix_16_0
Range: 0 … +65535
Update rate: 1 Msps

hq_adc_<ChannelNumber>_soc / Start of conversion Triggers the

sampling of the A/D converter. When the value is set to 1 for at least one clock
cycle, the ADC starts the conversion. The port allows a precise definition of the
starting point of ADC sampling. The End of conversion outport signals the
end of the conversion process.
Setting this value permanently to 1 results in continuous sampling.

hq_adc_<ChannelNumber>_eoc / End of conversion Outputs an end of

conversion signal if the conversion result is available on the specified channel. If
the flag changes from 0 to 1, the ADC data contains a new value. The flag is set
to 1 for only one clock cycle.
Data type: UFix_1_0
Range: 0 or 1

I/O mapping The following I/O mapping is relevant if you use the FPGA1401Tp1 (7K325) with
Engine Control I/O Module (DS1554) framework. The signals are available at the
DS1514 ZIF I/O connector.

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Buffer In

Purpose To read data from an intermodule-bus buffer with a data width of 32 bits.

If you generate the processor interface model for this FPGA I/O function,
a PROC_XDATA_WRITE_BL block is added to the processor model with the
configured data formats.

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Buffer In

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 129 … 160.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmemf_<ChannelNumber>_count / Data Count Outputs the number of

elements in the current buffer. The maximum range depends on the specified
buffer size. You can use the value to define the valid range for the Address
inport of 0 … (Data Count -1).

xmemf_<ChannelNumber>_dout / Data Outputs a 32-bit data value to be

read from an intermodule-bus buffer. The data format depends on the related
parameter settings.

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xmemf_<ChannelNumber>_new_data / Data New Outputs a flag that

xmemf_<ChannelNumber>_addr / Address Specifies an element in the

buffer you want to read. The block requires 1 clock cycle to update the value
of the Data outport according to the specified address. The maximum port
range depends on the specified buffer size. The valid port range depends on
the number of elements currently in the buffer. Refer to Data Count outport.
If you request data from an address that is greater than the Data Count value,
the output of the Data outport is undefined. The first element of a buffer is
addressed by 0.

Buffer Out.............................................................................................................................. 374

Buffer64 In

Purpose To read data from an intermodule-bus buffer with a data width of 64 bits.

If you generate the processor interface model for this FPGA I/O function,
a PROC_XDATA_WRITE_BL block is added to the processor model with the
configured data formats.

Parameters The I/O function number can be specified in the range 289 … 320.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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Buffer64 In

64-bit fixed-point data types are converted to double. Therefore, the fixed-
point resolution of fixed-point data types is restricted to 53 bits.
§ floating-point
The values of the Data outport are in floating‑point format. The parameter
then provides the fraction width.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(2).Init /
Format Lets you specify the data format of the Data outport.
§ signed/unsigned
The values of the Data outport are in fixed‑point format with or without one
bit reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
§ floating‑point
The values of the Data outport are in floating‑point format.
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is provided by the Binary point position (or fraction
width) setting.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmemf64_<ChannelNumber>_count / Data Count Outputs the number of

elements in the current buffer. The maximum range depends on the specified
buffer size. You can use the value to define the valid range for the Address
inport of 0 … (Data Count -1).

xmemf64_<ChannelNumber>_dout / Data Outputs a 64-bit data value to

be read from an intermodule-bus buffer. The data format depends on the related
parameter settings.

xmemf64_<ChannelNumber>_new_data / Data New Outputs a flag that

xmemf64_<ChannelNumber>_addr / Address Specifies an element in the

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Buffer64 Out.......................................................................................................................... 376

Buffer Out

Purpose To write data to an intermodule-bus buffer with a data width of 32 bits.

If you generate the processor interface model for this FPGA I/O function,
a PROC_XDATA_READ_BL block is added to the processor model with the
configured data formats.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 129 … 160.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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Buffer Out

§ floating‑point
The values of the Data inport are in floating‑point format.
The 32‑bit data value supports the single-precision floating‑point format with a
fraction width of 24, which complies with the IEEE 754 standard (single).
The fraction width is provided by the Binary point position (or fraction
width) setting.

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Buffer
size Lets you specify the size of the buffer in the range 1 … 32768.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmemp_<ChannelNumber>_din / Data Specifies a 32-bit data value to be

written to an intermodule-bus buffer. The data format depends on the related
parameter settings.

xmemp_<ChannelNumber>_write / Enable Specifies the current valid Data

port value.
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.

xmemp_<ChannelNumber>_finished / Ready Explicitly specifies the buffer

state as ready to send immediately, even if the buffer is not completely filled.
The data values are written to a new buffer in the following clock cycle. While
the port value is 1, the buffer switches every clock cycle. You are therefore
recommended to set the value for only one clock cycle. If the buffer is completely
filled, it is automatically switched, and the data values are stored in a new buffer.
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready for sending, even if it is not completely filled.
The buffer is switched and the data values are accessible via intermodule bus
in the next clock cycle.
The ready flag must be set no later than the last data value. Otherwise the buffer
switches twice.

xmemp_<ChannelNumber>_overflow / Overflow Outputs a flag that

Buffer In................................................................................................................................. 370

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Buffer64 Out

Purpose To write data to an intermodule-bus buffer with a data width of 64 bits.

If you generate the processor interface model for this FPGA I/O function,
a PROC_XDATA_READ_BL block is added to the processor model with the
configured data formats.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 289 ... 320.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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Buffer64 Out

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Buffer
size Lets you specify the size of the buffer in the range 1 … 32768.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmemp64_<ChannelNumber>_din / Data Specifies a 64-bit data value to

be written to an intermodule-bus buffer. The data format depends on the related
parameter settings.

xmemp64_<ChannelNumber>_write / Enable Specifies the current valid

Data port value.
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.

xmemp64_<ChannelNumber>_finished / Ready Explicitly specifies the

buffer state as ready to send the buffer immediately, even if it is not completely
filled. The data values will be written to a new buffer in the next clock cycle.
While the port value is 1, transmission switches buffer in every clock cycle. The
value should therefore be set for one clock cycle only. If the buffer is completely
filled, it is automatically switched, and the data values are stored in a new buffer.
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready for sending, even if it is not completely filled.
The buffer is switched and the data values are accessible via intermodule bus
in the next clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.

xmemp64_<ChannelNumber>_overflow / Overflow Outputs a flag that

Buffer64 In............................................................................................................................. 372

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Digital Crank/Cam Sensor

Purpose To provide bit-wise read access to digital camshaft and crankshaft sensors. Each
channel is 1 bit wide.

Description According to the number of physical connections available on the DS1554

Engine Control I/O Module, you can select the Digital Crank/Cam Sensor I/O
functions. There are five input channels.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 28 … 32.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.In.Fct(<IOFunctionNumber>).Parameter(1).Init / Low
threshold voltage Lets you set the low threshold level for the selected digital
input channel. Below this level, a logical 0 is detected, above this level, a logical
1 is detected if the high threshold voltage was crossed before.
§ Range: ‑40000 mV … +40000 mV
§ Resolution: 20 mV
§ Default: 1000 mV

IOProperties.In.Fct(<IOFunctionNumber>).Parameter(2).Init / High
threshold voltage Lets you set the high threshold level for the selected
digital input channel. The logical 1 is output if this level is crossed and stays 1
until the signal falls below the low threshold level.
§ Range: ‑40000 mV … +40000 mV
§ Resolution: 20 mV
§ Default: 1000 mV

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 4.

cam_<ChannelNumber> / Data Outputs the status of the crank/cam sensor.

Data type: UFix_1_0
§ 0: The input signal is lower than the Low threshold voltage parameter.
§ 1: The input signal is higher than the High threshold voltage parameter.
Update rate: 80 MHz

I/O mapping The following I/O mapping is relevant if you use the FPGA1401Tp1 (7K325) with
Engine Control I/O Module (DS1554) framework. The signals are available at the
DS1554 Sub-D I/O connector.

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Digital In (Type B)

Outport Channel Connector Pin Signal

Data 1 13 CrankCam Ch 1
2 32 CrankCam Ch 2
3 14 CrankCam Ch 3
4 33 CrankCam Ch 4
5 12 CrankCam Ch 5

Overview of the Frameworks Available for MicroAutoBox II (FPGA1401Tp1)............................. 34

Digital In (Type B)

Purpose To read data from a digital input signal in the FPGA application by using a digital
bidirectional channel.

Description According to the number of physical connections available on the DS1554

Engine Control I/O Module, you can select the Digital In (Type B) I/O functions.
There are eight digital input channels.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 2 … 9.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.In.Fct(<IOFunctionNumber>).Parameter(1).Init / Threshold
voltage Lets you specify the threshold level for the current digital channel
in steps of 100 mV. If the input signal is below this level, a logical 0 is detected.
Otherwise, a logical 1 is detected.
§ Range: 1000 mV … 7500 mV
§ Resolution: 100 mV
§ Default: 1500 mV

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Note

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 07.

bidir_<ChannelNumber>_in / Data Outputs the current results of digital

input channel.
§ 0: Input voltage of the channel is below the specified threshold voltage.
§ 1: Input voltage of the channel is higher than or equal to the specified
threshold voltage.
Update rate: 80 MHz

Note

§ The frequency that can be detected is much smaller than the update rate.
For information on the electrical characteristics of the DS1554 Engine
Control I/O Module, refer to Digital I/O (Bidirectional) (MicroAutoBox II
Hardware Reference ).
§ Asynchronous input data might lead to metastable register states. Further
synchronization techniques might be necessary.

I/O mapping The following I/O mapping is relevant if you use the FPGA1401Tp1 (7K325) with
Engine Control I/O Module (DS1554) framework. The signals are available at the
DS1514 ZIF I/O connector. You can use the same digital channel for input and
output signals.

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Digital Out (Type A)

Digital Out (Type A)................................................................................................................ 381

Digital Out (Type B)................................................................................................................. 383
Overview of the Frameworks Available for MicroAutoBox II (FPGA1401Tp1)............................. 34

Digital Out (Type A)

Purpose To write data to a digital output signal in the FPGA application using a digital
output channel.

Description According to the number of physical connections available on the DS1554

Engine Control I/O Module, you can select the Digital Out (Type A) I/O
functions. There are 40 digital output channels.

The voltage range for the high-side switch for all digital output channels is in the
range 0 V … 45 V.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 2 … 41.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 39.

dig_<ChannelNumber>_out / Data Outputs a signal in the specified range.

If driven with 0, the hardware output is 0 V. If driven with 1, the hardware
output is set to the specified high-supply voltage (VDRIVE). The hardware output
is only driven if the Enable port is set to 1. Otherwise, the output is set to high
impedance (High‑Z).
Data Type: UFix_1_0

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Update rate: 80 MHz

Note

The frequency that can be generated is much smaller than the update
rate. For information on the electrical characteristics of the DS1554 Engine
Control I/O Module, refer to Digital Outputs (MicroAutoBox II Hardware
Reference ).

dig_<ChannelNumber>_oe / Enable Controls the hardware output. If set to

1, the hardware output reacts to the Data outport. Otherwise, it is set to High‑Z.

I/O mapping The following I/O mapping is relevant if you use the FPGA1401Tp1 (7K325) with
Engine Control I/O Module (DS1554) framework. The signals are available at the
DS1514 ZIF I/O connector.

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Digital Out (Type B)

Digital In (Type B).................................................................................................................... 379

Digital Out (Type B)

Purpose To write data to a digital output signal in the FPGA application by using a digital
bidirectional channel.

Description According to the number of physical connections available on the DS1554

Engine Control I/O Module, you can select the Digital Out (Type B) I/O
functions. There are eight digital output channels.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 42 … 49.

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IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.Out.Fct(42).Parameter(1).Init / High supply Lets you select

the voltage for the high-side switch for all digital output channels.
§ 0: 3.3 V
§ 1: 5 V

Note

You can specify the high supply voltage value only globally for all digital
output channels.
The I/O function number must be specified as 42.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 07.

bidir_<ChannelNumber>_out / Data Outputs a signal in the specified

range. If driven with 0, the hardware output is 0 V. If driven with 1, the hardware
output is 3.3 V or 5 V according to the specified high supply voltage. The
hardware output is driven only if the Enable port is set to 1. Otherwise, the
output is set to high impedance (High‑Z).
Data Type: UFix_1_0
Update rate: 80 MHz

Note

bidir_<ChannelNumber>_oe / Enable Controls the hardware output. If set

to 1, the hardware output reacts to the Data outport, otherwise it is set to
High‑Z.
Data Type: UFix_1_0

Outport Channel Connector Pin Signal

Data 1 c3 DigIO ch1
2 b5 DigIO ch2
3 b2 DigIO ch3

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Inductive Zero Voltage Detector

Outport Channel Connector Pin Signal

4 c5 DigIO ch4
5 c4 DigIO ch5
6 c2 DigIO ch6
7 a2 DigIO ch7
8 Z2 DigIO ch8

Digital In (Type B).................................................................................................................... 379

Digital Out (Type A)................................................................................................................ 381
Overview of the Frameworks Available for MicroAutoBox II (FPGA1401Tp1)............................. 34

Inductive Zero Voltage Detector

Purpose To provide read access to an inductive zero voltage detector.

Description The FPGA1401Tp1 (7K325) with Engine Control I/O Module (DS1554)
framework provides one channel for the Inductive Zero Voltage Detector I/O
function.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 33.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

crank_0 / Data Detects the zero crossing points of the analog signals. If a
zero crossing from positive to negative is detected, the output signal is 1 for one
clock cycle.
Data type: UFix_1_0
§ 0: No zero crossing.
§ 1: Zero crossing is detected.
Update rate: 80 MHz

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I/O mapping The following I/O mapping is relevant if you use the FPGA1401Tp1 (7K325) with
Engine Control I/O Module (DS1554) framework. The signals are available at the
DS1554 Sub-D I/O connector.

Outport Connector Pin Signal

Data 10 ZeroDetection+
29 ZeroDetection–

Overview of the Frameworks Available for MicroAutoBox II (FPGA1401Tp1)............................. 34

Interrupt

Purpose To request a processor interrupt outside of the FPGA application.

Description The FPGA1401Tp1 frameworks provide 8 interrupt lines. An interrupt is

requested if the Int port is set to 1 for at least one clock cycle. If you set
the Int port to 0, the last interrupt is not released but saved. An interrupt is
edge-triggered.

If you generate the processor interface model for this FPGA I/O function, a
PROC_INT_BL block is added to the processor model with the configured data
formats.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 8.

IRQProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 7.

usr_<ChannelNumber>_interrupt / Int Provides the interrupt request line.

§ 0 to 1: Interrupt is requested (edge-triggered).
§ 0: No interrupt is requested. Last requested interrupt is saved.

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Knock Sensor

Overview of the Frameworks Available for MicroAutoBox II (FPGA1401Tp1)............................. 34

Knock Sensor

Purpose To read data from a knock sensor in the FPGA application.

Description According to the number of physical connections available on the DS1554

Engine Control I/O Module, you can select the Knock Sensor I/O functions.
There are 4 knock sensor input channels.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 24 … 27.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 03.

knock_<ChannelNumber>_data / Data Outputs the current results of the

A/D conversions on the current channel.
Data type: UFix_16_0
Range: 0 … +65535
Input voltage range: –5 V ... +5 V
Update rate: 1 Msps

knock_<ChannelNumber>_soc / Start of conversion Triggers the start of

an A/D conversion on the specified channel. When the value is set to 1 for at
least one clock cycle, the ADC starts the conversion. The port allows a precise
definition of the starting point of ADC sampling. The End of conversion
outport signals the end of the conversion process.
Setting this value permanently to 1 results in continuous sampling.
Data type: UFix_1_0

knock_<ChannelNumber>_eoc / End of conversion Outputs an end of

conversion signal if the conversion result is available on the specified channel.

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If the flag changes from 0 to 1, the ADC data contains a new value. The flag is
set to 1 for only one clock cycle.
Data type: UFix_1_0

I/O mapping The following I/O mapping is relevant if you use the FPGA1401Tp1 (7K325) with
Engine Control I/O Module (DS1554) framework. The signals are available at the
DS1554 Sub-D I/O connector.

Outport Channel Connector Pin Signal

Data 1 16 KnockIn+ ch 1
34 KnockIn– ch 11)
2 17 KnockIn+ ch 2
35 KnockIn– ch 21)
3 18 KnockIn+ ch 3
36 KnockIn– ch 31)
4 19 KnockIn+ ch 4
37 KnockIn– ch 41)
1) The negative input line of the knock sensor input channel is connected to GND. For
achieving optimum analog performance, refer to Connecting Sensor Ground Lines to
MicroAutoBox II (MicroAutoBox II Hardware Installation and Configuration Guide ).

Overview of the Frameworks Available for MicroAutoBox II (FPGA1401Tp1)............................. 34

LED Out

Purpose To write a digital signal that controls the FPGA status LED.

You can find the FPGA status LED near the DS1514 ZIF I/O connector.

Description The FPGA1401Tp1 (7K325) with Engine Control I/O Module (DS1554)
framework provides one channel for the LED Out I/O function.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 1.

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Register In

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

led_out / Data Controls the FPGA status LED.

Data type: UFix_1_0
§ 0: LED lights up green.
§ 1: LED lights up orange.

Overview of the Frameworks Available for MicroAutoBox II (FPGA1401Tp1)............................. 34

Purpose To read data from an intermodule-bus register with a data width of 32 bits.

If you generate the processor interface model for this FPGA I/O function,
a PROC_XDATA_WRITE_BL block is added to the processor model with the
configured data formats.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 128.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(3).Init / Register
group ID Lets you specify a number in the range 1 … 63 to create
register groups. Registers that you specified with the same group ID are
sampled simultaneously within the FPGA application. The values therefore form a
consistent data group that is written to the intermodule bus.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 127.

xreg_<ChannelNumber>_dout / Data Outputs a 32-bit data value to be

read from an intermodule-bus register. The data format depends on the related
parameter settings.

xreg_<ChannelNumber>_dout_wr / Data New Outputs a flag that

indicates the changes of the register status. If the flag changes from 0 to 1
and then back to 0, the requested register contains a new value. The flag is set
to 1 only within one clock cycle.

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Register64 In

Buffer In................................................................................................................................. 370

Register64 In

Purpose To read data from an intermodule-bus register with a data width of 64 bits.

If you generate the processor interface model for this FPGA I/O function,
a PROC_XDATA_WRITE_BL block is added to the processor model with the
configured data formats.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 161 … 288.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(2).Init /
Format Lets you specify the data format of the Data outport.
§ signed/unsigned
The values of the Data outport are in fixed‑point format with or without one
bit reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
§ floating‑point
The values of the Data outport are in floating‑point format.
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is provided by the Binary point position (or fraction
width) setting.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(3).Init / Register
group ID Lets you specify a number in the range 1 … 63 to create
register groups. Registers that you specified with the same group ID are
sampled simultaneously within the FPGA application. The values therefore form a
consistent data group that is written to the intermodule bus.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 127.

xreg64_<ChannelNumber>_dout / Data Outputs a 64-bit data value to be

read from an intermodule-bus register. The data format depends on the related
parameter settings.

xreg64_<ChannelNumber>_dout_wr / Data New Outputs a flag that

indicates the changes of the register status. If the flag changes from 0 to 1
and then back to 0, the requested register contains a new value. The flag is set
to 1 only within one clock cycle.

Buffer64 In............................................................................................................................. 372

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Register Out

Purpose To write data to an intermodule-bus register with a data width of 32 bits.

If you generate the processor interface model for this FPGA I/O function,
a PROC_XDATA_READ_BL block is added to the processor model with the
configured data formats.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 128.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Register
group ID Lets you specify a number in the range 1 … 63 to create register
groups. Registers that you specified with the same group ID are read from
the intermodule bus sequentially and then provided to the FPGA application
simultaneously.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 127.

xreg_<ChannelNumber>_din / Data Specifies a 32-bit data value to be

written to an intermodule-bus register. The data format depends on the related
parameter settings.

Buffer Out.............................................................................................................................. 374

Register64 Out

Purpose To write data to an intermodule-bus register with a data width of 64 bits.

If you generate the processor interface model for this FPGA I/O function,
a PROC_XDATA_READ_BL block is added to the processor model with the
configured data formats.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 161 … 288.

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Register64 Out

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Register
group ID Lets you specify a number in the range 1 … 63 to create register
groups. Registers that you specified with the same group ID are read from
the intermodule bus sequentially and then provided to the FPGA application
simultaneously.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 127.

xreg64_<ChannelNumber>_din / Data Specifies a 64-bit data value to be

written to an intermodule-bus register. The data format depends on the related
parameter settings.

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Buffer64 Out.......................................................................................................................... 376

Status In

Purpose To read digital signals that output state information, e.g., the state of the FPGA
initialization sequence.

Description The FPGA1401Tp1 (7K325) with Engine Control I/O Module (DS1554)
framework provides one channel for the Status In I/O function.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 1.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

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Temperature

Temperature

Purpose To read the FPGA die temperature.

Description The FPGA1401Tp1 (7K325) with Engine Control I/O Module (DS1554)
framework provides one channel for the Temperature I/O function.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 34.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

temperature / Temperature Outputs the raw value of the FPGA's die

temperature measurement. Use the 12 MSB bits to calculate the die
temperature.
Equation for calculating the die temperature:
Temperature [°C] = (float)(Temperature[hex] & 0xFFF0) ·
503.975 / 65536 - 273.15
Data type: UFix_16_0
Data width: 1
Value range: 0 ... 65536

high_temp / High Outputs a flag if the FPGA's die temperature exceeds

105 °C.
To reset the flag, the die temperature must fall below 85 °C.
Data type: UFix_1_0
§ 0: Die temperature does not exceed 105 °C.
§ 1: Die temperature exceeds 105 °C.

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Note

A high ambient temperature and an FPGA application with a very high

Overview of the Frameworks Available for MicroAutoBox II (FPGA1401Tp1)............................. 34

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I/O Functions of the FPGA1403Tp1 with Multi-I/O Module Frameworks

I/O Functions of the FPGA1403Tp1 with Multi-I/O

Module Frameworks

Introduction The FPGA1403Tp1 frameworks provide the standard I/O functionality of

MicroAutoBox II with DS1552 (FPGA1403Tp1_DS1552_XC7K325T) or with
DS1552B1 Multi-I/O Module (FPGA1403Tp1_DS1552B1_XC7K325T).

Where to go from here Information in this section

ADC (Type A)......................................................................................... 400

To read data from an Analog In 10/Analog In 11 channel.

ADC (Type B)......................................................................................... 402

To read data from an Analog In 12 channel.

Buffer In................................................................................................ 403

To read data from an intermodule-bus buffer with a data width of
32 bits.

Buffer64 In............................................................................................ 405

To read data from an intermodule-bus buffer with a data width of
64 bits.

Buffer Out............................................................................................. 407

To write data to an intermodule-bus buffer with a data width of 32 bits.

Buffer64 Out......................................................................................... 408

To write data to an intermodule-bus buffer with a data width of 64 bits.

DAC...................................................................................................... 410
To write data to an Analog Out 13 channel in the FPGA application.

Digital Crank/Cam Sensor...................................................................... 411

To provide bit-wise read access to digital camshaft and crankshaft
sensors.

Digital In (Type A).................................................................................. 413

To read data from a digital input signal in the FPGA application using a
Digital In 5 channel.

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Digital In (Type B)................................................................................... 415

To read data from a digital input signal in the FPGA application by using
a Digital InOut 6 channel.

Digital Out (Type A)............................................................................... 417

To write data to a digital output signal in the FPGA application using a
Digital Out 5 channel.

Digital Out (Type B)................................................................................ 418

To write data to a digital output signal in the FPGA application using a
digital bidirectional channel.

Inductive Zero Voltage Detector............................................................. 420

To provide read access to an inductive zero voltage detector.

Interrupt................................................................................................ 421
To request a processor interrupt outside of the FPGA application.

LED Out................................................................................................. 422

To write a digital signal that controls the FPGA status LED near the
DS1514 ZIF I/O connector.

Register In............................................................................................. 423

To read data from an intermodule-bus register with a data width of
32 bits.

Register64 In......................................................................................... 424

To read data from an intermodule-bus register with a data width of
64 bits.

Register Out.......................................................................................... 426

To write data to an intermodule-bus register with a data width of 32 bits.

Register64 Out...................................................................................... 427

To write data to an intermodule-bus register with a data width of 64 bits.

Sensor Supply........................................................................................ 429

To provide a supply voltage at a connected sensor.

Status In................................................................................................ 430

To read digital signals that outputs state information, e.g.: state of the
FPGA initialization sequence or the FPGA die temperature.

UART (RS232)........................................................................................ 431

To implement RS232 communication via a UART 3 channel.

UART (RS422/485)................................................................................. 436

To implement RS422/485 communication via a UART 3 channel.

ADC (Type A)

Purpose To read data from an analog input signal in the FPGA application using the ADC
(Type A) conversion function for the Analog In 10/Analog In 11 channel.

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ADC (Type A)

Description According to the number of physical connections available on the

DS1552/DS1552B1 I/O module, you can select the ADC (Type A) I/O functions.
There are eight analog input channels.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 26 … 33.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 7.

hq_adc_<ChannelNumber>_data / Data Outputs the current results of the

A/D conversions on the current channel.
Range: 0 … +65535
Update rate: 1 Msps

hq_adc_<ChannelNumber>_soc / Start of conversion Lets you trigger the

hq_adc_<ChannelNumber>_eoc / End of conversion Outputs an end of

conversion signal if the conversion result is available on the specified channel. If
the flag changes from 0 to 1, the ADC data contains a new value. The flag is set
to 1 for only one clock cycle.

I/O mapping The following I/O mapping is relevant if you use a FPGA1403Tp1 framework
for analog input channels using the Type A conversion function. The signals are
available at the DS1514 ZIF I/O connector.

Outport Channel Connector Pin Signal

Data 1 X3 Analog In Channel 1 Signal
X4 Analog In Channel 1 Reference
2 W3 Analog In Channel 2 Signal
W4 Analog In Channel 2 Reference
3 V3 Analog In Channel 3 Signal
V4 Analog In Channel 3 Reference
4 U3 Analog In Channel 4 Signal

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ADC (Type B).......................................................................................................................... 402

DAC....................................................................................................................................... 410
Overview of the Frameworks Available for MicroAutoBox III (FPGA1403Tp1)............................. 37

ADC (Type B)

Purpose To read data from an analog input signal in the FPGA application using the ADC
(Type B) conversion function for the Analog In 12 channel.

Description According to the number of physical connections available on the DS1552 Multi-
I/O Module, you can select the ADC (Type B) I/O functions. There are 16 analog
output channels.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 34 … 49.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 15.

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Buffer In

lq_adc_<ChannelNumber>_data / Data Outputs the current results of the

A/D conversions on the current channel in the range ‑32768 … +32767.
Update rate: 0.2 Msps

I/O mapping The following I/O mapping is relevant if you use a FPGA1403Tp1 framework for
analog input channels using the ADC (Type B) conversion function. The signals
are available at the DS1514 ZIF I/O connector.

ADC (Type A).......................................................................................................................... 400

Buffer In

Purpose To read data from an intermodule-bus buffer with a data width of 32 bits.

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Parameters The I/O function number can be specified in the range 129 … 160.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmemf_<ChannelNumber>_count / Data Count Outputs the number of

elements in the current buffer. The maximum range depends on the specified
buffer size. You can use the value to define the valid range for the Address
inport of 0 … (Data Count -1).

xmemf_<ChannelNumber>_dout / Data Outputs a 32-bit data value to be

read from an intermodule-bus buffer. The data format depends on the related
parameter settings.

xmemf_<ChannelNumber>_new_data / Data New Outputs a flag that

indicates the changes of the buffer status. If the flag changes from 0 to 1 and

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Buffer64 In

then back to 0, the requested buffer contains new values and is ready to be
read. The flag is set to 1 only within one clock cycle.

xmemf_<ChannelNumber>_addr / Address Specifies an element in the

Buffer Out.............................................................................................................................. 407

Overview of the Frameworks Available for MicroAutoBox III (FPGA1403Tp1)............................. 37
Register In.............................................................................................................................. 423

Buffer64 In

Purpose To read data from an intermodule-bus buffer with a data width of 64 bits.

Parameters The I/O function number can be specified in the range 289 … 320.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(2).Init /
Format Lets you specify the data format of the Data outport.
§ signed/unsigned
The values of the Data outport are in fixed‑point format with or without one
bit reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
§ floating‑point
The values of the Data outport are in floating‑point format.
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is provided by the Binary point position (or fraction
width) setting.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmemf64_<ChannelNumber>_count / Data Count Outputs the number of

elements in the current buffer. The maximum range depends on the specified
buffer size. You can use the value to define the valid range for the Address
inport of 0 … (Data Count -1).

xmemf64_<ChannelNumber>_dout / Data Outputs a 64-bit data value to

be read from an intermodule-bus buffer. The data format depends on the related
parameter settings.

xmemf64_<ChannelNumber>_new_data / Data New Outputs a flag that

xmemf64_<ChannelNumber>_addr / Address Specifies an element in the

Buffer64 Out.......................................................................................................................... 408

Overview of the Frameworks Available for MicroAutoBox III (FPGA1403Tp1)............................. 37
Register64 In.......................................................................................................................... 424

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Buffer Out

Buffer Out

Purpose To write data to an intermodule-bus buffer with a data width of 32 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 129 … 160.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Buffer
size Lets you specify the size of the buffer in the range 1 … 32768.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

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The channel number can be specified in the range 00 … 31.

xmemp_<ChannelNumber>_din / Data Specifies a 32-bit data value to be

written to an intermodule-bus buffer. The data format depends on the related
parameter settings.

xmemp_<ChannelNumber>_write / Enable Specifies the current valid Data

port value.
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.

xmemp_<ChannelNumber>_finished / Ready Explicitly specifies the buffer

state as ready to send the buffer immediately, even if it is not completely filled.
The data values will be written to a new buffer in the next clock cycle. While
the port value is 1, transmission switches buffer in every clock cycle. The value
should therefore be set for one clock cycle only. If the buffer is completely filled,
it is automatically switched, and the data values are stored in a new buffer.
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready for sending, even if it is not completely filled.
The buffer is switched and the data values are accessible via intermodule bus
in the next clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.

xmemp_<ChannelNumber>_overflow / Overflow Outputs a flag that

Buffer In................................................................................................................................. 403

Overview of the Frameworks Available for MicroAutoBox III (FPGA1403Tp1)............................. 37
Register Out........................................................................................................................... 426

Buffer64 Out

Purpose To write data to an intermodule-bus buffer with a data width of 64 bits.

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Buffer64 Out

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 289 ... 320.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Buffer
size Lets you specify the size of the buffer in the range 1 … 32768.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmemp64_<ChannelNumber>_din / Data Specifies a 64-bit data value to

be written to an intermodule-bus buffer. The data format depends on the related
parameter settings.

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xmemp64_<ChannelNumber>_write / Enable Specifies the current valid

Data port value.
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.

xmemp64_<ChannelNumber>_finished / Ready Explicitly specifies the

buffer state as ready to send the buffer immediately, even if it is not completely
filled. The data values will be written to a new buffer in the next clock cycle.
While the port value is 1, transmission switches buffer in every clock cycle. The
value should therefore be set for one clock cycle only. If the buffer is completely
filled, it is automatically switched, and the data values are stored in a new buffer.
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready for sending, even if it is not completely filled.
The buffer is switched and the data values are accessible via intermodule bus
in the next clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.

xmemp64_<ChannelNumber>_overflow / Overflow Outputs a flag that

Buffer64 In............................................................................................................................. 405

Overview of the Frameworks Available for MicroAutoBox III (FPGA1403Tp1)............................. 37
Register64 Out....................................................................................................................... 427

DAC

Purpose To write data to an Analog Out 13 channel in the FPGA application.

Description According to the number of physical connections available on the DS1552 Multi-
I/O Module, you can select the DAC I/O functions. There are four analog output
channels.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

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Digital Crank/Cam Sensor

The I/O function number can be specified in the range 26 … 29.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 3.

dac<ChannelNumber>_data / Data Outputs a signal in the range 0

I/O mapping The following I/O mapping is relevant if you use a FPGA1403Tp1 framework
for analog output channels. The signals are available at the DS1514 ZIF I/O
connector.

ADC (Type A).......................................................................................................................... 400

ADC (Type B).......................................................................................................................... 402
Overview of the Frameworks Available for MicroAutoBox III (FPGA1403Tp1)............................. 37

Digital Crank/Cam Sensor

Purpose To provide bit-wise read access to digital camshaft and crankshaft sensors. Each
channel is 1 bit wide.

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Description According to the number of physical connections available on the DS1552 Multi-
I/O Module, you can select the Digital Crank/Cam Sensor I/O functions. There
are three input channels.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 50 … 52.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.In.Fct(<IOFunctionNumber>).Parameter(1).Init / Low
threshold voltage To set the low threshold level for the selected digital input
channel. Below this level a logical 0 is detected, above this level a logical 1 is
detected, if the high threshold voltage was crossed before.
§ Range:
‑40000 mV … +40000 mV
§ Resolution:
20 mV
§ Default:
1000 mV

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 2.

cam_<ChannelNumber> / Data Data type: UFix_1_0

§ 0: The input signal is lower than the Low threshold voltage parameter.
§ 1: The input signal is higher than the High threshold voltage parameter.
Update rate: 80 MHz

I/O mapping The following I/O mapping is relevant if you use a FPGA1403Tp1 framework for
analog input channels. The signals are available at the DS1514 ZIF I/O connector.

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Digital In (Type A)

Outport Channel Connector Pin Signal

Data 1 R3 Digital In 6 Channel 1 +
R4 Digital In 6 Channel 1 -
2 B3 Digital In 6 Channel 2 +
B4 Digital In 6 Channel 2 -
3 A3 Digital In 6 Channel 3 +
A4 Digital In 6 Channel 3 -

Overview of the Frameworks Available for MicroAutoBox III (FPGA1403Tp1)............................. 37

Digital In (Type A)

Purpose To read data from a digital input signal in the FPGA application using a Digital
In 5 channel.

Description According to the number of physical connections available on the DS1552 Multi-
I/O Module, you can select the Digital In (Type A) I/O functions. There are 16
digital input channels.

The threshold level is fix:

§ 3.6 V for low-high transition
§ 1.2 V for high-low transition

Note

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 2 … 17.

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IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 15.

dig_<ChannelNumber>_in / Data Outputs the current results of digital

Note

§ The frequency that can be detected is much smaller than the update rate.
For information on the electrical characteristics of the DS1552 Multi‑I/O
Module, refer to Digital In 5 Characteristics (MicroAutoBox III Hardware
Installation and Configuration ).
§ Asynchronous input data might lead to metastable register states. Further
synchronization techniques might be necessary.

I/O mapping The following I/O mapping is relevant if you use a FPGA1403Tp1 framework for
digital input channels. The signals are available at the DS1514 ZIF I/O connector.

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Digital In (Type B)

Digital In (Type A)................................................................................................................... 413

Digital In (Type B).................................................................................................................... 415
Overview of the Frameworks Available for MicroAutoBox III (FPGA1403Tp1)............................. 37

Digital In (Type B)

Purpose To read data from a digital input signal in the FPGA application by using a
Digital InOut 6 channel.

Description According to the number of physical connections available on the DS1552 Multi-
I/O Module, you can select the Digital In (Type B) I/O functions. There are eight
digital input channels.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 18 … 25.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Note

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Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 07.

bidir_<ChannelNumber>_in / Data Outputs the current results of digital

Note

§ The frequency that can be detected is much smaller than the update
rate. For information on the electrical characteristics of the DS1552 Multi-
I/O Module, refer to Digital In/Out 6 Characteristics (MicroAutoBox III
Hardware Installation and Configuration ).
§ Asynchronous input data might lead to metastable register states. Further
synchronization techniques might be necessary.

I/O mapping The following I/O mapping is relevant if you use a FPGA1403Tp1 framework
for digital bidirectional channels. The signals are available at the DS1514 ZIF I/O
connector.

You can use the same digital channel for input and output signals.

Digital In (Type A)................................................................................................................... 413

Digital Out (Type B)................................................................................................................. 418
Overview of the Frameworks Available for MicroAutoBox III (FPGA1403Tp1)............................. 37

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Digital Out (Type A)

Digital Out (Type A)

Purpose To write data to a digital output signal in the FPGA application using a Digital
Out 5 channel.

Description According to the number of physical connections available on the DS1552 Multi-
I/O Module, you can select the Digital Out (Type A) I/O functions. There are 16
digital output channels.

The voltage range for the high side switch for all digital output channels is in the
range 0 V … 45 V.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 2 … 17.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 15.

dig_<ChannelNumber>_out / Data Outputs a signal in the specified range.

Note

The frequency that can be generated is much smaller than the update
rate. For information on the electrical characteristics of the DS1552 Multi-
I/O Module, refer to Digital Interface Characteristics (DS1552/DS1552B1)
(MicroAutoBox III Hardware Installation and Configuration ).

dig_<ChannelNumber>_oe / Enable Controls the hardware output. If set to

1, the hardware output reacts to the Data outport, otherwise it is set to High‑Z.

I/O mapping The following I/O mapping is relevant if you use a FPGA1403Tp1 framework
for digital output channels. The signals are available at the DS1514 ZIF I/O
connector.

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Digital In (Type A)................................................................................................................... 413

Digital Out (Type B)

Purpose To write data to a digital output signal in the FPGA application by using a Digital
InOut 6 channel.

Description According to the number of physical connections available on the DS1514 Multi-
I/O Module, you can select the Digital Out (Type B) I/O functions. There are
eight digital output channels.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 18 … 25.

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Digital Out (Type B)

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.Out.Fct(18).Parameter(1).Init / High supply Lets you select

the voltage for the high side switch for all digital output channels.
§ 0: 3.3 V
§ 1: 5 V

Note

You can specify the high supply voltage value only globally for all digital
output channels.
The I/O function number must be specified as 18.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 07.

bidir_<ChannelNumber>_out / Data Outputs a signal in the specified

Note

The frequency that can be generated is smaller than the update rate.
For information on the electrical characteristics of the DS1552 Multi-I/O
Module, refer to Digital In/Out 6 Characteristics (MicroAutoBox III Hardware
Installation and Configuration ).

bidir_<ChannelNumber>_oe / Enable Controls the hardware output. If set

to 1, the hardware output reacts to the Data outport, otherwise it is set to
High‑Z.

I/O mapping The following I/O mapping is relevant if you use a FPGA1403Tp1 framework
for digital bidirectional channels. The signals are available at the DS1514 ZIF I/O
connector.

Outport Channel Connector Pin Signal

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Outport Channel Connector Pin Signal

7 M6 Digital InOut 6 Channel 7 Signal
8 L4 Digital InOut 6 Channel 8 Signal

You can use the same digital channel for input and output signals.

Digital In (Type B).................................................................................................................... 415

Digital Out (Type A)................................................................................................................ 417
Overview of the Frameworks Available for MicroAutoBox III (FPGA1403Tp1)............................. 37

Inductive Zero Voltage Detector

Purpose To provide read access to an inductive zero voltage detector.

Description The FPGA1403Tp1 frameworks provide one channel for the Inductive Zero
Voltage Detector I/O function.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 53.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

I/O mapping The following I/O mapping is relevant if you use a FPGA1403Tp1 framework for
analog input channels. The signals are available at the DS1514 ZIF I/O connector.

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Interrupt

Outport Connector Pin Signal

Data P3 Digital In 7
Channel 1 +
P4 Digital In 7
Channel 1 -

Overview of the Frameworks Available for MicroAutoBox III (FPGA1403Tp1)............................. 37

Interrupt

Purpose To request a processor interrupt outside of the FPGA application.

Description The FPGA1403Tp1 frameworks provide 8 interrupt lines. An interrupt is

requested if the Int port is set to 1 for at least one clock cycle. If you set
the Int port to 0, the last interrupt is not released but saved. An interrupt is
edge-triggered.

If you generate the processor interface model for this FPGA I/O function, a
PROC_INT_BL block is added to the processor model with the configured data
formats.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 8.

IRQProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 7.

usr_<ChannelNumber>_interrupt / Int Provides the interrupt request line.

§ 0 to 1: Interrupt is requested (edge-triggered).
§ 0: No interrupt is requested. Last requested interrupt is saved.

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Overview of the Frameworks Available for MicroAutoBox III (FPGA1403Tp1)............................. 37

LED Out

Purpose To write a digital signal that controls the FPGA status LED.

You can find the FPGA status LED near the DS1514 ZIF I/O connector.

Description The FPGA1403Tp1 frameworks provide one channel for the LED Out I/O
function.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 1.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

led_out / Data Controls the Status LED on the board's bracket.

§ 0: LED lights green.
§ 1: LED lights orange.

Overview of the Frameworks Available for MicroAutoBox III (FPGA1403Tp1)............................. 37

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Register In

Purpose To read data from an intermodule-bus register with a data width of 32 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 128.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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sampled simultaneously within the FPGA application. The values therefore form a
consistent data group that is written to the intermodule bus.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 127.

xreg_<ChannelNumber>_dout / Data Outputs a 32-bit data value to be

read from an intermodule-bus register. The data format depends on the related
parameter settings.

xreg_<ChannelNumber>_dout_wr / Data New Outputs a flag that

indicates the changes of the register status. If the flag changes from 0 to 1
and then back to 0, the requested register contains a new value. The flag is set
to 1 only within one clock cycle.

Buffer In................................................................................................................................. 403

Register64 In

Purpose To read data from an intermodule-bus register with a data width of 64 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 161 … 288.

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Register64 In

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(2).Init /
Format Lets you specify the data format of the Data outport.
§ signed/unsigned
The values of the Data outport are in fixed‑point format with or without one
bit reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
§ floating‑point
The values of the Data outport are in floating‑point format.
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is provided by the Binary point position (or fraction
width) setting.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(3).Init / Register
group ID Lets you specify a number in the range 1 … 63 to create
register groups. Registers that you specified with the same group ID are
sampled simultaneously within the FPGA application. The values therefore form a
consistent data group that is written to the intermodule bus.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 127.

xreg64_<ChannelNumber>_dout / Data Outputs a 64-bit data value to be

read from an intermodule-bus register. The data format depends on the related
parameter settings.

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xreg64_<ChannelNumber>_dout_wr / Data New Outputs a flag that

indicates the changes of the register status. If the flag changes from 0 to 1
and then back to 0, the requested register contains a new value. The flag is set
to 1 only within one clock cycle.

Buffer64 In............................................................................................................................. 405

Purpose To write data to an intermodule-bus register with a data width of 32 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 128.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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Register64 Out

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Register
group ID Lets you specify a number in the range 1 … 63 to create register
groups. Registers that you specified with the same group ID are read from
the intermodule bus sequentially and then provided to the FPGA application
simultaneously.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 127.

xreg_<ChannelNumber>_din / Data Specifies a 32-bit data value to be

written to an intermodule-bus register. The data format depends on the related
parameter settings.

Buffer Out.............................................................................................................................. 407

Register64 Out

Purpose To write data to an intermodule-bus register with a data width of 64 bits.

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Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 161 … 288.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Register
group ID Lets you specify a number in the range 1 … 63 to create register
groups. Registers that you specified with the same group ID are read from
the intermodule bus sequentially and then provided to the FPGA application
simultaneously.

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Sensor Supply

Specify 0 for ungrouped read access.

§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 127.

xreg64_<ChannelNumber>_din / Data Specifies a 64-bit data value to be

written to an intermodule-bus register. The data format depends on the related
parameter settings.

Buffer64 Out.......................................................................................................................... 408

Sensor Supply

Purpose To provide a supply voltage, for example, for a connected sensor, in the range
2000 mV … 20000 mV in steps of 100 mV.

Description The FPGA1403Tp1 frameworks provide one channel for the Sensor Supply I/O
function.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 30.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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Port There is no port to be specified.

I/O mapping The following I/O mapping is relevant if you use a FPGA1403Tp1 framework
for for sensor supply. Depending on the MicroAutoBox variant the signals are
available at the DS1514 ZIF I/O connector.

Outport Channel Connector Pin Signal

Sim_Data 1 b6 VSENS-
c6 VSENS+

Overview of the Frameworks Available for MicroAutoBox III (FPGA1403Tp1)............................. 37

Status In

Purpose To read digital signals that outputs state information, e.g.: state of the FPGA
initialization sequence or the FPGA die temperature.

Description The FPGA1403Tp1 framework provides one channel for the Status In I/O
function.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 1.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

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UART (RS232)

temperature / Temperature Outputs the raw value of the FPGA's die

high_temp / High Outputs a flag if the FPGA's die temperature exceeds

105 °C.
To reset the flag, the die temperature must fall below 85 °C.
Data type: UFix_1_0
§ 0: Die temperature does not exceed 105 °C.
§ 1: Die temperature exceeds 105 °C.

Note

A high ambient temperature and an FPGA application with a very high

Overview of the Frameworks Available for MicroAutoBox III (FPGA1403Tp1)............................. 37

UART (RS232)

Purpose To implement RS232 communication via a UART 3 channel.

Description According to the number of physical connections available on the DS1552 Multi-
I/O Module, you can select the UART (RS232) I/O functions. There are two
interfaces.

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Note

UART 1 can be used without modification. To use UART 2, your DS1552 has
to be modified by dSPACE.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 31 … 32.

Most of the parameters are used for the UART (RS232) and UART 3 (RS422/485)
I/O functions.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(1).Init / Baud
rate Lets you specify the baud rate of the UART in the range 50 … 1,000,000
baud (bits per second).
With:

Variable Parameter Description

Note

Tip

In the framework folder you find a MATLAB file that provides some
calculated baud rates and the percentage deviations to the supported baud
rates according to the parameters m, d and the clock divider.
§ Framework folder:
<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\FPGA
1403Tp1_<Multi_I/O_Module_type>_<FPGA_type>
§ MATLAB file name: FPGA1403Tp1_XC7K325T_uart_parameters.mat

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UART (RS232)

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(6).Init / Stop
bits Lets you specify the length of the stop bits in half of bits.

Stop Bits Parameter Value

1 2
1.5 3
2 4

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(7).Init / UART
type Lets you specify the UART type.

Value UART Type

0 RS232
1 RS422/485

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(8).Init /
Termination Lets you specify the termination state.

Note

For the RS232 UART type, the termination must be set to 0 (disconnected).

Value Termination State Description

0 Disconnected § The RX/CTS and TX/RTS signals are not terminated.
1 Connected § Not allowed

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 1.

uart_<ChannelNumber>_rd / Read Enable Specifies to start receiving a

uart_<ChannelNumber>_rd_data_count / Read Data Count Outputs the

number of new entries in the RX FIFO buffer.
Two clock cycles are required to return the number of entries.

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If you only want to check whether a value is available in the RX FIFO buffer, use
the Read_Fifo_Empty signal instead of this.
Value range: 0 … 2047

uart_<ChannelNumber>_rd_fifo_empty / Read Fifo Empty Outputs the

uart_<ChannelNumber>_rd_data / Read Data Outputs the last read data

uart_<ChannelNumber>_wr / Write Enable Specifies to start sending a

value.
The Write_Data value is written to the TX FIFO buffer, from which it is
automatically send to the TX output pin of the I/O connector using the specified
UART communication settings.
Write_Enable must be set to 1 for only one clock cycle.
Before you write data to the TX FIFO buffer, you should check the
Write_Fifo_Full signal not to be set. The Write_Fifo_Full signal switches one
clock cycle after the Write_Enable signal has been set.
Do not use the Write_Data_Count signal (Write_Data_Count < 2047) to check
the TX FIFO buffer, because it requires one additional clock cycle to get the count
value.
The hardware output port is driven with the values from the TX FIFO buffer. It
is synchronously running to the UART clock defined by the UART baudrate. The
hardware port has inverted voltage levels of ‑6 V (logical high) and +6 V (logical
low).

uart_<ChannelNumber>_wr_data_count / Write Data Count Outputs the

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UART (RS232)

uart_<ChannelNumber>_wr_fifo_full / Write Fifo Full Outputs the status

uart_<ChannelNumber>_wr_data / Write Data Specifies the value to be

send.
The Write_Data signal is transferred at each clock cycle with Write_Enable set
to 1.
Range: 0 … 511

uart_<ChannelNumber>_rts / RTS Specifies the Ready‑To‑Send (RTS) signal.

The RTS/CTS handshake is handled by the user, the RTS signal is just passed
through and adapted to the physical layer.
The hardware port is synchronously running to the UART clock defined by the
UART baudrate. The hardware port has voltage levels of +6 V (active, logical
high) and ‑6 V (inactive).

uart_<ChannelNumber>_cts / CTS Outputs the state of the Clear‑To‑Send

(CTS) hardware port.
RTS/CTS handshake is handled by the user. CTS is just passed through with
conversion to logical 1 and 0.
Range:
§ 0: CTS inactive
§ 1: CTS active
The CTS hardware port is synchronously running to the UART clock defined by
the UART baudrate. The hardware port has voltage levels of +6 V (active, logical
high) and ‑6 V (inactive).

I/O mapping The following I/O mapping is relevant if you use a FPGA1403Tp1 framework for
serial communication using the UART (RS232) function. The signals are available
at the DS1514 ZIF I/O connector.

Inport Connector Pin Signal

UART 1 (RS232)
Write_Data a5 TX1
RTS a6 RTS1
Read_Data b5 RX1
CTS a4 CTS1
UART 2 (RS232)1)
Write_Data Z5 TX2
RTS Z6 RTS2

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Inport Connector Pin Signal

Read_Data Z3 RX2
CTS Z4 CTS2
1) To use UART 2, your DS1552 has to be modified by dSPACE.

Overview of the Frameworks Available for MicroAutoBox III (FPGA1403Tp1)............................. 37

UART (RS422/485).................................................................................................................. 436

UART (RS422/485)

Purpose To implement RS422/485 communication via a UART 3 channel.

Description According to the number of physical connections available on the DS1552 Multi-
I/O Module, you can select the UART 3 (RS422/485) I/O functions. There are two
interfaces.

Note

UART 1 can be used without modification. To use UART 2, your DS1552 has
to be modified by dSPACE.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 33 … 34.

Most of the parameters are used for the UART 3 (RS232) and UART (RS422/485)
I/O functions.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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UART (RS422/485)

With:

Variable Parameter Description

Tip

In the framework folder you find a MATLAB file providing some calculated
baud rates and the percentage deviations to the supported baud rates
according to the parameters m, d and the clock divider.
§ Framework folder:
<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\FPGA
1403Tp1_<Multi_I/O_Module_type>_<FPGA_type>
§ MATLAB file name: FPGA1403Tp1_XC7K325T_uart_parameters.mat

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(6).Init / Stop
bits Lets you specify the length of the stop bits in half of bits.

Stop Bits Parameter Value

1 2
1.5 3
2 4

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(7).Init / UART
mode Lets you specify the mode when using the RS422/485 UART type.

Value UART Mode

0 Full‑duplex mode
1 Half‑duplex mode

IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(8).Init / UART
type Lets you specify the UART type.

Value UART Type

0 RS232
1 RS422/485

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IOProperties.Out.Fct(<IOFunctionNumber>).Parameter(9).Init /
Termination Lets you specify the termination state.

Value Termination State Description

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 1.

uart_<ChannelNumber>_rd / Read Enable Specifies to start receiving a

uart_<ChannelNumber>_rd_data_count / Read Data Count Outputs the

uart_<ChannelNumber>_rd_fifo_empty / Read Fifo Empty Outputs the

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UART (RS422/485)

Range:
§ 0: The RX FIFO buffer is not empty.
§ 1: The RX FIFO buffer is empty.

uart_<ChannelNumber>_rd_data / Read Data Outputs the last read data

uart_<ChannelNumber>_wr / Write Enable Specifies to start sending a

uart_<ChannelNumber>_wr_data_count / Write Data Count Outputs the

uart_<ChannelNumber>_wr_fifo_full / Write Fifo Full Outputs the status

uart_<ChannelNumber>_wr_data / Write Data Specifies the value to be

send.
The Write_Data signal is transferred at each clock cycle with Write_Enable set
to 1.

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Range: 0 … 511

uart_<ChannelNumber>_driver_en / Driver Enable Specifies to enable the

output driver in the transceiver for data transmission.
If you use the UART (RS485/422) function in half-duplex mode, the output driver
must be disabled while receiving data.

I/O mapping The following I/O mapping is relevant if you use a FPGA1403Tp1 framework
for serial communication using the UART (RS422/485) function. The signals are
available at the DS1514 ZIF I/O connector. The mapping differs when using the
UART (RS422/485) in full-duplex or half-duplex mode.

Full-duplex mode:

Inport Connector Pin Signal

Half-duplex mode:

Inport Connector Pin Signal

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UART (RS422/485)

Overview of the Frameworks Available for MicroAutoBox III (FPGA1403Tp1)............................. 37

UART (RS232)......................................................................................................................... 431

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I/O Functions of the FPGA1403Tp1 with Engine Control I/O Module Framework

I/O Functions of the FPGA1403Tp1 with Engine

Control I/O Module Framework

Introduction The FPGA1403Tp1 (7K325) with Engine Control I/O Module (DS1554) provides
the I/O functionality of MicroAutoBox with a DS1554 Engine Control I/O Module.

Where to go from here Information in this section

ADC (Type A)......................................................................................... 444

To read data from an Analog In 14 channel in the FPGA application by
using the ADC (Type A) conversion function.

Buffer In................................................................................................ 446

To read data from an intermodule-bus buffer with a data width of
32 bits.

Buffer64 In............................................................................................ 448

To read data from an intermodule-bus buffer with a data width of
64 bits.

Buffer Out............................................................................................. 450

To write data to an intermodule-bus buffer with a data width of 32 bits.

Buffer64 Out......................................................................................... 451

To write data to an intermodule-bus buffer with a data width of 64 bits.

Digital Crank/Cam Sensor...................................................................... 453

To provide bit-wise read access to digital camshaft and crankshaft
sensors.

Digital In (Type B)................................................................................... 455

To read data from a digital input signal in the FPGA application by using
a Digital InOut 8 channel.

Digital Out (Type A)............................................................................... 456

To write data to a digital output signal in the FPGA application using a
Digital Out 7 channel.

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Digital Out (Type B)................................................................................ 459

To write data to a digital output signal in the FPGA application by using a
Digital In/Out 8 channel.

Inductive Zero Voltage Detector............................................................. 460

To provide read access to an inductive zero voltage detector.

Interrupt................................................................................................ 461
To request a processor interrupt outside of the FPGA application.

Knock Sensor........................................................................................ 462

To read data from a knock sensor in the FPGA application.

LED Out................................................................................................. 464

To write a digital signal that controls the FPGA status LED near the
DS1514 ZIF I/O connector.

Register In............................................................................................. 465

To read data from an intermodule-bus register with a data width of
32 bits.

Register64 In......................................................................................... 466

To read data from an intermodule-bus register with a data width of
64 bits.

Register Out.......................................................................................... 468

To write data to an intermodule-bus register with a data width of 32 bits.

Register64 Out...................................................................................... 469

To write data to an intermodule-bus register with a data width of 64 bits.

Status In................................................................................................ 471

To read digital signals that outputs state information, e.g.: state of the
FPGA initialization sequence.

Temperature.......................................................................................... 472
To read the FPGA die temperature.

ADC (Type A)

Purpose To read data from an Analog In 14 channel in the FPGA application by using the
ADC (Type A) conversion function.

Description According to the number of physical connections available on the DS1554

Engine Control I/O Module, you can select the Analog In 14 I/O functions. There
are 14 analog input channels.

This I/O function is not considered when you generate the processor interface
model.

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ADC (Type A)

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 10 … 23.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 13.

hq_adc_<ChannelNumber>_data / Data Outputs the current results of the

A/D conversions on the current channel.
Data type: UFix_16_0
Range: 0 … +65535
Update rate: 1 Msps

hq_adc_<ChannelNumber>_soc / Start of conversion Triggers the

hq_adc_<ChannelNumber>_eoc / End of conversion Outputs an end of

I/O mapping The following I/O mapping is relevant if you use the FPGA1403Tp1 (7K325) with
Engine Control I/O Module (DS1554) framework. The signals are available at the
DS1514 ZIF I/O connector.

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Buffer In

Purpose To read data from an intermodule-bus buffer with a data width of 32 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 129 … 160.

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Buffer In

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmemf_<ChannelNumber>_count / Data Count Outputs the number of

elements in the current buffer. The maximum range depends on the specified
buffer size. You can use the value to define the valid range for the Address
inport of 0 … (Data Count -1).

xmemf_<ChannelNumber>_dout / Data Outputs a 32-bit data value to be

read from an intermodule-bus buffer. The data format depends on the related
parameter settings.

xmemf_<ChannelNumber>_new_data / Data New Outputs a flag that

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xmemf_<ChannelNumber>_addr / Address Specifies an element in the

buffer you want to read. The block requires 1 clock cycle to update the value
of the Data outport according to the specified address. The maximum port
range depends on the specified buffer size. The valid port range depends on
the number of elements currently in the buffer. Refer to Data Count outport.
If you request data from an address that is greater than the Data Count value,
the output of the Data outport is undefined. The first element of a buffer is
addressed by 0.

Buffer Out.............................................................................................................................. 407

Buffer64 In

Purpose To read data from an intermodule-bus buffer with a data width of 64 bits.

Parameters The I/O function number can be specified in the range 289 … 320.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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Buffer64 In

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(2).Init /
Format Lets you specify the data format of the Data outport.
§ signed/unsigned
The values of the Data outport are in fixed‑point format with or without one
bit reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
§ floating‑point
The values of the Data outport are in floating‑point format.
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is provided by the Binary point position (or fraction
width) setting.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmemf64_<ChannelNumber>_count / Data Count Outputs the number of

elements in the current buffer. The maximum range depends on the specified
buffer size. You can use the value to define the valid range for the Address
inport of 0 … (Data Count -1).

xmemf64_<ChannelNumber>_dout / Data Outputs a 64-bit data value to

be read from an intermodule-bus buffer. The data format depends on the related
parameter settings.

xmemf64_<ChannelNumber>_new_data / Data New Outputs a flag that

xmemf64_<ChannelNumber>_addr / Address Specifies an element in the

Buffer64 Out.......................................................................................................................... 408

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Buffer Out

Purpose To write data to an intermodule-bus buffer with a data width of 32 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 129 … 160.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Buffer
size Lets you specify the size of the buffer in the range 1 … 32768.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

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Buffer64 Out

The channel number can be specified in the range 00 … 31.

xmemp_<ChannelNumber>_din / Data Specifies a 32-bit data value to be

written to an intermodule-bus buffer. The data format depends on the related
parameter settings.

xmemp_<ChannelNumber>_write / Enable Specifies the current valid Data

port value.
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.

xmemp_<ChannelNumber>_finished / Ready Explicitly specifies the buffer

xmemp_<ChannelNumber>_overflow / Overflow Outputs a flag that

Buffer In................................................................................................................................. 403

Buffer64 Out

Purpose To write data to an intermodule-bus buffer with a data width of 64 bits.

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Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 289 ... 320.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Buffer
size Lets you specify the size of the buffer in the range 1 … 32768.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 31.

xmemp64_<ChannelNumber>_din / Data Specifies a 64-bit data value to

be written to an intermodule-bus buffer. The data format depends on the related
parameter settings.

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Digital Crank/Cam Sensor

xmemp64_<ChannelNumber>_write / Enable Specifies the current valid

Data port value.
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.

xmemp64_<ChannelNumber>_finished / Ready Explicitly specifies the

buffer state as ready to send the buffer immediately, even if it is not completely
filled. The data values will be written to a new buffer in the next clock cycle.
While the port value is 1, transmission switches buffer in every clock cycle. The
value should therefore be set for one clock cycle only. If the buffer is completely
filled, it is automatically switched, and the data values are stored in a new buffer.
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready for sending, even if it is not completely filled.
The buffer is switched and the data values are accessible via intermodule bus
in the next clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.

xmemp64_<ChannelNumber>_overflow / Overflow Outputs a flag that

Buffer64 In............................................................................................................................. 405

Digital Crank/Cam Sensor

Purpose To provide bit-wise read access to digital camshaft and crankshaft sensors. Each
channel is 1 bit wide.

Description According to the number of physical connections available on the DS1554

Engine Control I/O Module, you can select the Digital Crank/Cam Sensor I/O
functions. There are five input channels.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 28 … 32.

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IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 4.

cam_<ChannelNumber> / Data Outputs the status of the crank/cam sensor.

Data type: UFix_1_0
§ 0: The input signal is lower than the Low threshold voltage parameter.
§ 1: The input signal is higher than the High threshold voltage parameter.
Update rate: 80 MHz

I/O mapping The following I/O mapping is relevant if you use the FPGA1403Tp1 (7K325) with
Engine Control I/O Module (DS1554) framework. The signals are available at the
DS1554 Sub-D I/O connector.

Outport Channel Connector Pin Signal

Data 1 13 Digital In 9 Channel 1 Signal
2 32 Digital In 9 Channel 2 Signal
3 14 Digital In 9 Channel 3 Signal
4 33 Digital In 9 Channel 4 Signal
5 12 Digital In 9 Channel 5 Signal

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Digital In (Type B)

Digital In (Type B)

Purpose To read data from a digital input signal in the FPGA application by using a
Digital InOut 8 channel.

Description According to the number of physical connections available on the DS1554

Engine Control I/O Module, you can select the Digital In (Type B) I/O functions.
There are eight digital input channels.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 2 … 9.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Note

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 07.

bidir_<ChannelNumber>_in / Data Outputs the current results of digital

input channel.
§ 0: Input voltage of the channel is below the specified threshold voltage.
§ 1: Input voltage of the channel is higher than or equal to the specified
threshold voltage.

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Update rate: 80 MHz

Note

§ The frequency that can be detected is much smaller than the update
rate. For information on the electrical characteristics of the DS1554
Engine Control I/O Module, refer to Digital In/Out 8 Characteristics
(MicroAutoBox III Hardware Installation and Configuration ).
§ Asynchronous input data might lead to metastable register states. Further
synchronization techniques might be necessary.

I/O mapping The following I/O mapping is relevant if you use the FPGA1403Tp1 (7K325) with
Engine Control I/O Module (DS1554) framework. The signals are available at the
DS1514 ZIF I/O connector. You can use the same digital channel for input and
output signals.

Digital Out (Type A)................................................................................................................ 456

Digital Out (Type B)................................................................................................................. 459
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Digital Out (Type A)

Purpose To write data to a digital output signal in the FPGA application using a Digital
Out 7 channel.

Description According to the number of physical connections available on the DS1554

Engine Control I/O Module, you can select the Digital Out (Type A) I/O
functions. There are 40 digital output channels.

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Digital Out (Type A)

The voltage range for the high-side switch for all digital output channels is in the
range 0 V … 45 V.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 2 … 41.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 39.

dig_<ChannelNumber>_out / Data Outputs a signal in the specified range.

Note

dig_<ChannelNumber>_oe / Enable Controls the hardware output. If set to

1, the hardware output reacts to the Data outport. Otherwise, it is set to High‑Z.

I/O mapping The following I/O mapping is relevant if you use the FPGA1403Tp1 (7K325) with
Engine Control I/O Module (DS1554) framework. The signals are available at the
DS1514 ZIF I/O connector.

Inport Channel Connector Pin Signal

Data 1 L5 Digital Out 7‑1 Channel 1 Signal
2 N2 Digital Out 7‑1 Channel 2 Signal
3 D3 Digital Out 7‑1 Channel 3 Signal
4 N5 Digital Out 7‑1 Channel 4 Signal
5 M6 Digital Out 7‑1 Channel 5 Signal
6 N3 Digital Out 7‑1 Channel 6 Signal
7 D5 Digital Out 7‑1 Channel 7 Signal

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Digital In (Type B).................................................................................................................... 455

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Digital Out (Type B)

Digital Out (Type B)

Purpose To write data to a digital output signal in the FPGA application by using a Digital
In/Out 8 channel.

Description According to the number of physical connections available on the DS1554

Engine Control I/O Module, you can select the Digital Out (Type B) I/O
functions. There are eight digital output channels.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 42 … 49.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

IOProperties.Out.Fct(42).Parameter(1).Init / High supply Lets you select

the voltage for the high-side switch for all digital output channels.
§ 0: 3.3 V
§ 1: 5 V

Note

You can specify the high supply voltage value only globally for all digital
output channels.
The I/O function number must be specified as 42.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 07.

bidir_<ChannelNumber>_out / Data Outputs a signal in the specified

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Update rate: 80 MHz

Note

bidir_<ChannelNumber>_oe / Enable Controls the hardware output. If set

to 1, the hardware output reacts to the Data outport, otherwise it is set to
High‑Z.
Data Type: UFix_1_0

Outport Channel Connector Pin Signal

Digital In (Type B).................................................................................................................... 455

Digital Out (Type A)................................................................................................................ 456
Overview of the Frameworks Available for MicroAutoBox III (FPGA1403Tp1)............................. 37

Inductive Zero Voltage Detector

Purpose To provide read access to an inductive zero voltage detector.

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Interrupt

Description The FPGA1403Tp1 (7K325) with Engine Control I/O Module (DS1554)
framework provides one channel for the Inductive Zero Voltage Detector I/O
function.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 33.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

I/O mapping The following I/O mapping is relevant if you use the FPGA1403Tp1 (7K325) with
Engine Control I/O Module (DS1554) framework. The signals are available at the
DS1554 Sub-D I/O connector.

Outport Connector Pin Signal

Data 10 Digital In 10 +
29 Digital In 10 -

Overview of the Frameworks Available for MicroAutoBox III (FPGA1403Tp1)............................. 37

Interrupt

Purpose To request a processor interrupt outside of the FPGA application.

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Description The FPGA1403Tp1 frameworks provide 8 interrupt lines. An interrupt is

requested if the Int port is set to 1 for at least one clock cycle. If you set
the Int port to 0, the last interrupt is not released but saved. An interrupt is
edge-triggered.

If you generate the processor interface model for this FPGA I/O function, a
PROC_INT_BL block is added to the processor model with the configured data
formats.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 8.

IRQProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 0 … 7.

usr_<ChannelNumber>_interrupt / Int Provides the interrupt request line.

§ 0 to 1: Interrupt is requested (edge-triggered).
§ 0: No interrupt is requested. Last requested interrupt is saved.

Overview of the Frameworks Available for MicroAutoBox III (FPGA1403Tp1)............................. 37

Knock Sensor

Purpose To read data from a knock sensor in the FPGA application.

Description According to the number of physical connections available on the DS1554

Engine Control I/O Module, you can select the Knock Sensor I/O functions.
There are 4 knock sensor input channels.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

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Knock Sensor

The I/O function number can be specified in the range 24 … 27.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 00 … 03.

knock_<ChannelNumber>_data / Data Outputs the current results of the

A/D conversions on the current channel.
Data type: UFix_16_0
Range: 0 … +65535
Input voltage range: –5 V ... +5 V
Update rate: 1 Msps

knock_<ChannelNumber>_soc / Start of conversion Triggers the start of

knock_<ChannelNumber>_eoc / End of conversion Outputs an end of

conversion signal if the conversion result is available on the specified channel.
If the flag changes from 0 to 1, the ADC data contains a new value. The flag is
set to 1 for only one clock cycle.
Data type: UFix_1_0

I/O mapping The following I/O mapping is relevant if you use the FPGA1403Tp1 (7K325) with
Engine Control I/O Module (DS1554) framework. The signals are available at the
DS1554 Sub-D I/O connector.

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LED Out

Purpose To write a digital signal that controls the FPGA status LED.

You can find the FPGA status LED near the DS1514 ZIF I/O connector.

Description The FPGA1403Tp1 (7K325) with Engine Control I/O Module (DS1554)
framework provides one channel for the LED Out I/O function.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 1.

IOProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

There is no channel number to be specified.

led_out / Data Controls the FPGA status LED.

Data type: UFix_1_0
§ 0: LED lights up green.
§ 1: LED lights up orange.

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Register In

Purpose To read data from an intermodule-bus register with a data width of 32 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 128.

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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I/O Functions of the FPGA1403Tp1 with Engine Control I/O Module Framework

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 127.

xreg_<ChannelNumber>_dout / Data Outputs a 32-bit data value to be

read from an intermodule-bus register. The data format depends on the related
parameter settings.

xreg_<ChannelNumber>_dout_wr / Data New Outputs a flag that

indicates the changes of the register status. If the flag changes from 0 to 1
and then back to 0, the requested register contains a new value. The flag is set
to 1 only within one clock cycle.

Buffer In................................................................................................................................. 446

Register64 In

Purpose To read data from an intermodule-bus register with a data width of 64 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 161 … 288.

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Register64 In

PHSProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(2).Init /
Format Lets you specify the data format of the Data outport.
§ signed/unsigned
The values of the Data outport are in fixed‑point format with or without one
bit reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
§ floating‑point
The values of the Data outport are in floating‑point format.
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is provided by the Binary point position (or fraction
width) setting.

PHSProperties.In.Fct(<IOFunctionNumber>).Parameter(3).Init / Register
group ID Lets you specify a number in the range 1 … 63 to create
register groups. Registers that you specified with the same group ID are
sampled simultaneously within the FPGA application. The values therefore form a
consistent data group that is written to the intermodule bus.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 127.

xreg64_<ChannelNumber>_dout / Data Outputs a 64-bit data value to be

read from an intermodule-bus register. The data format depends on the related
parameter settings.

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I/O Functions of the FPGA1403Tp1 with Engine Control I/O Module Framework

xreg64_<ChannelNumber>_dout_wr / Data New Outputs a flag that

indicates the changes of the register status. If the flag changes from 0 to 1
and then back to 0, the requested register contains a new value. The flag is set
to 1 only within one clock cycle.

Buffer64 In............................................................................................................................. 448

Purpose To write data to an intermodule-bus register with a data width of 32 bits.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 1 … 128.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

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Register64 Out

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Register
group ID Lets you specify a number in the range 1 … 63 to create register
groups. Registers that you specified with the same group ID are read from
the intermodule bus sequentially and then provided to the FPGA application
simultaneously.
Specify 0 for ungrouped read access.
§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 127.

xreg_<ChannelNumber>_din / Data Specifies a 32-bit data value to be

written to an intermodule-bus register. The data format depends on the related
parameter settings.

Buffer Out.............................................................................................................................. 450

Register64 Out

Purpose To write data to an intermodule-bus register with a data width of 64 bits.

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I/O Functions of the FPGA1403Tp1 with Engine Control I/O Module Framework

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number can be specified in the range 161 … 288.

PHSProperties.Out.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

PHSProperties.Out.Fct(<IOFunctionNumber>).Parameter(3).Init / Register
group ID Lets you specify a number in the range 1 … 63 to create register
groups. Registers that you specified with the same group ID are read from
the intermodule bus sequentially and then provided to the FPGA application
simultaneously.

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Status In

Specify 0 for ungrouped read access.

§ 0: Ungrouped access (default)
§ 1: Register group 1
§ …
§ 63: Register group 63

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

The channel number can be specified in the range 000 … 127.

xreg64_<ChannelNumber>_din / Data Specifies a 64-bit data value to be

written to an intermodule-bus register. The data format depends on the related
parameter settings.

Buffer64 Out.......................................................................................................................... 451

Status In

Purpose To read digital signals that output state information, e.g., the state of the FPGA
initialization sequence.

Description The FPGA1403Tp1 (7K325) with Engine Control I/O Module (DS1554)
framework provides one channel for the Status In I/O function.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 1.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

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I/O Functions of the FPGA1403Tp1 with Engine Control I/O Module Framework

Overview of the Frameworks Available for MicroAutoBox III (FPGA1403Tp1)............................. 37

Temperature

Purpose To read the FPGA die temperature.

Description The FPGA1403Tp1 (7K325) with Engine Control I/O Module (DS1554)
framework provides one channel for the Temperature I/O function.

This I/O function is not considered when you generate the processor interface
model.

Parameters You can find templates for the functions and the following parameters in the
handcode FPGA framework INI file.

The I/O function number must be specified as 34.

IOProperties.In.Fct(<IOFunctionNumber>).HcCustomName / Channel
name Lets you specify a custom name for the specified channel.

Port The following signals of the I/O function can be found in the port definition of
the custom module entity cm.

temperature / Temperature Outputs the raw value of the FPGA's die

high_temp / High Outputs a flag if the FPGA's die temperature exceeds

105 °C.
To reset the flag, the die temperature must fall below 85 °C.

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Temperature

Data type: UFix_1_0

§ 0: Die temperature does not exceed 105 °C.
§ 1: Die temperature exceeds 105 °C.

Note

A high ambient temperature and an FPGA application with a very high

Overview of the Frameworks Available for MicroAutoBox III (FPGA1403Tp1)............................. 37

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Index
Index
Buffer In (FPGA1403TP1) Analog Out (DS2655M1) 240
A DS1552 405 I/O mapping 241
DS1554 448 parameters 240
ADC (Type A) (FPGA1403TP1)
Buffer In (MicroLabBox II) 99 port 241
DS1554 444
Buffer64 In (DS1302) 50 Analog Out (DS6651) 276
I/O mapping
Buffer64 In (DS2655) 134 I/O mapping 277
DS1552 401
Buffer64 In (DS6601) 168 parameters 276
DS1554 445
Buffer64 In (DS6602) 203 port 277
parameters
Buffer64 In (FPGA1401TP1) Analog Out 13 (FPGA1403TP1)
DS1552 401
DS1552 331 DS1552 410
DS1554 445
DS1554 373 Analog Out 19 (MicroLabBox II) 90
port
Buffer64 In (FPGA1403TP1) I/O mapping 91
DS1552 401
DS1552 406 parameters 91
DS1554 445
DS1554 449 port 91
ADC (Type B) (FPGA1403TP1)
Buffer64 In (MicroLabBox II) 102 Analog Out 20 (MicroLabBox II) 92
I/O mapping 403
DDR4 32 Mode 1 210 I/O mapping 93
parameters 402
DDR4 64 Mode 1 215 parameters 92
port 402
I-FPGA In (IOCNET) (DS2655) 141 port 92
ADC (Type B) (FPGA1403TP3)
I-FPGA In (IOCNET) (DS6601) 175 Analog Out-T (DS6651) 278
DS1552 402
I-FPGA In (IOCNET) (DS6602) 219 I/O mapping 279
ADC Class 1 (DS1302) 44
I-FPGA64 In (IOCNET) (DS2655) 143 parameters 278
I/O mapping 45
I-FPGA64 In (IOCNET) (DS6601) 177 port 278
parameters 45
I-FPGA64 In (IOCNET) (DS6602) 221 Angle range
port 45
Address A APU Slave (DS2655) 129
ADC Class 2 (DS1302) 46
DDR4 32 Mode 2 212 APU Slave (DS6601) 163, 198
I/O mapping 46
DDR4 64 Mode 2 217 APU Slave (MicroLabBox II) 96
parameters 46
Address B Angle Range
port 46
DDR4 32 Mode 2 213 APU Slave (DS2655) 130
ADC Type A (FPGA1401TP1)
DDR4 64 Mode 2 217 APU Slave (DS6601) 164, 199
DS1552 325
Analog In (DS2655M1) 238 APU Slave (MicroLabBox II) 97
DS1554 368
I/O mapping 239 appl_run
I/O mapping
parameters 238 Proc App Status (DS1302) 64
DS1552 325
port 239 APU Master (DS2655) 127
DS1554 369
Analog In (DS6651) 270 I/O mapping 128
parameters
I/O mapping 273 parameters 127
DS1552 325
parameters 271 port 127
DS1554 369
ports 272 APU Master (DS6601) 161
port
Analog In 10 (FPGA1403TP1) I/O mapping 162
DS1552 325
DS1552 400 parameters 161
DS1554 369
Analog In 11 (FPGA1403TP1) port 161
ADC Type A (FPGA1403TP1)
DS1552B1 400 APU Master (DS6602) 195
DS1552 400
Analog In 12 (FPGA1403TP1) I/O mapping 197
ADC Type B (FPGA1401TP1) 326
DS1552 402 parameters 195
I/O mapping 327
Analog In 14 (FPGA1403TP1) port 196
parameters 327
DS1554 444 APU Master (MicroLabBox II) 93
port 327
Analog In 15 (FPGA1403TP1) I/O mapping 95
adctp1_<ChannelNumber>_busy
DS1554 462 parameters 93
ADC Class 1 (DS1302) 45
Analog In 23 (MicroLabBox II) 86 port 94
adctp1_<ChannelNumber>_convert
I/O mapping 87 APU Slave (DS2655) 129
ADC Class 1 (DS1302) 45
parameters 87 Angle range 129
adctp1_<ChannelNumber>_value
ports 87 I/O mapping 130
ADC Class 1 (DS1302) 45
Analog In 24 (MicroLabBox II) 88 parameters 129
adctp2_<ChannelNumber>_value
I/O mapping 89 port 130
ADC Class 2 (DS1302) 46
parameters 88 APU Slave (DS6601) 163, 197
Add internal pipeline register to relax timing
ports 88 Angle range 163, 198
I-FPGA In (SCALEXIO) 317
Analog In 25 (MicroLabBox II) 89 I/O mapping 164, 199
Address
I/O mapping 90 parameters 163, 197
Buffer In (DS1302) 48
parameters 89 port 164, 198
Buffer In (DS2655) 132
ports 89 APU Slave (MicroLabBox II) 95
Buffer In (DS6601) 166
Analog In-L (DS6651) 273 Angle range 96
Buffer In (DS6602) 200
I/O mapping 276 I/O mapping 97
Buffer In (FPGA1401TP1)
parameters 273 parameters 96
DS1552 329
ports 275 port 96
DS1554 372

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Index

Aurora 64b66b 128 Bit In DS1552 328 Register64 In (DS6601) 186

DS6601 303 DS1554 371 Register64 In (DS6602) 230
DS6602 303 Buffer In (FPGA1403TP1) Register64 In (FPGA1401TP1)
I/O mapping 305 DS1552 404 DS1552 349
parameters 304 DS1554 447 DS1554 391
port 304 Buffer In (MicroLabBox II) 98 Register64 In (FPGA1403TP1)
Aurora 64b66b 128 Bit Out Buffer Out (DS1302) 51 DS1552 425
DS6601 305 Buffer Out (DS2655) 135 DS1554 467
DS6602 305 Buffer Out (DS6601) 169 Register64 In (MicroLabBox II) 119
I/O mapping 307 Buffer Out (DS6602) 204 Register64 Out (DS1302) 69
parameters 306 Buffer Out (FPGA1401TP1) Register64 Out (DS2655) 155
port 306 DS1552 331 Register64 Out (DS6601) 189
Aurora 64b66b In DS1554 374 Register64 Out (DS6602) 233
DS6601 300 Buffer Out (FPGA1403TP1) Register64 Out (FPGA1401TP1)
DS6602 300 DS1552 407 DS1552 353
I/O mapping 301 DS1554 450 DS1554 395
parameters 300 Buffer Out (MicroLabBox II) 99 Register64 Out (FPGA1403TP1)
port 300 Buffer64 In (DS1302) 49 DS1552 428
Aurora 64b66b Out Buffer64 In (DS2655) 133 DS1554 470
DS6601 302 Buffer64 In (DS6601) 167 Register64 Out (MicroLabBox II) 120
DS6602 302 Buffer64 In (DS6602) 202 Bit length
I/O mapping 303 Buffer64 In (FPGA1401TP1) I-FPGA In (SCALEXIO) 315
parameters 302 DS1552 330 I-FPGA Out (SCALEXIO) 320
port 302 DS1554 372 Blue
Buffer64 In (FPGA1403TP1) LED Out (DS1302) 63
B DS1552 405 Buffer In (DS1302) 47
DS1554 448 parameters 47
Baud rate
Buffer64 In (MicroLabBox II) 101 port 48
UART RS232 (DS1302) 75
Buffer64 Out (DS1302) 53 Buffer In (DS2655) 131
UART RS232 (FPGA1401TP1) 357
Buffer64 Out (DS2655) 138 parameters 131
UART RS422/485 (DS1302) 79
Buffer64 Out (DS6601) 172 port 132
UART RS422/485 (FPGA1401TP1) 361
Buffer64 Out (DS6602) 206 Buffer In (DS6601) 165
UART RS422/485 (FPGA1403TP1) 436
Buffer64 Out (FPGA1401TP1) parameters 165
Beep Count
DS1552 333 port 166
Buzzer (DS1302) 55
DS1554 376 Buffer In (DS6602) 199
Beep Duration
Buffer64 Out (FPGA1403TP1) parameters 199
Buzzer (DS1302) 55
DS1552 409 port 200
bidir_<ChannelNumber>_in
DS1554 452 Buffer In (FPGA1401TP1)
Digital In (Type B) (FPGA1403TP1)
Buffer64 Out (MicroLabBox II) 103 DS1552 328
DS1552 416
Register In (DS1302) 65 DS1554 370
DS1554 455
Register In (DS2655) 151 parameters
Digital In Type B (FPGA1401TP1)
Register In (DS6601) 185 DS1552 328
DS1552 340
Register In (DS6602) 229 DS1554 371
DS1554 380
Register In (FPGA1401TP1) port
bidir_<ChannelNumber>_oe
DS1552 348 DS1552 329, 330
Digital Out (Type B) (FPGA1403TP1)
DS1554 389 DS1554 371, 373
DS1552 419
Register In (FPGA1403TP1) Buffer In (FPGA1403TP1)
DS1554 460
DS1552 423 DS1552 403
Digital Out Type B (FPGA1401TP1)
DS1554 465 DS1554 446
DS1552 344
Register In (MicroLabBox II) 115 parameters
DS1554 384
Register Out (DS1302) 68 DS1552 404
bidir_<ChannelNumber>_out
Register Out (DS2655) 154 DS1554 446
Digital Out (Type B) (FPGA1403TP1)
Register Out (DS6601) 188 port
DS1552 419
Register Out (DS6602) 232 DS1552 404, 406
DS1554 459
Register Out (FPGA1401TP1) DS1554 447, 449
Digital Out Type B (FPGA1401TP1)
DS1552 351 Buffer In (MicroLabBox II) 97
DS1552 344
DS1554 393 parameters 97
DS1554 384
Register Out (FPGA1403TP1) port 98
Binary point position
DS1552 426 Buffer Out (DS1302) 50
Buffer In (DS1302) 47
DS1554 468 parameters 51
Buffer In (DS2655) 131
Register Out (MicroLabBox II) 117 port 51
Buffer In (DS6601) 165
Register64 In (DS1302) 66 Buffer Out (DS2655) 135
Buffer In (DS6602) 199
Register64 In (DS2655) 152 parameters 135
Buffer In (FPGA1401TP1)

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Index

port 136 Buffer64 Out (FPGA1403TP1) DS1554 377

Buffer Out (DS6601) 169 DS1552 409 Buffer64 Out (FPGA1403TP1)
parameters 169 DS1554 452 DS1552 408
port 170 Buffer64 Out (MicroLabBox II) 104 DS1554 451
Buffer Out (DS6602) 203 I-FPGA In (IOCNET) (DS2655) 141 parameters
parameters 204 I-FPGA In (IOCNET) (DS6601) 175 DS1552 409
port 205 I-FPGA In (IOCNET) (DS6602) 219 DS1554 452
Buffer Out (FPGA1401TP1) I-FPGA Out (IOCNET) (DS2655) 144 port
DS1552 331 I-FPGA Out (IOCNET) (DS6601) 178 DS1552 409
DS1554 374 I-FPGA Out (IOCNET) (DS6602) 222 DS1554 452
parameters I-FPGA64 In (IOCNET) (DS2655) 143 Buffer64 Out (MicroLabBox II) 103
DS1552 331 I-FPGA64 In (IOCNET) (DS6601) 177 parameters 103
DS1554 374 I-FPGA64 In (IOCNET) (DS6602) 221 port 104
port I-FPGA64 Out (IOCNET) (DS2655) 146 Buffer64 size
DS1552 332 I-FPGA64 Out (IOCNET) (DS6601) 180 Buffer64 In (FPGA1401TP1)
DS1554 375 I-FPGA64 Out (IOCNET) (DS6602) 224 DS1552 330
Buffer Out (FPGA1403TP1) Buffer64 In (DS1302) 49 DS1554 373
DS1552 407 parameters 49 Buffer64 In (FPGA1403TP1)
DS1554 450 port 50 DS1552 406
parameters Buffer64 In (DS2655) 133 DS1554 449
DS1552 407 parameters 133 Busy
DS1554 450 port 134 ADC Class 1 (DS1302) 45
port Buffer64 In (DS6601) 167 DAC Class 1 (DS1302) 56
DS1552 407 parameters 167 DDR4 32 Mode 1 210
DS1554 450 port 168 DDR4 32 Mode 2 212
Buffer Out (MicroLabBox II) 99 Buffer64 In (DS6602) 201 DDR4 64 Mode 1 215
parameters 99 parameters 201 DDR4 64 Mode 2 217
port 100 port 202 Buzzer (DS1302) 54
Buffer size Buffer64 In (FPGA1401TP1) parameters 54
Buffer In (DS1302) 48 DS1552 329 port 54
Buffer In (DS2655) 131 DS1554 372 buzzer start
Buffer In (DS6601) 165 parameters Buzzer (DS1302) 55
Buffer In (DS6602) 200 DS1552 330 buzzer_beep_count
Buffer In (FPGA1401TP1) DS1554 372 Buzzer (DS1302) 55
DS1552 328 Buffer64 In (FPGA1403TP1) buzzer_beep_duration
DS1554 371 DS1552 405 Buzzer (DS1302) 55
Buffer In (FPGA1403TP1) DS1554 448 buzzer_frequency
DS1552 404 parameters Buzzer (DS1302) 55
DS1554 447 DS1552 405 buzzer_pause_duration
Buffer In (MicroLabBox II) 98 DS1554 448 Buzzer (DS1302) 55
Buffer Out (DS1302) 51 Buffer64 In (MicroLabBox II) 101
Buffer Out (DS2655) 136 parameters 101 C
Buffer Out (DS6601) 170 port 102
cam_<ChannelNumber>
Buffer Out (DS6602) 204 Buffer64 Out (DS1302) 52
Digital Crank/Cam Sensor (FPGA1401TP1)
Buffer Out (FPGA1401TP1) parameters 52
DS1552 337
DS1552 332 port 53
DS1554 378
DS1554 375 Buffer64 Out (DS2655) 137
Digital Crank/Cam Sensor (FPGA1403TP1)
Buffer Out (FPGA1403TP1) parameters 138
DS1552 412
DS1552 407 port 139
DS1554 454
DS1554 450 Buffer64 Out (DS6601) 171
Channel name
Buffer Out (MicroLabBox II) 100 parameters 172
ADC (Type A) (FPGA1403TP1)
Buffer64 In (DS1302) 50 port 173
DS1552 401
Buffer64 In (DS2655) 134 Buffer64 Out (DS6602) 206
DS1554 445
Buffer64 In (DS6601) 168 parameters 206
ADC (Type B) (FPGA1403TP1) 402
Buffer64 In (DS6602) 202 port 207
ADC Class 1 (DS1302) 45
Buffer64 In (MicroLabBox II) 102 Buffer64 Out (FPGA1401TP1)
ADC Class 2 (DS1302) 46
Buffer64 Out (DS1302) 53 DS1552 333
ADC Type A (FPGA1401TP1)
Buffer64 Out (DS2655) 138 DS1554 376
DS1552 325
Buffer64 Out (DS6601) 172 parameters
DS1554 369
Buffer64 Out (DS6602) 207 DS1552 333
ADC Type B (FPGA1401TP1) 327
Buffer64 Out (FPGA1401TP1) DS1554 376
Analog In (DS2655M1) 238
DS1552 334 port
Analog In (DS6651) 271
DS1554 377 DS1552 334
Analog In 23 (MicroLabBox II) 87

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Index

Analog In 24 (MicroLabBox II) 88 CN App Status (MicroLabBox II) 105 DS1554 385
Analog In 25 (MicroLabBox II) 89 DAC (FPGA1401TP1) 335 Inductive Zero Voltage Detector
Analog In-L (DS6651) 274 DAC (FPGA1403TP1) 410 (FPGA1403TP1)
Analog Out (DS2655M1) 240 DAC Class 1 (DS1302) 56 DS1552 420
Analog Out (DS6651) 277 Digital Crank/Cam Sensor (FPGA1401TP1) DS1554 461
Analog Out 19 (MicroLabBox II) 91 DS1552 336 Interrupt (DS1302) 62
Analog Out 20 (MicroLabBox II) 92 DS1554 378 Interrupt (DS2655) 148
Analog Out-T (DS6651) 278 Digital Crank/Cam Sensor (FPGA1403TP1) Interrupt (DS6601) 182
APU Master (DS2655) 127 DS1552 412 Interrupt (DS6602) 226
APU Master (DS6601) 161 DS1554 453 Interrupt (FPGA1401TP1)
APU Master (DS6602) 195 Digital In (DS2655M1) 242 DS1552 346
APU Master (MicroLabBox II) 93 Digital In (DS2655M2) 251 DS1554 386
APU Slave (DS2655) 129 Digital In (DS6651) 279 Interrupt (FPGA1403TP1)
APU Slave (DS6601) 163, 197 Digital In (Type A) (FPGA1403TP1) 413 DS1552 421
APU Slave (MicroLabBox II) 96 Digital In (Type B) (FPGA1403TP1) DS1554 462
Buffer In (DS1302) 47 DS1552 415 Interrupt (MicroLabBox II) 113
Buffer In (DS2655) 131 DS1554 455 IOCNET Global Time (DS2655) 149
Buffer In (DS6601) 165 Digital In Type A (FPGA1401TP1) 338 IOCNET Global Time (DS6601) 183
Buffer In (DS6602) 199 Digital In Type B (FPGA1401TP1) IOCNET Global Time (DS6602) 227
Buffer In (FPGA1401TP1) DS1552 340 IOCNET Global Time (MicroLabBox II) 114
DS1552 328 DS1554 379 Knock Sensor (FPGA1401TP1) 387
DS1554 371 Digital In/Out 14 (In) (MicroLabBox II) 106 Knock Sensor (FPGA1403TP1) 462
Buffer In (FPGA1403TP1) Digital In/Out 14 (In/Out-Z) LED Out (DS1302) 63
DS1552 404 (MicroLabBox II) 108 LED Out (DS2655) 150
DS1554 446 Digital In/Out 15 (MicroLabBox II) 111 LED Out (DS6601) 184
Buffer In (MicroLabBox II) 97 Digital In/Out-Z (DS6651) 281 LED Out (DS6602) 228
Buffer Out (DS1302) 51 Digital InOut (DS2655M1) 244 LED Out (FPGA1401TP1)
Buffer Out (DS2655) 135 Digital InOut Class 1 (DS1302) 57 DS1552 347
Buffer Out (DS6601) 169 Digital InOut Class 2 (DS1302) 60 DS1554 388
Buffer Out (DS6602) 204 Digital Out (DS2655M1) 246 LED Out (FPGA1403TP1)
Buffer Out (FPGA1401TP1) Digital Out (DS2655M2) 253 DS1552 422
DS1552 331 Digital Out (DS6651) 285 DS1554 464
DS1554 374 Digital Out (Type A) (FPGA1403TP1) LED Out (MicroLabBox II) 114
Buffer Out (FPGA1403TP1) DS1552 417 Proc App Status (DS1302) 64
DS1552 407 DS1554 457 Register In (DS1302) 64
DS1554 450 Digital Out (Type B) (FPGA1403TP1) Register In (DS2655) 150
Buffer Out (MicroLabBox II) 99 DS1552 418 Register In (DS6601) 184
Buffer64 In (DS1302) 49 DS1554 459 Register In (DS6602) 228
Buffer64 In (DS2655) 133 Digital Out Type A (FPGA1401TP1) Register In (FPGA1401TP1)
Buffer64 In (DS6601) 167 DS1552 342 DS1552 348
Buffer64 In (DS6602) 201 DS1554 381 DS1554 389
Buffer64 In (FPGA1401TP1) Digital Out Type B (FPGA1401TP1) Register In (FPGA1403TP1)
DS1552 330 DS1552 343 DS1552 423
DS1554 372 DS1554 383 DS1554 465
Buffer64 In (FPGA1403TP1) Digital Out-Z (DS2655M2) 256 Register In (MicroLabBox II) 115
DS1552 405 Digital Out-Z (DS6651) 287 Register Out (DS1302) 68
DS1554 448 I-FPGA In (IOCNET) (DS2655) 141 Register Out (DS2655) 154
Buffer64 In (MicroLabBox II) 101 I-FPGA In (IOCNET) (DS6601) 175 Register Out (DS6601) 188
Buffer64 Out (DS1302) 52 I-FPGA In (IOCNET) (DS6602) 219 Register Out (DS6602) 232
Buffer64 Out (DS2655) 138 I-FPGA In (SCALEXIO) 314 Register Out (FPGA1401TP1)
Buffer64 Out (DS6601) 172 I-FPGA Out (IOCNET) (DS2655) 144 DS1552 351
Buffer64 Out (DS6602) 206 I-FPGA Out (IOCNET) (DS6601) 178 DS1554 393
Buffer64 Out (FPGA1401TP1) I-FPGA Out (IOCNET) (DS6602) 222 Register Out (FPGA1403TP1)
DS1552 333 I-FPGA Out (SCALEXIO) 319 DS1552 426
DS1554 376 I-FPGA64 In (IOCNET) (DS2655) 142 DS1554 468
Buffer64 Out (FPGA1403TP1) I-FPGA64 In (IOCNET) (DS6601) 176 Register Out (MicroLabBox II) 117
DS1552 409 I-FPGA64 In (IOCNET) (DS6602) 220 Register64 In (DS1302) 66
DS1554 452 I-FPGA64 Out (IOCNET) (DS2655) 146 Register64 In (DS2655) 152
Buffer64 Out (MicroLabBox II) 103 I-FPGA64 Out (IOCNET) (DS6601) 180 Register64 In (DS6601) 186
Buzzer (DS1302) 54 I-FPGA64 Out (IOCNET) (DS6602) 224 Register64 In (DS6602) 230
CN App Status (DS2655) 140 Inductive Zero Voltage Detector Register64 In (FPGA1401TP1)
CN App Status (DS6601) 174 (FPGA1401TP1) DS1552 349
CN App Status (DS6602) 209 DS1552 345 DS1554 391

478
FPGA Programming Handcode Framework - FPGA Interface Reference May 2024
Index

Register64 In (FPGA1403TP1) CN App Status (DS6602) 208 Analog In (DS2655M1) 239

DS1552 424 parameters 209 Analog In (DS6651) 272
DS1554 466 port 209 Analog In 23 (MicroLabBox II) 87
Register64 In (MicroLabBox II) 119 CN App Status (MicroLabBox II) 105 Analog In 24 (MicroLabBox II) 88
Register64 Out (DS1302) 69 parameters 105 Analog In 25 (MicroLabBox II) 90
Register64 Out (DS2655) 155 port 105 Analog In-L (DS6651) 275
Register64 Out (DS6601) 189 CN Application Status Analog Out (DS2655M1) 241
Register64 Out (DS6602) 233 CN App Status (DS2655) 140, 149 Analog Out (DS6651) 277
Register64 Out (FPGA1401TP1) CN App Status (DS6601) 174, 183 Analog Out 19 (MicroLabBox II) 91
DS1552 353 CN App Status (DS6602) 209, 227 Analog Out 20 (MicroLabBox II) 92
DS1554 394 CN App Status (MicroLabBox II) 105, 114 Analog Out-T (DS6651) 278
Register64 Out (FPGA1403TP1) Common Program Data folder 12 Aurora 64b66b 128 Bit In 304
DS1552 428 Convert Aurora 64b66b 128 Bit Out 306
DS1554 470 ADC Class 1 (DS1302) 45 Aurora 64b66b In 300
Register64 Out (MicroLabBox II) 120 DAC Class 1 (DS1302) 56 Aurora 64b66b Out 303
Resolver (DS1302) 71 crank Buffer In (DS1302) 48
RS232 Rx (DS2655M2) 258 Inductive Zero Voltage Detector Buffer In (DS2655) 132
RS232 Tx (DS2655M2) 260 (FPGA1401TP1) Buffer In (DS6601) 166
RS485 Rx (DS2655M2) 261 DS1552 345 Buffer In (DS6602) 200
RS485 Rx (DS6651) 290 DS1554 385 Buffer In (FPGA1401TP1)
RS485 Rx/Tx (DS6651) 291 Inductive Zero Voltage Detector DS1552 329
RS485 RxTx (DS2655M2) 263 (FPGA1403TP1) DS1554 371
RS485 Tx (DS2655M2) 265 DS1552 420 Buffer In (FPGA1403TP1)
RS485 Tx (DS6651) 294 DS1554 461 DS1552 404
Sensor Supply (FPGA1401TP1) CTS DS1554 447
DS1552 354 UART 3 RS232 (FPGA1403TP1) 435 Buffer In (MicroLabBox II) 98
Sensor Supply (FPGA1403TP1) UART RS232 (DS1302) 78 Buffer Out (DS1302) 51
DS1552 429 UART RS232 (FPGA1401TP1) 360 Buffer Out (DS2655) 136
Status In (DS1302) 74 Buffer Out (DS6601) 170
Status In (DS2655) 157 D Buffer Out (DS6602) 205
Status In (DS6601) 191 Buffer Out (FPGA1401TP1)
DAC (FPGA1401TP1) 335
Status In (DS6602) 235 DS1552 332
I/O mapping 336
Status In (FPGA1401TP1) DS1554 375
parameters 335
DS1552 355 Buffer Out (FPGA1403TP1)
port 335
DS1554 396 DS1552 408
DAC (FPGA1403TP1)
Status In (FPGA1403TP1) DS1554 451
DS1552 410
DS1552 430 Buffer Out (MicroLabBox II) 100
I/O mapping 411
DS1554 471 Buffer64 In (DS1302) 50
parameters 410
Status In (MicroLabBox II) 122 Buffer64 In (DS2655) 134
port 411
Temperature (FPGA1401TP1) 397 Buffer64 In (DS6601) 168
DAC Class 1 (DS1302) 56
Temperature (FPGA1403TP1) 472 Buffer64 In (DS6602) 202
I/O mapping 56
Trigger (DS6651) 296 Buffer64 In (FPGA1401TP1)
parameters 56
UART 3 RS232 (FPGA1403TP1) 432 DS1552 330
port 56
UART 3 RS422/485 (FPGA1403TP1) 436 DS1554 373
dac<ChannelNumber>_data
UART RS232 (DS1302) 75 Buffer64 In (FPGA1403TP1)
DAC (FPGA1401TP1) 335
UART RS232 (FPGA1401TP1) 357 DS1552 406
DAC (FPGA1403TP1) 411
UART RS422/485 (DS1302) 79 DS1554 449
dactp1_<ChannelNumber>_busy
UART RS422/485 (FPGA1401TP1) 361 Buffer64 In (MicroLabBox II) 102
DAC Class 1 (DS1302) 56
Watchdog (DS6601) 192 Buffer64 Out (DS1302) 53
dactp1_<ChannelNumber>_convert
Watchdog (DS6602) 236 Buffer64 Out (DS2655) 139
DAC Class 1 (DS1302) 56
CLK_N Buffer64 Out (DS6601) 173
dactp1_<ChannelNumber>_value
MGT In 308 Buffer64 Out (DS6602) 207
DAC Class 1 (DS1302) 56
CLK_P Buffer64 Out (FPGA1401TP1)
Data
MGT In 308 DS1552 334
ADC (Type A) (FPGA1403TP1)
Clock DS1554 377
DS1552 401
I-FPGA In (SCALEXIO) 316 Buffer64 Out (FPGA1403TP1)
DS1554 445
I-FPGA Out (SCALEXIO) 320 DS1552 409
ADC (Type B) (FPGA1403TP1) 403
CN App Status (DS2655) 140 DS1554 452
ADC Class 1 (DS1302) 45
parameters 140 Buffer64 Out (MicroLabBox II) 104
ADC Class 2 (DS1302) 46
port 140 DAC (FPGA1401TP1) 335
ADC Type A (FPGA1401TP1)
CN App Status (DS6601) 174 DAC (FPGA1403TP1) 411
DS1552 325
parameters 174 DAC Class 1 (DS1302) 56
DS1554 369
port 174 Digital Crank/Cam Sensor (FPGA1401TP1)
ADC Type B (FPGA1401TP1) 327

479
May 2024 FPGA Programming Handcode Framework - FPGA Interface Reference
Index

DS1552 337 Register In (DS6601) 185 Buffer In (MicroLabBox II) 98

DS1554 378 Register In (DS6602) 229 Buffer64 In (DS1302) 50
Digital Crank/Cam Sensor (FPGA1403TP1) Register In (FPGA1401TP1) Buffer64 In (DS2655) 134
DS1552 412 DS1552 349 Buffer64 In (DS6601) 168
DS1554 454 DS1554 390 Buffer64 In (DS6602) 202
Digital In (DS2655M1) 242 Register In (FPGA1403TP1) Buffer64 In (FPGA1401TP1)
Digital In (DS2655M2) 251 DS1552 424 DS1552 330
Digital In (DS6651) 280 DS1554 466 DS1554 373
Digital In (Type A) (FPGA1403TP1) 414 Register In (MicroLabBox II) 116 Buffer64 In (FPGA1403TP1)
Digital In (Type B) (FPGA1403TP1) Register Out (DS1302) 69 DS1552 406
DS1552 416 Register Out (DS2655) 155 DS1554 449
DS1554 455 Register Out (DS6601) 189 Buffer64 In (MicroLabBox II) 102
Digital In Type A (FPGA1401TP1) 339 Register Out (DS6602) 233 I-FPGA In (IOCNET) (DS2655) 142
Digital In Type B (FPGA1401TP1) Register Out (FPGA1401TP1) I-FPGA In (IOCNET) (DS6601) 176
DS1552 340 DS1552 352 I-FPGA In (IOCNET) (DS6602) 219
DS1554 380 DS1554 394 I-FPGA64 In (IOCNET) (DS2655) 143
Digital Out (DS2655M1) 247 Register Out (FPGA1403TP1) I-FPGA64 In (IOCNET) (DS6601) 177
Digital Out (DS2655M2) 254 DS1552 427 I-FPGA64 In (IOCNET) (DS6602) 221
Digital Out (DS6651) 285 DS1554 469 Data direction
Digital Out (Type A) (FPGA1403TP1) Register Out (MicroLabBox II) 118 Digital InOut (DS2655M1) 245
DS1552 417 Register64 In (DS1302) 67 Data In
DS1554 457 Register64 In (DS2655) 153 Digital In/Out-Z (DS6651) 282
Digital Out (Type B) (FPGA1403TP1) Register64 In (DS6601) 187 Digital InOut Class 1 (DS1302) 58
DS1552 419 Register64 In (DS6602) 231 Digital InOut Class 2 (DS1302) 61
DS1554 459 Register64 In (FPGA1401TP1) Data New
Digital Out Type A (FPGA1401TP1) DS1552 350 Analog In (DS2655M1) 239
DS1552 342 DS1554 392 Analog In (DS6651) 272
DS1554 381 Register64 In (FPGA1403TP1) Analog In 23 (MicroLabBox II) 87
Digital Out Type B (FPGA1401TP1) DS1552 425 Analog In 24 (MicroLabBox II) 88
DS1552 344 DS1554 467 Analog In 25 (MicroLabBox II) 90
DS1554 384 Register64 In (MicroLabBox II) 120 Analog In-L (DS6651) 275
Digital Out-Z (DS2655M2) 256 Register64 Out (DS1302) 70 Aurora 64b66b 128 Bit In 304
Digital Out-Z (DS6651) 288 Register64 Out (DS2655) 156 Aurora 64b66b In 301
I-FPGA In (IOCNET) (DS2655) 142 Register64 Out (DS6601) 190 Buffer In (DS1302) 48
I-FPGA In (IOCNET) (DS6601) 176 Register64 Out (DS6602) 234 Buffer In (DS2655) 132
I-FPGA In (IOCNET) (DS6602) 220 Register64 Out (FPGA1401TP1) Buffer In (DS6601) 166
I-FPGA Out (IOCNET) (DS2655) 145 DS1552 354 Buffer In (DS6602) 200
I-FPGA Out (IOCNET) (DS6601) 179 DS1554 395 Buffer In (FPGA1401TP1)
I-FPGA Out (IOCNET) (DS6602) 223 Register64 Out (FPGA1403TP1) DS1552 329
I-FPGA64 In (IOCNET) (DS2655) 143 DS1552 429 DS1554 372
I-FPGA64 In (IOCNET) (DS6601) 177 DS1554 471 Buffer In (FPGA1403TP1)
I-FPGA64 In (IOCNET) (DS6602) 221 Register64 Out (MicroLabBox II) 121 DS1552 404
I-FPGA64 Out (IOCNET) (DS2655) 147 RS232 Rx (DS2655M2) 259 DS1554 447
I-FPGA64 Out (IOCNET) (DS6601) 181 RS232 Tx (DS2655M2) 260 Buffer In (MicroLabBox II) 98
I-FPGA64 Out (IOCNET) (DS6602) 225 RS485 Rx (DS2655M2) 262 Buffer64 In (DS1302) 50
Inductive Zero Voltage Detector RS485 Rx (DS6651) 290 Buffer64 In (DS2655) 134
(FPGA1401TP1) RS485 Tx (DS2655M2) 266 Buffer64 In (DS6601) 168
DS1552 345 RS485 Tx (DS6651) 294 Buffer64 In (DS6602) 203
DS1554 385 Data (In) Buffer64 In (FPGA1401TP1)
Inductive Zero Voltage Detector Digital InOut (DS2655M1) 245 DS1552 331
(FPGA1403TP1) Data (Out) DS1554 373
DS1552 420 Digital InOut (DS2655M1) 245 Buffer64 In (FPGA1403TP1)
DS1554 461 Data Count DS1552 406
Knock Sensor (FPGA1401TP1) 387 Buffer In (DS1302) 48 DS1554 449
Knock Sensor (FPGA1403TP1) 463 Buffer In (DS2655) 132 Buffer64 In (MicroLabBox II) 102
LED Out (FPGA1401TP1) Buffer In (DS6601) 166 I-FPGA In (IOCNET) (DS2655) 142
DS1552 347 Buffer In (DS6602) 200 I-FPGA In (IOCNET) (DS6601) 176
DS1554 389 Buffer In (FPGA1401TP1) I-FPGA In (IOCNET) (DS6602) 220
LED Out (FPGA1403TP1) DS1552 329 I-FPGA In (SCALEXIO) 317
DS1552 422 DS1554 371 I-FPGA64 In (IOCNET) (DS2655) 144
DS1554 464 Buffer In (FPGA1403TP1) I-FPGA64 In (IOCNET) (DS6601) 178
Register In (DS1302) 65 DS1552 404 I-FPGA64 In (IOCNET) (DS6602) 222
Register In (DS2655) 151 DS1554 447 Register In (DS1302) 65

480
FPGA Programming Handcode Framework - FPGA Interface Reference May 2024
Index

Register In (DS2655) 151 I/O mapping 214 DDR4 64 Mode 1 214

Register In (DS6601) 185 parameters 212 DDR4 64 Mode 2 216
Register In (DS6602) 229 port 212 ddr4_init_fail
Register In (FPGA1401TP1) DDR4 64 Mode 1 DDR4 32 Mode 1 210
DS1552 349 DS6602 214 DDR4 32 Mode 2 212
DS1554 390 I/O mapping 216 DDR4 64 Mode 1 215
Register In (FPGA1403TP1) parameters 214 DDR4 64 Mode 2 217
DS1552 424 port 214 ddr4_rd_data_valid_1_block_3
DS1554 466 DDR4 64 Mode 2 DDR4 32 Mode 2 213
Register In (MicroLabBox II) 116 DS6602 216 ddr4_rd_data_valid_1_block_4
Register64 In (DS1302) 67 I/O mapping 218 DDR4 64 Mode 2 217
Register64 In (DS2655) 153 parameters 216 ddr4_rd_data_valid_2_block_3
Register64 In (DS6601) 187 port 216 DDR4 32 Mode 2 213
Register64 In (DS6602) 231 ddr4_address_1_block_3 ddr4_rd_data_valid_2_block_4
Register64 In (FPGA1401TP1) DDR4 32 Mode 2 212 DDR4 64 Mode 2 218
DS1552 350 ddr4_address_1_block_4 ddr4_rd_data_valid_block_1
DS1554 392 DDR4 64 Mode 2 217 DDR4 32 Mode 1 211
Register64 In (FPGA1403TP1) ddr4_address_2_block_3 ddr4_rd_data_valid_block_2
DS1552 426 DDR4 32 Mode 2 213 DDR4 64 Mode 1 215
DS1554 468 ddr4_address_2_block_4 Delta Phi
Register64 In (MicroLabBox II) 120 DDR4 64 Mode 2 217 APU Master (DS2655) 128
Data Out ddr4_address_block_1 APU Master (DS6601) 162
Digital In/Out-Z (DS6651) 282 DDR4 32 Mode 1 210 APU Master (DS6602) 196
Digital InOut Class 1 (DS1302) 59 ddr4_address_block_2 APU Master (MicroLabBox II) 94
Digital InOut Class 2 (DS1302) 61 DDR4 64 Mode 1 215 APU Slave (DS2655) 130
Data Read ddr4_busy_flag APU Slave (DS6601) 164, 199
DDR4 32 Mode 1 211 DDR4 32 Mode 1 210 APU Slave (MicroLabBox II) 97
DDR4 64 Mode 1 215 DDR4 32 Mode 2 212 Delta Phi Enable
I-FPGA In (SCALEXIO) 317 DDR4 64 Mode 1 215 APU Master (DS2655) 128
Data Read A DDR4 64 Mode 2 217 APU Master (DS6601) 162
DDR4 32 Mode 2 213 ddr4_data_<PortNumber>_rd_32_block_1 APU Master (DS6602) 196
DDR4 64 Mode 2 218 DDR4 32 Mode 1 211 APU Master (MicroLabBox II) 94
Data Read B ddr4_data_<PortNumber>_rd_64_block_2 APU Slave (DS2655) 130
DDR4 32 Mode 2 213 DDR4 64 Mode 1 215 APU Slave (DS6601) 164, 199
DDR4 64 Mode 2 218 ddr4_data_<PortNumber>_wr_32_block_1 APU Slave (MicroLabBox II) 97
Data Sent Data Write 211 Desired excitation frequency
I-FPGA Master (SCALEXIO) 321 ddr4_data_<PortNumber>_wr_64_block_2 Resolver (DS1302) 71
Data valid Data Write 215 dig_<ChannelNumber>_in
DDR4 32 Mode 1 211 ddr4_data_1_<PortNumber>_rd_32_block_3 Digital In (Type A) (FPGA1403TP1) 414
DDR4 64 Mode 1 215 DDR4 32 Mode 2 213 Digital In Type A (FPGA1401TP1) 339
Data valid A ddr4_data_1_<PortNumber>_rd_64_block_4 dig_<ChannelNumber>_oe
DDR4 32 Mode 2 213 DDR4 64 Mode 2 218 Digital Out (Type A) (FPGA1403TP1)
DDR4 64 Mode 2 217 ddr4_data_1_<PortNumber>_wr_32_block_3 DS1552 417
Data valid B DDR4 32 Mode 2 213 DS1554 457
DDR4 32 Mode 2 213 ddr4_data_1_<PortNumber>_wr_64_block_4 Digital Out Type A (FPGA1401TP1)
DDR4 64 Mode 2 218 DDR4 64 Mode 2 218 DS1552 342
Data Write ddr4_data_2_<PortNumber>_rd_32_block_3 DS1554 382
DDR4 32 Mode 1 211 DDR4 32 Mode 2 213 dig_<ChannelNumber>_out
DDR4 64 Mode 1 215 ddr4_data_2_<PortNumber>_rd_64_block_4 Digital Out (Type A) (FPGA1403TP1)
I-FPGA Master (SCALEXIO) 321 DDR4 64 Mode 2 218 DS1552 417
Data Write A ddr4_data_en DS1554 457
DDR4 32 Mode 2 213 DDR4 32 Mode 1 210 Digital Out Type A (FPGA1401TP1)
DDR4 64 Mode 2 218 DDR4 32 Mode 2 212 DS1552 342
Data Write B DDR4 64 Mode 1 215 DS1554 381
DDR4 32 Mode 2 213 DDR4 64 Mode 2 217 DigIn
DDR4 64 Mode 2 218 ddr4_direction Digital In/Out 14 (In/Out-Z)
DDR4 32 Mode 1 DDR4 32 Mode 1 210 (MicroLabBox II) 107, 109
DS6602 209 DDR4 32 Mode 2 212 Digital In/Out 15 (MicroLabBox II) 111
I/O mapping 211 DDR4 64 Mode 1 215 Digital Crank/Cam Sensor (FPGA1401TP1)
parameters 209 DDR4 64 Mode 2 217 DS1552 336
port 210 ddr4_init_done DS1554 378
DDR4 32 Mode 2 DDR4 32 Mode 1 210 I/O mapping
DS6602 211 DDR4 32 Mode 2 212 DS1552 337

481
May 2024 FPGA Programming Handcode Framework - FPGA Interface Reference
Index

DS1554 378 Digital In Type A (FPGA1403TP1) DS1552 417

parameters DS1552 413 DS1554 456
DS1552 336 Digital In Type B (FPGA1401TP1) I/O mapping
DS1554 378 DS1552 340 DS1552 417
port DS1554 379 DS1554 457
DS1552 337 I/O mapping parameters
DS1554 378 DS1552 341 DS1552 417
Digital Crank/Cam Sensor (FPGA1403TP1) DS1554 380 DS1554 457
DS1552 411 parameters port
DS1554 453 DS1552 340 DS1552 417
I/O mapping DS1554 379 DS1554 457
DS1552 412 port Digital Out (Type B) (FPGA1403TP1)
DS1554 454 DS1552 340 DS1552 418
parameters DS1554 380 DS1554 459
DS1552 412 Digital In/Out 14 (In) (MicroLabBox II) 106 I/O mapping
DS1554 453 I/O mapping 107 DS1552 419
port parameters 106 DS1554 460
DS1552 412 ports 106 parameters
DS1554 454 Digital In/Out 14 (In/Out-Z) (MicroLabBox II) 107 DS1552 418
Digital In (DS2655M1) 242 I/O mapping 110 DS1554 459
I/O mapping 242 parameters 108 port
parameters 242 ports 109 DS1552 419
port 242 Digital In/Out 15 (MicroLabBox II) 110 DS1554 459
Digital In (DS2655M2) 250 I/O mapping 112 Digital Out 5 (FPGA1403TP1)
I/O mapping 251 parameters 110 DS1552 417
parameters 250 port 111 Digital Out 7 (FPGA1403TP1)
port 251 Digital In/Out 8 (FPGA1403TP1) DS1554 456
Digital In (DS6651) 279 DS1554 459 Digital Out Type A (FPGA1401TP1)
I/O mapping 280 Digital In/Out-Z (DS6651) 281 DS1552 341
parameters 279 I/O mapping 283 DS1554 381
port 280 parameters 281 I/O mapping
Digital In (Type A) (FPGA1403TP1) ports 282 DS1552 342
I/O mapping 414 Digital InOut (DS2655M1) 243 DS1554 382
parameters 413 I/O mapping 245 parameters
port 414 parameters 243 DS1552 342
Digital In (Type B) (FPGA1403TP1) port 244 DS1554 381
DS1552 415 Digital InOut 6 (FPGA1403TP1) port
DS1554 455 DS1552 415 DS1552 342
I/O mapping Digital InOut 6 (Out) (FPGA1403TP1) DS1554 381
DS1552 416 DS1552 418 Digital Out Type B (FPGA1401TP1)
DS1554 456 Digital InOut 8 (FPGA1403TP1) DS1552 343
parameters DS1554 455 DS1554 383
DS1552 415 Digital InOut Class 1 (DS1302) 57 I/O mapping
DS1554 455 I/O mapping 59 DS1552 344
port parameters 57 DS1554 384
DS1552 416 port 58 parameters
DS1554 455 Digital InOut Class 2 (DS1302) 60 DS1552 343
Digital In 10 (FPGA1403TP1) I/O mapping 61 DS1554 383
DS1554 460 parameters 60 port
Digital In 5 (FPGA1403TP1) port 60 DS1552 344
DS1552 413 Digital Out (DS2655M1) 246 DS1554 384
Digital In 6 (FPGA1403TP1) I/O mapping 247 Digital Out-Z (DS2655M2) 255
DS1552 411 parameters 246 I/O mapping 257
Digital In 7 (FPGA1403TP1) port 247 parameters 256
DS1552 420 Digital Out (DS2655M2) 253 port 256
Digital In 9 (FPGA1403TP1) I/O mapping 254 Digital Out-Z (DS6651) 287
DS1554 453 parameters 253 I/O mapping 288
Digital in threshold init voltage port 253 parameters 287
Digital InOut (DS2655M1) 244 Digital Out (DS6651) 284 ports 288
Digital In Type A (FPGA1401TP1) 338 I/O mapping 286 DigOut
I/O mapping 339 parameters 284 Digital In/Out 14 (In/Out-Z)
parameters 338 port 285 (MicroLabBox II) 109
port 338 Digital Out (Type A) (FPGA1403TP1) Digital In/Out 15 (MicroLabBox II) 111

482
FPGA Programming Handcode Framework - FPGA Interface Reference May 2024
Index

diotp1_<ChannelNumber>_dir Analog In 25 (MicroLabBox II) 90 DDR4 32 Mode 1 210

Digital InOut Class 1 (DS1302) 58 ds1303_ai25_<ChannelNumber>_trigger / DDR4 32 Mode 2 212
Digital InOut Class 2 (DS1302) 60 Trigger DDR4 64 Mode 1 215
diotp1_<ChannelNumber>_ena Analog In 25 (MicroLabBox II) 90 DDR4 64 Mode 2 217
Digital InOut Class 1 (DS1302) 58 ds1303_dio14_<ChannelNumber>_data / Data Digital In/Out-Z (DS6651) 283
Digital InOut Class 2 (DS1302) 60 Analog Out 19 (MicroLabBox II) 91 Digital InOut Class 1 (DS1302) 58
diotp1_<ChannelNumber>_in Analog Out 20 (MicroLabBox II) 92 Digital InOut Class 2 (DS1302) 60
Digital InOut Class 1 (DS1302) 58 ds1303_dio14_<ChannelNumber>_dir / Digital Out (Type A) (FPGA1403TP1)
Digital InOut Class 2 (DS1302) 61 Direction DS1552 417
diotp1_<ChannelNumber>_out Digital In/Out 14 (In/Out-Z) DS1554 457
Digital InOut Class 1 (DS1302) 59 (MicroLabBox II) 107, 110 Digital Out (Type B) (FPGA1403TP1)
Digital InOut Class 2 (DS1302) 61 ds1303_dio14_<ChannelNumber>_lvl_in / DigIn DS1552 419
Direction Digital In/Out 14 (In/Out-Z) Digital Out (Type B)(FPGA1403TP1)
DDR4 32 Mode 1 210 (MicroLabBox II) 107, 109 DS1554 460
DDR4 32 Mode 2 212 ds1303_dio14_<ChannelNumber>_lvl_out / Digital Out Type A (FPGA1401TP1)
DDR4 64 Mode 1 215 DigOut DS1552 342
DDR4 64 Mode 2 217 Digital In/Out 14 (In/Out-Z) DS1554 382
Digital In/Out 14 (In/Out-Z) (MicroLabBox II) 109 Digital Out Type B (FPGA1401TP1)
(MicroLabBox II) 107, 110 ds1303_dio14_<ChannelNumber>_trigger / DS1552 344
Digital In/Out 15 (MicroLabBox II) 112 Ready DS1554 384
Digital InOut Class 1 (DS1302) 58 Analog Out 19 (MicroLabBox II) 91 Digital Out-Z (DS2655M2) 256
Digital InOut Class 2 (DS1302) 60 Analog Out 20 (MicroLabBox II) 93 Digital Out-Z (DS6651) 288
Disable filter ds1303_dio14_<ChannelNumber>_trigger / I-FPGA Out (IOCNET) (DS2655) 145
Digital In/Out 14 (In) (MicroLabBox II) 106 Trigger I-FPGA Out (IOCNET) (DS6601) 179
Digital In/Out 14 (In/Out-Z) Analog Out 19 (MicroLabBox II) 91 I-FPGA Out (IOCNET) (DS6602) 223
(MicroLabBox II) 109 Analog Out 20 (MicroLabBox II) 92 I-FPGA64 Out (IOCNET) (DS2655) 147
Digital In/Out 15 (MicroLabBox II) 111 ds1303_dio15_<ChannelNumber>_dir / I-FPGA64 Out (IOCNET) (DS6601) 181
Documents folder 12 Direction I-FPGA64 Out (IOCNET) (DS6602) 225
Drive config Digital In/Out 15 (MicroLabBox II) 112 Resolver (DS1302) 72
Digital InOut (DS2655M1) 244 ds1303_dio15_<ChannelNumber>_lvl_in / DigIn RS485 Tx (DS2655M2) 266
Digital Out (DS2655M1) 246 Digital In/Out 15 (MicroLabBox II) 111 RS485 Tx (DS6651) 295
Digital Out (DS2655M2) 253 ds1303_dio15_<ChannelNumber>_lvl_out / Trigger (DS6651) 296
Digital Out-Z (DS2655M2) 256 DigOut Enable explicit data transmission
Drive Config Digital In/Out 15 (MicroLabBox II) 111 Buffer Out (DS2655) 136
Digital In/Out 14 (In/Out-Z) Buffer Out (DS6601) 170
(MicroLabBox II) 109 E Buffer Out (DS6602) 204
Digital In/Out-Z (DS6651) 281 Buffer64 Out (DS2655) 138
Enable
Digital Out (DS6651) 285 Buffer64 Out (DS6601) 172
Analog In (DS2655M1) 239
Digital Out-Z (DS6651) 287 Buffer64 Out (DS6602) 207
Analog Out (DS2655M1) 241
Driver Enable End of conversion
Aurora 64b66b 128 Bit Out 306
UART 3 RS422/485 (FPGA1403TP1) 440 ADC (Type A) (FPGA1403TP1)
Aurora 64b66b Out 302
UART RS422/485 (DS1302) 82 DS1552 401
Buffer Out (DS1302) 52
UART RS422/485 (FPGA1401TP1) 365 DS1554 445
Buffer Out (DS2655) 136
ds1303_ai23_<ChannelNumber>_data / Data ADC Type A (FPGA1401TP1)
Buffer Out (DS6601) 170
Analog In 23 (MicroLabBox II) 87 DS1552 325
Buffer Out (DS6602) 205
ds1303_ai23_<ChannelNumber>_event / Data DS1554 369
Buffer Out (FPGA1401TP1)
New Knock Sensor (FPGA1401TP1) 387
DS1552 332
Analog In 23 (MicroLabBox II) 87 Knock Sensor (FPGA1403TP1) 463
DS1554 375
ds1303_ai23_<ChannelNumber>_trigger / Endbit
Buffer Out (FPGA1403TP1)
Trigger I-FPGA In (SCALEXIO) 315
DS1552 408
Analog In 23 (MicroLabBox II) 87 I-FPGA Out (SCALEXIO) 320
DS1554 451
ds1303_ai24_<ChannelNumber>_data / Data Errors
Buffer Out (MicroLabBox II) 100
Analog In 24 (MicroLabBox II) 88 I-FPGA In (SCALEXIO) 317
Buffer64 Out (DS1302) 53
ds1303_ai24_<ChannelNumber>_event / Data Errors reset
Buffer64 Out (DS2655) 139
New I-FPGA In (SCALEXIO) 318
Buffer64 Out (DS6601) 173
Analog In 24 (MicroLabBox II) 88 Excitation RMS voltage
Buffer64 Out (DS6602) 207
ds1303_ai24_<ChannelNumber>_trigger / Resolver (DS1302) 71
Buffer64 Out (FPGA1401TP1)
Trigger
DS1552 334
Analog In 24 (MicroLabBox II) 88 F
DS1554 377
ds1303_ai25_<ChannelNumber>_data / Data
Buffer64 Out (FPGA1403TP1) Fault
Analog In 25 (MicroLabBox II) 90
DS1552 410 Resolver (DS1302) 72
ds1303_ai25_<ChannelNumber>_event / Data
DS1554 453 Filter depth
New
Buffer64 Out (MicroLabBox II) 104 I-FPGA In (SCALEXIO) 316

483
May 2024 FPGA Programming Handcode Framework - FPGA Interface Reference
Index

Format Register Out (FPGA1403TP1) APU Slave (MicroLabBox II) 96

Buffer In (DS1302) 48 DS1552 427 Aurora 64b66b 128 Bit In 304
Buffer In (DS2655) 131 DS1554 469 Aurora 64b66b 128 Bit Out 306
Buffer In (DS6601) 165 Register Out (MicroLabBox II) 117 Aurora 64b66b In 300
Buffer In (DS6602) 200 Register64 In (DS1302) 67 Aurora 64b66b Out 302
Buffer In (FPGA1401TP1) Register64 In (DS2655) 153 Buffer In (DS1302) 47
DS1552 328 Register64 In (DS6601) 187 Buffer In (DS2655) 131
DS1554 371 Register64 In (DS6602) 231 Buffer In (DS6601) 165
Buffer In (FPGA1403TP1) Register64 In (FPGA1401TP1) Buffer In (DS6602) 199
DS1552 404 DS1552 350 Buffer In (FPGA1401TP1)
DS1554 447 DS1554 392 DS1552 328
Buffer In (MicroLabBox II) 98 Register64 In (FPGA1403TP1) DS1554 371
Buffer Out (DS1302) 51 DS1552 425 Buffer In (FPGA1403TP1)
Buffer Out (DS2655) 136 DS1554 467 DS1552 404
Buffer Out (DS6601) 170 Register64 In (MicroLabBox II) 119 DS1554 446
Buffer Out (DS6602) 204 Register64 Out (DS1302) 70 Buffer In (MicroLabBox II) 97
Buffer Out (FPGA1401TP1) Register64 Out (DS2655) 156 Buffer Out (DS1302) 51
DS1552 332 Register64 Out (DS6601) 190 Buffer Out (DS2655) 135
DS1554 374 Register64 Out (DS6602) 234 Buffer Out (DS6601) 169
Buffer Out (FPGA1403TP1) Register64 Out (FPGA1401TP1) Buffer Out (DS6602) 204
DS1552 407 DS1552 353 Buffer Out (FPGA1401TP1)
DS1554 450 DS1554 395 DS1552 331
Buffer Out (MicroLabBox II) 100 Register64 Out (FPGA1403TP1) DS1554 374
Buffer64 In (DS1302) 49 DS1552 428 Buffer Out (FPGA1403TP1)
Buffer64 In (DS2655) 133 DS1554 470 DS1552 407
Buffer64 In (DS6601) 167 Register64 Out (MicroLabBox II) 121 DS1554 450
Buffer64 In (DS6602) 202 Frequency Buffer Out (MicroLabBox II) 99
Buffer64 In (FPGA1401TP1) Buzzer (DS1302) 55 Buffer64 In (DS1302) 49
DS1552 330 Buffer64 In (DS2655) 133
DS1554 373 G Buffer64 In (DS6601) 167
Buffer64 In (FPGA1403TP1) Buffer64 In (DS6602) 201
Green
DS1552 406 Buffer64 In (FPGA1401TP1)
LED Out (DS1302) 63
DS1554 449 DS1552 330
Buffer64 In (MicroLabBox II) 102 DS1554 372
Buffer64 Out (DS1302) 53 H Buffer64 In (FPGA1403TP1)
Buffer64 Out (DS2655) 138 HcCustomName DS1552 405
Buffer64 Out (DS6601) 172 ADC (Type A) (FPGA1403TP1) DS1554 448
Buffer64 Out (DS6602) 207 DS1552 401 Buffer64 In (MicroLabBox II) 101
Buffer64 Out (FPGA1401TP1) DS1554 445 Buffer64 Out (DS1302) 52
DS1552 334 ADC (Type B) (FPGA1403TP1) 402 Buffer64 Out (DS2655) 138
DS1554 376 ADC Class 1 (DS1302) 45 Buffer64 Out (DS6601) 172
Buffer64 Out (FPGA1403TP1) ADC Class 2 (DS1302) 46 Buffer64 Out (DS6602) 206
DS1552 409 ADC Type A (FPGA1401TP1) Buffer64 Out (FPGA1401TP1)
DS1554 452 DS1552 325 DS1552 333
Buffer64 Out (MicroLabBox II) 104 DS1554 369 DS1554 376
Register In (DS1302) 65 ADC Type B (FPGA1401TP1) 327 Buffer64 Out (FPGA1403TP1)
Register In (DS2655) 151 Analog In (DS2655M1) 238 DS1552 409
Register In (DS6601) 185 Analog In (DS6651) 271 DS1554 452
Register In (DS6602) 229 Analog In 23 (MicroLabBox II) 87 Buffer64 Out (MicroLabBox II) 103
Register In (FPGA1401TP1) Analog In 24 (MicroLabBox II) 88 Buzzer (DS1302) 54
DS1552 348 Analog In 25 (MicroLabBox II) 89 CN App Status (DS2655) 140
DS1554 390 Analog In-L (DS6651) 274 CN App Status (DS6601) 174
Register In (FPGA1403TP1) Analog Out (DS2655M1) 240 CN App Status (DS6602) 209
DS1552 423 Analog Out (DS6651) 277 CN App Status (MicroLabBox II) 105
DS1554 465 Analog Out 19 (MicroLabBox II) 91 DAC (FPGA1401TP1) 335
Register In (MicroLabBox II) 116 Analog Out 20 (MicroLabBox II) 92 DAC (FPGA1403TP1) 410
Register Out (DS1302) 68 Analog Out-T (DS6651) 278 DAC Class 1 (DS1302) 56
Register Out (DS2655) 154 APU Master (DS2655) 127 DDR4 32 Mode 1 210
Register Out (DS6601) 188 APU Master (DS6601) 161 DDR4 32 Mode 2 212
Register Out (DS6602) 232 APU Master (DS6602) 195 DDR4 64 Mode 1 214
Register Out (FPGA1401TP1) APU Master (MicroLabBox II) 93 DDR4 64 Mode 2 216
DS1552 351 APU Slave (DS2655) 129 Digital Crank/Cam Sensor (FPGA1401TP1)
DS1554 393 APU Slave (DS6601) 163, 197 DS1552 336

484
FPGA Programming Handcode Framework - FPGA Interface Reference May 2024
Index

DS1554 378 Interrupt (DS2655) 148 Register64 In (MicroLabBox II) 119

Digital Crank/Cam Sensor (FPGA1403TP1) Interrupt (DS6601) 182 Register64 Out (DS1302) 69
DS1552 412 Interrupt (DS6602) 226 Register64 Out (DS2655) 155
DS1554 453 Interrupt (FPGA1401TP1) Register64 Out (DS6601) 189
Digital In (DS2655M1) 242 DS1552 346 Register64 Out (DS6602) 233
Digital In (DS2655M2) 251 DS1554 386 Register64 Out (FPGA1401TP1)
Digital In (DS6651) 279 Interrupt (FPGA1403TP1) DS1552 353
Digital In (Type A) (FPGA1403TP1) 413 DS1552 421 DS1554 394
Digital In (Type B) (FPGA1403TP1) DS1554 462 Register64 Out (FPGA1403TP1)
DS1552 415 Interrupt (MicroLabBox II) 113 DS1552 428
DS1554 455 IOCNET Global Time (DS2655) 149 DS1554 470
Digital In Type A (FPGA1401TP1) 338 IOCNET Global Time (DS6601) 183 Register64 Out (MicroLabBox II) 120
Digital In Type B (FPGA1401TP1) IOCNET Global Time (DS6602) 227 Resolver (DS1302) 71
DS1552 340 IOCNET Global Time (MicroLabBox II) 114 RS232 Rx (DS2655M2) 258
DS1554 379 Knock Sensor (FPGA1401TP1) 387 RS232 Tx (DS2655M2) 260
Digital In/Out 14 (In) (MicroLabBox II) 106 Knock Sensor (FPGA1403TP1) 462 RS485 Rx (DS2655M2) 261, 263
Digital In/Out 14 (In/Out-Z) LED Out (DS1302) 63 RS485 Rx (DS6651) 290
(MicroLabBox II) 108 LED Out (DS2655) 150 RS485 Rx/Tx (DS6651) 291
Digital In/Out 15 (MicroLabBox II) 111 LED Out (DS6601) 184 RS485 Tx (DS2655M2) 265
Digital In/Out-Z (DS6651) 281 LED Out (DS6602) 228 RS485 Tx (DS6651) 294
Digital InOut (DS2655M1) 244 LED Out (FPGA1401TP1) Sensor Supply (FPGA1401TP1)
Digital InOut Class 1 (DS1302) 57 DS1552 347 DS1552 354
Digital InOut Class 2 (DS1302) 60 DS1554 388 Sensor Supply (FPGA1403TP1)
Digital Out (DS2655M1) 246 LED Out (FPGA1403TP1) DS1552 429
Digital Out (DS2655M2) 253 DS1552 422 Status In (DS1302) 74
Digital Out (DS6651) 285 DS1554 464 Status In (DS2655) 157
Digital Out (Type A) (FPGA1403TP1) LED Out (MicroLabBox II) 114 Status In (DS6601) 191
DS1552 417 MGT In 307 Status In (DS6602) 235
DS1554 457 MGT In Opto Ready 309 Status In (FPGA1401TP1)
Digital Out (Type B) (FPGA1403TP1) MGT Out 310 DS1552 355
DS1552 418 Proc App Status (DS1302) 64 DS1554 396
DS1554 459 Register In (DS1302) 64 Status In (FPGA1403TP1)
Digital Out Type A (FPGA1401TP1) Register In (DS2655) 150 DS1552 430
DS1552 342 Register In (DS6601) 184 DS1554 471
DS1554 381 Register In (DS6602) 228 Status In (MicroLabBox II) 122
Digital Out Type B (FPGA1401TP1) Register In (FPGA1401TP1) Temperature (FPGA1401TP1) 397
DS1552 343 DS1552 348 Temperature (FPGA1403TP1) 472
DS1554 383 DS1554 389 Trigger (DS6651) 296
Digital Out-Z (DS2655M2) 256 Register In (FPGA1403TP1) UART 3 RS232 (FPGA1403TP1) 432
Digital Out-Z (DS6651) 287 DS1552 423 UART 3 RS422/485 (FPGA1403TP1) 436
I-FPGA In (IOCNET) (DS2655) 141 DS1554 465 UART RS232 (DS1302) 75
I-FPGA In (IOCNET) (DS6601) 175 Register In (MicroLabBox II) 115 UART RS232 (FPGA1401TP1) 357
I-FPGA In (IOCNET) (DS6602) 219 Register Out (DS1302) 68 UART RS422/485 (DS1302) 79
I-FPGA In (SCALEXIO) 314 Register Out (DS2655) 154 UART RS422/485 (FPGA1401TP1) 361
I-FPGA Out (IOCNET) (DS2655) 144 Register Out (DS6601) 188 Watchdog (DS6601) 192
I-FPGA Out (IOCNET) (DS6601) 178 Register Out (DS6602) 232 Watchdog (DS6602) 236
I-FPGA Out (IOCNET) (DS6602) 222 Register Out (FPGA1401TP1) High
I-FPGA Out (SCALEXIO) 319 DS1552 351 FPGA1401TP1 port 397
I-FPGA64 In (IOCNET) (DS2655) 142 DS1554 393 DS1552 356
I-FPGA64 In (IOCNET) (DS6601) 176 Register Out (FPGA1403TP1) FPGA1403TP1 port 472
I-FPGA64 In (IOCNET) (DS6602) 220 DS1552 426 DS1552 431
I-FPGA64 Out (IOCNET) (DS2655) 146 DS1554 468 High supply
I-FPGA64 Out (IOCNET) (DS6601) 180 Register Out (MicroLabBox II) 117 Digital In/Out 14 (In/Out-Z)
I-FPGA64 Out (IOCNET) (DS6602) 224 Register64 In (DS1302) 66 (MicroLabBox II) 109
Inductive Zero Voltage Detector Register64 In (DS2655) 152 Digital InOut (DS2655M1) 244
(FPGA1401TP1) Register64 In (DS6601) 186 Digital InOut Class 1 (DS1302) 58
DS1552 345 Register64 In (DS6602) 230 Digital Out (DS2655M1) 247
DS1554 385 Register64 In (FPGA1401TP1) Digital Out (DS2655M2) 253
Inductive Zero Voltage Detector DS1552 349 Digital Out (Type B) (FPGA1403TP1)
(FPGA1403TP1) DS1554 391 DS1552 419
DS1552 420 Register64 In (FPGA1403TP1) DS1554 459
DS1554 461 DS1552 424 Digital Out Type B (FPGA1401TP1)
Interrupt (DS1302) 62 DS1554 466 DS1552 343

485
May 2024 FPGA Programming Handcode Framework - FPGA Interface Reference
Index

DS1554 384 port 219 DS1552 345

Digital Out-Z (DS2655M2) 256 I-FPGA In (SCALEXIO) 314 DS1554 385
RS485 Rx/Tx (DS6651) 291 parameters 314 Inductive Zero Voltage Detector (FPGA1403TP1)
RS485 Tx (DS6651) 294 port 317 DS1552 420
High Supply I-FPGA Out (IOCNET) (DS2655) 144 DS1554 460
Digital In/Out-Z (DS6651) 282 Buffer size 144 I/O mapping
Digital Out (DS6651) 285 I/O mapping 146 DS1552 420
Digital Out-Z (DS6651) 287 parameters 144 DS1554 461
High threshold voltage port 144 parameters
Digital Crank/Cam Sensor (FPGA1401TP1) I-FPGA Out (IOCNET) (DS6601) 178 DS1552 420
DS1552 337 Buffer size 178 DS1554 461
DS1554 378 I/O mapping 180 port
Digital Crank/Cam Sensor (FPGA1403TP1) parameters 178 DS1552 420
DS1552 412 port 178 DS1554 461
DS1554 454 I-FPGA Out (IOCNET) (DS6602) 222 Init Done
high_temp Buffer size 222 DDR4 32 Mode 1 210
FPGA1401TP1 port 397 I/O mapping 224 DDR4 32 Mode 2 212
DS1552 356 parameters 222 DDR4 64 Mode 1 214
FPGA1403TP1 port 472 port 222 DDR4 64 Mode 2 216
DS1552 431 I-FPGA Out (SCALEXIO) 318 FPGA1401TP1 port
hq_adc_<ChannelNumber>_data I/O mapping 318, 321 DS1552 355
ADC (Type A) (FPGA1403TP1) parameters 319 DS1554 396
DS1552 401 port 321 FPGA1403TP1 port
DS1554 445 I-FPGA64 In (IOCNET) (DS2655) 142 DS1552 430
ADC Type A (FPGA1401TP1) Buffer size 143 DS1554 472
DS1552 325 I/O mapping 144 Status In (DS1302) 74
DS1554 369 parameters 142 Status In (DS2655) 157
Knock Sensor (FPGA1401TP1) 387 port 143 Status In (DS6601) 191
Knock Sensor (FPGA1403TP1) 463 I-FPGA64 In (IOCNET) (DS6601) 176 Status In (DS6602) 235
hq_adc_<ChannelNumber>_eoc Buffer size 177 Status In (MicroLabBox II) 122
ADC (Type A) (FPGA1403TP1) I/O mapping 178 Init Failed
DS1552 401 parameters 176 DDR4 32 Mode 1 210
DS1554 445 port 177 DDR4 32 Mode 2 212
ADC Type A (FPGA1401TP1) I-FPGA64 In (IOCNET) (DS6602) 220 DDR4 64 Mode 1 215
DS1552 325 Buffer size 221 DDR4 64 Mode 2 217
DS1554 369 I/O mapping 222 init_done
Knock Sensor (FPGA1401TP1) 387 parameters 220 FPGA1401TP1 port
Knock Sensor (FPGA1403TP1) 463 port 221 DS1552 355
hq_adc_<ChannelNumber>_soc I-FPGA64 Out (IOCNET) (DS2655) 146 DS1554 396
ADC (Type A) (FPGA1403TP1) Buffer size 146 FPGA1403TP1 port
DS1552 401 I/O mapping 148 DS1552 430
DS1554 445 parameters 146 DS1554 472
ADC Type A (FPGA1401TP1) port 146 Status In (DS1302) 74
DS1552 325 I-FPGA64 Out (IOCNET) (DS6601) 180 Status In (DS2655) 157
DS1554 369 Buffer size 180 Status In (DS6601) 191
Knock Sensor (FPGA1401TP1) 387 I/O mapping 182 Status In (DS6602) 235
Knock Sensor (FPGA1403TP1) 463 parameters 180 Status In (MicroLabBox II) 122
port 180 Input filter
I I-FPGA64 Out (IOCNET) (DS6602) 224 Digital In/Out 14 (In) (MicroLabBox II) 106
Buffer size 224 Digital In/Out 14 (In/Out-Z)
I-FPGA In (IOCNET) (DS2655) 141
I/O mapping 226 (MicroLabBox II) 109
Buffer size 141
parameters 224 Digital In/Out 15 (MicroLabBox II) 111
I/O mapping 142
port 224 Digital InOut Class 1 (DS1302) 58
parameters 141
Inductive Zero Voltage Detector (FPGA1401TP1) Digital InOut Class 2 (DS1302) 60
port 141
DS1552 345 Input range
I-FPGA In (IOCNET) (DS6601) 175
DS1554 385 Analog In (DS2655M1) 238
Buffer size 175
I/O mapping Analog In (DS6651) 271
I/O mapping 176
DS1552 345 Analog In 24 (MicroLabBox II) 88
parameters 175
DS1554 386 Analog In 25 (MicroLabBox II) 89
port 175
parameters Analog In-L (DS6651) 274
I-FPGA In (IOCNET) (DS6602) 218
DS1552 345 Input RMS voltage
Buffer size 219
DS1554 385 Resolver (DS1302) 71
I/O mapping 220
port Int
parameters 219

486
FPGA Programming Handcode Framework - FPGA Interface Reference May 2024
Index

Interrupt (DS1302) 62 Interrupt (FPGA1403TP1) APU Slave (MicroLabBox II) 97

Interrupt (DS2655) 148 DS1552 421 iocnet_glob_angle<ChannelNumber>_pos
Interrupt (DS6601) 182 DS1554 461 APU Slave (DS2655) 130
Interrupt (DS6602) 226 parameters APU Slave (DS6601) 164, 198
Interrupt (FPGA1401TP1) DS1552 421 APU Slave (MicroLabBox II) 96
DS1552 346 DS1554 462 iocnet_glob_angle<ChannelNumber>_res
DS1554 386 port APU Slave (DS2655) 130
Interrupt (FPGA1403TP1) DS1552 421 APU Slave (DS6601) 164, 199
DS1552 421 DS1554 462 APU Slave (MicroLabBox II) 97
DS1554 462 Interrupt (MicroLabBox II) 113 iocnet_glob_angle<ChannelNumber>_rev
Interrupt (MicroLabBox II) 113 parameters 113 APU Slave (DS2655) 130
intercom_<ChannelNumber>_data_in port 113 APU Slave (DS6601) 164, 198
I-FPGA In (SCALEXIO) 317 Invert values APU Slave (MicroLabBox II) 96
intercom_<ChannelNumber>_data_new Digital In/Out 14 (In) (MicroLabBox II) 106 iocnet_glob_angle<ChannelNumber>_vel
I-FPGA In (SCALEXIO) 317 Digital In/Out 14 (In/Out-Z) APU Slave (DS2655) 130
intercom_<ChannelNumber>_data_out (MicroLabBox II) 108 APU Slave (DS6601) 164, 199
I-FPGA Master (SCALEXIO) 321 Digital In/Out 15 (MicroLabBox II) 111 APU Slave (MicroLabBox II) 97
intercom_<ChannelNumber>_data_sent_v Digital InOut Class 1 (DS1302) 57 iocnet_glob_master_angle<ChannelNumber>_bu
I-FPGA Master (SCALEXIO) 321 Digital InOut Class 2 (DS1302) 60 sy
intercom_<ChannelNumber>_errors IOCNET access (DS2655) APU Master (DS2655) 128
I-FPGA In (SCALEXIO) 317 buffer (32-bit) 131, 135 APU Master (DS6601) 162
intercom_<ChannelNumber>_ready buffer (64-bit) 133, 137 APU Master (DS6602) 196
I-FPGA Master (SCALEXIO) 321 register (32-bit) 150, 154 APU Master (MicroLabBox II) 94
intercom_<ChannelNumber>_reset_error register (64-bit) 152, 155 iocnet_glob_master_angle<ChannelNumber>_ctr
I-FPGA In (SCALEXIO) 318 IOCNET access (DS6601) APU Master (DS2655) 127
Intermodule bus access buffer (32-bit) 165, 169 APU Master (DS6601) 161
buffer buffer (64-bit) 167, 171 APU Master (DS6602) 196
DS1552 328, 331, 403, 407 register (32-bit) 184, 188 APU Master (MicroLabBox II) 94
DS1554 370, 374, 446, 450 register (64-bit) 186, 189 iocnet_glob_master_angle<ChannelNumber>_en
buffer64 IOCNET access (DS6602) APU Master (DS2655) 128
DS1552 329, 333, 405, 408 buffer (32-bit) 199, 203 APU Master (DS6601) 162
DS1554 372, 376, 448, 451 buffer (64-bit) 201, 206 APU Master (DS6602) 196
register register (32-bit) 228, 232 APU Master (MicroLabBox II) 94
DS1552 347, 349, 351, 352, 423, 424, register (64-bit) 230, 233 iocnet_glob_master_angle<ChannelNumber>_po
426, 427 IOCNET access (MicroLabBox II) s
DS1554 389, 391, 393, 394, 465, 466, buffer (32-bit) 97, 99 APU Master (DS2655) 127
468, 469 buffer (64-bit) 101, 103 APU Master (DS6601) 161
Internal bus access (DS1302) register (32-bit) 115, 117 APU Master (DS6602) 196
buffer (32-bit) 47, 50 register (64-bit) 118, 120 APU Master (MicroLabBox II) 94
buffer (64-bit) 49, 52 IOCNET Global Time (DS2655) 149 iocnet_glob_master_angle<ChannelNumber>_re
register (32-bit) 64, 68 parameters 149 s
register (64-bit) 66, 69 port 149 APU Master (DS2655) 128
Interrupt (DS1302) 62 IOCNET Global Time (DS6601) 183 APU Master (DS6601) 162
parameters 62 parameters 183 APU Master (DS6602) 196
port 62 port 183 APU Master (MicroLabBox II) 94
Interrupt (DS2655) 148 IOCNET Global Time (DS6602) 227 iocnet_glob_master_angle<ChannelNumber>_re
parameters 148 parameters 227 v
port 148 port 227 APU Master (DS2655) 128
Interrupt (DS6601) 182 IOCNET Global Time (MicroLabBox II) 113 APU Master (DS6601) 162
parameters 182 parameters 114 APU Master (DS6602) 196
port 182 port 114 APU Master (MicroLabBox II) 94
Interrupt (DS6602) 226 iocnet_appl_status iocnet_glob_master_angle<ChannelNumber>_up
parameters 226 CN App Status (DS2655) 140, 149 d_trig
port 226 CN App Status (DS6601) 174, 183 APU Master (DS2655) 128
Interrupt (FPGA1401TP1) CN App Status (DS6602) 209, 227 APU Master (DS6601) 162
DS1552 346 CN App Status (MicroLabBox II) 105, 114 APU Master (DS6602) 197
DS1554 386 iocnet_glob_angle<ChannelNumber>_ctr APU Master (MicroLabBox II) 95
parameters APU Slave (DS2655) 130 iocnet_glob_master_angle<ChannelNumber>_up
DS1552 346 APU Slave (DS6601) 164, 199 d_vel_deg_sec
DS1554 386 APU Slave (MicroLabBox II) 97 APU Master (DS2655) 128
port iocnet_glob_angle<ChannelNumber>_en APU Master (DS6601) 162
DS1552 346 APU Slave (DS2655) 130 APU Master (DS6602) 197
DS1554 386 APU Slave (DS6601) 164, 199 APU Master (MicroLabBox II) 95

487
May 2024 FPGA Programming Handcode Framework - FPGA Interface Reference
Index

iocnet_glob_master_angle<ChannelNumber>_ve LED Out (DS1302) 63 m<ModuleNumber>_rx<ChannelNumber>_trigg

l led_out er00 / Data In
APU Master (DS2655) 128 LED Out (DS2655) 150 Digital In/Out-Z (DS6651) 282
APU Master (DS6601) 162 LED Out (DS6601) 184 m<ModuleNumber>_rx<ChannelNumber>_trigg
APU Master (DS6602) 196 LED Out (DS6602) 228 er00 / Rx Data
APU Master (MicroLabBox II) 94 LED Out (FPGA1401TP1) RS485 Rx/Tx (DS6651) 292
DS1552 347 m<ModuleNumber>_tx<ChannelNumber>__dat
K DS1554 389 a00
LED Out (FPGA1403TP1) Analog In (DS2655M1) 239
Knock Sensor (FPGA1401TP1) 387
DS1552 422 m<ModuleNumber>_tx<ChannelNumber>_data
I/O mapping 388
DS1554 464 00_14_0_14_0
parameters 387
LED Out (MicroLabBox II) 115 Analog Out (DS2655M1) 241
port 387
Load Config m<ModuleNumber>_tx<ChannelNumber>_data
Knock Sensor (FPGA1403TP1)
Analog In-L (DS6651) 274 00_16_0_16_0i
DS1554 462
Local Program Data folder 12 Analog Out (DS2655M1) 241
I/O mapping 463
Low threshold voltage m<ModuleNumber>_tx<ChannelNumber>_data
parameters 462
Digital Crank/Cam Sensor (FPGA1401TP1)00_17_0_17_0i
port 463
DS1552 336 Analog Out (DS6651) 277
DS1554 378 Analog Out-T (DS6651) 278
L Digital Crank/Cam Sensor (FPGA1403TP1)m<ModuleNumber>_tx<ChannelNumber>_data
LED Out DS1552 412 01_0_0_0_0i
LED Out (DS2655) 150 DS1554 454 Digital InOut (DS2655M1) 245
LED Out (DS6601) 184 lq_adc_<ChannelNumber>_data m<ModuleNumber>_tx<ChannelNumber>_data
LED Out (DS6602) 228 ADC (Type B) (FPGA1403TP1) 403 01_0_0_1_1i
LED Out (MicroLabBox II) 115 ADC Type B (FPGA1401TP1) 327 Digital InOut (DS2655M1) 245
LED Out (DS1302) 62 m<ModuleNumber>_tx<ChannelNumber>_trigg
parameters 63 M er00
port 63 Digital Out (DS2655M1) 247
m<ModuleNumber>_io2raw_n_n_n_ni
LED Out (DS2655) 149 m<ModuleNumber>_tx<ChannelNumber>_trigg
Digital In (DS2655M2) 251
parameters 150 er00 / Data
RS232 Rx (DS2655M2) 259
port 150 Digital Out (DS6651) 285
RS485 Rx (DS2655M2) 262
LED Out (DS6601) 183 Digital Out-Z (DS6651) 288
RS485 RxTx (DS2655M2) 264
parameters 184 RS485 Tx (DS6651) 294
m<ModuleNumber>_raw2io_n_n_n_ni
port 184 m<ModuleNumber>_tx<ChannelNumber>_trigg
Digital Out (DS2655M2) 254
LED Out (DS6602) 227 er00 / Data Out
Digital Out-Z (DS2655M2) 256
parameters 228 Digital In/Out-Z (DS6651) 282
RS232 Tx (DS2655M2) 260
port 228 m<ModuleNumber>_tx<ChannelNumber>_trigg
RS485 Tx (DS2655M2) 266
LED Out (FPGA1401TP1) er00 / Enable
m<ModuleNumber>_raw2io_n+1_n+1_n+1_n+1
DS1552 347 Digital In/Out-Z (DS6651) 283
i
DS1554 388 Digital Out-Z (DS6651) 288
Digital Out-Z (DS2655M2) 256
parameters RS485 Tx (DS6651) 295
RS485 RxTx (DS2655M2) 263
DS1552 347 Trigger (DS6651) 296
RS485 Tx (DS2655M2) 266
DS1554 388 m<ModuleNumber>_tx<ChannelNumber>_trigg
m<ModuleNumber>_raw2io_n+2_n+2_n+2_n+2
port er00 / Tx Data
i
DS1552 347 RS485 Rx/Tx (DS6651) 292
RS485 Tx (DS2655M2) 263
DS1554 389 m<ModuleNumber>_tx<ChannelNumber>_trigg
m<ModuleNumber>_rx<ChannelNumber>_data
LED Out (FPGA1403TP1) er00 / Tx Enable
00
DS1552 422 RS485 Rx/Tx (DS6651) 292
Analog In (DS2655M1) 239
DS1554 464 Maximum speed
Analog In (DS6651) 272
parameters Resolver (DS1302) 72
Analog In-L (DS6651) 275
DS1552 422 Mechanical Position
m<ModuleNumber>_rx<ChannelNumber>_ready
DS1554 464 Resolver (DS1302) 72
_pulse
port MGT In
Analog In (DS2655M1) 239
DS1552 422 DS6601 307
Analog In (DS6651) 272
DS1554 464 DS6602 307
Analog In-L (DS6651) 275
LED Out (MicroLabBox II) 114 I/O mapping 308
m<ModuleNumber>_rx<ChannelNumber>_trigg
parameters 114 parameters 307
er00
port 114 port 308
Digital In (DS2655M1) 242
led_<ChannelNumber>_blue MGT In Opto Ready
Digital InOut (DS2655M1) 245
LED Out (DS1302) 63 DS6601 309
m<ModuleNumber>_rx<ChannelNumber>_trigg
led_<ChannelNumber>_green DS6602 309
er00 / Data
LED Out (DS1302) 63 I/O mapping 309
Digital In (DS6651) 280
led_<ChannelNumber>_red parameters 309
RS485 Rx (DS6651) 290

488
FPGA Programming Handcode Framework - FPGA Interface Reference May 2024
Index

port 309 Digital In/Out-Z (DS6651) 281 Processor Application Status

MGT Out Digital Out (DS6651) 285 Proc App Status (DS1302) 64
DS6601 310 Digital Out-Z (DS6651) 287
DS6602 310 Overflow R
I/O mapping 311 Buffer Out (DS1302) 52
Read Data
parameters 310 Buffer Out (DS2655) 137
UART 3 RS232 (FPGA1403TP1) 434
port 310 Buffer Out (DS6601) 171
UART 3 RS422/485 (FPGA1403TP1) 439
MGT reference clock frequency Buffer Out (DS6602) 205
UART RS232 (DS1302) 77
MGT In 307 Buffer Out (FPGA1401TP1)
UART RS232 (FPGA1401TP1) 359
MGT_CLK_N DS1552 333
UART RS422/485 (DS1302) 81
MGT In 308 DS1554 375
UART RS422/485 (FPGA1401TP1) 364
MGT_CLK_P Buffer Out (FPGA1403TP1)
Read Data Count
MGT In 308 DS1552 408
UART 3 RS232 (FPGA1403TP1) 433
mgt_lane<LaneNumber>_rx_data DS1554 451
UART 3 RS422/485 (FPGA1403TP1) 438
Aurora 64b66b 128 Bit In 304 Buffer Out (MicroLabBox II) 101
UART RS232 (DS1302) 77
Aurora 64b66b In 300 Buffer64 Out (DS1302) 54
UART RS232 (FPGA1401TP1) 358
mgt_lane<LaneNumber>_rx_ready Buffer64 Out (DS2655) 139
UART RS422/485 (DS1302) 81
Aurora 64b66b 128 Bit In 304 Buffer64 Out (DS6601) 173
UART RS422/485 (FPGA1401TP1) 363
Aurora 64b66b In 301 Buffer64 Out (DS6602) 208
Read Enable
mgt_lane<LaneNumber>_rx_valid Buffer64 Out (FPGA1401TP1)
UART 3 RS232 (FPGA1403TP1) 433
Aurora 64b66b 128 Bit In 304 DS1552 335
UART 3 RS422/485 (FPGA1403TP1) 438
Aurora 64b66b In 301 DS1554 377
UART RS232 (DS1302) 76
mgt_lane<LaneNumber>_tx_data Buffer64 Out (FPGA1403TP1)
UART RS232 (FPGA1401TP1) 358
Aurora 64b66b 128 Bit Out 306 DS1552 410
UART RS422/485 (DS1302) 81
Aurora 64b66b Out 303 DS1554 453
UART RS422/485 (FPGA1401TP1) 363
mgt_lane<LaneNumber>_tx_ready Buffer64 Out (MicroLabBox II) 104
Read Fifo Empty
Aurora 64b66b 128 Bit Out 306 I-FPGA Out (IOCNET) (DS2655) 145
UART 3 RS232 (FPGA1403TP1) 434
Aurora 64b66b Out 303 I-FPGA Out (IOCNET) (DS6601) 179
UART 3 RS422/485 (FPGA1403TP1) 438
mgt_lane<LaneNumber>_tx_valid I-FPGA Out (IOCNET) (DS6602) 223
UART RS232 (DS1302) 77
Aurora 64b66b 128 Bit Out 306 I-FPGA64 Out (IOCNET) (DS2655) 147
UART RS232 (FPGA1401TP1) 359
Aurora 64b66b Out 302 I-FPGA64 Out (IOCNET) (DS6601) 181
UART RS422/485 (DS1302) 81
mgt_opto_transceiver_ready I-FPGA64 Out (IOCNET) (DS6602) 225
UART RS422/485 (FPGA1401TP1) 363
MGT In Opto Ready 309
Read Request
MGT_RX_N P Buffer In (DS2655) 132
MGT In 308
Pause Duration Buffer In (DS6601) 166
MGT_RX_P
Buzzer (DS1302) 55 Buffer In (DS6602) 201
MGT In 308
Phi New Buffer64 In (DS2655) 134
MGT_TX_N
APU Master (DS2655) 128 Buffer64 In (DS6601) 168
MGT Out 310
APU Master (DS6601) 162 Buffer64 In (DS6602) 203
MGT_TX_P
APU Master (DS6602) 196 Ready
MGT Out 310
APU Master (MicroLabBox II) 94 Analog Out 19 (MicroLabBox II) 91
mgt_user_clk_156
APU Slave (DS2655) 130 Analog Out 20 (MicroLabBox II) 93
Aurora 64b66b In 301, 305
APU Slave (DS6601) 164, 198 Aurora 64b66b 128 Bit In 304
Mode
APU Slave (MicroLabBox II) 96 Aurora 64b66b 128 Bit Out 306
Analog Out-T (DS6651) 278
Phi Read Aurora 64b66b In 301
I-FPGA In (SCALEXIO) 315
APU Master (DS2655) 127 Aurora 64b66b Out 303
I-FPGA Out (SCALEXIO) 319
APU Master (DS6601) 161 Buffer Out (DS1302) 52
APU Master (DS6602) 196 Buffer Out (DS2655) 136
N APU Master (MicroLabBox II) 94 Buffer Out (DS6601) 170
Noise amplitude APU Slave (DS2655) 130 Buffer Out (DS6602) 205
Analog Out 20 (MicroLabBox II) 92 APU Slave (DS6601) 164, 198 Buffer Out (FPGA1401TP1)
APU Slave (MicroLabBox II) 96 DS1552 332
O Phi Read HD DS1554 375
APU Master (DS2655) 127 Buffer Out (FPGA1403TP1)
Opto_Ready
APU Master (DS6601) 161 DS1552 408
MGT In Opto Ready 309
APU Master (DS6602) 196 DS1554 451
Output mode
APU Master (MicroLabBox II) 94 Buffer Out (MicroLabBox II) 100
Digital InOut (DS2655M1) 244
APU Slave (DS2655) 130 Buffer64 Out (DS1302) 53
Digital Out (DS2655M1) 246
APU Slave (DS6601) 164, 199 Buffer64 Out (DS2655) 139
Digital Out (DS2655M2) 253
APU Slave (MicroLabBox II) 97 Buffer64 Out (DS6601) 173
Output Mode
Proc App Status (DS1302) 63 Buffer64 Out (DS6602) 207
Digital In/Out 14 (In/Out-Z)
parameters 64 Buffer64 Out (FPGA1401TP1)
(MicroLabBox II) 108
port 64 DS1552 334

489
May 2024 FPGA Programming Handcode Framework - FPGA Interface Reference
Index

DS1554 377 parameters 150 parameters 66

Buffer64 Out (FPGA1403TP1) port 151 port 67
DS1552 410 Register In (DS6601) 184 Register64 In (DS2655) 152
DS1554 453 parameters 184 parameters 152
Buffer64 Out (MicroLabBox II) 104 port 185 port 153
I-FPGA Master (SCALEXIO) 321 Register In (DS6602) 228 Register64 In (DS6601) 186
I-FPGA Out (IOCNET) (DS2655) 145 parameters 228 parameters 186
I-FPGA Out (IOCNET) (DS6601) 179 port 229 port 187
I-FPGA Out (IOCNET) (DS6602) 223 Register In (FPGA1401TP1) Register64 In (DS6602) 230
I-FPGA64 Out (IOCNET) (DS2655) 147 DS1552 347 parameters 230
I-FPGA64 Out (IOCNET) (DS6601) 181 DS1554 389 port 231
I-FPGA64 Out (IOCNET) (DS6602) 225 parameters Register64 In (FPGA1401TP1)
Red DS1552 348 DS1552 349
LED Out (DS1302) 63 DS1554 389 DS1554 391
Register group ID port parameters
Register In (DS1302) 65 DS1552 349 DS1552 349
Register In (DS2655) 151 DS1554 390 DS1554 391
Register In (DS6601) 185 Register In (FPGA1403TP1) port
Register In (DS6602) 229 DS1552 423 DS1552 350
Register In (FPGA1401TP1) DS1554 465 DS1554 392
DS1552 348 parameters Register64 In (FPGA1403TP1)
DS1554 390 DS1552 423 DS1552 424
Register In (FPGA1403TP1) DS1554 465 DS1554 466
DS1552 423 port parameters
DS1554 465 DS1552 424 DS1552 424
Register In (MicroLabBox II) 116 DS1554 466 DS1554 466
Register Out (DS1302) 68 Register In (MicroLabBox II) 115 port
Register Out (DS2655) 154 parameters 115 DS1552 425
Register Out (DS6601) 188 port 116 DS1554 467
Register Out (DS6602) 232 Register Out (DS1302) 68 Register64 In (MicroLabBox II) 118
Register Out (FPGA1401TP1) parameters 68 parameters 119
DS1552 352 port 69 port 120
DS1554 394 Register Out (DS2655) 154 Register64 Out (DS1302) 69
Register Out (FPGA1403TP1) parameters 154 parameters 69
DS1552 427 port 155 port 70
DS1554 469 Register Out (DS6601) 188 Register64 Out (DS2655) 155
Register Out (MicroLabBox II) 118 parameters 188 parameters 155
Register64 In (DS1302) 67 port 189 port 156
Register64 In (DS2655) 153 Register Out (DS6602) 232 Register64 Out (DS6601) 189
Register64 In (DS6601) 187 parameters 232 parameters 189
Register64 In (DS6602) 231 port 233 port 190
Register64 In (FPGA1401TP1) Register Out (FPGA1401TP1) Register64 Out (DS6602) 233
DS1552 350 DS1552 351 parameters 233
DS1554 392 DS1554 393 port 234
Register64 In (FPGA1403TP1) parameters Register64 Out (FPGA1401TP1)
DS1552 425 DS1552 351 DS1552 352
DS1554 467 DS1554 393 DS1554 394
Register64 In (MicroLabBox II) 119 port parameters
Register64 Out (DS1302) 70 DS1552 352 DS1552 353
Register64 Out (DS2655) 156 DS1554 394 DS1554 394
Register64 Out (DS6601) 190 Register Out (FPGA1403TP1) port
Register64 Out (DS6602) 234 DS1552 426 DS1552 354
Register64 Out (FPGA1401TP1) DS1554 468 DS1554 395
DS1552 353 parameters Register64 Out (FPGA1403TP1)
DS1554 395 DS1552 426 DS1552 427
Register64 Out (FPGA1403TP1) DS1554 468 DS1554 469
DS1552 428 port parameters
DS1554 470 DS1552 427 DS1552 428
Register64 Out (MicroLabBox II) 121 DS1554 469 DS1554 470
Register In (DS1302) 64 Register Out (MicroLabBox II) 117 port
parameters 64 parameters 117 DS1552 429
port 65 port 118 DS1554 471
Register In (DS2655) 150 Register64 In (DS1302) 66 Register64 Out (MicroLabBox II) 120

490
FPGA Programming Handcode Framework - FPGA Interface Reference May 2024
Index

parameters 120 I/O mapping 295 DS1552 325

port 121 parameters 294 DS1554 369
Reset ports 294 Knock Sensor (FPGA1401TP1) 387
Resolver (DS1302) 73 RTS Knock Sensor (FPGA1403TP1) 463
Resolver (DS1302) 71 UART 3 RS232 (FPGA1403TP1) 435 Startbit
I/O mapping 73 UART RS232 (DS1302) 78 I-FPGA In (SCALEXIO) 315
parameters 71 UART RS232 (FPGA1401TP1) 360 I-FPGA Out (SCALEXIO) 319
port 72 Rx Data status
resolver_<ChannelNumber>_enable RS485 Rx/Tx (DS6651) 292 Watchdog (DS6601) 192
Resolver (DS1302) 72 RS485 RxTx (DS2655M2) 264 Watchdog (DS6602) 236
resolver_<ChannelNumber>_err_rst RX_N Status
Resolver (DS1302) 73 MGT In 308 Watchdog (DS6601) 192
resolver_<ChannelNumber>_fault RX_P Watchdog (DS6602) 236
Resolver (DS1302) 72 MGT In 308 Status In (DS1302) 74
resolver_<ChannelNumber>_mech_pos parameters 74
Resolver (DS1302) 72 S port 74
resolver_<ChannelNumber>_update Status In (DS2655) 157
Sample period
Resolver (DS1302) 72 parameters 157
Analog In (DS6651) 272
resolver_<ChannelNumber>_valid port 157
Analog In-L (DS6651) 275
Resolver (DS1302) 72 Status In (DS6601) 191
Scaling
Rising edge delay parameters 191
Analog In (DS2655M1) 238
Digital In/Out 14 (In) (MicroLabBox II) 106 port 191
Analog In (DS6651) 271
Digital In/Out 14 (In/Out-Z) Status In (DS6602) 235
Analog In-L (DS6651) 274
(MicroLabBox II) 109 parameters 235
Analog Out (DS2655M1) 240
Digital InOut Class 1 (DS1302) 58 port 235
Analog Out (DS6651) 277
Digital InOut Class 2 (DS1302) 60 Status In (FPGA1401TP1)
Analog Out-T (DS6651) 278
RS232 Rx (DS2655M2) 258 DS1552 355
Send
I/O mapping 259 DS1554 396
I-FPGA Out (IOCNET) (DS2655) 145
parameters 258 parameters
I-FPGA Out (IOCNET) (DS6601) 179
port 258 DS1552 355
I-FPGA Out (IOCNET) (DS6602) 223
RS232 Tx (DS2655M2) 259 DS1554 396
I-FPGA64 Out (IOCNET) (DS2655) 147
I/O mapping 260 port
I-FPGA64 Out (IOCNET) (DS6601) 181
parameters 260 DS1552 355
I-FPGA64 Out (IOCNET) (DS6602) 225
port 260 DS1554 396
Send Acknowledge
RS485 Rx (DS2655M2) 261 Status In (FPGA1403TP1)
Buffer Out (DS2655) 137
I/O mapping 262 DS1552 430
Buffer Out (DS6601) 171
parameters 261 DS1554 471
Buffer Out (DS6602) 205
port 261 parameters
Buffer64 Out (DS2655) 139
RS485 Rx (DS6651) 289 DS1552 430
Buffer64 Out (DS6601) 173
I/O mapping 290 DS1554 471
Buffer64 Out (DS6602) 208
parameters 289 port
Sensor Supply (FPGA1401TP1)
port 290 DS1552 430
DS1552 354
RS485 Rx/Tx (DS6651) 291 DS1554 471
I/O mapping
I/O mapping 293 Status In (MicroLabBox II) 122
DS1552 354
parameters 291 parameters 122
parameters
ports 292 port 122
DS1552 354
RS485 RxTx (DS2655M2) 263 Stop bits
port
I/O mapping 264 UART RS232 (DS1302) 76
DS1552 354
parameters 263 UART RS232 (FPGA1403TP1) 358, 433
Sensor Supply (FPGA1403TP1)
port 263 UART RS422/485 (DS1302) 80
DS1552 429
RS485 Termination UART RS422/485 (FPGA1401TP1) 362, 437
I/O mapping
RS485 Rx (DS6651) 290 Supply voltage
DS1552 430
RS485 Rx/Tx (DS6651) 291 Sensor Supply (FPGA1401TP1)
parameters
RS485 Tx (DS6651) 294 DS1552 354
DS1552 429
RS485 Termination config Sensor Supply (FPGA1403TP1)
port
RS485 Rx (DS2655M2) 261 DS1552 429
DS1552 430
RS485 RxTx (DS2655M2) 263
Start
RS485 Tx (DS2655M2) 265 T
Buzzer (DS1302) 55
RS485 Tx (DS2655M2) 265
Start of conversion temperature
I/O mapping 266
ADC (Type A) (FPGA1403TP1) FPGA1401TP1 port 397
parameters 265
DS1552 401 DS1552 355
port 266
DS1554 445 FPGA1403TP1 port 472
RS485 Tx (DS6651) 294
ADC Type A (FPGA1401TP1) DS1552 431

491
May 2024 FPGA Programming Handcode Framework - FPGA Interface Reference
Index

Temperature (FPGA1401TP1) 397 I/O mapping 440 UART RS232 (FPGA1401TP1) 359
parameters 397 parameters 436 UART RS422/485 (DS1302) 81
port 397 port 438 UART RS422/485 (FPGA1401TP1) 363
Temperature (FPGA1403TP1) 472 UART mode uart_<ChannelNumber>_rts
parameters 472 UART RS422/485 (DS1302) 80 UART 3 RS232 (FPGA1403TP1) 435
port 472 UART RS422/485 (FPGA1401TP1) 362 UART RS232 (DS1302) 78
Termination UART RS422/485 (FPGA1403TP1) 437 UART RS232 (FPGA1401TP1) 360
Digital In/Out 15 (MicroLabBox II) 111 UART RS232 (DS1302) 74 uart_<ChannelNumber>_wr
UART RS232 (DS1302) 76 I/O mapping 78 UART 3 RS232 (FPGA1403TP1) 434
UART RS232 (FPGA1401TP1) 358 parameters 75 UART 3 RS422/485 (FPGA1403TP1) 439
UART RS232 (FPGA1403TP1) 433 port 76 UART RS232 (DS1302) 77
UART RS422/485 (DS1302) 80 UART RS232 (FPGA1401TP1) 356 UART RS232 (FPGA1401TP1) 359
UART RS422/485 (FPGA1401TP1) 363 I/O mapping 360 UART RS422/485 (DS1302) 82
UART RS422/485 (FPGA1403TP1) 438 parameters 357 UART RS422/485 (FPGA1401TP1) 364
Threshold init voltage port 358 uart_<ChannelNumber>_wr_data
Digital In (DS2655M1) 242 UART RS232 (FPGA1403TP1) 431 UART 3 RS232 (FPGA1403TP1) 435
Digital In (DS2655M2) 251 UART RS422/485 (DS1302) 79 UART 3 RS422/485 (FPGA1403TP1) 439
Digital In (DS6651) 279 parameters 79 UART RS232 (DS1302) 78
Digital In/Out-Z (DS6651) 282 port 81 UART RS232 (FPGA1401TP1) 360
Threshold voltage UART RS422/485 (FPGA1401TP1) 361 UART RS422/485 (DS1302) 82
Digital In (Type B) (FPGA1403TP1) I/O mapping 365 UART RS422/485 (FPGA1401TP1) 364
DS1552 415 parameters 361 uart_<ChannelNumber>_wr_data_count
DS1554 455 port 363 UART 3 RS232 (FPGA1403TP1) 434
Digital In Type B (FPGA1401TP1) UART RS422/485 (FPGA1403TP1) 436 UART 3 RS422/485 (FPGA1403TP1) 439
DS1552 340 UART type UART RS232 (DS1302) 77
DS1554 379 UART RS232 (DS1302) 76 UART RS232 (FPGA1401TP1) 359
Digital In/Out 14 (In) (MicroLabBox II) 106 UART RS232 (FPGA1401TP1) 358, 433 UART RS422/485 (DS1302) 82
Digital In/Out 14 (In/Out-Z) UART RS422/485 (DS1302) 80 UART RS422/485 (FPGA1401TP1) 364
(MicroLabBox II) 108 UART RS422/485 (FPGA1401TP1) 362, 437 uart_<ChannelNumber>_wr_fifo_full
Transformer uart_<Channel_Number>_driver_en UART 3 RS232 (FPGA1403TP1) 435
Analog Out 20 (MicroLabBox II) 92 UART RS422/485 (DS1302) 82 UART 3 RS422/485 (FPGA1403TP1) 439
Trigger uart_<ChannelNumber>_cts UART RS232 (DS1302) 78
Analog In 23 (MicroLabBox II) 87 UART 3 RS232 (FPGA1403TP1) 435 UART RS232 (FPGA1401TP1) 360
Analog In 24 (MicroLabBox II) 88 UART RS232 (DS1302) 78 UART RS422/485 (DS1302) 82
Analog In 25 (MicroLabBox II) 90 UART RS232 (FPGA1401TP1) 360 UART RS422/485 (FPGA1401TP1) 364
Analog Out 19 (MicroLabBox II) 91 uart_<ChannelNumber>_driver_en Update
Analog Out 20 (MicroLabBox II) 92 UART 3 RS422/485 (FPGA1403TP1) 440 Resolver (DS1302) 72
Trigger (DS6651) 296 UART RS422/485 (FPGA1401TP1) 365 usr_<ChannelNumber>_interrupt
I/O mapping 296 uart_<ChannelNumber>_rd Interrupt (DS2655) 148
parameters 296 UART 3 RS232 (FPGA1403TP1) 433 Interrupt (DS6601) 182
port 296 UART 3 RS422/485 (FPGA1403TP1) 438 Interrupt (DS6602) 226
Trigger mode UART RS232 (DS1302) 76 Interrupt (FPGA1401TP1)
Analog In (DS6651) 271 UART RS232 (FPGA1401TP1) 358 DS1552 346
Analog In-L (DS6651) 274 UART RS422/485 (DS1302) 81 DS1554 386
Tx Data UART RS422/485 (FPGA1401TP1) 363 Interrupt (FPGA1403TP1)
RS485 Rx/Tx (DS6651) 292 uart_<ChannelNumber>_rd_data DS1552 421
RS485 RxTx (DS2655M2) 263 UART 3 RS232 (FPGA1403TP1) 434 DS1554 462
Tx Enable UART 3 RS422/485 (FPGA1403TP1) 439 usr_interrupt_<ChannelNumber>
RS485 Rx/Tx (DS6651) 292 UART RS232 (DS1302) 77 Interrupt (DS1302) 62
RS485 Tx (DS2655M2) 263 UART RS232 (FPGA1401TP1) 359 Interrupt (MicroLabBox II) 113
TX_N UART RS422/485 (DS1302) 81
MGT Out 310 UART RS422/485 (FPGA1401TP1) 364 V
TX_P uart_<ChannelNumber>_rd_data_count
Valid
MGT Out 310 UART 3 RS232 (FPGA1403TP1) 433
Resolver (DS1302) 72
UART 3 RS422/485 (FPGA1403TP1) 438
U UART RS232 (DS1302) 77
UART RS232 (FPGA1401TP1) 358 W
UART (RS422/485) (DS1302)
UART RS422/485 (DS1302) 81 Watchdog (DS6601) 191
I/O mapping 82
UART RS422/485 (FPGA1401TP1) 363 parameters 192
UART 3 RS232 (FPGA1403TP1)
uart_<ChannelNumber>_rd_fifo_empty port 192
I/O mapping 435
UART 3 RS232 (FPGA1403TP1) 434 Watchdog (DS6602) 235
parameters 432
UART 3 RS422/485 (FPGA1403TP1) 438 parameters 236
port 433
UART RS232 (DS1302) 77 port 236
UART 3 RS422/485 (FPGA1403TP1)

492
FPGA Programming Handcode Framework - FPGA Interface Reference May 2024
Index

Word length Buffer64 In (DS6601) 168 I-FPGA64 Out (IOCNET) (DS2655) 147
UART RS232 (DS1302) 75 Buffer64 In (DS6602) 203 I-FPGA64 Out (IOCNET) (DS6601) 181
UART RS232 (FPGA1401TP1) 357 xmem64f_inter_<ChannelNumber>_addr I-FPGA64 Out (IOCNET) (DS6602) 225
UART RS232 (FPGA1403TP1) 433 I-FPGA64 In (IOCNET) (DS2655) 143 xmemf_<ChannelNumber>_addr
UART RS422/485 (DS1302) 80 I-FPGA64 In (IOCNET) (DS6601) 177 Buffer In (DS1302) 48
UART RS422/485 (FPGA1401TP1) 362 I-FPGA64 In (IOCNET) (DS6602) 221 Buffer In (DS2655) 132
UART RS422/485 (FPGA1403TP1) 437 xmem64f_inter_<ChannelNumber>_count Buffer In (DS6601) 166
Write Data I-FPGA64 In (IOCNET) (DS2655) 143 Buffer In (DS6602) 200
UART 3 RS232 (FPGA1403TP1) 435 I-FPGA64 In (IOCNET) (DS6601) 177 Buffer In (FPGA1401TP1)
UART 3 RS422/485 (FPGA1403TP1) 439 I-FPGA64 In (IOCNET) (DS6602) 221 DS1552 329
UART RS232 (DS1302) 78 xmem64f_inter_<ChannelNumber>_dout DS1554 372
UART RS232 (FPGA1401TP1) 360 I-FPGA64 In (IOCNET) (DS2655) 143 Buffer In (FPGA1403TP1)
UART RS422/485 (DS1302) 82 I-FPGA64 In (IOCNET) (DS6601) 177 DS1552 405
UART RS422/485 (FPGA1401TP1) 364 I-FPGA64 In (IOCNET) (DS6602) 221 DS1554 448
Write Data Count xmem64f_inter_<ChannelNumber>_new_data Buffer In (MicroLabBox II) 99
UART 3 RS232 (FPGA1403TP1) 434 I-FPGA64 In (IOCNET) (DS2655) 144 xmemf_<ChannelNumber>_count
UART 3 RS422/485 (FPGA1403TP1) 439 I-FPGA64 In (IOCNET) (DS6601) 178 Buffer In (DS1302) 48
UART RS232 (DS1302) 77 I-FPGA64 In (IOCNET) (DS6602) 222 Buffer In (DS2655) 132
UART RS232 (FPGA1401TP1) 359 xmem64p_<ChannelNumber>_din Buffer In (DS6601) 166
UART RS422/485 (DS1302) 82 Buffer64 Out (DS1302) 53 Buffer In (DS6602) 200
UART RS422/485 (FPGA1401TP1) 364 Buffer64 Out (DS2655) 139 Buffer In (FPGA1401TP1)
Write Enable Buffer64 Out (DS6601) 173 DS1552 329
UART 3 RS232 (FPGA1403TP1) 434 Buffer64 Out (DS6602) 207 DS1554 371
UART 3 RS422/485 (FPGA1403TP1) 439 Buffer64 Out (MicroLabBox II) 104 Buffer In (FPGA1403TP1)
UART RS232 (DS1302) 77 xmem64p_<ChannelNumber>_finished DS1552 404
UART RS232 (FPGA1401TP1) 359 Buffer64 Out (DS1302) 53 DS1554 447
UART RS422/485 (DS1302) 82 Buffer64 Out (DS2655) 139 Buffer In (MicroLabBox II) 98
UART RS422/485 (FPGA1401TP1) 364 Buffer64 Out (DS6601) 173 xmemf_<ChannelNumber>_dout
Write Fifo Full Buffer64 Out (DS6602) 207 Buffer In (DS1302) 48
UART 3 RS232 (FPGA1403TP1) 435 Buffer64 Out (MicroLabBox II) 104 Buffer In (DS2655) 132
UART 3 RS422/485 (FPGA1403TP1) 439 xmem64p_<ChannelNumber>_overflow Buffer In (DS6601) 166
UART RS232 (DS1302) 78 Buffer64 Out (DS1302) 54 Buffer In (DS6602) 200
UART RS232 (FPGA1401TP1) 360 Buffer64 Out (DS2655) 139 Buffer In (FPGA1401TP1)
UART RS422/485 (DS1302) 82 Buffer64 Out (DS6601) 173 DS1552 329
UART RS422/485 (FPGA1401TP1) 364 Buffer64 Out (DS6602) 208 DS1554 371
Buffer64 Out (MicroLabBox II) 104 Buffer In (FPGA1403TP1)
X xmem64p_<ChannelNumber>_send_ack DS1552 404
Buffer64 Out (DS2655) 139 DS1554 447
xmem64f_<ChannelNumber>_addr
Buffer64 Out (DS6601) 173 Buffer In (MicroLabBox II) 98
Buffer64 In (DS1302) 50
Buffer64 Out (DS6602) 208 xmemf_<ChannelNumber>_new_data
Buffer64 In (DS2655) 134
xmem64p_<ChannelNumber>_write Buffer In (DS1302) 48
Buffer64 In (DS6601) 168
Buffer64 Out (DS1302) 53 Buffer In (DS2655) 132
Buffer64 In (DS6602) 203
Buffer64 Out (DS2655) 139 Buffer In (DS6601) 166
Buffer64 In (MicroLabBox II) 102
Buffer64 Out (DS6601) 173 Buffer In (DS6602) 200
xmem64f_<ChannelNumber>_count
Buffer64 Out (DS6602) 207 Buffer In (FPGA1401TP1)
Buffer64 In (DS1302) 50
Buffer64 Out (MicroLabBox II) 104 DS1552 329
Buffer64 In (DS2655) 134
xmem64p_inter_<ChannelNumber>_din DS1554 372
Buffer64 In (DS6601) 168
I-FPGA64 Out (IOCNET) (DS2655) 147 Buffer In (FPGA1403TP1)
Buffer64 In (DS6602) 202
I-FPGA64 Out (IOCNET) (DS6601) 181 DS1552 404
Buffer64 In (MicroLabBox II) 102
I-FPGA64 Out (IOCNET) (DS6602) 225 DS1554 447
xmem64f_<ChannelNumber>_dout
xmem64p_inter_<ChannelNumber>_finished Buffer In (MicroLabBox II) 98
Buffer64 In (DS1302) 50
I-FPGA64 Out (IOCNET) (DS2655) 147 xmemf_<ChannelNumber>_read_req
Buffer64 In (DS2655) 134
I-FPGA64 Out (IOCNET) (DS6601) 181 Buffer In (DS2655) 132
Buffer64 In (DS6601) 168
I-FPGA64 Out (IOCNET) (DS6602) 225 Buffer In (DS6601) 166
Buffer64 In (DS6602) 202
xmem64p_inter_<ChannelNumber>_overflow Buffer In (DS6602) 201
Buffer64 In (MicroLabBox II) 102
I-FPGA64 Out (IOCNET) (DS2655) 147 xmemf_inter_<ChannelNumber>_addr
xmem64f_<ChannelNumber>_new_data
I-FPGA64 Out (IOCNET) (DS6601) 181 I-FPGA In (IOCNET) (DS2655) 141
Buffer64 In (DS1302) 50
I-FPGA64 Out (IOCNET) (DS6602) 225 I-FPGA In (IOCNET) (DS6601) 175
Buffer64 In (DS2655) 134
xmem64p_inter_<ChannelNumber>_strobe I-FPGA In (IOCNET) (DS6602) 219
Buffer64 In (DS6601) 168
I-FPGA64 Out (IOCNET) (DS2655) 147 xmemf_inter_<ChannelNumber>_count
Buffer64 In (DS6602) 203
I-FPGA64 Out (IOCNET) (DS6601) 181 I-FPGA In (IOCNET) (DS2655) 142
Buffer64 In (MicroLabBox II) 102
I-FPGA64 Out (IOCNET) (DS6602) 225 I-FPGA In (IOCNET) (DS6601) 176
xmem64f_<ChannelNumber>_read_req
xmem64p_inter_<ChannelNumber>_write I-FPGA In (IOCNET) (DS6602) 219
Buffer64 In (DS2655) 134

493
May 2024 FPGA Programming Handcode Framework - FPGA Interface Reference
Index

xmemf_inter_<ChannelNumber>_dout Buffer Out (DS6601) 171 Buffer64 Out (FPGA1403TP1)

I-FPGA In (IOCNET) (DS2655) 142 Buffer Out (DS6602) 205 DS1552 410
I-FPGA In (IOCNET) (DS6601) 176 Buffer Out (FPGA1401TP1) DS1554 453
I-FPGA In (IOCNET) (DS6602) 220 DS1552 333 xmemp64_<ChannelNumber>_write
xmemf_inter_<ChannelNumber>_new_data DS1554 375 Buffer64 Out (FPGA1401TP1)
I-FPGA In (IOCNET) (DS2655) 142 Buffer Out (FPGA1403TP1) DS1552 334
I-FPGA In (IOCNET) (DS6601) 176 DS1552 408 DS1554 377
I-FPGA In (IOCNET) (DS6602) 220 DS1554 451 Buffer64 Out (FPGA1403TP1)
xmemf64_<ChannelNumber>_addr Buffer Out (MicroLabBox II) 101 DS1552 410
Buffer64 In (FPGA1401TP1) xmemp_<ChannelNumber>_send_ack DS1554 453
DS1552 331 Buffer Out (DS2655) 137 xreg_<ChannelNumber>_din
DS1554 373 Buffer Out (DS6601) 171 Register Out (DS1302) 69
Buffer64 In (FPGA1403TP1) Buffer Out (DS6602) 205 Register Out (DS2655) 155
DS1552 406 xmemp_<ChannelNumber>_write Register Out (DS6601) 189
DS1554 449 Buffer Out (DS1302) 52 Register Out (DS6602) 233
xmemf64_<ChannelNumber>_count Buffer Out (DS2655) 136 Register Out (FPGA1401TP1)
Buffer64 In (FPGA1401TP1) Buffer Out (DS6601) 170 DS1552 352
DS1552 330 Buffer Out (DS6602) 205 DS1554 394
DS1554 373 Buffer Out (FPGA1401TP1) Register Out (FPGA1403TP1)
Buffer64 In (FPGA1403TP1) DS1552 332 DS1552 427
DS1552 406 DS1554 375 DS1554 469
DS1554 449 Buffer Out (FPGA1403TP1) Register Out (MicroLabBox II) 118
xmemf64_<ChannelNumber>_dout DS1552 408 xreg_<ChannelNumber>_dout
Buffer64 In (FPGA1401TP1) DS1554 451 Register In (DS1302) 65
DS1552 330 Buffer Out (MicroLabBox II) 100 Register In (DS2655) 151
DS1554 373 xmemp_inter_<ChannelNumber>_din Register In (DS6601) 185
Buffer64 In (FPGA1403TP1) I-FPGA Out (IOCNET) (DS2655) 145 Register In (DS6602) 229
DS1552 406 I-FPGA Out (IOCNET) (DS6601) 179 Register In (FPGA1401TP1)
DS1554 449 I-FPGA Out (IOCNET) (DS6602) 223 DS1552 349
xmemf64_<ChannelNumber>_new_data xmemp_inter_<ChannelNumber>_finished DS1554 390
Buffer64 In (FPGA1401TP1) I-FPGA Out (IOCNET) (DS2655) 145 Register In (FPGA1403TP1)
DS1552 331 I-FPGA Out (IOCNET) (DS6601) 179 DS1552 424
DS1554 373 I-FPGA Out (IOCNET) (DS6602) 223 DS1554 466
Buffer64 In (FPGA1403TP1) xmemp_inter_<ChannelNumber>_overflow Register In (MicroLabBox II) 116
DS1552 406 I-FPGA Out (IOCNET) (DS2655) 145 xreg_<ChannelNumber>_dout_wr
DS1554 449 I-FPGA Out (IOCNET) (DS6601) 179 Register In (DS2655) 151
xmemp_<ChannelNumber>_din I-FPGA Out (IOCNET) (DS6602) 223 Register In (DS6601) 185
Buffer Out (DS1302) 51 xmemp_inter_<ChannelNumber>_strobe Register In (DS6602) 229
Buffer Out (DS2655) 136 I-FPGA Out (IOCNET) (DS2655) 145 Register In (FPGA1401TP1)
Buffer Out (DS6601) 170 I-FPGA Out (IOCNET) (DS6601) 179 DS1552 349
Buffer Out (DS6602) 205 I-FPGA Out (IOCNET) (DS6602) 223 DS1554 390
Buffer Out (FPGA1401TP1) xmemp_inter_<ChannelNumber>_write Register In (FPGA1403TP1)
DS1552 332 I-FPGA Out (IOCNET) (DS2655) 145 DS1552 424
DS1554 375 I-FPGA Out (IOCNET) (DS6601) 179 DS1554 466
Buffer Out (FPGA1403TP1) I-FPGA Out (IOCNET) (DS6602) 223 xreg_<ChannelNumber>_wr
DS1552 408 xmemp64_<ChannelNumber>_din Register In (DS1302) 65
DS1554 451 Buffer64 Out (FPGA1401TP1) Register In (MicroLabBox II) 116
Buffer Out (MicroLabBox II) 100 DS1552 334 xreg64_<ChannelNumber>_din
xmemp_<ChannelNumber>_finished DS1554 377 Register64 Out (DS1302) 70
Buffer Out (DS1302) 52 Buffer64 Out (FPGA1403TP1) Register64 Out (DS2655) 156
Buffer Out (DS2655) 136 DS1552 409 Register64 Out (DS6601) 190
Buffer Out (DS6601) 170 DS1554 452 Register64 Out (DS6602) 234
Buffer Out (DS6602) 205 xmemp64_<ChannelNumber>_finished Register64 Out (FPGA1401TP1)
Buffer Out (FPGA1401TP1) Buffer64 Out (FPGA1401TP1) DS1552 354
DS1552 332 DS1552 334 DS1554 395
DS1554 375 DS1554 377 Register64 Out (FPGA1403TP1)
Buffer Out (FPGA1403TP1) Buffer64 Out (FPGA1403TP1) DS1552 429
DS1552 408 DS1552 410 DS1554 471
DS1554 451 DS1554 453 Register64 Out (MicroLabBox II) 121
Buffer Out (MicroLabBox II) 100 xmemp64_<ChannelNumber>_overflow xreg64_<ChannelNumber>_dout
xmemp_<ChannelNumber>_overflow Buffer64 Out (FPGA1401TP1) Register64 In (DS1302) 67
Buffer Out (DS1302) 52 DS1552 335 Register64 In (DS2655) 153
Buffer Out (DS2655) 137 DS1554 377 Register64 In (DS6601) 187

494
FPGA Programming Handcode Framework - FPGA Interface Reference May 2024
Index

Register64 In (DS6602) 231

Register64 In (FPGA1401TP1)
DS1552 350
DS1554 392
Register64 In (FPGA1403TP1)
DS1552 425
DS1554 467
Register64 In (MicroLabBox II) 120
xreg64_<ChannelNumber>_dout_wr
Register64 In (DS1302) 67
Register64 In (DS2655) 153
Register64 In (DS6601) 187
Register64 In (DS6602) 231
Register64 In (FPGA1401TP1)
DS1552 350
DS1554 392
Register64 In (FPGA1403TP1)
DS1552 426
DS1554 468
Register64 In (MicroLabBox II) 120

495
May 2024 FPGA Programming Handcode Framework - FPGA Interface Reference
Index

496
FPGA Programming Handcode Framework - FPGA Interface Reference May 2024

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