FPGA Programming Blockset

Guide
For FPGA Programming Blockset 2024-A

Release 2024-A – May 2024

How to Contact dSPACE
Mail: dSPACE GmbH
Rathenaustraße 26
33102 Paderborn
Germany
Tel.: +49 5251 1638-0
E-mail: info@dspace.de
Web: https://www.dspace.com

How to Contact dSPACE Support

If you encounter a problem when using dSPACE products, contact your local dSPACE
representative:
§ Local dSPACE companies and distributors: https://www.dspace.com/go/locations
§ For countries not listed, contact dSPACE GmbH in Paderborn, Germany.
Tel.: +49 5251 1638-941 or e-mail: support@dspace.de

You can also use the support request form: https://www.dspace.com/go/supportrequest. If

you are logged on to mydSPACE, you are automatically identified and do not have to add
your contact details manually.

If possible, always provide the serial number of the hardware, the relevant dSPACE License
ID, or the serial number of the CmContainer in your support request.

Software Updates and Patches

dSPACE strongly recommends that you download and install the most recent patches
for your current dSPACE installation. Visit https://www.dspace.com/go/patches for the
software updates and patches themselves and for more information, such as how to
receive an automatic notification when an update or a patch is available for your dSPACE
software.

Important Notice
This publication contains proprietary information that is protected by copyright. All rights
are reserved. The publication may be printed for personal or internal use provided all the
proprietary markings are retained on all printed copies. In all other cases, the publication
must not be copied, photocopied, reproduced, translated, or reduced to any electronic
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of dSPACE GmbH.

© 2009 - 2024 by:

dSPACE GmbH
Rathenaustraße 26
33102 Paderborn
Germany

This publication and the contents hereof are subject to change without notice.

AURELION, AUTERA, ConfigurationDesk, ControlDesk, MicroAutoBox, MicroLabBox,

SCALEXIO, SIMPHERA, SYNECT, SystemDesk, TargetLink, and VEOS are registered
trademarks of dSPACE GmbH in the United States or other countries, or both. Other
brand names or product names are trademarks or registered trademarks of their respective
companies or organizations.
 Contents

Contents

About This Guide 9

Introduction to the FPGA Programming Blockset 13

FPGA Basics...................................................................................... ............ 13
Basics on the System Architecture..................................................... ............ 15
Components of the FPGA Programming Blockset.......................................... 16
Basics on Exchanging Data Between Processor and FPGA.............................. 17
Software Tools for Working with the FPGA Programming Blockset.... ............ 19
Hardware Supported by the FPGA Programming Blockset.............................. 22

New Features and Migration 31

New Features of the FPGA Programming Blockset.................................................. 32
New Features of the FPGA Programming Blockset 2024-A............................. 32

Features History of the FPGA Programming Blockset............................................... 33

New Features of the FPGA Programming Blockset 2023-B............................. 33
New Features of the FPGA Programming Blockset 2023-A............................. 34
New Features of the FPGA Programming Blockset 2022-B............................. 37
New Features of the RTI FPGA Programming Blockset 3.13............................ 38
New Features of the RTI FPGA Programming Blockset 3.12............................ 39
New Features of the RTI FPGA Programming Blockset 3.11............................ 39

Migrating and Updating Existing FPGA Models....................................................... 41

Migrating FPGA Models..................................................................................... 41

Updating FPGA Frameworks to the Current Version....................................... 42
Migrating to Different FPGA Hardware.......................................................... 43

Updating FPGA Models with Settings of FPGA Custom Functions.......... ............ 45

How to Update FPGA Models with Imported Parameter Settings................... 45

Adapting Existing FPGA Models to be Used on dSPACE Hardware...................... 46

Replacing the Functionality of the System Generator Block............................ 46
Replacing Gateway Blocks............................................................................. 47

Resetting FPGA Models...................................................................................... 48

Resetting the Block Parameters to the Initial Values....................................... 48

Modeling Aspects and Implementation Workflow 51

Features of the FPGA Programming Blockset................................................. 51

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Modeling Aspects............................................................................. ............ 54

Typical Workflow for FPGA Modeling............................................................ 57
Features of the MicroLabBox Flexible I/O Framework......................... ............ 61
Workflow when Using MicroLabBox Flexible I/O Framework.......................... 62

Modeling the FPGA Functionality and the Access to I/O

Channels 65
Modeling FPGA Functionality.................................................................................. 67
Implementing the FPGA Functionality............................................................ 67
How to Use Simulink Blocks for Modeling the FPGA Functionality.................. 68
Notes on Using Multicycle Paths.................................................................... 71

Modeling External I/O Access..................................................................... ............ 73

Reading From Input Channels........................................................................ 73
Writing To Output Channels.......................................................................... 74
Effects of Modeling External I/O Access......................................................... 75

Using Multiple Clock Domains for FPGA Modeling..................................... ............ 78

Basics on Using Multiple Clock Domains........................................................ 78
Limitations on Using Multiple Clock Domains................................................ 80
How to Use Multiple Clock Domains for FPGA Modeling............................... 81
Using Clock Signals of Different Clock Domains in the Same
Subsystem..................................................................................................... 82
How to Use a Customized Clocking Circuit as Clock Domain Source. ............ 84

Using a Watchdog.................................................................................................. 86
How to Implement the Watchdog................................................................. 86
How to Configure the Condition when the Watchdog Expires....................... 88

Modeling DDR4 RAM Access.................................................................................. 90

Accessing the DDR4 RAM of the DS6602...................................................... 90
Initializing the DDR4 RAM of the DS6602 for Offline Simulation.................... 92
Initializing the DDR4 RAM of the DS6602 for Real-Time Simulation............... 93

Modeling UART Communication............................................................................ 95

Using the UART Demo Model for SCALEXIO Systems........................ ............ 96

Modeling Inter-FPGA Communication........................................................ ............ 99

Introduction to Inter-FPGA Communication........................................................ 99

Overview of Inter-FPGA Communication........................................................ 99

Modeling Inter-FPGA Communication via IOCNET............................................ 101

Implementing Inter-FPGA Communication via IOCNET................................. 101
Calculating the Latency (IOCNET)................................................................ 103

Modeling Inter-FPGA Communication via MGT Modules.................................. 104

Implementing Inter-FPGA Communication via MGT Modules....................... 104

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Modeling Inter-FPGA Communication via I/O Module Slots.............................. 105

Implementing Inter-FPGA Communication via I/O Module Slots................... 105
How to Specify I/O Module Slots of SCALEXIO FPGA Base Boards as
Inter-FPGA Interfaces................................................................................... 110
How to Determine the Bit Ranges for Inter-FPGA Subbuses Between
SCALEXIO FPGA Base Boards....................................................................... 111
Calculating the Data Rate and Latency (SCALEXIO)...................................... 114

Modeling FPGA Applications Supporting Multicore Processor Applications............ 117

Aspects on FPGA Applications Supporting Multicore Processor
Applications................................................................................................ 117
How to Select Subsystems for Multicore Support (MicroLabBox II,
MicroAutoBox III, SCALEXIO)....................................................................... 119

Modeling MGT Communication Using a Customized Protocol.............................. 123

Basic Structure of the MGT Interface........................................................... 123
Customized Protocol Demo (SCALEXIO)............................................ .......... 124
Notes on Implementing Customized Protocols............................................. 128

Modeling the Communication Between the FPGA and

the Real-Time Processor 129
Modeling Processor Model Access........................................................................ 130

Implementing the FPGA Functionality for Processor Communication................ 130

Exchanging Data With the Processor Model................................................. 130
How to Trigger Interrupt-Driven Processor Tasks........................................... 134

Using Simulink Buses for Modeling the Processor Communication................... 135

How to Use Simulink Buses of the FPGA Model to Model Processor
Communication.......................................................................................... 136
How to Use Simulink Buses of the Processor Model to Model the
Processor Communication........................................................................... 138
How to Specify the Data Type Conversion for Processor
Communication.......................................................................................... 141
How to Change the Bus Topology of a Simulink Bus.................................... 142
How to Configure the Bus Data Transmission Method................................. 144
Using Subchannels for Data Exchange......................................................... 146
Notes on Handling Simulink Buses............................................................... 147

Implementing the Processor Interface to the Processor Model............................... 148

How to Generate a Processor Interface........................................................ 148
Modeling Aspects for Multicore Processor Applications..................... .......... 151
How to Transfer 64-Bit Fixed-Point Data with Full Resolution
(MicroLabBox II, SCALEXIO)......................................................................... 152

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Preprocessing and Postprocessing the Signals Between the FPGA and the
Processor Model................................................................................................... 155
Basics on Preprocessing and Postprocessing the Processor
Communication.......................................................................................... 156
Characteristics of Scaling Subsystems.......................................................... 158
Limitations Concerning Scaling Subsystems................................................. 160
How to Prepare FPGA Models to Use Scaling Subsystems............................ 162
How to Implement the Interfaces of Scaling Subsystems.............................. 164
How to Implement Data Exchange Between Scaling Subsystems.................. 167
How to Implement the Interfaces for Offline Simulation.................... .......... 168
How to Update an FPGAC File with Modified Scaling Subsystems................ 170

Simulating and Debugging Processor and FPGA

Applications 173
Running Processor Models and FPGA Subsystems in Simulink Simulation
Mode................................................................................................................... 174
Simulating an FPGA Subsystem................................................................... 174
Simulating a Processor Model...................................................................... 175

Debugging Processor Models and FPGA Subsystems............................................. 177

Analyzing FPGA Models.............................................................................. 177
Features of the dSPACE Timing Analyzer..................................................... 179
Features of the dSPACE Utilization Analyzer...................................... .......... 181

Building FPGA and Processor Applications 185

Building the Applications (MicroLabBox II, MicroAutoBox III, SCALEXIO)................ 186
How to Build FPGA Applications (MicroLabBox II, MicroAutoBox III,
SCALEXIO).................................................................................................. 186
How to Prepare the Processor Models for Separating
(MicroLabBox II, MicroAutoBox III, SCALEXIO).............................................. 189
How to Export Build Results and Processor Models to
ConfigurationDesk Projects......................................................................... 191
How to Build Processor Applications (MicroLabBox II,
MicroAutoBox III, SCALEXIO)....................................................................... 193

Building the Applications (MicroAutoBox II, MicroLabBox)..................................... 195

How to Build FPGA Applications (MicroAutoBox II, MicroLabBox)...... .......... 195
Basics on Building the Processor Application (MicroAutoBox II,
MicroLabBox).............................................................................................. 198
How to Build Single-Core Processor Applications (MicroAutoBox II,
MicroLabBox).............................................................................................. 200
How to Build Multicore Processor Applications for MicroLabBox.................. 201
How to Create Burn Applications for MicroAutoBox II....................... .......... 203

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Achieving Successful Builds at High FPGA Utilization.................................. .......... 205

How to Build FPGA Applications Incrementally.................................. .......... 205

Using an FPGA Build Server.................................................................................. 207

Basics on the FPGA Build Server........................................................ .......... 207
How to Prepare the Computer for the FPGA Build Server............................. 209
How to Install and Start the FPGA Build Server............................................ 211
How to Build FPGA Applications via a Server............................................... 212
FPGA Build Server Configuration File Reference........................................... 214

Monitoring the Build Process................................................................................ 216

How to Monitor the Build Process............................................................... 216
FPGA Build Monitor 2024-A Reference........................................................ 218

Backing Up the Build Results................................................................................ 225

Configuring the Backing Up of Build Results................................................ 225
How to Open Backed Up Vivado Reports..................................................... 227

Running Processor and FPGA Applications on the Real-

Time Hardware 229
Experimenting with an FPGA Application..................................................... 229

Accessing FPGA Applications with your Experiment

Software 233
Accessing Elements of FPGA Applications............................................................. 234
Introduction to Access FPGA Applications.................................................... 234

Tracing FPGA Signals............................................................................................ 237

Basics on Tracing FPGA Signals.................................................................... 237
How to Make FPGA Signals Traceable.......................................................... 240
How to Exclude FPGA Signals from Tracing.................................................. 242

Adjusting Values of FPGA Constants..................................................................... 244

Basics on Tunable FPGA Constants.............................................................. 244
How to Make FPGA Constants Tunable....................................................... 245

Enabling the FPGA Test Access and Scaling........................................................... 248

Basics on FPGA Test Access and Scaling....................................................... 248
How to Enable FPGA Test Access and Scaling.............................................. 252
How to Change the Data Type of Analog Signals......................................... 253
How to Specify Scaling Presettings.................................................... .......... 254

Displaying FPGA Signals in ControlDesk................................................................ 256

Capturing FPGA Signals for Display in ControlDesk...................................... 256

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 Contents

Troubleshooting 259
Problems and Their Solutions....................................................................... 259

Index 269

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 About This Guide

About This Guide

Content This guide provides basic information about the FPGA Programming Blockset,
including the entire software environment and the supported hardware. You will
also learn how to apply the main features of the blockset.

Audience profile It is assumed that you have good knowledge in:

§ Applying generally accepted FPGA design rules to ensure a stable and reliable
FPGA application.
§ The architectural structure of FPGAs (CLB architecture, slice flip-flops, memory
resources, DSP resources, clocking resources) with a verifiable experience on
digital designs (structural mapping, tool-flow knowledge, synthesis options,
timing analysis).
§ Modeling with Simulink®.
§ Modeling with the HDL library of the AMD® VitisTM Model Composer
§ Using the AMD design tools for simulation and debugging.

Symbols dSPACE user documentation uses the following symbols:

Symbol Description
Indicates a hazardous situation that, if not avoided,
V DANGER
will result in death or serious injury.
Indicates a hazardous situation that, if not avoided,
V WARNING could result in death or serious injury.
Indicates a hazardous situation that, if not avoided,
V CAUTION could result in minor or moderate injury.
Indicates a hazard that, if not avoided, could result in
NOTICE
property damage.
Indicates important information that you should take
Note
into account to avoid malfunctions.
Indicates tips that can make your work easier.
Tip

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 About This Guide

Symbol Description
Indicates a link that refers to a definition in the
glossary, which you can find at the end of the
document unless stated otherwise.
Follows the document title in a link that refers to
another document.

Naming conventions dSPACE user documentation uses the following naming conventions:

%name% Names enclosed in percent signs refer to environment variables for

file and path names.

<> Angle brackets contain wildcard characters or placeholders for variable

file and path names, etc.
Examples:
§ Where you find terms such as rti<XXXX> replace them by the RTI platform
support you are using, for example, rti1202.
§ Where you find terms such as <model> or <submodel> in this document,
replace them by the actual name of your model or submodel. For example,
if the name of your Simulink model is smd_1202_sl.slx and you are
asked to edit the <model>_usr.c file, you actually have to edit the
smd_1202_sl_usr.c file.

RTI block name conventions All I/O blocks have default names based on
dSPACE's board naming conventions:
§ Most RTI block names start with the board name.
§ A short description of functionality is added.
§ Most RTI block names also have a suffix.

Suffix Meaning
M Module number (for MicroAutoBox II)
C Channel number
G Group number
CON Converter number
BL Block number
P Port number
I Interrupt number

A suffix is followed by the appropriate number. For example,

DS1202SER_INT_C2_I1 represents an interrupt block located on a
MicroLabBox. The suffix indicates channel number 2 and interrupt number
1 of the block. For more general block naming, the numbers are replaced by
variables (for example, DS1202SER_INT_Cx_Iy).

Special Windows folders Windows‑based software products use the following special folders:

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 About This Guide

Common Program Data folder A standard folder for application-specific

program data that is used by all users.
%PROGRAMDATA%\dSPACE\<InstallationGUID>\<ProductName>
or
%PROGRAMDATA%\dSPACE\<ProductName>\<VersionNumber>

Documents folder A standard folder for application‑specific files that are

used by the current user.
%USERPROFILE%\Documents\dSPACE\<ProductName>\<VersionNumber>

Local Program Data folder A standard folder for application-specific

program data that is used by the current user.
%USERPROFILE%\AppData\Local\dSPACE\<InstallationGUID>\
<ProductName>

Accessing dSPACE Help and After you install and decrypt Windows‑based dSPACE software, the
PDF files documentation for the installed products is available in dSPACE Help and as PDF
files.

dSPACE Help (local) You can open your local installation of dSPACE Help:
§ On its home page via Windows Start Menu
§ On specific content using context-sensitive help via F1

PDF files You can access PDF files via the icon in dSPACE Help. The PDF
opens on the first page.

dSPACE Help (Web) Independently of the software installation, you can

access the Web version of dSPACE Help at https://www.dspace.com/go/help.
To access the Web version, you must have a mydSPACE account.
For more information on the mydSPACE registration process, refer to
https://www.dspace.com/faq?097.

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 About This Guide

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 Introduction to the FPGA Programming Blockset

Introduction to the FPGA Programming Blockset

Basic feature of the blockset The FPGA Programming Blockset is a Simulink® blockset that allows you to
program an FPGA in a dSPACE system.

Where to go from here Information in this section

FPGA Basics............................................................................................. 13
General information on FPGAs.

Basics on the System Architecture............................................................ 15

The system architecture determines the signals your FPGA applications
can read, process and update. It shows the data flow to download
applications and to analyze data.

Components of the FPGA Programming Blockset.................................... 16

The FPGA Programming Blockset is a Simulink blockset for integrating an
FPGA application into a dSPACE system.

Basics on Exchanging Data Between Processor and FPGA........................ 17

Only the processor application initiates data exchange between the real-
time processor and the FPGA. To be able to exchange data, the FPGA
and processor interfaces provide different data storages.

Software Tools for Working with the FPGA Programming Blockset........... 19

Information about the required software tools.

Hardware Supported by the FPGA Programming Blockset........................ 22

Overview of the supported hardware.

FPGA Basics

FPGA architecture FPGA stands for Field Programmable Gate Array. It is used in digital technology
to allow modifications in a circuit's functionality without replacing hardware. A
specific circuit is implemented as a specific configuration of the internal logic

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 Introduction to the FPGA Programming Blockset

cells. The configurable logic blocks (CLBs) are connected with each other via
switch boxes. The external connection is realized by I/O pins.

Reasons for using FPGAs The main advantages of an FPGA are its flexibility and high speed for signal
processing:
§ Flexibility
You can implement any kind of circuit, from a simple counter to an entire
microprocessor.
You can reconfigure your implementation in the development phase without
hardware changes.
§ Speed
The specific implementations are usually concentrated on one functionality
without any overhead.
The bit architecture is often more efficiently than the word architecture with a
fix data width.
Execution can be done in parallel which results in a high throughput.
Control loops (input of data, result calculation, output of data) can usually
be performed at higher overall sample rates on an FPGA than on non-FPGA
platforms.

Fields of application All of the above-mentioned features of an FPGA are very useful for function
prototyping, which can be performed with dSPACE hardware and software.

FPGAs are used, if you have a task that cannot be solved by standard
implementations. They are used for tasks that require high performance, for
example, for complex signal processing, or if you want to move some of your
model's functionality to a separate application.

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 Basics on the System Architecture

Basics on the System Architecture

Introduction The system architecture determines the signals your FPGA applications can read,
process, and update. It shows the data flow to download applications and to
analyze data.

Components of a dSPACE The following illustration shows you the components and the signal connections
system and their connections of a dSPACE system, such as a MicroAutoBox III.

dSPACE system

Real-time I/O
Host PC processor channels

External
device

FPGA I/O
channels

Description of the elements shown in the illustration:

§ Host PC
With the host PC, you download the processor and FPGA application. You
can use dSPACE software installed on the host PC to experiment with your
real-time application.
§ Real-time processor
The real-time processor executes your processor application. It initiates sending
and receiving data to/from the FPGA via a board-specific bus. The real-time
processor can also be connected to its own I/O channels to provide I/O
functionality independently of the FPGA.
§ FPGA
The FPGA processes your FPGA application (FPGA logic implementation). The
FPGA is connected to its own I/O channels to process I/O signals independently
of the real-time processor. If the real-time processor initiates data exchange,
the FPGA sends and receives data to/from a board-specific bus.
§ I/O channels
To access the external I/O signals of the external device, the signals must be
converted so that they meet the requirements of the connected components.
This is done, for example, by filters, signal amplifiers or analog-to-digital
converters.

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 Introduction to the FPGA Programming Blockset

§ External device
Device that can be connected to the dSPACE system, such as an ECU.

Components of the FPGA Programming Blockset

Introduction The FPGA Programming Blockset is a Simulink blockset for integrating an FPGA
application into a dSPACE system. It provides Simulink blocks for implementing
the interface between the FPGA and the I/O channels of the dSPACE I/O board
on which the FPGA is mounted, and the interface between the FPGA and the
real-time processor. Furthermore, script functions let you execute functions via
command line or M file.

Overview of the blockset

FPGA interface Processor interface

board-specific bus

FPGA_XDATA_WRITE_BL PROC_XDATA_READ_BL

Processor
model

FPGA_XDATA_READ_BL PROC_XDATA_WRITE_BL

FPGA logic

FPGA_IO_WRITE_BL

I/O channel

FPGA_IO_READ_BL

FPGA interface The blocks of the FPGA Interface library are used to model the interface of an
FPGA application in the FPGA model. The blocks let you configure the interface
between the FPGA and the I/O channels of the FPGA board that provides access
to external I/O signals. The blocks also provide access to data storage that is used
for exchanging data with the real-time processor.

The data exchange and all other communication between the FPGA board and
the processor board runs via the board‑specific bus:
§ Intermodule bus when the MicroAutoBox II/III is used.
§ Local bus when MicroLabBox is used.
§ IOCNET when SCALEXIO or MicroLabBox II is used.

Processor interface Processor interface when using a MicroAutoBox II or a

MicroLabBox The Simulink blocks of the Processor Interface library are
used to implement processor communication with the FPGA via the board-

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 Basics on Exchanging Data Between Processor and FPGA

specific bus. These blocks in the processor model are the counterparts of the
related FPGA_XDATA blocks in the FPGA model. They access the data storage
that you configured in the FPGA model. The setup block of the Processor
Interface library lets you automatically generate the interface blocks for the
processor model.

Processor interface when using a MicroLabBox II, MicroAutoBox III, or

a SCALEXIO system When you use a MicroLabBox II, MicroAutoBox III, or
a SCALEXIO system, the Processor Interface library is not required. Instead,
you implement the data exchange between the FPGA model and the processor
model with generated interface blocks of the Model Interface Package for
Simulink.

Available script functions The FPGA Programming Blockset comes with script functions for executing
functions via command line or M file. You can use them, for example, to execute
scheduled build processes at night. For more information on the available script
functions, refer to Introduction to the Script Interface of the FPGA Programming
Software (FPGA Programming Software Script Interface Reference ).

Related topics Basics

Implementing the Processor Interface to the Processor Model................................................. 148

Modeling External I/O Access.................................................................................................... 73

Basics on Exchanging Data Between Processor and FPGA

Introduction Only the processor application initiates a data exchange between the real-time
processor and the FPGA. To be able to exchange data, the FPGA and processor
interfaces provide different data storages.

Provided data storage You can choose the data storage that you want to use for the data exchange
with the following access types:
§ Register
Registers are implemented as flip-flops to exchange scalar values.
§ Register group
Register groups are implemented as flip-flops to exchange a data package
with synchronized elements.
§ Buffer
Buffers are implemented in the FPGA RAM to exchange data packages with a
buffer size of up to 32,768 elements.

For board-specific details on, such as data width or data format, refer to
Exchanging Data With the Processor Model on page 130.

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Details on the access types Register access Register access lets you access a scalar value in the register.
The data is identified by the specified channel number. The values are
transmitted element by element.

Register group access You can group registers to a register group via a
common Register Group ID. All the values that belong to the same Register
Group ID are synchronously updated in the FPGA subsystem.
For read access, the registers of a register group are read from the board-specific
bus sequentially and then provided to the FPGA application simultaneously. For
write access, the registers of a register group are sampled simultaneously in the
FPGA application. These values form a consistent data group that is written to
the board-specific bus.

Buffer access Buffer access lets you access a vector value in the data buffer.
One specific value of the data is identified by the specified channel number and
the position within the buffer.
Data exchange is implemented via a FIFO buffer that works as a swinging buffer.
This means that there are two separate buffers for reading and writing, and
one buffer that switches between reading and writing. Only the pointer has to
be changed to switch the buffer so that no buffer has to be copied from one
position to another.

Free buffer

Application Read buffer Write buffer FPGA application

running on the
processor board

Processing the data exchange Only the processor application can initiate data exchange between the real-time
processor and the FPGA. The following illustration shows you the main steps that
a processor task performs.

Processor task
From external device To external device
Read Process Update
inputs model outputs

From FPGA To FPGA

From external device To external device

FPGA

The FPGA executes its operations in parallel because the FPGA application is a
logic implementation: i.e., the execution time of an FPGA is much faster than the
execution time of the real-time processor.

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 Software Tools for Working with the FPGA Programming Blockset

Several processor tasks with different task periods can request read/write access
to the FPGA at different points in time. These read/write requests are executed
by the FPGA in parallel. The following illustration shows you the read/write
requests of a real-time application with two processor tasks.

Read Read Read Compute Write Read Read Read Compute Write Read
Processor FPGA FPGA FPGA model of
Write
FPGA FPGA FPGA FPGA model of
Write
FPGA FPGA
Idle Idle
task 1 FPGA FPGA
Reg1 Reg3 Reg7 task 1 Reg9 Reg1 Reg3 Reg7 task 1 Reg9 Reg1
Reg4 Reg4

t Task 1 t Task 1

Processor Read Read Compute Write Read Read Compute Write Read Read Compute Write
FPGA FPGA model of FPGA Idle FPGA FPGA model of FPGA Idle FPGA FPGA model of FPGA Idle
task 2 Reg2 Reg4 task 2 Reg8 Reg2 Reg4 task 2 Reg8 Reg2 Reg4 task 2 Reg8

t Task 2 t Task 2 t Task 2

Related topics Basics

Exchanging Data With the Processor Model............................................................................ 130

Software Tools for Working with the FPGA Programming Blockset

Introduction To model and build an FPGA application for dSPACE hardware, several software
tools are necessary.

Tools from The MathWorks® MATLAB®, Simulink® and Simulink® CoderTM are required for modeling and
simulating the application.

The following tools from The MathWorks are optional:

§ In addition to the Word Length Calculator of the FPGA Programming Blockset,
you can use the Fixed-Point DesignerTM to optimize the use of fixed-point
data types. Using fixed-point data types reduces the FPGA utilization of your
application.
§ HDL CoderTM can be used to generate VHDL code from parts of the FPGA
model that use Simulink blocks. HDL Coder is not required if you use only
the HDL library of the AMD Vitis Model Composer for the functionality of the
FPGA model.
§ Simulink Report GeneratorTM to generate an HTML model of the FPGA model.
The backup process of the FPGA Programming Blockset can automatically back
up the Simulink model of the entire model. In addition, you can specify that
a web view (HTML model) of the Simulink model is generated to display the
entire model in any Internet browser. Refer to Configuring the Backing Up of
Build Results on page 225.

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 Introduction to the FPGA Programming Blockset

For compatibility information, refer to Supported software versions on page 21.

Tools from AMD AMD provides several tools for designing applications for AMD FPGAs. The
Vivado® Design Suite covers all the aspects of designing FPGAs. Working with
the FPGA Programming Blockset requires the following products:

Vivado Design Suite The Vivado Design Suite provides a logic design
environment for AMD FPGAs. It contains tools and wizards, for example, for I/O
assignment, power analysis, timing-driven design closure, and HDL simulation.
With the Vivado software, you can build the FPGA application according to the
implemented FPGA model.
The FPGA Programming Blockset uses the Vivado software in the background
without the GUI.

AMD Vitis Model Composer AMD® VitisTM Model Composer for modeling
FPGA applications with Simulink is the unified AMD add-on for MATLAB
Simulink.
The following items of the AMD Vitis Model Composer are required for modeling
and generating the FPGA application:
§ The AMD Vitis Model Composer Blockset.
The AMD Vitis Model Composer Blockset is a Simulink block library that lets
you graphically model FPGA applications. The AMD Vitis Model Composer
Blockset requires a separate license.
The FPGA Programming Blockset supports only the HDL library of the AMD
Vitis Model Composer.
§ The code generator that is included in the AMD Vitis Model Composer.
The code generator is used to generate the HDL code based on blocks of the
FPGA Programming Blockset and the AMD Vitis Model Composer Blockset.

Tip

To use the AMD Vitis Model Composer with a specific MATLAB version, the
-matlab "<matlabdir>" parameter must be specified. You can add this
parameter to the Vitis Model Composer icon on the desktop, for example.

Xilinx System Generator for DSP (XSG) As of Vivado 2021.1, the AMD
Vitis Model Composer includes the functionality of the Xilinx System Generator
for DSP (XSG). For licensing issues related to this change, refer to AMD Answer
Record 76039 (https://support.xilinx.com/s/article/76039).

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Ordering AMD software Currently, you cannot order the AMD software
from dSPACE. Install the AMD software before or after installing dSPACE
software and follow the installation instructions from the AMD manuals.

Supported software versions The following table shows you the supported products and their software
versions for the current version of the FPGA Programming Blockset.

Design Tool Version MATLAB Operating System

Version1)
AMD Vivado 2023.22) MATLAB Windows operating system that is supported by the RCP and HIL software
R2022b of the current Release.
For a list of supported operating systems, refer to Operating System (New
Features and Migration ). The listed Windows Server operating systems
are not supported by AMD.
1) The Processor Interface sublibrary of the FPGA Programming Blockset also supports
MATLAB R2023a, R2023b, and R2024a.
2) In general, Vivado ML Enterprise edition and the AMD Vitis Model Composer are
needed. The Vivado ML Standard edition with AMD Vitis Model Composer can also be
used for the DS2655 (7K160) and DS6601 FPGA base boards. The AMD Vitis Model
Composer is required only for modeling FPGA applications with the FPGA Programming
Blockset.

For software versions that are compatible with older versions of the FPGA
Programming Blockset, refer to https://www.dspace.com/faq?295.

MATLAB compatibility The limited MATLAB compatibility reflects the

requirements of the AMD Design Tools and its impacts on the building processes
for creating an FPGA application.
In contrast to the FPGA build process, the blocksets and tools for modeling and
building the processor application support the regular MATLAB compatibility of
a dSPACE Release. Therefore, you can extend the MATLAB compatibility if you
model and build the processor application separately from the FPGA application.
The only requirement is that the same dSPACE Release is used to build the FPGA
application and the processor application.
For example: The FPGA application is created with an installation set containing
the current dSPACE Release, Vivado 2023.2, and MATLAB R2022b. You can
transfer and import the generated FPGA application to an installation set
containing the current dSPACE Release and MATLAB R2024a to continue your
work with ConfigurationDesk or the Processor Interface sublibrary of the FPGA
Programming Blockset.

Required blocksets for the The MicroLabBox II, MicroAutoBox III, and SCALEXIO require the dSPACE Model
processor model Interface Package for Simulink to implement the interface between the real-
time processor and the FPGA. The Model Interface Package for Simulink is the
blockset for specifying all interfaces of processor models (behavior models) used
in ConfigurationDesk.

For the MicroAutoBox II and MicroLabBox the FPGA Programming Blockset

includes a Processor Interface blockset that you can use in the processor
model.

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ConfigurationDesk ConfigurationDesk is the required dSPACE implementation tool for the

MicroLabBox II, MicroAutoBox III, or SCALEXIO system. ConfigurationDesk lets
you implement I/O functionality, bus communication, and the connection to
processor models and FPGA applications. ConfigurationDesk is used to build
the real-time application that includes the FPGA application and runs on the
MicroLabBox II/MicroAutoBox III/SCALEXIO.

ControlDesk ControlDesk is the dSPACE software tool for experimenting with a dSPACE
system. It can be used to register the connected hardware, to manage the
simulation platform, to download the real-time application (processor and FPGA
application), and to control the experiment. The great variety of instruments
allows you to access and visualize variables of the processor application.

Related topics HowTos

Step 1: How to Install the Required Software (FPGA Programming Blockset Getting
Started )

Hardware Supported by the FPGA Programming Blockset

Introduction The FPGA Programming Blockset is not board-specific. Here is an overview of the
supported hardware.

MicroLabBox Internally, MicroLabBox consists of the two boards DS1202 and DS1302. The
DS1302 board provides the FPGA capabilities.

MicroLabBox's I/O FPGA module provides channels for analog input and
output, digital input and output, and bus communication. The DS1302 board
of MicroLabBox provides an FPGA unit with an AMD FPGA that can be
programmed by using the FPGA Programming Software.

An FPGA application is automatically integrated into a MicroLabBox application

when building.

Note

dSPACE also provides RTI blocksets for MicroLabBox. To use blocks from the
FPGA Programming Blockset and the RTI blocksets in the same model, you
have to use the flexible I/O framework for MicroLabBox. Refer to Features of
the MicroLabBox Flexible I/O Framework on page 61.

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The following table shows the main features of MicroLabBox's I/O FPGA:

Feature Description
Programmable FPGA § AMD® Kintex®-7 XC7K325T
§ 326,080 logic cells
§ 50,950 slices
§ 4,000 kbit distributed RAM (max.)
§ 840 DSP slices
§ 16,020 kbit block RAM
§ 100 MHz hardware clock frequency
§ Multiple clock domains: Up to ten clock domains can be used to process FPGA subsystems
with individual clock periods.
Analog input § ADC (Class 1): 24 parallel A/D converters with 16-bit resolution and a sample rate of
1 MS/s.
§ ADC (Class 2): 8 parallel A/D converters with 16-bit resolution and a sample rate of
10 MS/s.
Analog output DAC (Class 1): 16 parallel D/A converters with 16-bit resolution.
Digital I/O § Digital InOut (Class 1): 48 digital bidirectional channels, single‑ended.
§ Digital InOut (Class 2): 8 digital bidirectional channels, differential.
Resolver interface 2 resolver interfaces that support resolvers with an excited single coil.
Serial interface 2 UART (RS232) and 2 UART (RS422/485) interfaces.
The UART (RS422/485) function supports full‑duplex mode and half‑duplex mode.
Feedback elements § Status In: State of the initialization sequence that is started after programming the FPGA.
§ LED Out: 4 customizable LEDs.
§ Proc App Status: Execution state of the loaded executable application.

For further information on the hardware, refer to General Data (MicroLabBox

Hardware Reference ).

For further information on the software features, refer to Block Settings for
the MicroLabBox Frameworks (FPGA Programming Blockset - FPGA Interface
Reference ).

MicroLabBox II Internally, the MicroLabBox II consists of the two boards DS1203 Processor Board
and DS1303 Multi-I/O Board. The DS1303 Multi-I/O Board provides the FPGA
capabilities.

The following table shows the main features of the MicroLabBox II:

Feature Description
Programmable § AMD® Kintex® UltraScale+TM XCKU15P-2FFVE1517E
FPGA § 1,143,450 system logic cells
§ 1,045,440 FlipFlops
§ 1,968 DSP slices
§ 9.8 Mbit maximum distributed RAM

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Feature Description
§ 34.6 Mbit block RAM
§ 36.0 Mbit Ultra RAM
§ 125 MHz hardware clock frequency
§ Multiple clock domains: Up to ten clock domains can be used to process FPGA subsystems
with individual clock periods.
Analog input § Analog In 23: Input channel to measure differential analog voltage signals in the range ±10 V
with max. 2 MS/s.
Number of channels: 24
§ Analog In 24: Input channel to measure differential analog voltage signals in the range ±1 V or
±10 V with max. 5 MS/s.
Number of channels: 6
§ Analog In 25: Input channel to measure differential analog voltage signals in the range ±1 V or
±10 V with max. 5 MS/s. A load can be activated.
Number of channels: 2
Analog output § Analog Out 19: Output channel to generate ground-based analog voltage signals in the range
±10 V with max. 2 MS/s.
Number of channels: 14
§ Analog Out 20: Output channel to generate analog signals. Each channel can be configured to
generate a ground-based signal (±10 V) or a transformer-coupled signal (±20 V AC) with max.
5 MS/s.
Number of channels: 2
Digital I/O § Digital In/Out 14: Bidirectional channels to measure or generate ground-based digital signals.
Number of channels: 48
§ Digital In/Out 15: Bidirectional channels to measure or generate differential digital signals.
Number of channels: 12
Feedback § Status In: State of the initialization sequence that is started after programming the FPGA.
elements § LED Out: 1 customizable LED.
§ Proc App Status: Execution state of the loaded executable application.

For further information on the hardware, refer to MicroLabBox II Data Sheet

(MicroLabBox II Hardware Installation and Configuration ).

For further information on the software features, refer to Block Settings for
the MicroLabBox II Framework (FPGA Programming Blockset - FPGA Interface
Reference ).

MicroAutoBox II/III The MicroAutoBox II/III consists of a board with the real-time processor and at
least one I/O board. An FPGA base board provides the FPGA and the interfaces
for adding different I/O modules.

DS1514 FPGA Base Board The DS1514 FPGA Base Board provides an FPGA.
The following table shows the main features of the DS1514 FPGA Base Board.

Feature Description
Programmable § AMD Kintex®-7 XC7K325T
FPGA § 326,080 logic cells
§ 50,950 slices

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Feature Description
§ 4,000 kbit distributed RAM (max.)
§ 840 DSP slices
§ 80 MHz hardware clock frequency.
§ Multiple clock domains: Up to ten clock domains can be used to process FPGA subsystems
with individual clock periods.
I/O interfaces I/O interfaces are provided by I/O modules that are installed to the FPGA base board. Refer to
I/O modules available for MicroAutoBox II/III on page 25.
Feedback elements § Status In: State of the initialization sequence that is started after programming the FPGA.
§ Temperature: Sensor to measure the FPGA's die temperature.
§ LED Out: 1 FPGA Status LED.

For further information on the hardware, refer to the following data sheets:
§ MicroAutoBox II 1401/1511/1514: General Data (MicroAutoBox II Hardware
Reference )
§ MicroAutoBox II 1401/1513/1514: General Data (MicroAutoBox II Hardware
Reference )
§ MicroAutoBox III: DS1514 FPGA Base Board Data Sheet (MicroAutoBox III
Hardware Installation and Configuration )

I/O modules available for I/O modules provide the I/O interface for the DS1514 FPGA Base Board. The
MicroAutoBox II/III following table shows the main features of the supported I/O modules:

Feature DS1552 Multi-I/O Module DS1552B1 Multi-I/O Module DS1554 Engine

Control I/O Module
Analog input § ADC (Type A), Analog In 101): 8 § ADC (Type A), Analog In 111): 8 ADC (Type A), Analog
parallel A/D converters with 16- parallel A/D converters with 16- In 141): 14 parallel
bit resolution and a conversion bit resolution and a conversion A/D converters with 16-
time of 1 µs, conversion can be time of 1 µs, conversion can be bit resolution and a
triggered. triggered. conversion time of 1 µs.
Input voltage range: 0 V ... +5 V Input voltage range: Input voltage range:
§ ADC (Type B), Analog In 121): 16 -10 V ... +10 V -10 V ... +10 V
parallel A/D converters with 16- § ADC (Type B), Analog In 121): 16
bit resolution and a conversion parallel A/D converters with 16-
time of 5 µs. Input voltage range: bit resolution and a conversion
-10 V ... +10 V. time of 5 µs. Input voltage range:
-10 V ... +10 V.
Analog ADC (Type B), Analog Out 131): ‑
output 16 parallel A/D converters with 16-bit resolution and a conversion time of
5 µs.
Input voltage range: -10 V ... +10 V
Digital I/O § Digital In (Type A), Digital In 51): 16 digital input channels. § Digital In (Type
§ Digital In (Type B)/Digital Out (Type B), Digital InOut 61): 8 digital B)/Digital Out (Type
bidirectional channels. B), Digital InOut 81):
§ Digital Out (Type A), Digital Out 5 1): 16 digital output channels. 8 digital bidirectional
channels.
§ Digital Out (Type
A), Digital Out 7:

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Feature DS1552 Multi-I/O Module DS1552B1 Multi-I/O Module DS1554 Engine

Control I/O Module
40 digital output
channels.
Digital 3 digital inputs to read digital camshaft and crankshaft sensors. 5 digital inputs to read
Crank/Cam digital camshaft and
input crankshaft sensors.
Inductive 1 digital input to read an inductive zero voltage detector.
zero voltage
detector
Knock signal ‑ 4 analog inputs to read
input knock sensors.
Serial 2 UART (RS232/422/485) interfaces. RS422/485 supports full‑duplex mode ‑
interface and half‑duplex mode.
UART 1 can be used without modification. To use UART 2, your DS1552
has to be modified by dSPACE.
Sensor supply 1 adjustable supply voltage in the voltage range 2 V ... 20 V. 1 supply voltage
providing 5 V.
1) The channel name depends on the framework.

Note

dSPACE also provides an RTI blockset for the DS1552 Multi-I/O Module.
You cannot use blocks from the FPGA Programming Blockset and the RTI
DS1552 I/O Extension Blockset in the same model.

For further information on the hardware, refer to the following data sheets.
§ MicroAutoBox II:
§ Data Sheet DS1552 Multi-I/O Module (MicroAutoBox II Hardware
Reference )
§ Data Sheet DS1554 Engine Control I/O Module (MicroAutoBox II Hardware
Reference )
§ MicroAutoBox III:
§ DS1552 Multi-I/O Module Data Sheet (MicroAutoBox III Hardware
Installation and Configuration )
§ DS1554 Engine Control I/O Module Data Sheet (MicroAutoBox III Hardware
Installation and Configuration )

For more information on the software features, refer to the following framework
references.
§ MicroAutoBox II
§ Block Settings for the FPGA1401Tp1 with Multi-I/O Module Frameworks
(FPGA Programming Blockset - FPGA Interface Reference )
§ Block Settings for the FPGA1401Tp1 with Engine Control I/O Module
Framework (FPGA Programming Blockset - FPGA Interface Reference )
§ MicroAutoBox III
§ Block Settings for the FPGA1403Tp1 with Multi‑I/O Module Frameworks
(FPGA Programming Blockset - FPGA Interface Reference )

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§ Block Settings for the FPGA1403Tp1 with Engine Control I/O Module
Framework (FPGA Programming Blockset - FPGA Interface Reference )

SCALEXIO system A SCALEXIO system consists of SCALEXIO processing hardware and a selection
of I/O boards. The SCALEXIO processing hardware, such as a SCALEXIO Real-
Time PC, provides the computation power of the system.

I/O boards are available for the various requirements, for example, for accessing
analog input and output signals, digital input and output signals, and bus
communication.

With the SCALEXIO FPGA base boards, you can integrate an FPGA application
into a SCALEXIO system. The board provides an FPGA that you can program
using the FPGA Programming Blockset.

The following table shows the main features of the supported SCALEXIO FPGA
base boards.

Feature DS2655 (7K160) DS2655 (7K410) DS6601 DS6602

Programmable AMD® KINTEX®-7-160T AMD® KINTEX®-7-410T AMD® KINTEX® AMD® KINTEX®
FPGA § 162,240 logic cells § 406,720 logic cells UltraScale™ KU035 UltraScale+™ KU15P
§ 600 DSP slices § 1,540 DSP slices § 444,343 system § 1,143,450 system
logic cells logic cells
§ 2,188 kbit maximum § 5,663 kbit maximum
distributed RAM distributed RAM § 1,700 DSP slices § 1,968 DSP slices
§ 11,700 kbit total § 28,620 kbit total § 5,908 kbit § 9,800 kbit
block RAM block RAM maximum maximum
distributed RAM distributed RAM
§ 125 MHz hardware § 125 MHz hardware
clock frequency clock frequency § 19,000 kbit total § 34,600 kbit total
block RAM block RAM
§ Multiple clock § Multiple clock
domains: Up to ten domains: Up to ten § 125 MHz hardware § 36,000 kbit
clock domains can clock domains can clock frequency UltraRAM
be used to process be used to process § Multiple clock § 125 MHz hardware
FPGA subsystems FPGA subsystems domains: Up to ten clock frequency
with individual clock with individual clock clock domains can § Multiple clock
periods. periods. be used to process domains: Up to ten
FPGA subsystems clock domains can
with individual be used to process
clock periods. FPGA subsystems
with individual clock
periods.
I/O interfaces I/O interfaces are provided by up to 5 I/O modules that are installed to the SCALEXIO FPGA base
board. Refer to I/O modules available for SCALEXIO FPGA base board on page 28.
Angular § APU Master: You can write angle-based time base values to the IOCNET bus with up to 6
processing units angular processing units of the SCALEXIO FPGA base board. Other boards connected to the
APU bus as APU slaves can read the corresponding time base value.
§ APU Slave: You can read angle-based time base values from the IOCNET with up to 6 angular
processing units of the SCALEXIO FPGA base board. Another board connected to the IOCNET is
specified as the APU master and writes the time base value.
MGT interface ‑ 1 Multi-Gigabit Transceiver (MGT) interface
with 4 bidirectional lanes that can be used for

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Feature DS2655 (7K160) DS2655 (7K410) DS6601 DS6602

communication with external devices or with
other DS6601/DS6602 FPGA Base Boards.
To support MGT communication, an MGT
module must be installed to the FPGA base
board.
Inter-FPGA Direct data exchange with other SCALEXIO FPGA base boards via inter-FPGA communication bus.
communication
Interrupt lines 8 16
Feedback § Status In: State of the initialization sequence that is started after programming the FPGA.
elements § CN App Status: Execution state of the loaded executable application on the computation node.
§ IOCNET Global Time: Time that is specified for all modules connected to IOCNET.
§ LED Out: 1 FPGA Status LED.

For further information on the hardware, refer to Hardware for FPGA

Applications (SCALEXIO Hardware Installation and Configuration ).

For further information on the software features, refer to the following:

§ Block Settings for the DS2655 FPGA Base Board Framework (FPGA
Programming Blockset - FPGA Interface Reference )
§ Block Settings for the DS6601 FPGA Base Board Framework (FPGA
Programming Blockset - FPGA Interface Reference )
§ Block Settings for the DS6602 FPGA Base Board Framework (FPGA
Programming Blockset - FPGA Interface Reference )

I/O modules available for I/O modules provide the I/O interface for the SCALEXIO FPGA base boards
SCALEXIO FPGA base board DS2655, DS6601, and DS6602. The following table shows the main features
of the supported I/O modules:

Feature DS2655M1 DS2655M2 DS6651

Analog Analog In: 5 analog ‑ A total of 6 analog input channels with
input input channels with 14‑bit 16‑bit resolution and 5 MS/s sample rate:
resolution and 4 MS/s § 4 Analog In channels
sample rate.
§ 2 Analog In-L channels with a
switchable load.
All channels can be triggered by different
trigger sources.
Analog Analog Out: 5 analog ‑ A total of 6 analog output channels with
output output channels with 16‑bit resolution and 10.417 MS/s update
14‑bit resolution and rate:
7.8125 MS/s update rate. § 4 Analog Out channels
§ 2 Analog Out-T channels that can
output the voltage signal via a
transformer.

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Feature DS2655M1 DS2655M2 DS6651

Digital 10 digital I/O channels 32 versatile digital I/O channels 16 versatile digital I/O channels that
I/O that can be used as that can handle bit-wise data can handle bit-wise data or serial
follows: or serial communication. The communication. The main features are I/O
§ Digital In main features are I/O functions functions that use the digital channels to
that use the digital channels implement a specific I/O functionality.
§ Digital Out
to implement a specific I/O § Digital In: Up to 16 digital input
§ Digital InOut
functionality. functions that provide bit-wise access.
(bidirectional): An
§ Digital In: Up to 32 digital § Digital In/Out-Z: Up to 4 digital I/O
external signal is only
input functions that provide functions that provide bit-wise access
available if the direction
bit-wise access. and a high-impedance output state
of a channel is set to
In, otherwise the input § Digital Out: Up to 32 digital (tristate).
signal is consistent with output functions that provide § Digital Out: Up to 16 digital output
the output signal. bit-wise access. functions that provide bit-wise access.
§ Digital Out-Z: Up to 16 § Digital Out-Z: Up to 8 digital output
digital output functions that functions that provide bit-wise access
provide bit-wise access and a and a high-impedance output state
high-impedance output state (tristate).
(tristate).
§ RS485 Tx: Up to 8 serial functions that
§ RS232 Rx: Up to 8 serial transmit data values to RS485 networks
functions that receive data in simplex mode.
values from RS232 networks.
§ RS485 Rx: Up to 8 serial functions
§ RS232 Tx: Up to 8 serial that receive data values from RS485
functions that transmit data networks in simplex mode.
values to RS232 networks.
§ RS485 Rx/Tx: Up to 4 serial functions
§ RS485 Rx: Up to 8 serial that exchange data values with RS485
functions that receive data networks in half-duplex mode.
values from RS485 networks
in simplex mode.
§ RS485 Rx/Tx: Up to 8 serial
functions that exchange data
values with RS485 networks
in half-duplex mode.
§ RS485 Tx: Up to 8 serial
functions that transmit data
values to RS485 networks in
simplex mode.

For further information on the hardware, refer to the following:

§ Data Sheet of the DS2655M1 Multi-I/O Module (SCALEXIO Hardware
Installation and Configuration )
§ Data Sheet of the DS2655M2 Digital I/O Module (SCALEXIO Hardware
Installation and Configuration )
§ Data Sheet of the DS6651 Multi-I/O Module (SCALEXIO Hardware Installation
and Configuration )

For further information on the software features, refer to the following:

§ Block Settings for the DS2655M2 I/O Module Framework (FPGA Programming
Blockset - FPGA Interface Reference )

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§ Block Settings for the DS2655M2 I/O Module Framework (FPGA Programming
Blockset - FPGA Interface Reference )
§ Block Settings for the DS6651 Multi-I/O Module Framework (FPGA
Programming Blockset - FPGA Interface Reference )

Using different dSPACE Note

hardware
Using an FPGA model on different dSPACE hardware requires some model
modifications, refer to Migrating to Different FPGA Hardware on page 43.

Related topics Basics

Software Tools for Working with the FPGA Programming Blockset............................................ 19

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New Features and Migration

Introduction New FPGA Programming Blockset features of the current and historical versions
and information on using and updating existing FPGA models to use them in
your current project.

Where to go from here Information in this section

New Features of the FPGA Programming Blockset.................................... 32

New features of the current FPGA Programming Blockset version.

Features History of the FPGA Programming Blockset................................ 33

New features of the historical FPGA Programming Blockset versions.

Migrating and Updating Existing FPGA Models........................................ 41

You can use and update existing FPGA models to use them in your
current project.

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New Features of the FPGA Programming Blockset

New Features of the FPGA Programming Blockset 2024-A

General enhancements to the Enhanced resource utilization reports The FPGA Programming Blockset
FPGA Programming Blockset now provides resource utilization reports including the resources required for
HDL Coder subsystems. This means that the total resource utilization of an FPGA
model that uses Simulink blocks in addition to AMD® VitisTM Model Composer
and FPGA Programming Blockset blocks is now reported.
For more information, refer to Features of the dSPACE Utilization Analyzer on
page 181.

Data exchange between scaling subsystems The FPGA Programming

Blockset now supports connections within FPGA functions to directly exchange
signal values between scaling subsystems. The data exchange takes place on
the real-time processor and does not use any FPGA resources. The following
illustration shows an example:

For more information on scaling subsystems, refer to Basics on Preprocessing and

Postprocessing the Processor Communication on page 156.

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 Features History of the FPGA Programming Blockset

Features History of the FPGA Programming Blockset

Where to go from here Information in this section

New Features of the FPGA Programming Blockset 2023-B....................... 33

Provides an overview of the functions introduced with FPGA
Programming Blockset 2023-B.

New Features of the FPGA Programming Blockset 2023-A....................... 34

Provides an overview of the functions introduced with FPGA
Programming Blockset 2023-A.

New Features of the FPGA Programming Blockset 2022-B....................... 37

Provides an overview of the functions introduced with FPGA
Programming Blockset 2022-B.

New Features of the RTI FPGA Programming Blockset 3.13...................... 38

Provides an overview of the functions introduced with RTI FPGA
Programming Blockset 3.13.

New Features of the RTI FPGA Programming Blockset 3.12...................... 39

Provides an overview of the functions introduced with RTI FPGA
Programming Blockset 3.12.

New Features of the RTI FPGA Programming Blockset 3.11...................... 39

Provides an overview of the functions introduced with RTI FPGA
Programming Blockset 3.11.

New Features of the FPGA Programming Blockset 2023-B

General enhancements to the Incremental build The FPGA Programming Blockset now lets you enable the
FPGA Programming Blockset incremental build feature of Vivado to help in consistently achieving successful
builds at high FPGA utilizations. A known good reference build is used as a
starting point for implementation, so that new builds can assume a working
FPGA configuration and only the actual changes need to be implemented. An
incremental build increases the likelihood of successful FPGA builds and reduces
build times for rather small changes in the FPGA model.
Refer to How to Build FPGA Applications Incrementally on page 205.

dSPACE Timing Analyzer The new dSPACE Timing Analyzer helps you to fix
timing errors that are detected during the build process.
The timing analyzer helps you with the following features:
§ Shows the most critical FPGA signal paths of the built FPGA application
independently of the used block libraries (HDL library of the AMD Vitis Model
Composer and/or standard Simulink library (HDL Coder subsystems)).
The number of FPGA signal paths is limited to 1,000 bits of signals. For
example, 50 20-bit wide data paths can be displayed.

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§ Provides details on the used blocks within a failed signal path.

§ Opens a selected block of a failed signal path in the FPGA model. This gives
you a fast access to fix the error.
§ Provides the timing report with details on the selected signal path. The details
help to fix errors that require detailed analysis.
For more information, refer to Features of the dSPACE Timing Analyzer on
page 179.

Message handling The FPGA Programming Blocks now provides a new

message handling that informs you about possible problems or upcoming
actions. The messages are issued in the MATLAB Command Window or in
dialogs. They provide links and/or buttons for you to open the related topic in
the new FPGA Programming Blockset Message Reference, which contains more
information.

New MicroLabBox II The MicroLabBox II provides an FPGA on the DS1303 Multi-I/O Board that can be
framework programmed with the FPGA Programming Blockset. The FPGA custom function
block type built with the FPGA Programming Blockset replaces the standard
I/O functionality of the I/O board. In ConfigurationDesk, you can either use
the FPGA custom function block type or the function block types provided by
ConfigurationDesk to implement the I/O functionality.

For an overview of the provided I/O functionality, refer to Block Settings for
the MicroLabBox II Framework (FPGA Programming Blockset - FPGA Interface
Reference ).

If you handcode the FPGA application, use the provided Tcl script to build
the FPGA application. Refer to How to Build the FPGA Application (FPGA
Programming Handcode Framework Guide ).

Enhancements to The frameworks now provide clock signals and additional information for
the SCALEXIO and subsystems using a user clock domain:
MicroAutoBox III frameworks § Clock signal with the base rate of the FPGA.
§ Clock signal of another subsystem using a user clock domain.
§ System information on the FPGA application, the processor application, and an
optional MGT module.

For more information, refer to Using Clock Signals of Different Clock Domains in
the Same Subsystem on page 82.

New Features of the FPGA Programming Blockset 2023-A

General enhancements to the Support of Simulink blocks to model parts of the FPGA model The FPGA
FPGA Programming Blockset Programming Blockset now supports MathWorks© HDL CoderTM for modeling
parts of the FPGA model with SimulinkTM blocks. This feature lets you use
existing Simulink models directly as part of your FPGA application. For example:

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You can use a Simulink model of a controller for first functionality tests before
you optimize the FPGA utilization of the controller.
The FPGA Programming Blockset provides gateway blocks to transfer the signals
and buses between the separated model parts. During the build process, the
following tools generate the HDL code:
§ MathWorks HDL Coder generates the VHDL code from blocks of the Simulink
blockset.
§ AMD Vitis Model Composer generates the VHDL code from blocks of the HDL
library and the FPGA Programming Blockset.
The build process merges the individual VHDL codes into a synthesizable overall
model. For instructions, refer to How to Use Simulink Blocks for Modeling the
FPGA Functionality on page 68.
Using MathWorks HDL coder does not affect the MATLAB compatibility of the
FPGA Programming Blockset, because only parts of the FPGA model can be
modeled with Simulink blocks.

Support of new ControlDesk instruments for scaling The FPGA test

access and scaling feature now supports the FPGA Scale ControlDesk
instruments to conveniently scale the I/O interfaces of an FPGA application.
For more information, refer to FPGA Scale ADC (ControlDesk Instrument
Handling ) and FPGA Scale DAC (ControlDesk Instrument Handling ).

Advanced preferences Advanced preferences of the FPGA Programming

Blockset let you perform workarounds or disable features. Changing the default
settings is recommended only for special use cases. For example: If the error code
changes again, you can ignore critical warnings during the build process.
However, some preferences let you disable convenience features. For example,
you can speed up the copy & paste process by deactivating the automatic
reassignment of new hardware resources.
For more information, refer to Dialog Settings of the Advanced Preferences
Dialog (FPGA Programming Blockset - FPGA Interface Reference ).
For information on setting advanced preferences with script functions, refer to
Script Functions to Manage Advanced Preferences (FPGA Programming Software
Script Interface Reference ).

Enhancements to the More comfortable transfer of the FPGA container After the FPGA build,
MicroAutoBox III/SCALEXIO a publish link in the MATLAB Command Window and a Publish button on
frameworks the ConfigurationDesk Interface page of the FPGA Setup block now let you
publish the path of the built FPGA container file to the global user location file
of ConfigurationDesk. This makes the build FPGA application available as FPGA
custom function block types in the Function Browser of ConfigurationDesk.

Enhanced support of mask parameters of scaling subsystems Two-

dimensional mask parameter matrices in the row-based array layout for FPGA
scaling subsystems are now supported by ConfigurationDesk and ControlDesk.
Scaling subsystems are a feature of the FPGA Programming Blockset to specify
the preprocessing and postprocessing of the signals between the FPGA and
the real-time processor. For more information on scaling subsystems, refer to
Characteristics of Scaling Subsystems on page 158.

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New method to provide clock domains The new User Clock Out block
lets you use a customized clocking circuit (user clock) as clock domain source.
For example, you can use the clock of the MGT interface to process the data
synchronous to the MGT transceivers.
For instructions, refer to How to Use a Customized Clocking Circuit as Clock
Domain Source on page 84.
The user clock feature is available only for modeling the FPGA application, not
for handcoding.

Enhancements to the New watchdog feature The frameworks of the DS6601/DS6602 FPGA base
SCALEXIO frameworks boards now provide a Watchdog block to check if the processor application is
alive.
For more information, refer to Using a Watchdog on page 86.

New bus data transmission method for the Bus Out block The Bus Out
block now supports the User acknowledged bus data transmission method.
This method lets you acknowledge the data to be transmitted to the processor
application, for example, to trigger the processing of some data before it is
transmitted to the processor application.
For instruction, refer to How to Configure the Bus Data Transmission Method on
page 144.

New MGT In Opto Ready block The MGT In Opto Ready block indicates
whether the MGT module is ready for data exchange.
The MGT In Opto Ready block replaces the Opto_Ready port of the MGT In
block, because the signal of the Opto_Ready port cannot be provided in a user
clock domain.
Rework is necessary if you migrate an FPGA model using a MGT In block. Refer
to Updating FPGA Frameworks to the Current Version on page 42.

Enhancements to the script New script function for MicroAutoBox III/SCALEXIO The script interface is
interface enhanced with a script function to publish the path of the built FPGA container
file to the global user location file of ConfigurationDesk. This makes the build
FPGA application available as FPGA custom function block types in the Function
Browser of ConfigurationDesk.
For more information, refer to PublishFPGACustomFunction (FPGA Programming
Software Script Interface Reference ).

New script interface to manage advanced preferences For information

on setting advanced preferences with script functions, refer to Script Functions
to Manage Advanced Preferences (FPGA Programming Software Script Interface
Reference ).

Enhancement to the A new Getting Started document introduces you to the first steps in FPGA
documentation programming with the FPGA Programming Blockset. A tutorial introduces you
to the basic steps of modeling and building an FPGA application when using a
MicroAutoBox III or SCALEXIO.

Refer to FPGA Programming Blockset Getting Started .

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New Features of the FPGA Programming Blockset 2022-B

Enhancements to the Preprocessing and postprocessing of processor signals The SCALEXIO and
MicroAutoBox III/SCALEXIO the MicroAutoBox III blocksets now support scaling subsystems as a part of
frameworks the FPGA model. Scaling subsystems lets you specify the preprocessing and
postprocessing of the signals between the FPGA and the real-time processor.
Scaling subsystems are executed on the real-time processor even though they are
part of the FPGA model.
Scaling subsystems can be used for the following points:
§ Scaling the signals.
§ Implementing complex algorithms to process the signals. For example, an
FPGA input signal can be calculated from several processor output signals.
§ Grouping of signals for more clarity.
For more information, refer to Basics on Preprocessing and Postprocessing the
Processor Communication on page 156.

New container file format for the build result files The FPGA
Programming Blockset now supports the FPGAC file format for the build results.
FPGAC files let you manage FPGA applications in repositories. If you add or
update an FPGAC file to a search path of ConfigurationDesk, ConfigurationDesk
adds the FPGA custom function block type to the Functions browser and
updates instantiated function blocks if you open the ConfigurationDesk
application or you reload the custom functions.
For more information, refer to How to Import FPGA Custom Function Block Types
Provided by an FPGAC File (ConfigurationDesk I/O Function Implementation
Guide ).

New script function for MicroAutoBox III/SCALEXIO The script interface is

enhanced with a script function to update an existing FPGAC file, for example,
to implement a changed scaling subsystem without building a new FPGA
application.
For more information, refer to How to Update an FPGAC File with Modified
Scaling Subsystems on page 170.

Enhancements to the 64-bit fixed-point support for processor communication The data types
SCALEXIO frameworks without a binary position (Fix_64_0 and UFix_64_0) for the Register64 and
Buffer64 access types now support the full 64-bit fixed-point resolution.
All other 64-bit fixed-point data types are still converted to double and their
fixed-point resolution is restricted to 53 bits. This also applies to the Bus access
types.

Note

The default data type of generated processor interface blocks is always

double. To use the full resolution of a 64-bit fixed-point data type, you have
to set the data type of the generated blocks to int64 or uint64. Refer to
How to Transfer 64-Bit Fixed-Point Data with Full Resolution (MicroLabBox II,
SCALEXIO) on page 152.

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General enhancements to the Backup of the build results Before you build an FPGA application, you
FPGA Programming Blockset can now enable and configure the automatic backup of the FPGA application,
models, and reports that are generated and used during the build process. A link
to the backup folder is provided in the MATLAB Command Window after the
build process finished.
For configuring the automatic backup, refer to Backing Up the Build Results on
page 225.

New reports about the model and build results The framework now
provides model and build reports that are generated at the end of an FPGA
build.
The model report contains information about the FPGA channels, software and
tools used. The build report contains information about the FPGA utilization and
the build duration.
Links to the reports are provided in the MATLAB Command Window after the
build process finished. The reports are located in the build folder or in the
backup folder.

Word length calculator dialog The word length calculator now lets you
calculate an optimal fixed-point data type for a user-defined floating-point value.
Refer to Word Length Calculator (FPGA Programming Blockset - FPGA Interface
Reference ).

Enhancement to the FPGA The FPGA Build Monitor 2022-B now provides the warning messages, if any
Build Monitor were issued during the build process.

For more information, refer to FPGA Build Monitor 2024-A Reference on

page 218.

New Features of the RTI FPGA Programming Blockset 3.13

General enhancement for the The FPGA Scope block now lets you connect up to 16 FPGA signals that can be
SCALEXIO FPGA base boards captured. Nevertheless, only 8 FPGA signals can be displayed in ControlDesk at
the same time. You can select the signals to be displayed in ControlDesk.

For more information, refer to Displaying FPGA Signals in ControlDesk on

page 256.

Enhancement to the FPGA The FPGA Build Monitor 1.2 now supports the following features:
Build Monitor § A Reset button to reset defective builds.
§ A Clear Caches button to clear the build caches.
§ A sort functionality to display the monitored build processes by date, name, or
state.

For more information, refer to FPGA Build Monitor 2024-A Reference on

page 218.

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New Features of the RTI FPGA Programming Blockset 3.12

Framework enhancements New function blocks for the processor communication The new
Bus In/Bus Out blocks for the MicroAutoBox III/SCALEXIO frameworks replace
the transfer mode of the Buffer64 In/Buffer64 Out blocks.
The new Blocks support the following new features:
§ You can copy a Simulink bus topology from a corresponding Data
Inport/Data Outport block of the processor model.
§ A bus editor lets you change the bus topology, including the bus signals of the
Simulink bus used.
For more information, refer to Using Simulink Buses for Modeling the Processor
Communication on page 135.

New ports for the MGT interfaces The Aurora 64b66b In and Aurora
64b66b 128 Bit In blocks now provide a Ready port to specify that the
communication channel is ready to read new data. The new port lets you prevent
data overflow.
Furthermore, the MGT In block now provides an Opto_Ready port. The port
indicates whether the MGT module is ready for data exchange.
Handcoding interface only: The Aurora 64b66b I/O functions provide a
mgt_user_clk_156 clock port. You can use the clock port to implement parts
of your FPGA application synchronously with the clock frequency of the MGT
module, i.e., with 156.25 MHz.
Working with synchronous frequencies has the following benefits:
§ Less latency because there is no clock transition between the clock frequencies
of the FPGA and the MGT module.
§ No need for clock compensation due to drifting clocks. The Aurora protocol
automatically synchronizes the different clocks.

Enhancements to the script New script function for MicroAutoBox III/SCALEXIO The script interface is
interface enhanced with a script function to configure a Bus In/Bus Out block with the
bus configuration of the coresponding processor block.
For more information, refer to CopyProcFPGAXDATABus (FPGA Programming
Software Script Interface Reference ).

New Features of the RTI FPGA Programming Blockset 3.11

Framework enhancements The MicroAutoBox III and SCALEXIO frameworks now provide the following
enhancements:
§ When using the bus transfer mode, you can select the following bus data
transmission methods to transmit data to the processor application:
§ The Synchronous to Read_Req method to transmit data that is captured
synchronously to the processor task.

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§ The Free-running method for applications where the transmission time is

crucial.
For more information, refer to How to Configure the Bus Data Transmission
Method on page 144
§ DS6602 only: The framework for the DS6602 FPGA Base Board now lets you
initialize the DDR4 RAM for offline simulation. Refer to Initializing the DDR4
RAM of the DS6602 for Offline Simulation on page 92.

Enhancements to the script The following table shows the new script functions of the script interface.
interface
Script Function Purpose
AnalyzeFPGAXDATAWriteBus To trigger the bus analysis of the Simulink bus
that is connected to a Bus Out FPGA block. This
script function supports only MicroAutoBox III
and SCALEXIO system models.
CopyFPGAXDATAReadBus To copy an existing FPGA bus topology
from a specified Simulink Bus Creator block,
subsystem inport block, or subsystem outport
block to the Data port of the Bus In
FPGA block. This script function supports only
MicroAutoBox III and SCALEXIO system models.
GetFPGAXDATABusSettings To get the bus settings of a Bus In/Bus Out
FPGA block. This script function supports only
MicroAutoBox III and SCALEXIO system models.
GetMCSubsystems To get the Simulink subsystems that provide the
access for the processor cores of a multicore
system. This script function supports only
MicroAutoBox III and SCALEXIO system models.
GetTraceSubsystems To get the Simulink subsystems that are
traceable with your experiment software.
ResetFPGAXDATABus To clear the bus settings of a Bus In
FPGA block. This script function supports only
MicroAutoBox III and SCALEXIO system models.
SetFPGAXDATABusSettings To set the bus settings of a Bus In/Bus Out
FPGA block. This script function supports only
MicroAutoBox III and SCALEXIO system models.
SetMCSubsystems To set the Simulink subsystems that provide the
access for the processor cores of a multicore
system. This script function supports only
MicroAutoBox III and SCALEXIO system models.
SetTraceSubsystems To set the Simulink subsystems that are
traceable with your experiment software.

For more information, refer to Script Functions Supporting the FPGA Interface
Sublibrary (FPGA Programming Software Script Interface Reference ).

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Migrating and Updating Existing FPGA Models

Introduction You can use and update existing FPGA models to use them in your current
project.

Where to go from here Information in this section

Migrating FPGA Models........................................................................... 41

You can migrate FPGA models to another dSPACE hardware or update
the framework of an FPGA model to the current version.

Updating FPGA Models with Settings of FPGA Custom Functions............ 45

You can update your FPGA model with imported parameter settings of
an FPGA custom function in ConfigurationDesk.

Adapting Existing FPGA Models to be Used on dSPACE Hardware........... 46

To integrate an FPGA application based on the HDL library of the AMD
Vitis Model Composer into a dSPACE system, you must replace certain
blocks with blocks from the FPGA Programming Blockset.

Resetting FPGA Models........................................................................... 48

You can reset the block parameters of the FPGA framework to the initial
values.

Migrating FPGA Models

Introduction You can migrate FPGA models to another dSPACE hardware or update the
framework of an FPGA model to the current version.

Where to go from here Information in this section

Updating FPGA Frameworks to the Current Version................................. 42

Enhancements to the FPGA framework can be made available to older
models by updating it.

Migrating to Different FPGA Hardware.................................................... 43

FPGA models can be migrated to another framework to build an FPGA
application for different FPGA hardware.

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Updating FPGA Frameworks to the Current Version

Introduction If you have implemented your FPGA application using an older version of
the FPGA Programming Blockset, and you want to use it with a current
version, the FPGA framework must be updated. This involves only a few
internal modifications that do not affect the blocks' inputs and outputs or their
parameters.

Migrating from previous The FPGA Programming Blockset automatically updates existing FPGA models
FPGA Programming Blocksets to the current framework version. The update affects all subsystems in the
model/subsystem. The parameters of the blocks stay the same after updating
to the current framework version.

You can also use a script to migrate processor interface blocks, for example, to
migrate RTI processor models without the FPGA model. For more information,
refer to MigrateToModelPortBlocks (FPGA Programming Software Script Interface
Reference ).

Changed process to generate FPGA scope rasters If you use an FPGA

custom function built with the RTI FPGA Programming Blockset 3.13 (Release
2022-A) in ConfigurationDesk, you have to generate the FPGA scope raster that
is used by ControlDesk.
As of FPGA Programming Blockset 2022-B, an FPGA custom function block
with FPGA scope functions automatically generates the FPGA scope raster for
ControlDesk.
If you use an existing ConfigurationDesk project and update the FPGA custom
function of Release 2022-A with a newer FPGA custom function, the existing
FPGA scope raster (<application>_usr.trc) causes an error.

Note

Before you update the existing FPGA custom function in ConfigurationDesk

with a new FPGAC file, delete the <application>_usr.trc file in the
model folder. ConfigurationDesk shows the location of the model.

Changed interface to modify analog output signals FPGA scaling lets you
modify analog output signals. As of Release 2022-B, the interface scales the
signal values that are replaced with FPGA test access.
The following illustration shows the analog output interface. For more
information on FPGA test access and scaling, refer to Basics on FPGA Test Access
and Scaling on page 248.

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Analog output
I/O logic
channel
Scaling
FPGA test access Saturation
and offset

FPGA_IO_WRITE_BL

Up to Release 2022-A, the interface scales signal values first and then you can
replace the scaled values with FPGA test access.

Bus In blocks replace Buffer64 blocks As of RTI FPGA Programming

Blockset 3.12, the Bus In/Bus Out blocks for the MicroAutoBox III/SCALEXIO
frameworks replace the transfer mode of the Buffer64 In/Buffer64 Out blocks.
The update process automatically replaces the Buffer64 In/Buffer64 Out blocks
that use the bus transfer mode with Bus In/Bus Out blocks.

Renaming of bus data transmission method As of FPGA Programming

Blockset 23-A, the Synchronous to Read_Req method is named Synchronous
to task method. The functionality does not change.

Rework necessary when migrating MGT In blocks Up to Release 2022-B,

the MGT In block provides an Opto_Ready port. As of Release 2023-A, the
MGT In Opto Ready blocks provides the Opto_Ready port, because the signal
of the Opto_Ready port cannot be provided in a user clock domain.
After migration, you have to manually replace the MGT In block of the previous
framework with a MGT In Opto Ready block and a MGT In block of the
current framework.

Migrating to Different FPGA Hardware

Introduction The FPGA Programming Blockset supports different dSPACE FPGA boards and
hardware platforms. If you want to use an existing FPGA model on another
platform, it might be not sufficient to select the hardware-specific framework.
Some modifications are required.

Intended use cases The automatic migration mechanism is intended primarily to migrate from one
framework to another framework of the same platform:
§ From one SCALEXIO FPGA base board framework to another. For example:
§ From the DS2655 (7K160) FPGA Base Board framework to the DS2655
(7K410) FPGA Base Board framework.
§ From the DS2655 (7K160) FPGA Base Board framework to the DS6601
(KU035) FPGA Base Board framework.

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Tip

All FPGA models of the DS2655 (7K160) FPGA Base Board framework can
be migrated to the DS6601 (KU035) FPGA Base Board/DS6602 (KU15P)
FPGA Base Board frameworks. The DS6601 and DS6602 FPGA base
boards are compatible and provide more FPGA resources.
However, you have to use the same I/O modules and to consider the I/O
slot assignments.

§ From FPGA1401Tp1 (7K325) with Multi-I/O Module (DS1552) framework to

FPGA1401Tp1 (7K325) with Multi-I/O Module (DS1552B1) framework.
§ From FPGA1403Tp1 (7K325) with Multi-I/O Module (DS1552) framework to
FPGA1403Tp1 (7K325) with Multi-I/O Module (DS1552B1) framework.
§ From FPGA1401Tp1 (7K325) with Multi-I/O Module (DS1552) framework
(MicroAutoBox II) to FPGA1403Tp1 (7K325) with Multi-I/O Module (DS1552)
framework (MicroAutoBox III).
§ From FPGA1401Tp1 (7K325) with Multi-I/O Module (DS1552B1) framework
(MicroAutoBox II) to FPGA1403Tp1 (7K325) with Multi-I/O Module
(DS1552B1) framework (MicroAutoBox III).
The automatic migration also works for the migration from one platform to
another, for example from MicroLabBox to MicroAutoBox, but their I/O functions
have no or only little compatible compliances.

Migrating FPGA models Note

§ Before you start a migration, you should make a backup of your model.
§ To build and run a migrated FPGA model, the new FPGA board must have
sufficient FPGA resources.

If you switch to another framework, the framework migration process is started:

1. A dialog opens that lists all the blocks in your model that might be
incompatible.
2. Then, a second dialog opens in which you have to confirm the migration.
3. If the migration is running, the compatible blocks in the model are replaced
and parameterized again.
Differently parameterized or renamed blocks will not be replaced.
4. If the migration is finished, a dialog opens that lists the incompatible blocks
that you have to replace manually.

The parameterization of the found incompatible blocks is empty. You are not
able to reparameterize the blocks concerning the selected framework. While
you have not replaced the incompatible blocks, you can switch back to the
framework used for the configuration to reset the block parameters to their
former values.

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Updating FPGA Models with Settings of FPGA Custom

Functions
Introduction You can update your FPGA model with imported parameter settings of an FPGA
custom function in ConfigurationDesk.

How to Update FPGA Models with Imported Parameter Settings

Objective If you add a FPGA application as FPGA custom function block to

ConfigurationDesk, you can import changed settings of analog channels to
update the FPGA model.

Preconditions The following preconditions must be fulfilled:

§ The FPGA application is build and added to ConfigurationDesk as an FPGA
custom function block.
§ The blocks of the FPGA Programming Blockset are not moved to other I/O
channels.

Method To update FPGA models with imported parameter settings

1 Double-click the FPGA_SETUP_BL block and open the Interface tab.
2 Select the ConfigurationDesk project from which you want to import the
parameter settings.

Tip

Click Refresh to import the list of recent projects from

ConfigurationDesk. If needed, the FPGA Programming Blockset opens
ConfigurationDesk to refresh the list.

3 Click Import ADC/DAC Scaling Parameters.

The FPGA Programming Blcokset opens the ConfigurationDesk project to
import the parameters settings.
If several instances of the FPGA custom function are instantiated, the Select
dialog opens.
4 If the Select dialog opens, select the FPGA custom function from which you
want to import the parameter settings and click OK.

Result The framework analyzes the FPGA custom function and imports the FPGA
parameter settings. At the end of the import process, the FPGA Update dialog
opens. The dialog displays the settings that have been updated.

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Related topics Basics

Accessing the FPGA Application with the Experiment Software (ConfigurationDesk

I/O Function Implementation Guide )
Basics on FPGA Test Access and Scaling.................................................................................. 248

Adapting Existing FPGA Models to be Used on dSPACE

Hardware
Introduction To integrate an FPGA application based on the HDL library of the AMD Vitis
Model Composer into a dSPACE system, you must replace certain blocks with
blocks from the FPGA Programming Blockset.

Where to go from here Information in this section

Replacing the Functionality of the System Generator Block...................... 46

The functionality of the System Generator block must be replaced by the
FPGA_SETUP block.

Replacing Gateway Blocks....................................................................... 47

Gateway In/Out blocks in the FPGA model must be replaced by blocks
from the FPGA Interface library.

Replacing the Functionality of the System Generator Block

Introduction The System Generator setup block remains in the FPGA model, but all the
settings for the setup functionality are specified in the FPGA_SETUP_BL block

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(it is assumed that you do not use System Generator blocks in various model
hierarchies).

Setup block in the FPGA The FPGA_SETUP_BL block assumes control about the blocks used in the FPGA
subsystem model.

Specifying the framework Before you can configure the blocks from the
FPGA Programming Blockset in your FPGA subsystem, you must specify the FPGA
hardware to be used.

Executing model actions The FPGA_SETUP_BL block can be used to start

several AMD Design Tools without leaving your dSPACE environment. For
example:
§ Building the FPGA application. Refer to Building FPGA and Processor
Applications on page 185.
§ Analyzing the FPGA model, for example, analyzing of the timing behavior.
Refer to Simulating and Debugging Processor and FPGA Applications on
page 173.

Tracing FPGA signals You can activate the tracing of FPGA signals and
tuning of FPGA constants at run time. Refer to Using Multiple Clock Domains
for FPGA Modeling on page 78.

Using multiple clock domains You can specify subsystems that are
processed with different clock periods. Refer to Using Multiple Clock Domains
for FPGA Modeling on page 78.

Replacing Gateway Blocks

Introduction Gateway In/Gateway Out blocks from the HDL library of the AMD Vitis Model
Composer must be replaced by blocks from the FPGA Interface library.

AMD Gateway blocks The Gateway blocks provide the interface between the Simulink inports and
outports and the signals processed within the FPGA model.

A Gateway In block provides an inport to your FPGA model. It converts Simulink

integer, double and fixed-point data types into the AMD Vitis Model Composer
fixed-point data type.

A Gateway Out block provides an outport from your FPGA model. It converts
the AMD Vitis Model Composer fixed-point data type into the Simulink double
data type.

Reading a signal with FPGA If the FPGA model reads a signal, you usually have a Simulink Inport block
Interface blocks followed by a Gateway In block that realizes the specified data type conversion.

If the input signal comes from the processor model, you must replace the
Gateway In block with an FPGA_XDATA_READ_BL block. The Simulink Inport

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block must also be removed because the counterpart in the processor model
(PROC_XDATA_WRITE_BL block) communicates with the FPGA block without a
signal line.

The replaced blocks from the FPGA Interface library also implement the
necessary data type conversion.

If the input signal comes from an external hardware signal, you must replace
the Gateway In block with an FPGA_IO_READ_BL block. The Simulink Inport
block must also be removed because it is no longer required. The configuration
of the block depends on the signal type, for example, on whether the hardware
delivers an analog or digital input signal.

Writing a signal with FPGA If the FPGA model writes a signal, you usually have a Gateway Out block that
Interface blocks realizes the specified data type conversion, followed by a Simulink Outport.

If the output signal is to be written to the processor model, you must replace
the Gateway Out block with an FPGA_XDATA_WRITE_BL block. The Simulink
Outport must also be removed because the counterpart in the processor model
(PROC_XDATA_READ_BL block) communicates with the FPGA block without a
signal line.

The replaced blocks from the FPGA Interface library also implement the
necessary data type conversion.

If the output signal is used for an external hardware signal, you must replace the
Gateway Out block with an FPGA_IO_WRITE_BL block. The Simulink Outport
must also be removed because it is no longer required. The configuration of the
block depends on the signal type, for example, on whether the hardware expects
an analog or digital output signal.

Related topics Basics

Implementing the Processor Interface to the Processor Model................................................. 148

Modeling External I/O Access.................................................................................................... 73
Replacing the Functionality of the System Generator Block....................................................... 46

Resetting FPGA Models

Resetting the Block Parameters to the Initial Values

Introduction With the script interface, you can reset the block parameters of the FPGA
framework to the initial values.

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Resetting to the initial values The FPGA Programming Blockset provides a script interface that you can use
to reset the block parameters of the FPGA framework to the initial values by
executing the FPGAFrameworkUpdate script function in the MATLAB Command
Window.
rtifpga_scriptinterface('FPGAFrameworkUpdate',
<SimulinkHandle>, 'ReInit')

The script considers all subsystems that are contained in the model/subsystem
which is specified by the Simulink handle. The parameters of the blocks are reset
to the initial values.

Example: The following script will reset the FPGA framework for any FPGA
subsystems found in the processor model that is called MyProcModel. The
specified values of the block parameters will be set to the initial values.
ProcModelHandle = get_param('MyProcModel','handle')
rtifpga_scriptinterface('FPGAFrameworkUpdate',
ProcModelHandle,'ReInit')

Related topics References

FPGAFrameworkUpdate (FPGA Programming Software Script Interface

Reference )

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Modeling Aspects and Implementation Workflow

Introduction Introduces to the features of the FPGA Programming Blockset and how you
implement an FPGA application.

Where to go from here Information in this section

Features of the FPGA Programming Blockset............................................ 51

The FPGA Programming Blockset provides dynamically configured dialog
settings and an interface to some development features of the AMD Vitis
Model Composer Blockset.

Modeling Aspects.................................................................................... 54
Describes general modeling aspects that have no particular context.

Typical Workflow for FPGA Modeling....................................................... 57

Describes the typical workflow to implement an FPGA application
graphically by using the FPGA Programming Blockset.

Features of the MicroLabBox Flexible I/O Framework................................ 61

The DS1202 FPGA IO Type 1 (Flexible I/O) framework lets you model
real-time application with the FPGA Programming Blockset together with
the RTI1202 and EMC blocksets.

Workflow when Using MicroLabBox Flexible I/O Framework.................... 62

The compatibility of the MicroLabBox frameworks lets you save time
when you model and test the FPGA application.

Features of the FPGA Programming Blockset

Introduction The FPGA Programming Blockset provides dynamically configured dialog settings
and an interface to some development features of the AMD Vitis Model
Composer Blockset.

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Supported third party For modeling the FPGA functionality, the following third-party blockstes are
blocksets supported:
§ The AMD Vitis Model Composer Blockset.
The AMD Vitis Model Composer Blockset is a Simulink block library that lets
you graphically model FPGA applications. The AMD Vitis Model Composer
Blockset requires a separate license.
The FPGA Programming Blockset supports only the HDL library of the AMD
Vitis Model Composer.
§ Simulink blocks to model parts of the FPGA model.
To use Simulink blocks, the Mathworks HDL Coder is required and
the used Simulink blocks must be supported by the HDL Coder.
Refer to https://www.mathworks.com/help/comm/ug/find-blocks-and-system-
objects-supporting-hdl-code-generation.html.
The use of Simulink blocks to model parts of the FPGA model requires
special handling, refer to How to Use Simulink Blocks for Modeling the FPGA
Functionality on page 68.

Hardware-specific settings You can specify the hardware to be used in the block dialog of
the FPGA_SETUP_BL block. After you selected the hardware, the FPGA
Programming Blockset loads the hardware-specific framework. The framework
provides the following interfaces:
§ Communication with the real-time processor via the hardware-specific bus,
such as IOCNET.
§ Access to the I/O channels of the FPGA board.
§ Interrupt handling.

The following illustration shows the features of a framework.

FGPA
IOCNET

ADC unit
dSPACE
User application framework DAC unit

Digital I/O unit

Frame work ID and
configuration data

Function-specific settings The block dialogs have several pages. The Parameters and the Description
pages are empty until you select a function by specifying the access type for
board communication or specifying the I/O type for an I/O access on the Unit
page of a block dialog. These pages are dynamically filled with text and settings
according to the selected function.

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Flexible signal handling To model data exchange via the external I/O pins,
you must only add the I/O block for a specific access direction (read or write)
to the model. The signal type (analog or digital) can be configured in the block
dialog. The availability of the signal types depends on the selected framework.

Interaction with the AMD If you implemented the required functionality of the FPGA application by using
Vitis Model Composer the HDL library of the AMD Vitis Model Composer only, you have direct access
to all its features for configuring, debugging and building the application. If you
want to integrate the FPGA model in a dSPACE system, certain blocks of the
HDL library must be replaced by blocks from the FPGA Programming Blockset.
Most of the above-mentioned features are now available indirectly by using the
blocks from the FPGA Programming Blockset, for example, the timing analysis for
debugging purposes.

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Modeling Aspects

Introduction Describes general modeling aspects that have no particular context.

General notes Code generation and the build process are managed by the FPGA Programming
Software. The software uses the AMD Vitis Model Composer to generate
VHDL code and starts the Vivado implementation process, including synthesis,
mapping, routing, and generating the bitstream file.

Notes on the build process The effort required to successfully place and
route an FPGA model increases with the FPGA model content. Starting with an
FPGA utilization of approx. 70%, the probability that an FPGA model cannot
be placed and routed increases exponentially. High FPGA utilization can lead
to unpredictable build aborts. Even the smallest change can lead to an abort.
Therefore, dSPACE recommends to leave enough FPGA resources for changes in
the FPGA model, libraries, or dSPACE FPGA framework.
There are several aspects that determine whether an FPGA model can be
successfully placed and routed. These include:
§ The effectiveness of optimization methods during the build process. The
performance of different versions of the AMD Design Tools increases in
general, but optimizing most FPGA models can impair the performance of
a specific FPGA model.
§ The design of the FPGA model itself:
§ Used libraries might be changed and need more FPGA resources.
§ The FPGA model cannot be mapped to the FPGA architecture efficiently.
For more information, refer to Measuring Device Performance and Utilization: A
Competitive Overview (https://docs.xilinx.com/v/u/en-US/wp496-comp-perf-util)
and UG906 Design Analysis and Closure Techniques (https://docs.xilinx.com/r/en-
US/ug906-vivado-design-analysis).

Notes on the build results Even if no errors occurred during modeling,

simulating, and building, your FPGA application is not guaranteed to work
correctly. Some combination of factors might prohibit the execution of your
FPGA application, e.g., combinations of the operating temperature, the power
of the entire hardware system, technological limitations of the FPGA, the sample
rate, etc. Some FPGA applications do not start at all, others start correctly but fail
during operation.
Due to the complexity of FPGA applications and their dependency on the used
FPGA hardware, the AMD Design Tools cannot ensure that all possible design
problems are detected during the analysis and simulation of the FPGA model.
To solve the problem, you have to modify the FPGA model and make sure that
you consider generally accepted FPGA design rules to ensure a stable and reliable
FPGA application (refer to Audience profile on page 9). For more information,
contact dSPACE Support.

One subsystem for one FPGA The FPGA application which you implement for one FPGA board must be
board encapsulated in a Simulink subsystem. If the dSPACE hardware provides several

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FPGA boards, you must provide a subsystem for each FPGA board you want to
use.

Each subsystem must contain an FPGA_SETUP_BL block in the root element.

Assignment of the FPGA boards The assignment of a subsystem to an

FPGA board depends on the used dSPACE hardware:
§ MicroLabBox II, MicroAutoBox III, and SCALEXIO systems: The assignment of a
subsystem to an FPGA board is done in ConfigurationDesk.
§ MicroAutoBox II and MicroLabBox: The assignment a subsystem to the FPGA
board is done in the PROC_SETUP_BL block of the processor model.

Name of the FPGA application You can specify the name of the FPGA application via the dialog of the
FPGA_SETUP_BL block. The name is used as a description for the built
FPGA application and can be displayed in your experiment software, such
as ControlDesk. For MicroLabBox II, MicroAutoBox III, and SCALEXIO systems,
the FPGA application name is used as the custom function block type in
ConfigurationDesk.

By default, the name of the subsystem is automatically used as the first part of
the application name when you build the FPGA application.

Tip

If you use the same FPGA application name for variants of the FPGA model
for the MicroLabBox II, MicroAutoBox III, or SCALEXIO systems, all the
variants have the same custom function block type. This helps you reuse
FPGA variants in ConfigurationDesk, because you can exchange the FPGA
application without changing the custom function block in the signal chain.

Implementing data exchange Application data that you want to process in the processor model or other
between FPGA application subsystems of your Simulink model must be exchanged via the board-specific
and processor application bus.

You implement the data exchange between the processor application and the
FPGA application by generating processor interface blocks which uses the blocks
from the FPGA Programming Blockset's Processor Interface library.

Note

If the FPGA application supports SCALEXIO multicore processor applications,

implement the FPGA interface blocks to the subsystems of your FPGA model
in a way that a subsystem always exchange data with the same processor
model. Refer to Aspects on FPGA Applications Supporting Multicore
Processor Applications on page 117.

Preprocessing and postprocessing of processor signals The

MicroLabBox II, MicroAutoBox III, and SCALEXIO blocksets support scaling
subsystems that are part of the FPGA model. Scaling subsystems let you
preprocess and postprocess the signals between the FPGA model and the

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processor model. For more information, refer to Basics on Preprocessing and

Postprocessing the Processor Communication on page 156.

Synchronizing FPGA data If different data paths have different length, the data is valid at different points
in time and the outputs are asynchronous. This might cause an unexpected
behavior of your application.

For more information, refer to Timing in FPGA Designs (FPGA Programming

Blockset Getting Started ).

Modeling FPGA tasks with You can set multiple clock domains inside one FPGA model to adapt the clock
individual clock periods period of specific parts of your FPGA application to your requirements.

For instructions, refer to Using Multiple Clock Domains for FPGA Modeling on
page 78.

Methods to access the FPGA You can enable access to the FPGA application with your experiment software
application via experiment when the FPGA application runs on the platform.
software
The following methods to trace and tune FPGA signals are supported:
§ FPGA signal tracing.
§ SCALEXIO systems only: Scope for FPGA signals.
§ Tunable FPGA constants.
§ FPGA test access.
§ FPGA scaling:
§ Scaling of analog I/O signals.
§ Inverting digital I/O signals.
§ Inverting RS232/485 signals.

For more information, refer to Accessing FPGA Applications with your

Experiment Software on page 233 and Displaying FPGA Signals in ControlDesk
on page 256.

Modifying models for If you use a MicroLabBox II, MicroAutoBox III, or a SCALEXIO system, you should
a MicroLabBox II, modify the FPGA model or the processor model only in the entire model. If you
MicroAutoBox III, or a export the FPGA build results and the processor model to a ConfigurationDesk
SCALEXIO system project, the project will automatically be updated. You cannot update the entire
model to updates that are done outside of it. Refer to How to Export Build
Results and Processor Models to ConfigurationDesk Projects on page 191.

If you do not use the export functionality, you have to update the model
modifications in ConfigurationDesk.

Related topics Basics

Typical Workflow for FPGA Modeling........................................................................................ 57

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Typical Workflow for FPGA Modeling

Introduction When you use the FPGA Programming Blockset, there is a typical workflow
which you can follow.

Graph of the workflow The following image shows the workflow that branches for SCALEXIO and
non‑SCALEXIO platforms for integrating the built FPGA application in the
processor application.

For a description of the working steps, refer to:

§ Workflow when using a MicroLabBox II, MicroAutoBox III, or SCALEXIO system
on page 58
§ Workflow when using a MicroAutoBox II or a MicroLabBox on page 60
or

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Specify the framework via

FPGA_SETUP block

Implement the FPGA functionality

Specify the FPGA interface

Simulate the FPGA model and optimize it

SCALEXIO, MicroAutoBox III, MicroAutoBox II, MicroLabBox,

MicroLabBox II and IOCNET-based system

Build the FPGA application

Implement the processor model interface

Specify the processor model interface

Simulate the entire model and optimize it

Configure the build settings in the

Build the FPGA application PROC_SETUP block

Build the processor application via

Export to ConfigurationDesk Simulink Coder

Build the processor application Simulate

Experiment

Workflow when using It is assumed that you start with a new empty Simulink model.
a MicroLabBox II, 1. Create at least two subsystems in the Simulink model:
MicroAutoBox III, or § A subsystem for the processor model that is executed on the processor
SCALEXIO system board.
§ One subsystem for each FPGA board that you want to use with your
processor model.
2. Implement the FPGA functionality. Refer to Modeling FPGA Functionality on
page 67.

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Do not use the Gateway In and the Gateway Out blocks in the subsystem.
If you use an existing FPGA model, you have to replace the Gateway In and
Gateway Out blocks with blocks from the FPGA Programming Blockset.
3. Specify the interface of the FPGA.
You must firstly add the FPGA_SETUP_BL block to the FPGA subsystem
and specify general settings such as the framework and the I/O modules
to be used with the block's dialog. Then you can add the required blocks
from the FPGA Programming Blockset to the FPGA subsystem to implement
read/write access to external I/O and to exchange data with the behavior
model.

Note

Do not open and update the System Generator block added by

the FPGA Programming Blockset. The update process will migrate the
System Generator block to the Vitis Model Composer Hub block
that is not compatible to the FPGA Programming Blockset.

For more information on specifying the interfaces, refer to Modeling External

I/O Access on page 73 and Modeling Processor Model Access on page 130.
4. Simulate the behavior of the FPGA subsystem.
You can use the simulation ports of the FPGA Interface blocks to stimulate
the FPGA subsystem or to view the outputs in an offline simulation. You
can also execute a timing analysis by using the Timing Analyzer to check
whether required timing constraints can be met. For further information,
refer to Simulating an FPGA Subsystem on page 174.
5. Generate the corresponding processor interface blocks for the processor
model and add them to the subsystem of the processor model. For further
information, refer to Implementing the Processor Interface to the Processor
Model on page 148.
6. Add further blocks to the processor model to implement the required
functionality on the processor side.
7. Simulate the entire model in Simulink simulation mode. For further
information, refer to Simulating a Processor Model on page 175.
8. Build the FPGA application from the FPGA subsystem.
You can start the build process for the FPGA subsystem in the
FPGA_SETUP_BL block. The AMD Vitis Model Composer and the Vivado
compiler are used to generate the FPGA application. For further information,
refer to How to Build FPGA Applications (MicroLabBox II, MicroAutoBox III,
SCALEXIO) on page 186.
9. Export the FPGA application and the processor model to ConfigurationDesk.
For further information, refer to How to Export Build Results and Processor
Models to ConfigurationDesk Projects on page 191.
10. Configure the signal properties in your instantiated FPGA function, for
example, the electrical characteristics. For further information, refer to
Configuring Function Blocks (ConfigurationDesk Real-Time Implementation
Guide ).
11. Build the processor application using ConfigurationDesk. For further
information, refer to How to Build Processor Applications (MicroLabBox II,
MicroAutoBox III, SCALEXIO) on page 193.

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12. Execute the entire model on the real-time hardware for experimenting. For
further information, refer to Experimenting with an FPGA Application on
page 229.

Workflow when using a It is assumed that you start with a new empty Simulink model.
MicroAutoBox II or a 1. Create a subsystem in the Simulink model.
MicroLabBox There must be always a root model that is executed on the processor board
and one FPGA subsystem for each FPGA board that you want to use for your
processor application.
2. Implement the desired FPGA functionality. Refer to Modeling FPGA
Functionality on page 67.
Do not use the Gateway In and the Gateway Out blocks in the subsystem.
If you use an existing FPGA model, you have to replace the Gateway In and
Gateway Out blocks with blocks from the FPGA Programming Blockset.
3. Specify the interface of the FPGA
You must first add the FPGA_SETUP_BL block to the FPGA subsystem and
specify general settings such as the framework to be used with the block's
dialog. Then you can add the required blocks from the FPGA Programming
Blockset to the FPGA subsystem to implement read/write access to external
I/O and to exchange data with the processor model.

Note

Do not open and update the System Generator block added by

the FPGA Programming Blockset. The update process will migrate the
System Generator block to the Vitis Model Composer Hub block
that is not compatible to the FPGA Programming Blockset.

For more information on specifying the interfaces, refer to Modeling External

I/O Access on page 73 and Modeling Processor Model Access on page 130.
4. Simulate the behavior of the FPGA subsystem.
You can use the simulation ports of the FPGA Interface blocks to stimulate
the FPGA subsystem or to view the outputs in an offline simulation. You can
also execute a timing analysis using the Timing Analyzer to check whether
required timing constraints can be met. For further information, refer to
Simulating an FPGA Subsystem on page 174.
5. Build the FPGA application from the FPGA subsystem.
You can start the build process for the FPGA subsystem in the
FPGA_SETUP_BL block. The AMD Vitis Model Composer and the Vivado
compiler are used to generate the FPGA application. For further information,
refer to How to Build FPGA Applications (MicroAutoBox II, MicroLabBox) on
page 195.
6. Add a PROC_SETUP_BL block to the processor model and use it to create
the interface blocks required for communication with the FPGA subsystem.
For further information, refer to Implementing the Processor Interface to the
Processor Model on page 148.
7. Add further blocks to the processor model to implement the required
functionality on the processor side.
8. Build the processor application by using the PROC_SETUP_BL block.

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You can integrate the programming of the FPGA into the processor
application or generate a separate burn application to integrate the
programming. For further information, refer to How to Build Single-Core
Processor Applications (MicroAutoBox II, MicroLabBox) on page 200 and
How to Create Burn Applications for MicroAutoBox II on page 203.
9. Simulate the entire model in Simulink simulation mode or execute it on
the real-time hardware for experimenting. For further information, refer to
Simulating a Processor Model on page 175 and Experimenting with an FPGA
Application on page 229.

Related topics Basics

Building FPGA and Processor Applications.............................................................................. 185

Implementing the Processor Interface to the Processor Model................................................. 148
Modeling the FPGA Functionality and the Access to I/O Channels............................................. 65
Simulating and Debugging Processor and FPGA Applications.................................................. 173

Features of the MicroLabBox Flexible I/O Framework

Introduction The DS1202 FPGA IO Type 1 (Flexible I/O) framework lets you model real-time
applications for MicroLabBox together with the RTI1202 and the RTI Electric
Motor (EMC) blocksets.

An I/O channel of MicroLabBox is either used by the standard I/O features of

MicroLabBox or by a custom FPGA application. The standard I/O features of
MicroLabBox let you access the I/O interface with the RTI1202 and the EMC
blocksets. These features are automatically implemented into the FPGA if the
real‑time application that you load to the hardware does not contain a custom
FPGA application. Custom FPGA applications that are built with the DS1202
FPGA I/O Type 1 framework do not provide the standard I/O features for
remaining I/O channels. Therefore, you cannot access the remaining I/O channels
with the RTI1202 and the EMC blocksets.

Features of the DS1202 FPGA The framework provides the following features:
I/O Type 1 (Flexible I/O) § During the build process of the custom FPGA application, the standard I/O
framework features for remaining I/O channels are added. The standard I/O features let
you use the remaining I/O channels with the RTI1202 and the EMC blocksets.
§ The framework provides the same blocks as the DS1202 FPGA I/O Type 1
framework.
§ The framework is compatible with the DS1202 FPGA I/O Type 1 framework.
You can switch between the DS1202 FPGA I/O Type 1 (Flexible I/O) and the
DS1202 FPGA I/O Type 1 frameworks. The compatibility lets you save time
when you model and test the the FPGA application. Refer to Workflow when
Using MicroLabBox Flexible I/O Framework on page 62.

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§ I/O channels that are used by the DS1202 FPGA I/O Type 1 (Flexible I/O)
framework are marked within the RTI1202 and the EMC blocksets with an
asterisk.

You must not access the same channel with the DS1202 FPGA I/O Type 1
(Flexible I/O) framework and the RTI1202 or EMC blocksets.

Note

The DS1202 Serial Interface blocks (rti1202serlib) do not mark I/O

channels that are used by the custom FPGA application with an asterisk.
§ If you use DS1202 Serial Interface blocks, make sure that the custom
FPGA application does not use the same communication channels.

Related topics Basics

Overview of the RTI Electric Motor Control Blockset (RTI Electric Motor Control
Blockset Reference )

References

Overview of RTI1202 (MicroLabBox RTI Reference )

Workflow when Using MicroLabBox Flexible I/O Framework

Introduction Building FPGA applications with the DS1202 FPGA I/O Type 1 framework is
substantially faster than building FPGA applications with the DS1202 FPGA
I/O Type 1 (Flexible I/O) framework. The implementation of the standard I/O
features, which let you use the remaining I/O channels with the RTI1202 and the
EMC blocksets, takes additional FPGA resources and more build time.

The compatibility of the frameworks lets you use the DS1202 FPGA I/O Type 1
framework for modeling and testing and the DS1202 FPGA I/O Type 1 (Flexible
I/O) framework for building the final FPGA application including the standard I/O
features for the remaining I/O channels.

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Recommended workflow 1. Model, test, and build the FPGA application with the DS1202 FPGA I/O
Type 1 framework until you have the final version.
2. Open the FPGA SETUP BL dialog and select the DS1202 FPGA I/O Type 1
(Flexible I/O) framework.
A Framework Incompatibilities confirmation prompt and a Framework
Upgrade confirmation prompt are displayed. Confirm both prompts.
3. Build the final FPGA application. Refer to How to Build FPGA Applications
(MicroAutoBox II, MicroLabBox) on page 195.
4. Generate the processor interface for the processor model. Refer to How to
Generate a Processor Interface on page 148.
5. Use the RTI1202 and the EMC blocksets to access the remaining I/O
channels. Refer to MicroLabBox RTI Reference and RTI Electric Motor
Control Blockset Reference .
6. Build the processor application. Refer to How to Build Single-Core Processor
Applications (MicroAutoBox II, MicroLabBox) on page 200.
The build process makes sure that no I/O channel is accessed multiple times,
for example, by the FPGA application and the processor application.
7. Download the application to MicroLabBox.

Modifying the FPGA I/O The DS1202 FPGA I/O Type 1 (Flexible I/O) framework cannot display whether
interface an I/O channel is already used by a processor application. If you modify the FPGA
I/O interface, you must ensure that no I/O channel is used multiple times.

Related topics Basics

Features of the MicroLabBox Flexible I/O Framework................................................................. 61

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Modeling the FPGA Functionality and the Access to

I/O Channels

Introduction The FPGA Programming Blockset is a Simulink blockset for using an FPGA model
created with the AMD Vitis Model Composer Blockset on a dSPACE FPGA board.

Where to go from here Information in this section

Modeling FPGA Functionality................................................................... 67

Aspects on modeling the FPGA functionality with the HDL library of the
AMD Vitis Model Composer.

Modeling External I/O Access................................................................... 73

The FPGA Programming Blockset provides blocks for reading from input
channels and writing to output channels of the FPGA board.

Using Multiple Clock Domains for FPGA Modeling................................... 78

You can implement FPGA functionality that is processed with different
clock periods.

Using a Watchdog................................................................................... 86
Implementing a watchdog to check if the processor application is alive.

Modeling DDR4 RAM Access................................................................... 90

The FPGA Programming Blockset provides blocks to implement a
communication interface for the DDR4 RAM of the DS6602.

Modeling UART Communication............................................................. 95

The FPGA Programming Blockset provides blocks to implement an UART
communication interface.

Modeling Inter-FPGA Communication...................................................... 99

An inter-FPGA communication bus lets you exchange data directly
between FPGA boards.

Modeling FPGA Applications Supporting Multicore Processor

Applications.......................................................................................... 117
Aspects you have to consider when you model an FPGA application with
multicore support.

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Modeling MGT Communication Using a Customized Protocol............... 123

A demo project (Aurora 8b10b demo) for SCALEXIO systems shows how
to implement a customized protocol.

Information in other sections

Accessing FPGA Applications with your Experiment Software........ ........ 233

You can build FPGA applications that provide access to FPGA signals and
constants with your experiment software.

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Modeling FPGA Functionality

Introduction Aspects on modeling the FPGA functionality with the HDL library of the AMD
Vitis Model Composer.

Where to go from here Information in this section

Implementing the FPGA Functionality...................................................... 67

Aspects on the support of the FPGA Programming Blockset to implement
the FPGA functionality with blocks of the HDL library of the AMD Vitis
Model Composer.

How to Use Simulink Blocks for Modeling the FPGA Functionality............ 68

Using existing Simulink models directly as part of your FPGA application.

Notes on Using Multicycle Paths.............................................................. 71

Solving timing problems of DSPs in down-sample paths.

Implementing the FPGA Functionality

Modeling the functionality Note

Modeling the FPGA functionality has an significant impact on the resulting

timing performance, utilization grade, and the overall FPGA system
reliability. Therefore, consider the generally accepted FPGA design rules to
ensure a stable and reliable FPGA application.

You model the FPGA functionality with blocks of the HDL library of the AMD
Vitis Model Composer. Alternatively, you can use Simulink blocks. Refer to Using
Simulink blocks for FPGA modeling on page 68.

The FPGA interface to the board-specific bus and I/O channels is provided by the
FPGA Programming Blockset. Do not use the Gateway In and Gateway Out
blocks of the AMD Vitis Model Composer blockset. For more information on
the HDL library of the AMD Vitis Model Composer, refer to the AMD user
documentation.

The dSPACE FPGA boards provide multiple clock domains for modeling specific
parts of your FPGA design with an individual clock period. For instructions, refer
to How to Use Multiple Clock Domains for FPGA Modeling on page 81.

Reusing existing FPGA models You can adapt existing FPGA models based on the HDL library of the AMD
Vitis Model Composer to use them on the dSPACE hardware. Refer to Adapting
Existing FPGA Models to be Used on dSPACE Hardware on page 46.

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Using Simulink blocks for The FPGA Programing Blockset supports subsystems in the FPGA model that
FPGA modeling are modeled with Simulink blocks (HDL coder subsystems). This feature lets you
directly use existing Simulink models in your FPGA application. For example: You
can use a Simulink model of a controller for first functionality tests before you
optimize the FPGA utilization of the controller.

The use of Simulink blocks to model parts of the FPGA model requires
special handling, refer to How to Use Simulink Blocks for Modeling the FPGA
Functionality on page 68.

Note on modeling with AMD If you use Black Box blocks from the AMD Toolbox to incorporate hardware
Black Box blocks description language models, the files of the incorporated models must be
located in special folders before you start the FPGA build process. The following
table lists the folders that you can use.

Folder Supported Files of Incorporated Models

Model root folder All files with the following file extensions are supported during the build
of the FPGA model process: .vhdl, .vhd, .v, .dcp, .ncg, .ncd, .edit, .edf, .m, and .slx.
The files must not be located in a subfolder
/Includes All file types are supported during the build process. You can also use subfolders.
subfolder in the Before you start the build process, the Includes subfolder and optional subfolders must be
model root folder added to the MATLAB search paths as relative paths. For example: addpath('.\Includes').

The special folders are mandatory for the build process, because the FPGA
Programming Blockset automatically copy all files to the build folder before the
build starts. If the files are outside the given folders, they are not available for the
build process.

Related topics Basics

Modeling External I/O Access.................................................................................................... 73

Modeling Processor Model Access.......................................................................................... 130

HowTos

How to Use Simulink Blocks for Modeling the FPGA Functionality............................................. 68

How to Use Simulink Blocks for Modeling the FPGA Functionality

Objective Using subsystems based on Simulink blocks (HDL coder subsystems) to model
parts of the FPGA model.

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Basics The FPGA Programming Blockset provides gateway blocks to use Simulink
models directly as part of your FPGA model. The gateway blocks transfer the
signals and buses between the separated model parts.

During the build process, the following tools generate the HDL code:
§ The MathWorks© HDL CoderTM generates the VHDL code from blocks of the
Simulink blockset.
§ The AMD Vitis Model Composer generates the VHDL code from blocks of the
HDL library of the AMD Vitis Model Composer and the FPGA Programming
Blockset.

The build process merges the individual VHDL codes into a synthesizable overall
model. Using MathWorks HDL coder does not affect the MATLAB compatibility
of the FPGA Programming Blockset, because only parts of the FPGA model can
be modeled with Simulink blocks.

Demo The DemoHDLCoder model shows how to use the gateway blocks. Double-click
the Demo button in the blockset to open the library containing the demo
models.

Preconditions The following preconditions must be fulfilled:

§ The MathWorks HDL Coder must be installed.
§ The used Simulink blocks must be supported by the HDL Coder.
Refer to https://www.mathworks.com/help/comm/ug/find-blocks-and-system-
objects-supporting-hdl-code-generation.html.

Method To use Simulink blocks for modeling the FPGA functionality

1 Add the Simulink blocks to a subsystem to create an HDL coder subsystem.
2 From the FPGA Interface sublibrary of the FPGA Programming Blockset,
connect the Intramodel Out blocks to all inputs of the HDL coder
subsystem.

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The following illustration shows you an example with a Simulink bus and
two signals as inputs.

3 Connect the Intramodel In blocks to all outputs of the HDL coder

subsystem.
4 Make sure that the following items are all met so that the FPGA
Programming Blockset can differ between the different parts of the FPGA
model:
§ All input and output signals of the HDL coder subsystem pass through the
intramodel blocks.
§ The intramodel blocks are directly connected to the HDL coder subsystem.
There are no other blocks in between.
5 Press Ctrl + D to update the diagram. The intramodel blocks adapt their
signal/bus types to the connected input signal/bus types.

6 Repeat steps 1 to 5 to add more HDL coder subsystems.

Result You implement HDL coder subsystems.

When you start the build process, the process automatically detects the different
parts of the FPGA model to select the correct code generator for VHDL code
generation.

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Notes on Using Multicycle Paths

DSPs can cause timing Adding a DSP with a latency greater than z-0 to a down-sampled path can result
problems in down-sampled in a timing problem.
paths
Note

In FPGA logic, timing is always measured between two flip-flops. This

means that if a signal does not make its way through combinatorial logic
(i.e., all operations with latency 0) between two flip-flops in the FPGA clock
period, the timing is violated and the FPGA build is aborted.

Mechanism of down-sampled paths The following illustration shows the

normal mechanism of down-sampled paths. As an example, the combinatorial
logic has a latency of 42 ns. The signal path is down-sampled from 100 MHz to
20 MHz by adding a Down Sample block from the HDL library of the AMD Vitis
Model Composer at the beginning of the path and an Up Sample block at the
end. The added blocks are based on D-flip-flops.

100 MHz

C Q C Q
CE 42 ns CE
D D
DFF Combinatorial logic DFF

50 ns

DSP problem The normal mechanism of simply increasing block latency for
DSPs does not work in down-sample paths due to its mechanisms:
§ An n-time down-sample path enables each element on its path using the chip
enable (CE) port only at every n-th clock cycle.
§ Additionally, a timing constraint is generated that allows n-times the time
between two flip-flops on the down-sample path for all elements with a CE
port.
DSPs do not have a CE port, so they cannot support the normal mechanism. This
means that DSPs cannot transfer the timing constraint to their flip-flops.
The following illustration shows the problem. In the example, a DSP is added to
the down-sampled path.
100 MHz

C Q C Q
CE 42 ns z-3 47 ns CE
D D
DFF DSP DFF
10 ns 10 ns

Remedy Take the flip-flops out of the DSP into the down-sample path,
because the flip-flops themselves have a CE-port. This can be done by a
modeling trick: Add a Delay block from the HDL library of the AMD Vitis Model

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Composer after the DSP and Vivado automatically moves the flip-flops behind
the time-critical object within the DSP. The latency of the Delay block must
match the latency of the DSP.
The following illustration shows the modified DSP in the down-sample path. The
timing constraints are now effective between flip-flops.
100 MHz

C Q C Q
CE 42 ns z-0 z-3 47 ns CE
D D
DFF DSP Delay DFF
50 ns 50 ns

Troubleshooting For known build problems and their solution, refer to Building an FPGA
application on page 262

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Modeling External I/O Access

Introduction The FPGA Programming Blockset provides blocks for reading from input channels
and writing to output channels of the FPGA board.

Where to go from here Information in this section

Reading From Input Channels.................................................................. 73

The FPGA Programming Blockset provides a block for accessing input
channels of the FPGA board.

Writing To Output Channels.................................................................... 74

The FPGA Programming Blockset provides a block for accessing output
channels of the FPGA board.

Effects of Modeling External I/O Access................................................... 75

Read and write accesses to external devices depend on the used
platform.

Reading From Input Channels

Introduction The FPGA Programming Blockset provides a block for accessing input channels of
the FPGA board.

Type and number of input The FPGA_IO_READ_BL block provides read access to an input channel of the
channels hardware used. You can select different types of input channels depending on
the framework for the FPGA board or piggyback module.

The channels are represented by their functionality defined in the selected

framework. For example, if you have specified the DS1303 (KU15P) Multi-I/O
Board framework (MicroLabBox II), the Digital channel list entry represents a
digital input channels and the Analog channel list entry represents the analog
input channels.

The number of available input channels also depends on the specified

framework.

The channel list only provides input channels that are not already assigned to a
block.

Note

An FPGA_IO_READ_BL block can only be connected to one input channel.

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I/O mapping for the input For the mapping between the input channels and the I/O connector pins,
channels refer to the hardware-specific description in the FPGA Programming Blockset -
FPGA Interface Reference . For example, for the I/O mapping of the input
channels defined by the DS1303 (KU15P) Multi-I/O Board framework, refer
to Parameters Page (FPGA_IO_READ_BL) (FPGA Programming Blockset - FPGA
Interface Reference ).

Function-specific settings of After you have selected an input channel, the function-specific settings
the FPGA_IO_READ_BL block are loaded on the Parameters page where you can configure them. For
detailed information, refer to the FPGA Programming Blockset - FPGA Interface
Reference .

Tip

You can copy & paste previously configured interface blocks of the FPGA
Programming Blockset. The blockset automatically analyzes the FPGA model
and reassigns new hardware resources.
You can speed up the copy & paste process for the current
session by deactivating the automatic reassignment of new hardware
resources. Open the Advanced Preferences dialog and set the
PASTE_KEEP_CHANNEL_NUM preference to false. Refer to Dialog
Settings of the Advanced Preferences Dialog (FPGA Programming Blockset -
FPGA Interface Reference ).

Related topics Basics

Modeling External I/O Access.................................................................................................... 73

Writing To Output Channels

Introduction The FPGA Programming Blockset provides a block for accessing output channels
of the FPGA board.

Type and number of output The FPGA_IO_WRITE_BL block is providing write access to an output channel
channels of the hardware used. Depending on the framework for the FPGA board or
piggyback module, you can select different types of output channels.

The channels are represented by their functionality defined in the selected

framework. For example, if you have specified the DS1303 (KU15P) Multi-I/O
Board framework (MicroLabBox II), the Digital channel list entry represents
digital output channels and the Analog channel list entry represents the analog
output channels.

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The number of available output channels also depends on the specified

framework.

The channel list provides only output channels that are not already assigned to a
block.

Note

An FPGA_IO_WRITE_BL block can be connected to only one output

channel.

I/O mapping for the output For the mapping between the output channels and the I/O connector pins,
channels refer to the hardware-specific description in the FPGA Programming Blockset -
FPGA Interface Reference . For example, for the I/O mapping of the output
channels defined by the DS1303 (KU15P) Multi-I/O Board framework, refer
to Parameters Page (FPGA_IO_WRITE_BL) (FPGA Programming Blockset - FPGA
Interface Reference ).

Function-specific settings of After you have selected an output channel, the function-specific settings
the FPGA_IO_WRITE_BL block are loaded to the Parameters page, where you can configure them. For
detailed information, refer to the FPGA Programming Blockset - FPGA Interface
Reference .

Tip

You can copy & paste previously configured interface blocks of the FPGA
Programming Blockset. The blockset automatically analyzes the FPGA model
and reassigns new hardware resources.
You can speed up the copy & paste process for the current
session by deactivating the automatic reassignment of new hardware
resources. Open the Advanced Preferences dialog and set the
PASTE_KEEP_CHANNEL_NUM preference to false. Refer to Dialog
Settings of the Advanced Preferences Dialog (FPGA Programming Blockset -
FPGA Interface Reference ).

Related topics Basics

Modeling External I/O Access.................................................................................................... 73

Effects of Modeling External I/O Access

Introduction Read and write accesses to external devices depend on the platform.

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Demo model The demo model below contains some FPGA_IO_READ_BL and
FPGA_IO_WRITE_BL blocks configured with different I/O functions to show
how they will be connected to the hardware.

Effects in a MicroLabBox II, The FPGA_IO_READ_BL and FPGA_IO_WRITE_BL blocks provide different
a MicroAutoBox III, or a types of I/O functions for the MicroLabBox II, MicroAutoBox III, or SCALEXIO
SCALEXIO system system:
§ I/O functions without external connection, for example, Status In, LED
Out or APU Slave, are not represented in the FPGA custom function in
ConfigurationDesk and can only be handled within the FPGA subsystem.
§ I/O functions with external connection provide their signals as signal ports in
ConfigurationDesk.

The signal ports of the I/O functions have to be connected to external

devices. For further information on hardware resource assignment, refer to
Assigning Hardware Resources to Function Blocks (ConfigurationDesk Real-Time
Implementation Guide ).

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Effects in a MicroAutoBox II The FPGA_IO_READ_BL and FPGA_IO_WRITE_BL blocks provide different

or a MicroLabBox types of I/O functions for the MicroAutoBox II and the MicroLabBox:
§ I/O functions without external connection, for example, the Status In
function, can only be handled within the FPGA subsystem.
§ I/O functions with external connection provide their signals via the board's I/O
connector.

APU Slave Status In Digital In

FPGA

Processor bus connector

I/O connector
Time-base connector

LED Out Digital Out

Related topics Basics

Modeling External I/O Access.................................................................................................... 73

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Using Multiple Clock Domains for FPGA Modeling

Introduction You can implement FPGA functionality that is processed with different clock
periods.

Where to go from here Information in this section

Basics on Using Multiple Clock Domains.................................................. 78

Required clock transitions and implementation features.

Limitations on Using Multiple Clock Domains.......................................... 80

Observe the following limitations when using multiple clock domains.

How to Use Multiple Clock Domains for FPGA Modeling......................... 81

You can use multiple clock domains for modeling parts of your FPGA
design with individual clock periods.

Using Clock Signals of Different Clock Domains in the Same

Subsystem............................................................................................... 82
Using the clock signal of another clock domain, for example, to provide
multiple clock signals to Black Box blocks of the AMD Vitis Model
Composer.

How to Use a Customized Clocking Circuit as Clock Domain

Source..................................................................................................... 84
Using the clock of a customized clocking circuit to drive the FPGA
functionality specified in a subsystem.

Basics on Using Multiple Clock Domains

Using multiple clock domains When you use multiple clock domains, the FPGA application must be partitioned
in one application into subsystems, where each subsystem has an individual clock period.

The subsystems are decoupled via logic blocks from the HDL library of the AMD
Vitis Model Composer. The following logic blocks can be used for decoupling:
FIFO block, Dual Port RAM block, Register block, or Black Box block. As a
result, only the FPGA_Setup_BL block and the listed logic blocks for decoupling
can be added to the top level of your FPGA model as shown in the following
illustration.

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Note

Using Register blocks to decouple the subsystems:

§ Vivado incorrectly detects the use of registers to decouple the
transmission of individual bits (UFix_1_0) as an error. Refer to
Error message (Vivado clock interaction report detected unsafe clock
interactions) on page 265.
§ The System Generator block generates 4 registers for each Register
block. The first register is driven by the clock period of the input signal.
The other registers are driven by the clock period of the output signal.

Customizing the update rate The update rate of digital I/O functions depend on the FPGA clock period. Digital
of digital I/O I/O functions of a SCALEXIO system or a MicroAutoBox II/III can be used with an
individual clock period to customize the update rate.

A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.

If you implement a UART communication, you can adapt the update rate to the
require baud rate.

For maximum update rates of digital I/O, refer to Limitations on Using Multiple
Clock Domains on page 80.

Specifying clock domains The FPGA Programming Blockset supports the following methods to specify the
clock period for clock domains:
§ In the FPGA_Setup_BL block dialog, you can specify clock periods for up to
ten subsystems. The specified clock periods are derived from the FPGA clock.

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For instructions, refer to How to Use Multiple Clock Domains for FPGA
Modeling on page 81.
§ MicroAutoBox III and SCALEXIO systems only: You can use a customized
clocking circuit (user clock) as clock domain source. For example, you can use
the user clock of the MGT interface to process the data synchronous to the
MGT transceiver.
For instructions, refer to How to Use a Customized Clocking Circuit as Clock
Domain Source on page 84.

More information on using For more information on the hardware design for using multiple independent
multiple clock domains clocks, refer to https://docs.xilinx.com/r/en-US/ug897-vivado-sysgen-user/Timing-
and-Clocking.

Related topics HowTos

How to Use a Customized Clocking Circuit as Clock Domain Source......................................... 84

How to Use Multiple Clock Domains for FPGA Modeling.......................................................... 81

Limitations on Using Multiple Clock Domains

Limitations § Only the following I/O blocks of the FPGA Programming Blockset can be used
with individual clock periods:
§ DS2655M1: All digital I/O blocks, except Digital InOut
§ DS2655M2: All I/O blocks, incl. UART
§ DS6651: All digital I/O blocks, including the Trigger I/O block.
§ DS1552: All digital I/O blocks, incl. UART
§ DS1554: All digital I/O blocks
All other blocks must be used with the base rate of the FPGA base board, such
as blocks for analog I/O and processor communication.

Maximum update rate of The update rate (FPGA clock frequency) can theoretically be increased up to the
digital I/O maximum frequency of the clock buffers (BUFG) and IO buffers (BUFIO) of the
FPGA. However, this theoretical value cannot be implemented. The following
table gives an indication of configurable update rates.

Platform I/O Board/Module Recommended Update Rate

SCALEXIO DS2655M1 Max. 400 MHz
DS2655M2 Input: Max. 250 MHz1)
Output: Max. 400 MHz
DS6651 Input: Max. 250 MHz1)
Output: Max. 400 MHz
Bidirectional: Max. 400 MHz1)

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Platform I/O Board/Module Recommended Update Rate

MicroAutoBox II/III DS1552 Max. 400 MHz
DS1554 Max. 400 MHz
1) Maximum time resolution of the input channel is 4 ns.

Related topics HowTos

How to Use a Customized Clocking Circuit as Clock Domain Source......................................... 84

How to Use Multiple Clock Domains for FPGA Modeling.......................................................... 81

How to Use Multiple Clock Domains for FPGA Modeling

Objective You can use multiple clock domains for modeling parts of your FPGA design with
individual clock periods.

Preconditions The FPGA_SETUP_BL block is added to the FPGA model and a suitable
framework is selected.

Method To use an individual clock period for an FPGA subsystem

1 In the FPGA model, create the subsystem to be driven by individual clock
periods and subsystems for the I/O functions of the FPGA Programming
Blockset.
2 To pass data to or from the subsystem, connect one of the following logic
blocks from the HDL library of the AMD Vitis Model Composer to the inports
and outports of the subsystem:
§ FIFO block
§ Dual Port RAM block
§ Register block
§ Black Box block
The logic blocks decouple the data paths with different clock periods.
3 On the top level of the FPGA model, double-click the FPGA_SETUP_BL
block and open the Clocks tab.

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4 On the Clocks tab, select a subsystem of the FPGA model.

5 Specify the clock and simulation period for the selected subsystem:
§ The value for the offline simulation period must be greater than or equal
to the clock period of the selected subsystem.
§ Set the clock period of subsystems with I/O functions that do not support
individual clock periods to the FPGA clock period. Refer to Limitations on
Using Multiple Clock Domains on page 80.
The FPGA clock period is displayed on the Analysis tab of the
FPGA_SETUP_BL block.
After entering the clock period, the dialog recalculates all clock periods for
a clock setup with a minimum error for all clock periods. After recalculation,
the dialog immediately updates the clock period's values to the calculated
values in double precision.
6 Repeat steps 4 ... 5 until you specified the clock period for all subsystems.
7 Verify all recalculated clock periods.

Result Subsystems of the FPGA model are driven with individual clock periods.

Related topics Basics

Notes on Using Multicycle Paths............................................................................................... 71

Using Clock Signals of Different Clock Domains in the Same Subsystem

Introduction The FPGA Programming Blockset provides the system clock signal and clock
signals of other subsystems to use Black Box blocks of the AMD Vitis Model
Composer that require multiple clock signals.

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Framework support The SCALEXIO and the MicroAutoBox III frameworks provide the System Clock
and Subsystem Clock blocks to provide clock signals of another clock domain.

Block Description
Outputs the clock signal of the FPGA (base clock rate).

Outputs the clock signal of the subsystem clock domain that

you select in the block dialog.
You specify the subsystem clock domains in the FPGA Setup
block. Refer to How to Use Multiple Clock Domains for FPGA
Modeling on page 81.

Example The following example shows a part of a MGT communication model using a
customized protocol.

A user clock is used as the clock domain for the subsystem to process MGT data
synchronous to the MGT transceiver. To generate the user clock, the AURORA
Black Box block requires the clock of the MGT transceiver (MGT In block) and
the FPGA base clock rate (System Clock 1 block).

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Related topics Basics

Basics on Using Multiple Clock Domains................................................................................... 78

Implementing the FPGA Functionality....................................................................................... 67

How to Use a Customized Clocking Circuit as Clock Domain Source

Objective Using a customized clocking circuit (user clock) as clock domain source, for
example, to process MGT data synchronous to the MGT transceiver.

Basics and limitations Refer to the following topics:

§ Basics on Using Multiple Clock Domains on page 78
§ Limitations on Using Multiple Clock Domains on page 80

Preconditions The following preconditions must be fulfilled:

§ You use a MicroAutoBox III or SCALEXIO framework.
§ You use a Black Box block from the HDL library of the AMD Vitis Model
Composer providing a user clock.
You can use the AMD Clocking Wizard to specify the Black Box block.
Refer to https://docs.xilinx.com/r/en-US/pg065-clk-wiz/Clocking-Wizard-v6.0-
LogiCORE-IP-Product-Guide.

Method To use a user clock as clock domain source

1 In the FPGA model, create the subsystem to be driven by a user clock.
2 To pass data to or from the subsystem, connect one of the following logic
blocks to the inports and outports of the subsystem:
§ FIFO block
§ Dual Port RAM block
§ Register block
§ Black Box block
The logic blocks decouple the data paths with different clock periods. For
more information, refer to Basics on Using Multiple Clock Domains on
page 78.

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3 Open the subsystem and add a User Clock Out block of the FPGA
Interface sublibrary.

4 Connect the user clock of your Black Box block to the User Clock port of
the User Clock Out block.
5 Open the User Clock Out block dialog.
6 On the Parameters page, enter the following clock values:
§ The expected user clock period.
The value is used during the build process when no user clock is available,
for example, to specify timing constraints.
§ The clock period during offline simulation.

Result The subsystem of the FPGA model is driven with the user clock period.

Related topics Examples

Customized Protocol Demo (SCALEXIO).................................................................................. 124

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Using a Watchdog
Introduction Implementing a watchdog to check if the processor application is alive.

Where to go from here Information in this section

How to Implement the Watchdog........................................................... 86

Implementing the functionality to check if the processor application is
alive.

How to Configure the Condition when the Watchdog Expires................. 88

To specify a fixed or adaptive timeout for the watchdog timer.

How to Implement the Watchdog

Objective Implementing the functionality to check if the processor application is alive.

Limitation Only the following FPGA boards support the watchdog functionality:
§ DS6601 FPGA Base Board
§ DS6602 FPGA Base Board
§ MicroLabBox II

Basics on the watchdog timer There are two timeout modes to configure the expiration of the watchdog timer:
§ You can use a fixed timeout, i.e., you specify a time interval in seconds that
does not change.
The fixed timeout is useful if a periodic task triggers the keep-alive signal.
§ You can use an adaptive timeout, i.e., you specify a factor by how much
longer than the last task execution time to wait for the keep-alive signal. In
this mode, the watchdog measures the time interval between the last two
keep-alive signals and multiplies it by the specified factor to constantly adjust
the timeout value.
The adaptive timeout is useful if an asynchronous task triggers the keep-alive
signal.

If the specified time interval expires without a keep-alive signal being transmitted
to the FPGA application, the watchdog timer expires and outputs a timeout.

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Workflow Perform the following steps to implement a watchdog:

§ Add the watchdog to the FPGA model. Refer to Part 1.
§ Implement the keep-alive signal generation in the processor model. Refer to
Part 2.

Part 1 To add the watchdog to the FPGA application

1 From the FPGA Interface sublibrary of the FPGA Programming Blockset, add
the Watchdog block to the FPGA model.

If the watchdog timer expires before the processor application transmits the
keep-alive signal, the Status port changes from 1 to 0.
2 Add the FPGA functionality that is executed when the watchdog expires.
Trigger the execution of the FPGA functionality with the Status port of the
watchdog.

Interim result You added the watchdog to the FPGA model and implemented the functionality
if the watchdog expires.

Part 2 To generate the keep-alive signal

1 In the processor model, select a subsystem whose execution will be critical
for your application. The task execution will trigger the generation of the
keep-alive signal. You can select subsystems that are executed periodically or
asynchronously (function-call subsystem).
2 Add a Simulink constant and a Data Outport block from the Model
Interface Package for Simulink to the selected subsystem.

When the real-time application is running on the dSPACE processing

hardware, each read process triggers the generation of the keep-alive signal.
The read value itself has no influence on the signal.

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Result You added the watchdog functionality to the FPGA model and the generation of
the keep-alive signal to the FPGA model.

Tip

In ConfigurationDesk, you deactivate the watchdog functionality by not

mapping the Trigger port of the watchdog function to a model port.
If deactivated, the Status port of the Watchdog block always outputs 1 in
the FPGA application.

Next steps After you built the FPGA application and exported it to ConfiguratinDesk, you
can map the trigger signal to the FPGA custom function block and specify the
trigger condition for the watchdog. Refer to How to Configure the Condition
when the Watchdog Expires on page 88.

Related topics HowTos

How to Configure the Condition when the Watchdog Expires.................................................. 88

How to Configure the Condition when the Watchdog Expires

Objective To specify a fixed or adaptive timeout for the watchdog timer.

Basics on the watchdog timer For basics on the watchdog timer, refer to How to Implement the Watchdog on
page 86.

Preconditions The following preconditions must be fulfilled:

§ The FPGA application provides watchdog functionalities. Refer to How to
Implement the Watchdog on page 86.
§ In ConfigurationDesk, the FPGA application is added to the signal chain
as an FPGA custom function block. Refer to Building the Applications
(MicroLabBox II, MicroAutoBox III, SCALEXIO) on page 186.

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Method To configure the condition when the watchdog expires

1 In ConfigurationDesk, select the Watchdog function of the FPGA custom
function block.

2 In the Properties Browser, select the timeout mode for the watchdog.
3 If you selected the fixed timeout mode, enter a fixed timeout in seconds.
4 If you selected an adaptive timeout, enter an integer factor by how much
longer than the last task execution time the watchdog timer waits for the
keep-alive signal.
5 To activate the watchdog feature, map the Trigger function inport to the
Trigger model port of the behavior model.

Result You configured the timeout for the watchdog timer. If the specified time interval
expires without a keep-alive signal being transmitted to the FPGA application,
the watchdog timer expires and outputs a timeout to trigger the implemented
FPGA functionality.

If a timeout occurs, you must restart the real-time application to reset the
watchdog.

Tip

In ConfigurationDesk, you deactivate the watchdog functionality by not

mapping the Trigger port of the watchdog function to a model port.
If deactivated, the Status port of the Watchdog block always outputs 1 in
the FPGA application.

Related topics Basics

Configuring the Basic Functionality (FPGA) (ConfigurationDesk I/O Function

Implementation Guide )

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Modeling DDR4 RAM Access

Introduction The FPGA Programming Blockset provides blocks to implement a communication
interface for the DDR4 RAM of the DS6602.

Where to go from here Information in this section

Accessing the DDR4 RAM of the DS6602................................................ 90

The DS6602 FPGA Base Board provides a 4 GB DDR4 RAM that can be
used by the FPGA application.

Initializing the DDR4 RAM of the DS6602 for Offline Simulation.............. 92

Simulating the FPGA application with defined DDR4 RAM data values.

Initializing the DDR4 RAM of the DS6602 for Real-Time

Simulation............................................................................................... 93
Executing the FPGA application with defined DDR4 RAM data values.

Accessing the DDR4 RAM of the DS6602

Introduction The DS6602 FPGA Base Board provides a 4 GB DDR4 RAM that can be used by
the FPGA application.

The RAM interface always handles 512 bits at once. Therefore, the FPGA
application can read/write 16 x 32 bits data or 8 x 64 bits data within one
memory access.

You can select different I/O types to access the DDR4 RAM:
§ DDR4 32 Mode 1 and DDR4 64 Mode 1 to read/write 32/64-bit values.
These I/O types use the memory access mode 1.
§ DDR4 32 Mode 2 and DDR4 64 Mode 2 to read/write 32/64-bit values.
These I/O types use the memory access mode 2.

Tip

The DDR4 RAM processes the data values as raw data. To use certain data
types, such as single, you have to add Reinterpret blocks from the HDL
library of the AMD Vitis Model Composer to the FPGA model.

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Memory access modes The FPGA Programming Blockset provides two memory access modes:
§ Mode 1
Mode 1 addresses one memory area of 512 bits, each with read/write access.
§ Mode 2
Mode 2 addresses two memory areas of 256 bits, each with read/write access.

The following example shows the memory areas addressed by the different
access modes.
Mode 1 Mode 2

2 1024 4 1024

768 3 768

1 512 2 512

256 1 256

Address 0 Bit 0 Address 0 Bit 0

Memory Memory

Note

The memory areas are addressed differently by the different access modes.

Optimizing read/write access To decrease the read/write time, use consecutive addresses for read/write
accesses. A random address access approximately triples the read/write time:

Read access Linear addressing 7.37 GB/s

Random addressing 2.58 GB/s
Write access Linear addressing 6.77 GB/s
Random addressing 2.29 GB/s

Related topics Basics

Exchanging Data With the Processor Model............................................................................ 130

References

Parameters Page (FPGA_IO_WRITE_BL) (FPGA Programming Blockset - FPGA

Interface Reference )

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Initializing the DDR4 RAM of the DS6602 for Offline Simulation

Introduction You can provide a workspace variable with initial values for the RAM memory to
simulate the FPGA application with defined DDR4 RAM data values.

Generating an initialization The initialization variable is a MATLAB workspace variable. You can use one of
variable the following MATLAB scripts to generate an initialization variable.

32-bit values The following examples generate an initialization variable for

32-bit values (DDR4 32 Mode 1 and DDR4 32 Mode 2).
% generate sample 32 bit values (4GB – 1 Word) 1..2^30-1 (2^30*4 Byte = 4 GB)
% For initialization with datatype double values, use: single(<values>)
% For initialization with datatype uint32/UFix_32_0, use: uint32(<values>)

% Use less than 2^30 values for faster experimenting.

% Small example for datatype single:

>> initValues = single((1:10)/3.1)
initValues =
1×10 single row vector
0.3226 0.6452 0.9677 1.2903 1.6129 1.9355 2.2581 2.5806 2.9032 3.2258

% Small example for datatype uint32/UFix_32_0:

>> initValues = uint32((1:10)/3.1)
initValues =
1×10 uint32 row vector
0 1 1 1 2 2 2 3 3 3

64-bit values The following examples generate an initialization variable for

64-bit values (DDR4 64 Mode 1 and DDR4 64 Mode 2).
% generate sample 64 bit values (4GB – 1 Word) 1..2^29-1 (2^29*8 Byte = 4 GB)
% For initialization with datatype double values, use: double(<values>)
% For initialization with datatype uint64/UFix64_0, use: fi(<values>, 0, 64, 0)

% Use less than 2^29 values for faster experimenting.

% Small example for datatype double:

>> initValues = double((1:10)/3.1)
initValues =
0.3226 0.6452 0.9677 1.2903 1.6129 1.9355 2.2581 2.5806 2.9032 3.2258

% Small example for datatype uint64/UFix_64_0:

>> initValues = fi((1:10)/3.1, 0, 64, 0)
initValues =
0 1 1 1 2 2 2 3 3 3
DataTypeMode: Fixed-point: binary point scaling
Signedness: Unsigned
WordLength: 64
FractionLength: 0

Initializing the RAM with the To initialize the RAM at the beginning of the offline simulation, you have to
variable enter the variable name to the Simulation init variable parameter on the
Parameters page of the used DDR4 block.

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Related topics References

Parameters Page (FPGA_IO_WRITE_BL) (FPGA Programming Blockset - FPGA

Interface Reference )

Initializing the DDR4 RAM of the DS6602 for Real-Time Simulation

Introduction You can provide a file with initial values for the RAM memory to start the FPGA
application with defined DDR4 RAM data values. The processing hardware writes
the initial values from a SCALEXIO SSD to the FPGA base board during the
initialization phase of the SCALEXIO system.

Generating an initialization The initialization file is a binary file. You can use the following MATLAB script to
file generate an initialization file with MATLAB.
% generate sample 32 bit values (4GB – 1 Word) 1..2^30-1 (2^30*4 Byte = 4 GB)
% generate sample 64 bit values (4GB – 1 Word) 1..2^29-1 (2^29*8 Byte = 4 GB)
ddr4_4gb = 1:2^30-1;
% open, write, close file
fid = fopen('ddr4_4gb.bin', 'w');
fwrite(fid, ddr4_4gb, 'uint32');
% or as different data type
% fwrite(fid, ddr4_4gb, 'single');
% fwrite(fid, ddr4_4gb, 'double');
% 64 bit -> use only half as many elements
…
fclose(fid)

Note

You can use any data type to initialize the DDR4 RAM.

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Providing the initialization You download the initialization file to a SCALEXIO SSD to provide the initial
file to the SCALEXIO system values. For instructions, refer to How to Initialize the DDR4 RAM of the DS6602
(ConfigurationDesk I/O Function Implementation Guide ).

Related topics References

Parameters Page (FPGA_IO_WRITE_BL) (FPGA Programming Blockset - FPGA

Interface Reference )

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Modeling UART Communication

Introduction The FPGA Programming Blockset provides blocks to implement a UART
communication interface. A UART demo project for SCALEXIO systems provides
a model block that simplifies the implementation of UART interfaces.

Where to go from here Information in this section

Using the UART Demo Model for SCALEXIO Systems............................... 96

The FPGA Programming Blockset provides a UART demo project that you
can use to implement UART communication.

Information in other sections

UART interface blocks for MicroLabBox:

Parameters Page (FPGA_IO_WRITE_BL) (FPGA Programming
Blockset - FPGA Interface Reference )
To specify relevant settings for the selected I/O function.

UART interface blocks for SCALEXIO (DS2655M2 Digital I/O

Module):
Parameters Page (FPGA_IO_READ_BL) (FPGA Programming
Blockset - FPGA Interface Reference )
To specify relevant settings for the selected I/O function.

Parameters Page (FPGA_IO_WRITE_BL) (FPGA Programming

Blockset - FPGA Interface Reference )
To specify relevant settings for the selected I/O function.

UART interface blocks for the MicroAutoBox II (DS1552 Multi-I/O

Module):
Parameters Page (FPGA_IO_WRITE_BL) (FPGA Programming
Blockset - FPGA Interface Reference )
To specify relevant settings for the selected I/O function.

UART interface blocks for the MicroAutoBox III (DS1552 Multi-

I/O Module):
Parameters Page (FPGA_IO_WRITE_BL) (FPGA Programming
Blockset - FPGA Interface Reference )
To specify relevant settings for the selected I/O function.

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Using the UART Demo Model for SCALEXIO Systems

Supported platforms The demo model supports only SCALEXIO systems.

Accessing the demo Open the block library and select Demos – DemoFPGAuart –
DS2655_XC7K160T.

Demo overview The following illustration shows the FPGA model with the subsystem of a
RS232_UART model block.

The demo model provides eight UART communication interfaces: Four RS232
interfaces and four RS485 interfaces. The main component for all interfaces is
the Buffer UART model block that resides in every UART subsystem.

Using the demo You can use the Buffer UART model block in your FPGA application to
implement a UART communication interface in your project.

The Buffer UART model block provides the following features:

§ Configures the UART frames.
§ Configures the baud rate.
§ Controls the data direction for RS485 communication.
§ Controls the sequential read of a Buffer In block to send the elements of the
buffer with UART frames.

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§ Controls the sequential write to a Buffer Out block to send received UART
frames to the processor application.

Description of the Buffer Appearance of the block:

UART model block

I/O characteristics The following table describes the ports of the block:

Port Description
Input
rst Resets the model block.
Value range:
§ 0: No reset
§ 1: Reset
din Receives new data value to be sent with an UART frame.
Data type: UFix_32_0
Value range: Depends on the specified number of data bits of the UART frame.
data_new Indicates a change in the buffer status of a connected Buffer In interface block.
Data type: UFix_1_0
data count Specifies the current number of elements in the buffer of a connected Buffer In interface block.
Data type: UFix_16_0
RX Receives the UART frame as a sequence of bits.
Data type: UFix_1_0
divider Specifies the clock divider value to set the baud rate of the UART interface. You can calculate the
value for the clock divider to set the baud rate as follows:
1
Clock divider = −1
Baud rate · 32 ns

For values to set common baud rates, refer to Settings for common baud rates on page 98.
Data type: Fix_32_0
The value range depends on the maximum baud rate of the UART interface hardware:
§ RS232: 125 ... nmax
§ RS485: 1 ... nmax

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Port Description
data_bits Specifies the number of data bits. The data bits include optional parity bits and exclude the start bit
of the UART frame.
Data type: Fix_32_0
Value range: 5 ... 9
stop_half_bits Specifies the number of stop half-bits of the UART frame. The number value specifies the number of
half bits. For example: 2 specifies 1 stop bit in the frame.
Data type: Fix_32_0
Value range: 1 ... 5
Output
addr Outputs the buffer address of the next element in a Buffer In interface block to be sent with the
next frame.
Data type: UFix_16_0
dout Outputs the data value of the received UART frame at the RX port.
Data type: UFix_32_0
Value range: Depends on the specified number of data bits of the UART frame.
we Specifies that the current value of the dout port is valid to control a connected Buffer Out interface
block.
Data type: UFix_1_0
TX Outputs the UART frame as a sequence of bits.
Data type: UFix_1_0

Settings for common baud The following table gives you clock divider values for the divider port to set the
rates UART interface to a common baud rate:

Desired Baud Rate Clock Divider Value

9600 3254
19200 1627
38400 813
57600 542
115200 270
1000000 30

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Modeling Inter-FPGA Communication

Introduction An inter-FPGA communication bus lets you exchange data directly between
FPGA boards.

Where to go from here Information in this section

Introduction to Inter-FPGA Communication............................................. 99

Different types of inter-FPGA communication buses.

Modeling Inter-FPGA Communication via IOCNET.................................. 101

Implementing inter-FPGA communication by using the board-specific bus
of SCALEXIO systems.

Modeling Inter-FPGA Communication via MGT Modules........................ 104

Implementing inter-FPGA communication by using MGT modules that
are installed to the DS6601/DS6602 FPGA Base Boards.

Modeling Inter-FPGA Communication via I/O Module Slots.................... 105

Implementing inter-FPGA communication by using the I/O module slots
of SCALEXIO FPGA base boards.

Introduction to Inter-FPGA Communication

Overview of Inter-FPGA Communication

Platforms supporting inter- The following platforms support inter-FPGA communication:

FPGA communication § SCALEXIO systems with SCALEXIO FPGA base boards DS2655, DS6601, or
DS6602.
SCALEXIO provides different types of inter-FPGA communication. Refer
to Overview of inter-FPGA communication between SCALEXIO boards on
page 100.

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Overview of inter-FPGA The following table shows the different types of inter-FPGA communication
communication between between SCALEXIO FPGA base boards.
SCALEXIO boards

Inter-FPGA via I/O Module Inter-FPGA via MGT Inter-FPGA via IOCNET
Slots Module
Topology 1:1 1:1 1:n
FPGA stack1) Next to each other No restriction § Within the same IOCNET
location segment2)
§ Other I/O boards must not
be connected to this IOCNET
segment.
Number of direct 2 4 Not directly limited
connections
Data rate Max. 582.3 Mbit/s with default Max. 10.3125 Gbit/s with § 1.25 Gbit/s IOCNET:
values Aurora 64b66b 128 Bit Approx. 800 Mbit/s
block § 2.5 Gbit/s IOCNET:
Typ. 1 Gbit/s, max.
1.6 Gbit/s3)
Latency 72 ns … 96 ns with default Typ. 384 ns, max. 472 ns Typ. 1.0 µs per network hop,
values for single words including onboard hops
Supported FPGA § DS2655 § DS6601 § DS2655
base boards § DS6601 § DS6602 § DS6601
§ DS6602 § DS6602
Required accessory SCLX_INT_FPGA_CAB1 DS6601_MGT1 or –
DS6602_MGT1
1) FPGA base board with installed I/O modules.
2) Refer to Implementing Inter-FPGA Communication via IOCNET on page 101.
3) Theoretical maximum

Implementing the inter-FPGA To implement an inter-FPGA communication bus, you have to implement the
interface functionality to the FPGA model.

Depending on the used hardware, refer to one of the following topics:

§ Implementing Inter-FPGA Communication via IOCNET on page 101
§ Implementing Inter-FPGA Communication via MGT Modules on page 104
§ Implementing Inter-FPGA Communication via I/O Module Slots on page 105

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Modeling Inter-FPGA Communication via IOCNET

Where to go from here Information in this section

Implementing Inter-FPGA Communication via IOCNET........................... 101

IOCNET can be used to transfer data directly between FPGA boards of a
SCALEXIO system.

Calculating the Latency (IOCNET)........................................................... 103

Calculating the latency of an inter-FPGA connection via IOCNET.

Implementing Inter-FPGA Communication via IOCNET

Introduction IOCNET can be used to transfer data directly between FPGA boards of a
SCALEXIO system.

Basic interface characteristics You have to consider the following interface characteristics if you implement
inter-FPGA communication via IOCNET.
§ Up to 32 channels to transmit 32-bit values and up to 32 channels to transmit
64-bit values can be implemented.
§ The data rate depends on the IOCNET data rate:
§ 1.25 Gbit/s IOCNET:
About 800 Mbit/s
§ 2.5 Gbit/s IOCNET:
Typ. 1 Gbit/s, max. 1.6 Gbit/s theoretical
§ The latency is typ. 1 µs per network hop. Refer to Calculating the Latency
(IOCNET) on page 103.
§ Each 32-bit channel can address up to 1024 data values.
§ Each 64-bit channel can address up to 512 data values.
§ The data type is a raw data type: UFix_32_0 or UFix_64_0.
You can transfer any data type with a matching bit width via inter-FPGA over
IOCNET. Use the Reinterpret block from the HDL library of the AMD Vitis
Model Composer to change your data type to UFix_32_0 or UFix_64_0 and
vice versa. Reinterpreting data types does not cost any hardware or latency.

Restrictions on the IOCNET Inter-FPGA via IOCNET can only be used for FPGA base boards if the following
topology requirements on the IOCNET topology are fulfilled:
§ The boards are installed to the same IOCNET segment. An IOCNET segment
are the IOCNET nodes (I/O unit/LabBox/AutoBox) that are linked in serial to the
processing hardware. The following illustrations shows an example.

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Downlink

Downlink

IOCNET segment

Tip

In ConfigurationDesk, switch the Platform Manager to the network

view via the context menu.

§ Other I/O boards must not be connected to the used IOCNET segment.

Adding the inter-FPGA The frameworks of the FPGA base boards provide inter-FPGA blocks to add the
communication functionality inter-FPGA communication functionality to the FPGA application.
to the FPGA application
For more information, refer to the following topics:
§ Block Settings for the DS2655 FPGA Base Board Framework (FPGA
Programming Blockset - FPGA Interface Reference )
§ Block Settings for the DS6601 FPGA Base Board Framework (FPGA
Programming Blockset - FPGA Interface Reference )
§ Block Settings for the DS6602 FPGA Base Board Framework (FPGA
Programming Blockset - FPGA Interface Reference )

Specifying the inter-FPGA After you added the FPGA application to the signal chain in ConfigurationDesk,
connections you can reference the Inter-FPGA In blocks to the Inter-FPGA Out blocks to
specify the communication bus.

For more information, refer to Configuring the Basic Functionality (FPGA)

(ConfigurationDesk I/O Function Implementation Guide ).

Related topics Basics

Overview of Inter-FPGA Communication................................................................................... 99

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Calculating the Latency (IOCNET)

Latency calculation The latency depends on the network hops between the FPGA base boards. A
network hop occurs when a data packet is passed from one network connection
to the next. Each hop takes about 1.0 µs.

To calculate the latency, you have to count the IOCNET routers between the
FPGA base boards, including the onboard routers.

Tip

In ConfigurationDesk, switch the Platform Manager to the network view

via the context menu.

Example #1 The following illustration shows a topology with 3 network hops between the
FPGA base boards.

These are the network hops:

§ Onboard IOCNET router of the DS6601 FPGA Base Board (Slot 3)
§ Onboard IOCNET router of the DS6001 Processor Board
§ Onboard IOCNET router of the DS6601 FPGA Base Board (Slot 4)

Latency = 3 hops · 1.0 µs/hop (typ.) ≈ 3 µs

Example #2 The following illustration shows a topology with 5 network hops between the
FPGA base boards.

These are the network hops:

§ Onboard IOCNET router of the DS6601 FPGA Base Board (Slot 2)
§ IOCNET router of the DS2703 6-Slot I/O Unit (1)
§ IOCNET router of the Processing Unit
§ IOCNET router of the DS2703 6-Slot I/O Unit (2)
§ Onboard IOCNET router of the DS6601 FPGA Base Board (Slot 4)

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Latency = 5 hops · 1.0 µs/hop (typ.) = 5.0 µs

Modeling Inter-FPGA Communication via MGT Modules

Implementing Inter-FPGA Communication via MGT Modules

Introduction Multi-gigabit transceiver (MGT) modules can be used to transfer data directly
between FPGA boards of a SCALEXIO system.

Basic interface characteristics You have to consider the following interface characteristics if you implement
inter-FPGA communication via MGT modules.
§ MGT modules are optional modules that must be installed to the FPGA base
board.
§ Up to 4 channels to transmit data values to up to 4 FPGA base boards.
§ The maximum data rate is 10.3125 Gbit/s if you use an Aurora 64b66b 128
Bit block.
§ The typical latency is 384 ns for single words. The maximum latency is 472 ns.
§ Each 64-bit channel can address up to 512 data values.
§ The data type is a raw data type: UFix_32_0 or UFix_64_0.
You can transfer any data type with a matching bit width via inter-FPGA over
IOCNET. Use the Reinterpret block from the HDL library of the AMD Vitis
Model Composer to change your data type to UFix_32_0 or UFix_64_0 and
vice versa. Reinterpreting data types does not cost any hardware or latency.

Adding the inter-FPGA The DS660X_MGT framework provides I/O functions to transmit and receive data
communication functionality via an installed MGT module using the Aurora protocol, but you can also use
to the FPGA application customized protocols.

Preventing additional latencies for data streams Latency can increase if

the transmission must pause to prevent the RX-FIFO buffer from overflowing
due to clock drift between the different FPGA boards. When data is sent with
every FPGA clock cycle, a pause can happen despite the high precision clocks
of the DS6202 FPGA Base Boards. The latency is about 5.4 µs for 64‑bit data
transmission and 10.4 µs for 128‑bit data transmission.
To transfer data with minimal latency, pause the transmission of data at least
every 16.666 FPGA clock cycles for one clock cycle. This can be implemented
with a 14-bit counter that pauses the transmission every 16.384 clock cycles, for
example.

Further information For more information, refer to the following topics:

§ Parameters Page (FPGA_IO_READ_BL) (FPGA Programming Blockset - FPGA
Interface Reference )

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§ Parameters Page (FPGA_IO_WRITE_BL) (FPGA Programming Blockset - FPGA

Interface Reference )
§ Modeling MGT Communication Using a Customized Protocol on page 123

Related topics Basics

Overview of Inter-FPGA Communication................................................................................... 99

Modeling Inter-FPGA Communication via I/O Module Slots

Where to go from here Information in this section

Implementing Inter-FPGA Communication via I/O Module Slots............. 105

Aspects on implementing inter-FPGA communication between SCALEXIO
FPGA base boards via I/O module slots.

How to Specify I/O Module Slots of SCALEXIO FPGA Base Boards

as Inter-FPGA Interfaces......................................................................... 110
You have to specify the inter-FPGA connector only if you use the inter-
FPGA communication on SCALEXIO FPGA base boards.

How to Determine the Bit Ranges for Inter-FPGA Subbuses

Between SCALEXIO FPGA Base Boards.................................................. 111
When you specify subbuses to send and receive data, you must observe
limitations for the bit ranges of subbuses.

Calculating the Data Rate and Latency (SCALEXIO)................................ 114

Optimizing the bus settings for the inter-FPGA communication bus via I/O
module ports.

Implementing Inter-FPGA Communication via I/O Module Slots

Introduction With the Inter-FPGA Interface framework, the I/O module slots of the SCALEXIO
FPGA base boards can be used to establish an inter-FPGA communication bus.

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Avoiding damage to the NOTICE

board
The improper assembly of inter-FPGA communication buses will
damage the FPGA boards
For inter-FPGA communication buses, special inter-FPGA communication
cables must be used. Other cables, such as the cables used for connecting
the I/O modules, will damage the FPGA boards. Furthermore, special rules
for attaching the FPGA boards must be observed to ensure proper bus
communication.
§ Use the SCLX_INT_FPGA_CAB1 inter-FPGA cables and observe the
enclosed documentation for assembling.
§ Do not connect FPGA boards via inter-FPGA cables if the FPGA boards are
connected to different processors via IOCNET.

Basic interface characteristics You have to consider the following interface characteristics if you implement
inter-FPGA communication via I/O module slots.
§ The inter-FPGA communication bus is a point-to-point one-way
communication. It is implemented directly between the connected FPGA
boards without using IOCNET.
§ An inter-FPGA communication cable can only connect FPGA base boards that
are installed next to each other. Therefore, up to two FPGA base boards can be
directly connected to an FPGA base board. For an example, refer to Inter-FPGA
communication between multiple SCALEXIO FPGA base boards on page 109.
§ The maximum data rate is 582.3 Mbit/s with default values. Refer to
Calculating the Data Rate and Latency (SCALEXIO) on page 114.
§ The latency is 72 ns … 96 ns with default values. Refer to Calculating the Data
Rate and Latency (SCALEXIO) on page 114.
§ The maximum data width for inter-FPGA communication with bus
synchronization is 27 bits.
The interface provides a 28‑bit parallel data bus. One data bit of each subbus
is reserved for synchronization purposes.
In expert mode, the Inter-FPGA Interface framework provides inter-FPGA
communication without bus synchronization. In this mode, the maximum data
width for inter-FPGA communication is 28 bits.
§ You can configure up to eight subbuses for each inter-FPGA communication
bus.
§ Inter-FPGA communication between different types of SCALEXIO FPGA boards
is supported. For example: A DS2655 FPGA Base Board can be connected to a
DS6601 FPGA Board and a DS6602 FPGA Base Board.

Adding the inter-FPGA The Inter-FPGA Interface framework provides the functionality to implement the
communication functionality inter-FPGA communication. You must select the framework on the Platform
to the FPGA application tab of the FPGA_SETUP_BL block. With the selection you also specify the I/O
module slot that supports the inter-FPGA communication.

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For instructions, refer to How to Specify I/O Module Slots of SCALEXIO FPGA
Base Boards as Inter-FPGA Interfaces on page 110.

Specifying the inter-FPGA The I‑FPGA In and I‑FPGA Out I/O blocks let you specify the inter-FPGA
communication communication.

The blocks' dialogs let you enable an expert mode. In expert mode, you can
implement an inter-FPGA communication bus without bus synchronization or
you can change the default values for clock, bit length, and filter depth. For
robust communication, it is not recommended to activate expert mode if you do
not have enough experience with configuring buses and knowledge of checking
whether the configured transmission is correct with regard to the observed signal
integrity at the applicable temperature range.

For more information on the inter-FPGA I/O functions, refer to Block Settings
for the Inter-FPGA Interface Framework (FPGA Programming Blockset - FPGA
Interface Reference ).

Configuring subbuses Eight communication channels let you use up to eight subbuses. If you configure
subbuses, you can access a specific subbus by specifying a bit range with the
related start bits and end bits in the Parameters pages of the inter-FPGA I/O
block dialogs. The bit ranges of the subbuses must not overlap. One bit has to be
reserved for synchronization purposes for each configured subbus. The maximum
data width of a synchronized subbus is therefore Endbit ‑ Startbit.

You cannot use two I/O blocks that use the same communication channel within
the same FPGA application. For example, you cannot use an I‑FPGA In 1 block if
there is already an I‑FPGA Out 1 block, but you can add an I‑FPGA In 2 block.

Note

If you send and receive data with the same inter-FPGA interface, you have
to consider limitations on the bit ranges for the subbuses. Refer to How
to Determine the Bit Ranges for Inter-FPGA Subbuses Between SCALEXIO
FPGA Base Boards on page 111.

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General configuration aspects NOTICE

An incorrect configuration might damage the electrical interface.

If you configure both ends of an inter-FPGA connection bus to write on the
bus, the connection results in a short circuit. This short circuit might damage
the electrical interface of the used I/O module slots. In multiprocessor
applications, an incorrect configuration cannot be detected automatically
to beware hardware damage.
§ Make sure that you implement for each I‑FPGA Out block an I‑FPGA In
block as counterpart on the other FPGA board.
§ Make sure that the inter-FPGA I/O blocks of the same subbus uses the
same Startbit and Endbit to send or receive data.
§ Do not use inter-FPGA communication in a multiprocessor application
to transmit data between FPGA boards that are connected to different
processors via IOCNET.

Application examples The hardware connections, the implemented model, and the block settings for
the bus configuration have to match to get the required data transfer.

Inter‑FPGA communication in one direction without a subbus In the

following example with two FPGA base boards, the FPGA application that runs
on board 1 uses the entire data width of the bus to send data to board 2.

Inter-FPGA
Board 1 communication Board 2

I-FPGA I-FPGA
Start bit: 0 Master 1 Slave 1 Start bit: 0
27 bit data + 1 bit sync.
End bit: 27 End bit: 27

Inter‑FPGA communication in both directions with two subbuses In the

following example, the FPGA applications can exchange data with a data width
of 8 bits in both directions. At the inports and outports of an I-FPGA Block, the
position of the LSB is always 0. The offset configured by the start bit for an
Inter-FPGA subbus does only apply to the arrangement of bits on the Inter-FPGA
bus.
The master and the slave which are communicating have to be configured with
the same communication settings. For example, it is not allowed to specify the
slave settings to receive only a subrange of the transmitted data.

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Inter-FPGA
Board 1 communication Board 2

I-FPGA Subbus 1 I-FPGA

Start bit: 0 Master 1 Slave 1 Start bit: 0
8 bit data + 1 bit sync.
End bit: 8 End bit: 8

I-FPGA Subbus 2 I-FPGA

Start bit: 14 Slave 2 Master 2 Start bit: 14
8 bit data + 1 bit sync.
End bit: 22 End bit: 22

Inter-FPGA communication between multiple SCALEXIO FPGA base

boards In the following example with three SCALEXIO FPGA base boards,
the FPGA application of board 2 can directly send data to board 1 and board 3.
The FPGA application that runs on board 2 uses two inter-FPGA interfaces, one
interface for each connected board.
Inter-FPGA
Board 2 communication Board 1

I-FPGA Bus 1 I-FPGA

Start bit: 0 Master 1 Slave 1 Start bit: 0
End bit: 27 End bit: 27

I-FPGA Bus 2
Start bit: 0 Master 2 Board 3
End bit: 27
I-FPGA
Slave 2 Start bit: 0
End bit: 27

More than three boards can be connected via inter-FPGA communication cables,
but only the boards that are located next to each other can be connected with
an inter-FPGA communication cable.

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The following illustration shows the assembly of four FPGA stacks (FPGA base
board with I/O modules) that are used for inter-FPGA communication.
Inter-FPGA communication cables
Rear

5 5 5 5
4 4 4 4
3 3 3 3
2 2 2 2

One or more I/O modules

One or more I/O modules

One or more I/O modules

One or more I/O modules

1 1 1 1

Base board 1
...
Base board 2

Base board 3

Base board 4
...
Stack 1 Stack 2 Stack 3 Stack 4

Front

Related topics Basics

Overview of Inter-FPGA Communication................................................................................... 99

HowTos

How to Determine the Bit Ranges for Inter-FPGA Subbuses Between SCALEXIO FPGA
Base Boards............................................................................................................................ 111
How to Specify I/O Module Slots of SCALEXIO FPGA Base Boards as Inter-FPGA
Interfaces............................................................................................................................... 110

How to Specify I/O Module Slots of SCALEXIO FPGA Base Boards as Inter-
FPGA Interfaces

Objective You have to specify the inter-FPGA connector only if you use the inter-FPGA
communication on SCALEXIO FPGA base boards.

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Method To specify I/O module slots of a SCALEXIO FPGA base board as inter-FPGA
interface
1 Via the Platform Manager in ConfigurationDesk, for example, check the
I/O module slots that are used for inter-FPGA communication.

2 On the Platform tab of the FPGA_SETUP_BL block dialog, make sure that a
SCALEXIO FPGA base board is selected.
3 Select Inter-FPGA Interface for the I/O module slot that is connected to
another FPGA board for inter-FPGA communication.
4 Repeat step 3 to specify other I/O module slots as inter-FPGA interface.

Result You specified the I/O module slots that support inter-FPGA communication.
Now, the I/O function blocks to implement the inter-FPGA communication are
available.

Related topics Basics

Modeling Inter-FPGA Communication....................................................................................... 99

How to Determine the Bit Ranges for Inter-FPGA Subbuses Between

SCALEXIO FPGA Base Boards

Objective When you implement subbuses to send and receive data via an inter-FPGA
communication bus between SCALEXIO FPGA base boards, you must observe
limitations for the bit ranges of subbuses.

Limitations For a robust communication, the wires of the interface cable are grouped to six
cable segments. Within a cable segment, data can only be sent in one direction.
That means, you cannot use the same cable segment to send and receive data.
Furthermore, the interface cable supports only two cable segment ranges that
transmit data as shown in the example below.

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Inter-FPGA Interface Inter-FPGA

interface 1 cable interface 2
Data Data
Subbus 1 Cable segment 1...2 Subbus 1

Data Data
Subbus 2 Cable segment 3...6 Subbus 2

The following example shows an unsupported subbus configuration, because the

subbuses use three cable segment ranges.
Inter-FPGA Interface Inter-FPGA
interface 1 cable interface 2
Data Data
Subbus 1 Cable segment 1...2 Subbus 1

Data Data
Subbus 2 Cable segment 3...4 Subbus 2

Data Data
Subbus 3 Cable segment 5...6 Subbus 3

Note

If you use the inter-FPGA communication bus only in one direction, you can
specify the bit ranges of subbuses without limitations. You must consider
the limitations only if you send and receive data with the same inter-FPGA
interface.

Bit ranges supported by the The following table shows which cable segment supports which bit range:
cable segments
Cable Segment Bit range
1 0 ... 5
2 6 ... 7
3 8 ... 13
4 14 ... 19
5 20 ... 21
6 22 ... 27

Method To determine the bit ranges for inter-FPGA subbuses between SCALEXIO
FPGA base boards
1 Choose one continuous range of cable segments that can be used to send
data and one continuous range that can be used to receive data. The
ranges must not overlap. For examples, refer to Configuration examples on
page 113.
2 Identify the bit range that is supported by the chosen cable segment range
for sending data. This bit range can be used by subbuses to send data.
For example: The cable segments 1 ... 3 support the bit range 0 ... 13.

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3 Use the identified bit range to determine the bit ranges of subbuses to
send data. You can determine multiple subbuses, as shown by Example 2 on
page 113.
4 Identify the bit range that is supported by the chosen cable segment range
for receiving data. This bit range can be used by subbuses to receive data.
5 Use the identified bit range to determine the bit ranges of subbuses to
receive data.

Result You determined the bit ranges of the subbuses.

Next step Add the I-FPGA In and I-FPGA Out function blocks to the FPGA model to
implement the inter-FPGA communication and configure their start and end bits
with the determined bit ranges.

Configuration examples The examples help you configure the bit ranges of your subbuses and show you
possible configuration errors.

Example 1 The following table shows you an example for bit ranges of two
subbuses.

Bus Direction Chosen Cable Segments Configured Subbuses

Segment Range Resulting Bit range for Subbuses I/O Function Block Start Bit End Bit
Sending data 1 ... 3 0 ... 13 I-FPGA Out 0 8
Receiving data 4 ... 6 14 ... 27 I-FPGA In 14 22

Example 2 The following table shows you an example for bit ranges of four
subbuses.

Bus Direction Chosen Cable Segments Configured Subbuses

Segment Range Resulting Bit range for Subbuses I/O Function Block Start Bit End Bit
Sending data 1 ... 2 0 ... 7 I-FPGA Out 0 4
I-FPGA Out 5 6
Receiving data 3 ... 6 8 ... 27 I-FPGA In 8 16
I-FPGA In 19 27

Example 3 (unsupported configuration) The following table shows you an

example of an unsupported configuration of two subbuses.

Configured Subbuses Bus Affected Resulting Conflict

Direction Cable
I/O Function Start End
Segments
Block Bit Bit
I-FPGA Out 0 8 Sending data 1 ... 3 Cable segment 3 is used in both directions, but
I-FPGA In 9 17 Receiving 3 ... 4 one cable segment can be used either to send
data data or to receive data.
Remedy: Use the bit range 14 ... 22 for the
I‑FPGA In function block.

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Example 4 (unsupported configuration) The following table shows you an

example of an unsupported configuration of three subbuses.

Configured Subbuses Bus Affected Resulting Conflict

Direction Cable
I/O Function Start End
Segments
Block Bit Bit
I-FPGA Out 0 4 Sending 1 More than two segment ranges are affected by the
data subbuses.
I-FPGA In 8 12 Receiving 3 Remedy: Use cable segment 6 for the I‑FPGA In
data function block and cable segment 3 for the I‑FPGA
Out function block. Thus cable segment range 1 ... 3
I-FPGA Out 22 26 Sending 6
is used to send data and cable segment 6 is used to
data
receive data.

Related topics References

Block Settings for the Inter-FPGA Interface Framework (FPGA Programming Blockset
- FPGA Interface Reference )

Calculating the Data Rate and Latency (SCALEXIO)

Calculating data rate The data rate of an inter-FPGA (sub)bus depends on the block settings for the
clock, the bit length and the data width.

DataRateMax = I-FPGA_Clock · (DataWidth ‑ 1) / BitLength

Resulting data rate for data transfer with bus synchronization The
maximum data rate with the default values is 562.5 Mbit/s for the entire bus
or 20.83 Mbit/s per bit.
DataRateMax,Bus = 125 MHz · (28 ‑ 1) Bit / 6
DataRateMax,Bit = 125 MHz · 1 Bit / 6

Resulting data rate for data transfer without bus synchronization The
maximum data rate with the default values is 582.3 Mbit/s for the entire bus or
20.83 Mbit/s per bit.
DataRateMax,Bus = 125 MHz · 28 Bit / 6
DataRateMax,Bit = 125 MHz · 1 Bit / 6

Calculating latency The latency consists of a constant value and dependencies on the clock rate of
the inter-FPGA bus, filter depth, and on whether jitters and spikes occur.

General formula for the latency:

Latency = TI-FPGA Out + Tinter-FPGA Master + Tinter-FPGA Slave + TI-FPGA In

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The formula use the following parameters:

TI-FPGA Out: Latency of the I‑FPGA Out FPGA function.

TI-FPGA Out = 8 ns

Tinter-FPGA Master: Latency of the inter-FPGA component to write data to the inter-FPGA bus.
Tinter-FPGA Master = ClockPeriodinter-FPGA · 2 ClockCycles

Tinter-FPGA Slave: Latency of the inter-FPGA component to read data from the inter-FPGA bus.

Tinter-FPGA Slave depends on the filter depth, and jitter and spikes on the bus lines:

§ Filter depth = 0, no jitter and spikes on the bus lines:

Tinter-FPGA Slave = ClockPeriodinter-FPGA · 4 ClockCycles

§ Filter depth = 0 and jitter occurs:

Tinter-FPGA Slave = ClockPeriodinter-FPGA · (4 + 1) ClockCycles

§ Filter depth >0, no jitter and spikes on the bus lines:

Tinter-FPGA Slave = ClockPeriodinter-FPGA · (3 ClockCycles + FilterDepth)

§ Filter depth >0 and jitter occurs:

Tinter-FPGA Slave = ClockPeriodinter-FPGA · (3 ClockCycles + (FilterDepth + 1))

§ Filter depth >0 and jitter and spikes on the bus lines:
Tinter-FPGA Slave = ClockPeriodinter-FPGA · (3 ClockCycles +
(FilterDepth + 1 + [0 … FilterDepth]))
With the range [0 … FilterDepth] as the latency caused by spikes.

TI-FPGA In: Latency of the I‑FPGA In FPGA function.

TI-FPGA In = 8 ns

Latency calculation examples The following examples display the resulting latency for different applications.

Calculation example for an inter-FPGA bus in standard mode The clock

rate of the inter-FPGA bus is 125 MHz in standard mode and the filter depth is
set to 2:
§ Latency = 56 ns + FilterDepth · 8 ns
§ If jitter occurs: Latency = 56 ns + (FilterDepth + 1) · 8 ns
§ If spikes occur: Latency = 56 ns + (FilterDepth +
[0 … FilterDepth]) · 8 ns
§ Maximal: Latency = 64 ns + (2 · FilterDepth) · 8 ns
With the default values, the latency is in the range 72 ns … 96 ns.
LatencyMin = 56 ns + 2 · 8 ns = 72 ns
LatencyMax = 64 ns + (2 · 2)· 8 ns = 96 ns

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Calculation example for an inter-FPGA bus in expert mode

Note

Use the expert mode only if you have enough experience of configuring
buses and knowledge of checking the correctness of the configured
transmission with regard to the observed signal integrity at the applicable
temperature range.
The default values for the bit length, clock, and filter depth have been
tested by dSPACE.

The clock rate of the inter-FPGA bus is set to 250 MHz.

§ If the filter depth is set to 0:
Latency = 40 ns
§ If jitter occurs: Latency = 44 ns
§ If the filter depth is set to >0:
Latency = 36 ns + FilterDepth · 4 ns
§ If jitter occurs: Latency = 36 ns + (FilterDepth + 1) · 4 ns
§ If spikes occur: Latency = 36 ns + (FilterDepth +
[0 … FilterDepth]) · 4 ns
§ Maximal: Latency = 40 ns + (2 · FilterDepth) · 4 ns
With the default values and a 250 MHz clock rate, the latency is in the range
44 ns … 56 ns.
LatencyMin = 36 ns + 2 · 4 ns = 44 ns
LatencyMax = 40 ns + (2 · 2)· 4 ns = 56 ns

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Modeling FPGA Applications Supporting Multicore Processor

Applications
Introduction The FPGA Programming Blockset lets you model FPGA applications that support
multicore processor applications. There are some aspects you have to consider
when you model an FPGA application with multicore support.

Where to go from here Information in this section

Aspects on FPGA Applications Supporting Multicore Processor

Applications.......................................................................................... 117
You have to consider some aspects when you model an FPGA application
with multicore support.

How to Select Subsystems for Multicore Support (MicroLabBox II,

MicroAutoBox III, SCALEXIO)................................................................. 119
To support a multicore processor application with your FPGA application,
you have to select the subsystems of the FPGA model that are connected
to the different processor cores.

Aspects on FPGA Applications Supporting Multicore Processor Applications

Platforms for FPGA FPGA applications of MicroLabBox, MicroLabBox II, MicroAutoBox III and
application with multicore SCALEXIO systems can support multicore processor applications (multicore real-
support time applications).

Multicore support for There are no special aspects you have to consider when you are modeling an
MicroLabBox FPGA application with multicore support. Keep in mind, that the assignment
to the processor interface must be unique. You cannot access the same FPGA
interface block from different processor interface blocks.

Multicore support ConfigurationDesk lets you implement and build processor applications for
for MicroLabBox II, MicroLabBox II, MicroAutoBox III, and SCALEXIO systems. In ConfigurationDesk,
MicroAutoBox III, and model port blocks represent the interfaces of processor models and FPGA
SCALEXIO systems function blocks represent the FPGA application. Model port blocks let you
connect FPGA function blocks with the processor model, but model port blocks
that reside in different processor models must not be mapped to the same
function block as shown below.

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Function block Model port block

Model A

Model B

However, a multicore processor application is built from different processor

models (behavior models in ConfigurationDesk), so there must be one processor
model for each processor core. Therefore, the FPGA application can be
represented by several FPGA custom function block types. This lets you use one
FPGA application by model port blocks that reside in different processor models.

Specifying the representation of FPGA applications The FPGA custom

function block types are defined by XML files during the build process of the
FPGA. To specify which parts of the FPGA model are represented by one FPGA
custom function block type, you can select subsystems of the FPGA model.
For instructions on selecting the subsystems so that the build process generates
several FPGA custom functions, refer to How to Select Subsystems for Multicore
Support (MicroLabBox II, MicroAutoBox III, SCALEXIO) on page 119.

Modeling FPGA applications with multicore support You cannot access

one subsystem and its subelements of the FPGA model from several processor
models, but several subsystems of the FPGA model can access the same
processor model. Therefore, implement subsystems to your FPGA in the way that
the FPGA interface of one subsystem provides the access for only one processor
model. The following illustration shows this modeling rule.

FPGA model

Subsystem 1 Processor model core A

Subsystem 2

Processor model core B

Subsystem 3

The following illustrations show FPGA interfaces that are not supported in
ConfigurationDesk.

FPGA model

Processor model core A

Subsystem 1

Processor model core B

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FPGA model

Subsystem 1 Processor model core A

Subsystem 1_1 Processor model core B

Related topics Basics

Modeling FPGA Applications Supporting Multicore Processor Applications.............................. 117

References

GetMCSubsystems (FPGA Programming Software Script Interface Reference )

SetMCSubsystems (FPGA Programming Software Script Interface Reference )

How to Select Subsystems for Multicore Support (MicroLabBox II,

MicroAutoBox III, SCALEXIO)

Objective To support a multicore processor application of a MicroLabBox II,

MicroAutoBox III, or a SCALEXIO system with your FPGA application, you have
to select the subsystems of the FPGA model that are connected to the different
processor cores.

Aspects on modeling Refer to Aspects on FPGA Applications Supporting Multicore Processor

multicore support Applications on page 117.

FPGA application with To support multicore processor applications, at least three function block
multicore support in types represent the entire FPGA application in ConfigurationDesk. The
ConfigurationDesk separation of the FPGA application into one FPGA Setup function block type
(<application name>_Setup) and at least two FPGA custom function block
types let you use one FPGA application by at least two processor models
(behavior models in ConfigurationDesk).

In ConfigurationDesk, the FPGA Setup function block lets you configure and
initialize the access to the FPGA base board. At least two FPGA custom function
blocks provide the interfaces to map different processor models and external
devices.

Representation in ConfigurationDesk The following illustration shows you

an FPGA application in ConfigurationDesk that is mapped to the processor

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models of the different processor cores (behavior models) and assigned to the
FPGA Setup block.

Logical signal chain

FPGA custom function A Model A

Block of behavior
model A

assigned to

FPGA custom function B Model B

Block of behavior
model B

assigned to

FPGA Setup

Precondition The FPGA interface is implemented to the FPGA model.

Possible methods You can use the following methods to select the subsystems for multicore
support:
§ Using tags. Refer to Method 1.
§ Selecting the subsystems in a tree view. Refer to Method 2.

Method 1 To select subsystems for multicore support by using tags

1 Open the context menu of the subsystem that provide blocks of the
FPGA interface to a processor core (FPGA_XDATA_WRITE_BL blocks,
FPGA_XDATA_READ_BL blocks, and FPGA_INT_BL blocks).

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2 Enter the Tag property fpgafunction=1 and click OK.

Method 2 To select subsystems for multicore support in a tree view

1 On the top level of the FPGA model, double-click the FPGA_SETUP_BL
block and open the Interface tab.
2 In the tree view, click the subsystem that provide blocks of the
FPGA interface to a processor model (FPGA_XDATA_WRITE_BL blocks,
FPGA_XDATA_READ_BL blocks, and FPGA_INT_BL blocks).
You select the subsystem and all subelements. The selected subelements are
not click-able.
3 Repeat step 2 until you selected all other subsystems providing blocks of an
FPGA interface to a processor model.

Result The Interface tab of the FPGA_SETUP_BL block dialog displays the number of
function block types that will be defined by the build process. The tree view
grouped the subsystems according to the FPGA custom function block types
they belong to. The top level of the FPGA model and all unselected subsystems
belong to one FPGA custom function block.

The following example shows you which FPGA custom function block type
represents which part of the FPGA model.

Tree-View Resulting Function Block Types Represented Subsystems

DS2655_Multicore § DS2655_Multicore
§ Subsystem1
§ Subsystem5
DS2655_Multicore_Subsystem2 § Subsystem2
DS2655_Multicore_Subsystem3 § Subsystem3
§ Subsystem3_1
§ Subsystem3_1_1

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Tree-View Resulting Function Block Types Represented Subsystems

DS2655_Multicore_Subsystem4 § Subsystem4
DS2655_Multicore_Setup —

Related topics Basics

Modeling FPGA Applications Supporting Multicore Processor Applications.............................. 117

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Modeling MGT Communication Using a Customized Protocol

Introduction A DemoFPGAurora8b10b demo project (Aurora 8b10b demo) for SCALEXIO
systems shows how to implement a customized protocol.

Where to go from here Information in this section

Basic Structure of the MGT Interface..................................................... 123

Basic components of the FPGA base boards to support the MGT
communication bus.

Customized Protocol Demo (SCALEXIO)................................................. 124

Using a demo to implement a customized protocol.

Notes on Implementing Customized Protocols....................................... 128

General notes to avoid problems when customizing protocols.

Basic Structure of the MGT Interface

Block diagram of the The MicroLabBox II, DS6601 FPGA Base Board, and the DS6602 FPGA Base
interface Board provide a connector to insert an optical adapter for MGT (MGT module).
The following illustration shows the basic components to support the MGT
communication bus.

FPGA base board

Reference
GTH transceiver clock
(master)
GTH transceiver
FPGA (slave 1)
MGT module
GTH transceiver
(slave 2)
GTH transceiver
(slave 3)

Components description The following table shows the description of the components.

Component Description
FPGA The FPGA processes the build FPGA application.
GTH The GTH transceivers are configurable transceivers that are integrated with the logic resources of
transceiver the FPGA. The GTH transceivers support line rates from 500 Mbit/s … 16.375 Gbit/s. The master

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Component Description
transceiver receives the differential reference clock signal and provide it to the slave transceivers.
Master or slave has no influence on the MGT communication.
The GTH transceivers can be configured by the FPGA application to support different protocols, line
rates, etc.
For details on the GTH transceiver, refer to
https://www.xilinx.com/support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf.
Reference This clock provides the configured reference frequency for the GTH transceivers.
clock
MGT module The MGT module is an optical adapter that can be connected to the FPGA base board. The MGT
module provides four channels for communication.
The order number of the SCALEXIO MGT modules are as follows:
§ DS6601_MGT1 for the DS6601 FPGA Base Board.
§ DS6602_MGT1 for the DS6602 FPGA Base Board.
For MicroLabBox II, the recommended and tested MGT module is the QSFP28-SR4-100G module
manufactured by FS (https://www.fs.com)

Related topics Basics

Overview of the DS6601 FPGA Base Board (SCALEXIO Hardware Installation and
Configuration )
Overview of the DS6602 FPGA Base Board (SCALEXIO Hardware Installation and
Configuration )

References

MGT Characteristics (MicroLabBox II Hardware Installation and Configuration )

Customized Protocol Demo (SCALEXIO)

Supported platforms MGT communication is supported by SCALEXIO systems with a DS6601 or

DS6602 FPGA Base Board with an installed MGT module.

Accessing the demo Open the block library and select Demos – DemoFPGAurora8b10b –
DS6601_XCKU035 or DS6602_XCKU15P.

Use case The Aurora8b10b demo uses a customized transfer protocol to send data values
in a loop via the MGT interface. The customized transfer protocol is the Aurora
8b10b protocol for data transmission.

The demo measures the latency, lets you inject errors and provides
status information about the communication bus. Backup projects for
ConfigurationDesk and ConrolDesk let you directly experiment with the demo.

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Demo overview The following table shows the top level of the Simulink model with the
subsystems.

Subsystem Description
AURORA 8b10b Provides the interface and configuration of the GTH transceiver to support a
customized protocol.
For more information, refer to AURORA 8b10b subsystem on page 126.

CN interface Provides the interface to the processor model.

The subsystem writes the following status information of the protocol lanes to the
processor model:
§ RX_COUNTER: Number of received data values.
§ TX_COUNTER: Number of transmit data values.
§ LATENCY: Measured latencies.
§ ERROR_COUNTER: Number of detected hard errors.
§ SOFT_ERROR: Number of detected soft errors.
§ AURORA_FLAGS: Bit-coded protocol information.
The subsystem reads the following values from the processor model:
§ RESETN: Flag to enable the GTH transceiver.
§ ENABLE_TX: Flags to enable the different protocol lanes.
§ SKIP: Flags to skip the data transmission for the different protocol lanes. The flags
can be used to control the fill level of the FIFO buffers.
§ ERROR_INJECTION: Flags to inject errors in the data transmission for the different
protocol lanes.
§ TX_LAST: Flags to indicate the last data value to be transmitted for the different
protocol lanes.
Lane 1 … 4 Controls the data transfer.
The subsystem provides the following features:
§ Generates the data values and detects transmission errors. The data values are the
output of an incrementing counter.
§ Enables and resets the counter.
§ Delays the transmission of data values.
Latency 1 … 4 Calculates the latency to send and receive data values over an optical loop.

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AURORA 8b10b subsystem The following illustration shows the components of the AURORA 8b10b
subsystem.

Block Description
Black Box1) Instantiates the GTH transceivers and defines the used transfer protocol.
The MGT module provides four channels for communication. Each channel is connected to one
GTH transceiver.
To customize the protocol, the Black Box must be changed.
MGT In Receives the provided data from the MGT module and lets you specify the reference clock
frequency.
MGT In is a block of the FPGA Programming Blockset.
MGT In Indicates whether the MGT module is ready for data exchange.
Opto Ready MGT In Opto Ready is a block of the FPGA Programming Blockset.
MGT Out Outputs the provided data to the MGT module.
MGT Out is a block of the FPGA Programming Blockset.
1) HDL library of the AMD Vitis Model Composer

Using a customized protocol You can use the IP Catalog of Vivado to customize a predefined protocol.
The IP Catalog provides a list of IP cores that can be customized. For more
information, refer to https://docs.xilinx.com/r/en-US/ug896-vivado-ip.

The IP Catalog lets you generate a net list that you can integrate in a Black Box.
You can also include optional features like FIFOs for the inports and outports, or
a reset logic for the GTH transceiver.

Required settings The following parameters depend on the FPGA base board and must be set to a
specific value in the VHDL file:
§ The low power mode of the equalizer must be enabled.
gt_rxlpmen => (others => '1')

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§ The differential swing voltage must be set to board-specific value:

§ DS6601: 460 mVpp (peak-to-peak voltage)
gt_txdiffctrl => "0100"
§ DS6602: 498 mVpp
gt_txdiffctrl => "01010"

Provided demo files The table shows the files that are provided with the demo. You can use these
files to experiment with the demo, to change the demo, or to specify a new
Black Box.

File Name Description

Files for Experimenting
CD_DemoFPGAAurora8b10b.ZIP Provides a ControlDesk project to experiment with the demo.
CFG_DemoFPGAAurora8b10b.ZIP Provides a ConfigurationDesk project including a build real-time
application.
Files for Changing the Demo
DemoFPGAAurora8b10b.slx Provides the FPGA model.
aurora_8b10b_top_config_ds6601.m Provides the configuration for the Black Box.
aurora_8b10b_top_config_ds6602.m The file name must match the FPGA base board used.
aurora_8b10b_top.vhd Provides the top level design entry for the Black Box.
aurora_8b10b_top_sim.vhd Provides a dummy design for the Black Box for offline simulation.
The outports of the Black Box are set to 0 during offline simulation to
avoid error messages concerning the data types.
aurora_8b10b_master.edn Provides the Aurora master net list.
The master net list is used to instantiate the GTH master transceiver.
aurora_8b10b_slave.edn Provides the Aurora slave net list.
The slave net list is used to instantiate the three GTH slave transceivers.
axis_fifo.edn Provides the net list of the added FIFOs.
FIFOs are implemented to the Black Box for buffering. Four FIFOs for
reception and four FIFOs for transmission are used in total.

Related topics Basics

Basic Structure of the MGT Interface...................................................................................... 123

Notes on Implementing Customized Protocols........................................................................ 128

HowTos

How to Use a Customized Clocking Circuit as Clock Domain Source......................................... 84

References

Block Settings for the DS660X_MGT Framework (FPGA Programming Blockset -

FPGA Interface Reference )

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Notes on Implementing Customized Protocols

File ending of net lists The file ending of net list files must be .edn if you use net lists for the Black Box
from the HDL library of the AMD Vitis Model Composer.

Offline simulation of the During offline simulation, the data types of the Black Box outports can lead to
Black Box error messages.

To avoid the error messages, you can provide a dummy design with the outports
set to 0 for offline simulation. The aurora_8b10b_top_sim.vhd file of the
Aurora8b10b demo is an example for such a dummy design.

Aurora-specific transmission The last frame of a Aurora transmission must be flagged, for example, with the
TX_LAST flag in the Aurora8b10b demo.

The receiver outputs a frame when it receives a new frame. If the last frame is
not flagged, the frame remains in the memory of the receiver.

Using a user clock domain for If you are using a clock domain that is synchronous to the GTH transceivers, you
MGT communication must add the MGT In Opto Ready block outside the subsystem into a clock
domain at the base rate of the FPGA.

For more information on using multiple clock domains, refer to Using Multiple
Clock Domains for FPGA Modeling on page 78.

Related topics Examples

Customized Protocol Demo (SCALEXIO).................................................................................. 124

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Modeling the Communication Between the FPGA

and the Real-Time Processor

Introduction You must implement interfaces to the FPGA model and the processor model to
exchange data between the FPGA application and the processor application.

Where to go from here Information in this section

Modeling Processor Model Access......................................................... 130

You have to implement the interface to the board-specific bus to access
the processor application.

Implementing the Processor Interface to the Processor Model................ 148

The processor interface is the counterpart of the FPGA interface
to exchange data between the processor application and the FPGA
application.

Preprocessing and Postprocessing the Signals Between the FPGA

and the Processor Model....................................................................... 155
The MicroLabBox II, MicroAutoBox III, and SCALEXIO blocksets support
scaling subsystems to preprocess and postprocess the signals between
the FPGA model and the processor model.

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Modeling Processor Model Access

Introduction You have to implement the interface to the board-specific bus to exchange data
with the processor application and to trigger interrupts.

Where to go from here Information in this section

Implementing the FPGA Functionality for Processor

Communication..................................................................................... 130
Different FPGA interfaces let you access the local bus for data exchange
or triggering processor tasks.

Using Simulink Buses for Modeling the Processor Communication......... 135

The MicroLabBox II, MicroAutoBox III, and SCALEXIO blocksets support
Simulink buses to implement the communication between the real-time
processor and the FPGA application.

Implementing the FPGA Functionality for Processor

Communication
Introduction Different FPGA interfaces let you access the local bus for data exchange or
triggering processor tasks.

Where to go from here Information in this section

Exchanging Data With the Processor Model........................................... 130

The FPGA Programming Blockset provides blocks for exchanging data
between the FPGA subsystem and the processor model.

How to Trigger Interrupt-Driven Processor Tasks..................................... 134

Gives you instructions how to trigger an asynchronous task by the FPGA
application.

Exchanging Data With the Processor Model

Introduction The FPGA Programming Blockset provides blocks for exchanging data between
the FPGA subsystem and the processor model.

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Basics on the processor The data is exchanged via the communication line between MicroLabBox's
communication using base board and the I/O FPGA module mounted on the DS1302 board.
MicroLabBox/MicroLabBox II For MicroLabBox, communication runs via the local bus. For MicroLabBox II,
communication runs via IOCNET.

The 32‑bit parallel data bus enables a complete 32‑bit word to be transferred in
a single operation. For transferring a 64‑bit word, two operations are internally
required.

The data is transmitted via the local bus to specific data storage areas. The
implementation details of these storage areas are defined in the framework.

Data Data Data Storage Size Data Format

Storage Width
Area
Register 32 bit 256 32-bit registers Can be specified to fixed-point or floating-point format.
64 bit and 256 64-bit § Fixed-point format:
registers Signed or unsigned data format with adjustable binary point
Buffer 32 bit 32 32-bit buffers and position.
64 bit 32 64-bit buffers MicroLabBox: 64-bit fixed-point data types are converted to double.
Each buffer with up to Therefore, the fixed-point resolution of fixed-point data types is
32,768 elements restricted to 53 bits.
MicroLabBox II: 64-bit fixed-point data types are converted to
double, except the data type without a binary point (binary point
position = 0). Therefore, the fixed-point resolution of fixed-point
data types with a binary point (binary point position > 0) is restricted
to 53 bits.1)
§ 32-bit floating-point format:
Single precision (IEEE 754 standard) data format with a fraction
width of 24.
§ 64-bit floating-point format:
Double precision (IEEE 754 standard) data format with a fraction
width of 53.
1) The default data type of generated processor interface blocks is always double. To use
the full resolution of a 64-bit fixed-point data type, you have to set the data type of the
generated blocks to int64 or uint64. Refer to How to Transfer 64-Bit Fixed-Point Data
with Full Resolution (MicroLabBox II, SCALEXIO) on page 152.

Basics on the processor The data is exchanged via the communication line between the real-time
communication using processor of the MicroAutoBox II/III and the FPGA module mounted on the
MicroAutoBox II/III DS1514 I/O board. The communication runs via the intermodule bus of the
MicroAutoBox II/IIII.

The 16‑bit parallel data bus enables a complete 16‑bit word to be transferred in
a single operation.

The data is transmitted via the intermodule bus to specific data storage areas.
The implementation details of these storage areas are defined in the framework.

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Data Data Data Storage Size Data Format

Storage Width
Area
Register 32 bit 128 32‑bit registers and Can be specified to fixed-point or floating-point format.
64 bit 128 64‑bit registers § Fixed-point format:
Signed or unsigned data format with adjustable binary point
Buffer 32 bit 32 32‑bit buffers and
position
64 bit 32 64‑bit buffers
64-bit fixed-point data types are converted to double. Therefore,
Each buffer with up to
the fixed-point resolution of fixed-point data types is restricted to
32,768 elements
53 bits.
§ 32-bit floating-point format:
Single precision (IEEE 754 standard) data format with a fraction
width of 24
§ 64-bit floating-point format:
Double precision (IEEE 754 standard) data format with a fraction
width of 53

Basics on the processor The internal communication between the real-time processor and a SCALEXIO
communication using a FPGA base board runs via IOCNET (I/O carrier network). IOCNET lets you connect
SCALEXIO system more than 100 I/O nodes and even place the parts of your SCALEXIO system
long distances apart. IOCNET is dSPACE's proprietary protocol that gives you
real-time performance plus time and angular clocks.

The data is transmitted via IOCNET to specific data storage areas. The
implementation details of these storage areas are defined in the framework.

Data Data Data Storage Size Data Format

Storage Width
Area
Register 32 bit 256 32-bit registers Can be specified to fixed-point or floating-point format.
64 bit and 256 64-bit § Fixed-point format:
registers Signed or unsigned data format with adjustable binary point
Buffer 32 bit 32 32-bit buffers and position.
64 bit 32 64-bit buffers 64-bit fixed-point data types are converted to double, except the
Each buffer with up to data type without a binary point (binary point position = 0).
32,768 elements Therefore, the fixed-point resolution of fixed-point data types with a
binary point (binary point position > 0) is restricted to 53 bits.1)
§ 32-bit floating-point format:
Single precision (IEEE 754 standard) data format with a fraction
width of 24.
§ 64-bit floating-point format:
Double precision (IEEE 754 standard) data format with a fraction
width of 53.
1) The default data type of generated processor interface blocks is always double. To use
the full resolution of a 64-bit fixed-point data type, you have to set the data type of the
generated blocks to int64 or uint64. Refer to How to Transfer 64-Bit Fixed-Point Data
with Full Resolution (MicroLabBox II, SCALEXIO) on page 152.

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Access types You can select different access types for data exchange.

Register access type If you have to exchange certain data and high
performance is not required, it is recommended to use the register access type.

Note

Notes only for MicroLabBox II, MicroAutoBox III, and SCALEXIO:

§ Any specified register that does not belong to a group is automatically
collected in one single group called Ungrouped in the FPGA custom
function built for ConfigurationDesk. There is one group for register input
data and one group for register output data. Independently of the groups
specified in your FPGA model, the ungrouped registers are automatically
grouped in the Simulink model tasks in ConfigurationDesk to increase the
performance of IOCNET transfers.
§ You can access a register group by one task only.

Buffer access type If you have to exchange a lot of data with high
performance, it is recommended to use the buffer access type. However, to
access a specific data item within the buffer, you have to address it explicitly.

Bus access type The bus access type lets you use Simulink buses to model the
data exchange between the processor and the FPGA. The bus access type uses
buffer to exchange data.
The bus access type is available only for MicroLabBox II, MicroAutoBox III, and
SCALEXIO.

Read/write blocks in the FPGA You can use the FPGA_XDATA_READ_BL block from the FPGA Interface
subsystem library to read data from the processor bus, and the FPGA_XDATA_WRITE_BL
block to write data to the board-specific bus.

The values in the FPGA subsystem are processed as fixed-point values. The data
exchange with the processor model requires data type conversion between fixed-
point and floating-point values. Automatic data conversion is implemented in
these blocks. The fixed-point format to be used can be set in the blocks' dialogs.

Tip

You can copy & paste previously configured interface blocks of the FPGA
Programming Blockset. The blockset automatically analyzes the FPGA model
and reassigns new hardware resources.
You can speed up the copy & paste process for the current
session by deactivating the automatic reassignment of new hardware
resources. Open the Advanced Preferences dialog and set the
PASTE_KEEP_CHANNEL_NUM preference to false. Refer to Dialog
Settings of the Advanced Preferences Dialog (FPGA Programming Blockset -
FPGA Interface Reference ).

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Read/write blocks in the The Processor Interface library of the FPGA Programming Blockset provides the
processor model PROC_XDATA_READ_BL and PROC_XDATA_WRITE_BL blocks to read data
from and write data to the board-specific bus. These blocks must be configured
as counterparts to the related blocks in the FPGA subsystem. The simplest way to
create and configure these blocks in the processor model is to use the Generate
command.

For instructions, refer to How to Generate a Processor Interface on page 148.

Related topics Basics

Modeling Processor Model Access.......................................................................................... 130

How to Trigger Interrupt-Driven Processor Tasks

Objective You can use an output signal from the FPGA application to trigger an
asynchronous task in the processor model.

Basics As with the other interface blocks from the FPGA Programming Blockset, you
need an interrupt block in the FPGA subsystem and its counterpart in the
processor model to trigger a function-call subsystem by a value coming from
the FPGA.

Method To trigger an interrupt-driven processor task

1 Add an FPGA_INT_BL block to the FPGA subsystem.
2 Double-click the block to open its dialog.
3 Specify a channel number and enter a descriptive channel name.
4 Connect the Int inport with the signal that you want to use for triggering a
task in the processor model.

Result When the FPGA_INT_BL block in the FPGA subsystem receives the specified
data, it is transferred to the processor model.

Next steps After you implemented the processor interface, you connect the processor
interface block to a function-call subsystem in the processor model. For
instructions on implementing the processor interface, refer to Implementing the
Processor Interface to the Processor Model on page 148.

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Examples The following example shows the resulting processor model implementation of
an interrupt-driven task.

Related topics Basics

Modeling Processor Model Access.......................................................................................... 130

Using Simulink Buses for Modeling the Processor

Communication
Introduction The MicroLabBox II, MicroAutoBox III, and SCALEXIO blocksets support Simulink
buses to implement the communication between the real-time processor and the
FPGA application.

Where to go from here Information in this section

How to Use Simulink Buses of the FPGA Model to Model

Processor Communication..................................................................... 136
Modeling the processor interface on the basis of Simulink buses of the
FPGA model.

How to Use Simulink Buses of the Processor Model to Model the

Processor Communication..................................................................... 138
Modeling the processor interface on the basis of Simulink buses of the
processor model.

How to Specify the Data Type Conversion for Processor

Communication..................................................................................... 141
Specifying the data type conversion between the processor model and
the FPGA model, for example, after you copied the bus topology from a
corresponding processor block.

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How to Change the Bus Topology of a Simulink Bus.............................. 142

Adding or deleting signals/subbuses or changing the signal order of
Simulink buses used for processor communication.

How to Configure the Bus Data Transmission Method........................... 144

Configuring the method for writing data to the processor application
when using a Bus Out block.

Using Subchannels for Data Exchange................................................... 146

Using a single buffer to exchange data via several Simulink buses.

Notes on Handling Simulink Buses......................................................... 147

Simulink tools that support the handling of buses.

How to Use Simulink Buses of the FPGA Model to Model Processor

Communication

Objective Modeling the processor interface on the basis of Simulink buses of the FPGA
model.

Platforms supporting data The following platforms support the use of Simulink buses for modeling the data
exchange via Simulink buses exchange with the processor interface:
§ MicroLabBox II
§ MicroAutoBox III
§ SCALEXIO

Methods Depending on the data direction, refer to one of the following methods:
§ To write data to the processor model, refer to Method 1.
§ To read data from the processor model, refer to Method 2.

Method 1 To use a Simulink bus of the FPGA model to write data to the processor
model
1 Add an FPGA_XDATA_WRITE_BL block to the FPGA model.
2 Open the Unit page of the block dialog and select the Bus access type.
3 Connect the Simulink bus to the Data inport.
4 Press Ctrl + D to update the model.
5 On the Parameters page, click Analyze bus topology of input.
The FPGA Programming Blockset analyzes the connected Simulink bus and
configures the Data inport.

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Method 2 To use a Simulink bus of the FPGA model to read data from the processor
model
1 Add a FPGA_XDATA_READ_BL block to the FPGA model.
2 Open the Unit page of the block dialog and select the Bus access type.
3 If the Simulink bus is not already implemented in the FPGA model,
implement a temporary Simulink bus:
§ Add a Simulink Bus Creator block to the FPGA model.
§ Connect FPGA blocks to the input with matching data types, for example,
Counter blocks from the HDL library of the AMD Vitis Model Composer.
4 Press Ctrl + D to update the model.
5 Select the Simulink bus to be copied by selecting a Bus Creator block,
subsystem inport block, or subsystem outport block.
6 On the Parameters page, click Copy bus topology from gcb.
The FPGA Programming Blockset analyzes the selected Simulink bus and
configures the Data outport.
7 You can delete the temporary Simulink bus from step 3.

Result You modeled the processor communication with Simulink buses. The buffer
block displays the used subchannel and the number of signals that must be
connected to the Data port. The following example shows a Bus In block.

Next step To use the Simulink bus in the processor model, open the Unit page and click
Generate. The generated processor interface use the same Simulink.bus object
as the Bus In/Bus Out block.

Related topics Basics

Exchanging Data With the Processor Model............................................................................ 130

Notes on Handling Simulink Buses.......................................................................................... 147

HowTos

How to Change the Bus Topology of a Simulink Bus............................................................... 142

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References

AnalyzeFPGAXDATAWriteBus (FPGA Programming Software Script Interface

Reference )
CopyFPGAXDATAReadBus (FPGA Programming Software Script Interface
Reference )
GetFPGAXDATABusSettings (FPGA Programming Software Script Interface
Reference )
ResetFPGAXDATABus (FPGA Programming Software Script Interface Reference )
SetFPGAXDATABusSettings (FPGA Programming Software Script Interface
Reference )

How to Use Simulink Buses of the Processor Model to Model the Processor
Communication

Objective Modeling the processor interface on the basis of Simulink buses of the processor
model.

Platforms supporting data The following platforms support the use of Simulink buses for modeling the data
exchange via Simulink buses exchange with the processor interface:
§ MicroLabBox II
§ MicroAutoBox III
§ SCALEXIO

Methods Depending on the data direction, refer to one of the following methods:
§ To write data to the processor model, refer to Method 1.
§ To read data from the processor model, refer to Method 2.

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Method 1 To use a Simulink bus of the processor model to write data to the
processor model
1 Open the Signal Configurations page of the Data Inport block dialog that
is connected to a Simulink bus.

2 Select the root signal and check the Type signal property.

If the Type property is set to untyped, click to assign a Simulink.Bus

object that matches the signal configuration of the selected signal. If no
matching Simulink.Bus object exists in the base workspace or the model's
Data Dictionary, the Model Interface Package for Simulink creates this object
for temporary use and assigns it to the selected signal.
3 Open the Block Connections page and select Enable Block Connections.
4 Set Type to Bus and specify the channel and subchannel numbers to
transmit data from the FPGA model to the processor model.
5 Click Ok.
6 Add an FPGA_XDATA_WRITE_BL block to the FPGA model.
7 Open the Unit page of the block dialog and select Bus as Access type.
8 Specify the same channel and subchannel numbers as in step 4.
9 Open the Parameters page and click Copy bus topology from
corresponding processor block.
The Bus Out block creates its own Simulink.bus object based on the
copied bus topology and propagates the new Simulink.bus object to the
corresponding Data Inport block.
10 Click OK.

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Method 2 To use a Simulink bus of the processor model to read data from the
processor model
1 If not already implemented, add a Data Outport block from the Model
Interface Package for Simulink to the FPGA model and connect it to the
Simulink bus.
2 From the context menu of the Data Outport block, select Model Port
Blocks - Update Selected Outport block from Input Signals.
3 Open the Signal Configuration page of the Data Outport block dialog.

4 Select the root signal and check the Type signal property.

If the Type property is set to untyped, click to assign a Simulink.Bus

object that matches the signal configuration of the selected signal. If no
matching Simulink.Bus object exists in the base workspace or the model's
Data Dictionary, the Model Interface Package for Simulink creates this object
for temporary use and assigns it to the selected signal.
5 Open the Block Connections page and select Enable Block Connections.
6 Set Type to Bus and specify the channel and subchannel numbers to
transmit data from the processor model to the FPGA model.
7 Click Ok.
8 In the FPGA model, add an FPGA_XDATA_READ_BL block.
9 Open the Unit page of the block dialog and select the Bus access type and
specify the same channel and subchannel numbers as in step 6.
10 Open the Parameters page and click Copy bus topology from
corresponding processor block.
The Bus In block creates a new Simulink.bus object based on the copied bus
topology and automatically propagates the new Simulink.bus object to the
corresponding Data Outport block.
11 Click OK.

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Result You modeled the processor communication with Simulink buses. The bus block
displays the used subchannel and the number of signals that must be connected
to the Data port. The following example shows a Bus In block.

Next step In the FPGA model, change the data types of the signals to FPGA data types.
Refer to How to Specify the Data Type Conversion for Processor Communication
on page 141.

Related topics Basics

Exchanging Data With the Processor Model............................................................................ 130

Notes on Handling Simulink Buses.......................................................................................... 147
Using Subchannels for Data Exchange.................................................................................... 146

HowTos

How to Change the Bus Topology of a Simulink Bus............................................................... 142

How to Specify the Data Type Conversion for Processor Communication

Objective Specifying the data type conversion between the processor model and the FPGA
model, for example, after you copied the bus topology from a corresponding
processor block.

Basics Data transmitted from the processor to the FPGA is converted from the double
to an FPGA data type and vice versa. If processor communication is based on a
Simulink bus of the processor model, you have to specify the data types that are
used on the FPGA for each bus signal. Double is the default data type if you copy
the bus topology from a corresponding processor block.

Method To specify the data type conversion for processor communication

1 In the FPGA model, open the block dialog of the Bus In or Bus Out block
that is used by the Simulink bus you want to change.

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2 On the Parameters page, click Edit bus topology.

The bus editor dialog opens.

3 Select the signal to be changed in the Signals table.

4 In the Signal Properties table, specify the data type. For
more information on the properties, refer to Bus Editor Dialog
- FPGA_XDATA_READ_BL/FPGA_XDATA_WRITE_BL (FPGA Programming
Blockset - FPGA Interface Reference ).
5 Click Ok.

Result You specified the data type that is used in the FPGA model. Data values that are
exchanged between the processor and the FPGA are converted from the double
data type used in the processor application and the specified data type used in
the FPGA application.

How to Change the Bus Topology of a Simulink Bus

Objective Adding or deleting signals/subbuses or changing the signal order of Simulink

buses used for processor communication.

Method To change the bus topology of a Simulink bus

1 In the FPGA model, open the block dialog of the Bus In or Bus Out block
that is used by the Simulink bus you want to change.

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2 On the Parameters page, click Edit bus topology.

The bus editor dialog opens.

3 In the Signals table, use the buttons to add or delete bus signals.
For more information on the buttons, refer to Bus Editor Dialog
- FPGA_XDATA_READ_BL/FPGA_XDATA_WRITE_BL (FPGA Programming
Blockset - FPGA Interface Reference ).

To add a subbus, select a signal and click . A new signal is added to the
bus with the configuration of the selected signal and the data type of the
selected signal changes to the bus data type.
The following illustration shows the result.

4 Click Ok.

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Result You changed the Simulink bus in the FPGA model. The changes are automatically
propagated to the corresponding Data Inport/Data Outport block in the
processor model.

Related topics Basics

Using Subchannels for Data Exchange.................................................................................... 146

How to Configure the Bus Data Transmission Method

Objective Configuring the method for writing data to the processor application when
using a Bus Out block.

Supported platforms The platforms support different bus data transmission methods.
§ MicroLabBox II:
The Synchronous to Read_Req and the Free running methods.
§ MicroAutoBox III:
The Free running method.
§ SCALEXIO:
The Synchronous to task, the Free running, and the User acknowledged
methods.

Basics To transmit data from the FPGA to the processor, the processor application
makes a read request. The currentness of the transmitted data depends on the
bus data transmission method:
§ Synchronous to task method
Select this method to transmit data that is captured synchronously to the
processor task.
The FPGA application writes data to the swinging buffer when the processor
application makes a read request. After the data is written to the buffer, the
buffer swings and sends the data to the processor application.
§ Synchronous to Read_Req method
Select this method to transmit data that is captured synchronously to the read
request.
The FPGA application writes data to the swinging buffer when the processor
application makes a read request. After the data is written to the buffer, the
buffer swings and sends the data to the processor application.
§ Free running method
Select this method if the transmission time is crucial.

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The FPGA application continuously writes data to the swinging buffer. A read
request of the processor application immediately transmits the last complete
data set of the swinging buffer to the processor application.
§ User acknowledged method
Select this method to acknowledge the data to be transmitted to the processor
application, for example, to trigger the processing of some data before it is
transmitted to the processor application.
The FPGA application writes data to the swinging buffer when you
acknowledge the data with the Send_Ack port. After the data is written to
the buffer, the buffer swings and sends the data to the processor application.
You must acknowledge each data transmission request so that data transfer is
synchronous to the processor task, as with the Synchronous to task method.
A data transmission request that is not acknowledged by Send Ack leads to
task overrun in the processor application. A task overrun will be logged as an
I/O error in the Messages page of the . The FPGA buffer that caused the task
overrun will also be logged.

For more information on the swinging buffer, refer to Basics on Exchanging Data
Between Processor and FPGA on page 17.

Limitation The selected bus data transmission method applies to all subchannels of a
Bus Out channel. To use different bus data transmission methods, you must
use different Bus Out channels.

For more information on subchannels, refer to Using Subchannels for Data

Exchange on page 146.

Method To configure the bus data transmission method

1 Select the Bus Out block of subchannel 1.
Subchannel 1 is the default subchannel.
2 Open the Parameters page of the block dialog and select a bus data
transmission method.
3 Click Apply or OK.

Result You configured the bus data transmission method. If you use subchannels, the
selected method applies to all subchannels of the selected Bus Out channel.

Related topics Basics

Basics on Exchanging Data Between Processor and FPGA......................................................... 17

HowTos

How to Use Simulink Buses of the FPGA Model to Model Processor Communication.............. 136

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Using Subchannels for Data Exchange

Introduction The MicroLabBox II, MicroAutoBox III, and SCALEXIO frameworks support
subchannels to implement the communication between a task of the processor
application and the FPGA application.

With subchannels, you can use a single buffer to exchange data via several
Simulink buses. This gives you the flexibility of registers with the performance of
buffers with the support of Simulink buses.

Implementing subchannels After you enabled the bus transfer mode for a Bus Out/Bus In function, you can
set the buffer to a channel that is in use and select a different subchannel. You
have to add a Bus Out/Bus In function for each subchannel.

FPGA model Processor model (behavior model)

FPGA_ [Model name] _1_R64_1_1_000001 Simulink bus 1

Data Inport
Channel number: 1
Bus Out channel 1 Subchannel number: 1

Simulink bus 1 Subchannel 1 FPGA_ [Model name] _1_R64_1_2_000001 Simulink bus 2

Data Inport
Channel number: 1
Simulink bus 2 Subchannel 2
Subchannel number: 2

Simulink bus 3 Subchannel 3

FPGA_ [Model name] _1_R64_1_3_000001 Simulink bus 3
Data Inport
Channel number: 1
Subchannel number: 3
Internal bus

Observe the following requirements if you use subchannels:

§ Up to 256 subchannels can be used for each channel. Subchannel number 1
of a buffer channel must always be used, the other subchannels can be used
in any order.
§ In the processor model, all subchannels of the same buffer channel must be
implemented to the same application process.

Related topics HowTos

How to Use Simulink Buses of the FPGA Model to Model Processor Communication.............. 136
How to Use Simulink Buses of the Processor Model to Model the Processor
Communication...................................................................................................................... 138

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Notes on Handling Simulink Buses

Using Simulink data The FPGA Programming Blockset can use a data dictionary instead using the
dictionaries base workspace for the bus elements.

Using models that are linked to data dictionaries If the model is already
linked to a data dictionary, the FPGA Programming Blockset automatically uses
this data dictionary for the bus elements.

Migrating to data dictionaries To use a data dictionary instead the base

workspace, create a data dictionary, link it to the model, and import the bus
elements from the base workspace into this data dictionary.
Alternatively, you can create a data dictionary, link it to the model, close the
model, and reopen it. The FPGA Programming Blockset recreates the Simulink
bus objects each time you open the model and automatically saves the bus
elements in the linked data dictionary instead in the base workspace.

More information on data dictionaries For more information on Simulink

data dictionaries, refer to the Simulink help.

Observing bus elements The Simulink bus editor lets you observe Simulink bus elements.

To use the bus editor, open the Simulink Model Explorer, select a bus element,
and click Launch Bus Editor.

For more information on the bus editor, refer to the Simulink help.

Related topics HowTos

How to Use Simulink Buses of the FPGA Model to Model Processor Communication.............. 136
How to Use Simulink Buses of the Processor Model to Model the Processor
Communication...................................................................................................................... 138

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Implementing the Processor Interface to the Processor Model

Introduction The processor interface is the counterpart of the FPGA interface to exchange
data between the processor application and the FPGA application.

Where to go from here Information in this section

How to Generate a Processor Interface.................................................. 148

The interface blocks in the processor model for exchanging data with the
FPGA application can be generated with all the relevant settings

Modeling Aspects for Multicore Processor Applications.......................... 151

There are some points to note when implementing the processor
interface of multicore processor applications.

How to Transfer 64-Bit Fixed-Point Data with Full Resolution

(MicroLabBox II, SCALEXIO)................................................................... 152
Transferring fixed-point data with a word length of 64 bits without
converting the data to double.

Information in other sections

Using Simulink Buses for Modeling the Processor Communication......... 135

The MicroLabBox II, MicroAutoBox III, and SCALEXIO blocksets support
Simulink buses to implement the communication between the real-time
processor and the FPGA application.

How to Trigger Interrupt-Driven Processor Tasks..................................... 134

Gives you instructions how to trigger an asynchronous task by the FPGA
application.

Exchanging Data With the Processor Model........................................... 130

The FPGA Programming Blockset provides blocks for exchanging data
between the FPGA subsystem and the processor model.

How to Generate a Processor Interface

Objective The interface blocks in the processor model for exchanging data with the FPGA
application can be generated with all the relevant settings

Basics Usually, you implement the FPGA subsystem first, and then the interface to the
processor model. This means that all information required for the data exchange
is already specified in the FPGA interface blocks. It therefore makes sense to

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generate the corresponding preconfigured interface blocks automatically instead

of adding them to the processor model and configuring them manually.

The information that is required to generate the processor interface is contained

in the FPGA subsystem and the FPGA model INI file that is available as
build result after the build process (see How to Build FPGA Applications
(MicroAutoBox II, MicroLabBox) on page 195). The processor interface can
therefore be generated from either the FPGA subsystem or the FPGA model
INI file.

Preconditions The following preconditions must be fulfilled:

§ The FPGA_XDATA_READ_BL, FPGA_XDATA_WRITE_BL and FPGA_INT_BL
blocks in the FPGA subsystem should be completely configured before
generating the corresponding blocks for the processor model.
§ The processor model must not be a part of the FPGA model as shown below.
SCALEXIO, MicroAutoBox III, MicroAutoBox II, MicroLabBox,
MicroLabBox II and IOCNET-based system

Entire model Processor model

Processor FPGA FPGA

model model model

§ For MicroLabBox II, MicroAutoBox III or a SCALEXIO system only: dSPACE

Model Interface Package for Simulink is required.

Possible methods The method to generate the processor interface depends on the platform used:
§ To generate a processor interface for a MicroLabBox II, MicroAutoBox III or a
SCALEXIO system, refer to Method 1.
§ To generate a processor interface for a MicroAutoBox II or a MicroLabBox,
refer to Method 2.

Method 1 To generate a processor interface for a MicroLabBox II, MicroAutoBox III,

or SCALEXIO system
1 In the FPGA model, double-click the FPGA_SETUP_BL block to open its
dialog.
2 On the Interface tab, click Generate corresponding processor blocks for
FPGA XDATA blocks to generate the blocks for the processor interface.

Method 2 To generate a processor interface for MicroAutoBox II or MicroLabBox

1 Add a PROC_SETUP_BL block to the processor model.
2 Double-click the block to open its dialog.
3 On the Unit page, select the FPGA subsystem whose model interface you
want to generate.

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If you already built the FPGA application, you can also specify the FPGA
model INI file after you have added the file to the FPGA model INI files list on
the Advanced page.
4 On the Interface page, click Generate to generate the interface blocks
required for the processor interface.

Result You have created a new model containing interface blocks to implement the
processor interface to the processor model. The blocks are configured with all
the relevant settings of their counterparts in the FPGA subsystem.

The generated blocks depend on the used platform.

FPGA Interface Block Generated Processor Interface Block

MicroLabBox II, MicroAutoBox III, MicroLabBox, MicroAutoBox II2)
SCALEXIO1)
Register

Buffer

Interrupt

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FPGA Interface Block Generated Processor Interface Block

MicroLabBox II, MicroAutoBox III, MicroLabBox, MicroAutoBox II2)
SCALEXIO1)

1) Model port blocks of the dSPACE Model Interface Package for Simulink.
2) Processor interface blocks of the Processor Interface sublibrary of the FPGA
Programming Blockset

Next steps Copy the generated blocks to your processor model and connect them to the
other Simulink blocks. You must not reconfigure these blocks manually. The
settings for data type conversion (floating-point to fixed-point and vice versa) are
implicit and can only be modified in the appropriate FPGA blocks.

After you copy the generated processor model interface blocks to the processor
model, you can close the generated interface model without saving.

Related topics Basics

Exchanging Data With the Processor Model............................................................................ 130

Model Interface Blockset (Model Interface Package for Simulink Reference )

HowTos

How to Trigger Interrupt-Driven Processor Tasks...................................................................... 134

References

GenerateProcessorInterface (FPGA Programming Software Script Interface

Reference )
GenerateProcInterfaceBlocks (FPGA Programming Software Script Interface
Reference )
Processor Interface Blocks (MicroAutoBox III, MicroLabBox II, SCALEXIO) (FPGA
Programming Blockset - Processor Interface Reference )
Processor Interface RTI Blocks (MicroAutoBox II, MicroLabBox) (FPGA Programming
Blockset - Processor Interface Reference )

Modeling Aspects for Multicore Processor Applications

Multicore processor The RTI-MP Blockset allows you to assign parts of your processor model to
applications for MicroLabBox different CPU cores. MicroLabBox provides two cores, so the processor model is
separated into one master model and one slave model. You must implement the
slave model as a subsystem of the master model. The inports and outports of the

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slave subsystem are connected with interprocessor communication blocks in the

master model.

Processor model containing the FPGA model Either the master or the
slave model must contain the FPGA model INI file with the FPGA bitstream.
However, both models must contain a PROC_SETUP_BL block when you build
the processor application.

Implementing the processor interface After you generated the processor

interface, you move the interface blocks to the master and slave models as
needed. For instructions on generating the processor interface, refer to How to
Generate a Processor Interface on page 148.

For more information on modeling multicore processor applications, refer

to Distributing the Model for MP Systems (RTI and RTI-MP Implementation
Guide ).

Multicore processor You can implement an application where several single processor models can
applications for be linked to ConfigurationDesk. With this, you can build a multicore processor
MicroLabBox II, application (multicore real-time application) which can be downloaded to
MicroAutoBox III and dSPACE real-time hardware to execute the models in parallel on single cores
SCALEXIO systems of the processor.

Modeling the processor models You implement the different processor

models as subsystems to the entire model. Then, the different processor models
can be separated before the build process starts. Refer to Workflow for
Creating a Multicore Real-Time Application Using One Overall Behavior Model
(ConfigurationDesk Real-Time Implementation Guide ).

Implementing the processor interface After you generate processor

interface blocks to implement the processor interface, you move the blocks to
the processor models as needed. Keep in mind that processor interface blocks
residing in different processor models must not be mapped to the same function
block. For more information, refer to Aspects on FPGA Applications Supporting
Multicore Processor Applications on page 117.

Related topics Basics

Details on MP Systems (RTI and RTI-MP Implementation Guide )

Modeling Executable Applications and Tasks (ConfigurationDesk Real-Time
Implementation Guide )

How to Transfer 64-Bit Fixed-Point Data with Full Resolution (MicroLabBox II,
SCALEXIO)

Objective Transferring fixed-point data with a word length of 64 bits without converting
the data to double.

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Limitations The following limitations apply to 64-bit fixed-point processor communication

with full resolution:
§ The platform must be MicroLabBox II or SCALEXIO.
§ The access type must be Register64 or Buffer64.

Basics on the processor 64-bit fixed-point data types are usually converted to double. Therefore, the
communication fixed-point resolution of fixed-point data types is restricted to 53 bits.

The exception is Register64 and Buffer64 blocks, which can transfer 64-bit
fixed-point data values with the full resolution. For this, the binary point position
must be set to zero.

Note

The default data type of generated processor interface blocks is always

double. To use the full resolution of a 64-bit fixed-point data type, you have
to set the data type of the generated blocks to int64 or uint64.

Method To transfer 64-bit fixed-point data with full resolution

1 Generate the processor interface blocks and add the generated blocks to
the processor model. Refer to How to Generate a Processor Interface on
page 148.
2 Open the block dialog of a generated processor interface block intended to
transfer 64-bit fixed-point data values.
3 Set the Type property to int64/uint64.

Result You configured the processor interface to transfer 64-bit fixed-point data with
full resolution.

Related topics Basics

Basics on Exchanging Data Between Processor and FPGA......................................................... 17

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HowTos

How to Generate a Processor Interface................................................................................... 148

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Preprocessing and Postprocessing the Signals Between the

FPGA and the Processor Model
Introduction The MicroLabBox II, MicroAutoBox III, and SCALEXIO blocksets support scaling
subsystems that are part of the FPGA model. Scaling subsystems let you
preprocess and postprocess the signals between the FPGA model and the
processor model.

Where to go from here Information in this section

Basics on Preprocessing and Postprocessing the Processor

Communication..................................................................................... 156
Scaling subsystems that are a part of the FPGA model are flexible
interfaces which let you adapt the signals between the FPGA model and
the processor model.

Characteristics of Scaling Subsystems.................................................... 158

Features and limitations of scaling subsystems and their representation in
ConfigurationDesk.

Limitations Concerning Scaling Subsystems........................................... 160

Limitations that you have to consider when modeling a scaling
subsystem.

How to Prepare FPGA Models to Use Scaling Subsystems....................... 162

Creating subsystems in the FPGA model to implement scaling
subsystems.

How to Implement the Interfaces of Scaling Subsystems........................ 164

Adding the interface blocks to scaling subsystems that provide the
interfaces to the processor model and the FPGA subsystem.

How to Implement Data Exchange Between Scaling Subsystems............ 167

Directly exchanging signal values between scaling subsystems.

How to Implement the Interfaces for Offline Simulation......................... 168

Connecting the processor model (behavior model) with the scaling
subsystems for offline simulation.

How to Update an FPGAC File with Modified Scaling Subsystems.......... 170

Updating the FPGAC file without rebuilding the FPGA application.

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Basics on Preprocessing and Postprocessing the Processor Communication

Platforms supporting the The following platforms support the preprocessing and postprocessing of
processing of processor processor communication via scaling subsystems:
communication § MicroLabBox II
§ MicroAutoBox III
§ SCALEXIO

Introduction Scaling subsystems that are a part of the FPGA model are flexible interfaces
which let you adapt the signals between the FPGA model and the processor
model. The following overview shows the implementation of scaling subsystems
and the resulting data flow between the FPGA application and the processor
application.

Entire model

FPGA model
FPGA function A

Scaling subsystem FPGA subsystem Scaling subsystem

signal1 signal1
Processor model
(behavior model)
From processor To processor

signal1 signal1

FPGA function B
signal1 signal1

Scaling subsystem FPGA subsystem Scaling subsystem

signal1 signal1

From processor To processor

FPGA model The FPGA model is a Simulink subsystem that includes the
FPGA Setup block and one or more FPGA functions.

FPGA function An FPGA function is a subsystem that lets you generate a

dedicated FPGA custom function block type in ConfigurationDesk. An FPGA
function includes the FPGA subsystem and one or more scaling subsystems.

Scaling subsystem A scaling subsystem modifies the signals between the

FPGA subsystem and the processor model. Scaling subsystems can be used for
the following actions:
§ Scaling the signals.
§ Implementing complex algorithms to preprocess and postprocess the signals.
For example, a processor input signal can be calculated from several FPGA
output signals.
§ Grouping and naming of signals for more clarity.

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Scalings subsystems are part of an FPGA function. You implement scaling

subsystems with blocks of the dSPACE Model Interface Package for Simulink
and blocks of the Simulink blockset.
A scaling subsystem is executed on the real-time processor. Therefore, a scaling
subsystem must not include any FPGA functionality, i.e. you must not use blocks
of the HDL library of the AMD Vitis Model Composer or FPGA Programming
Blockset.
Signal processing requires different scaling subsystems for the FPGA input signals
and output signals. Different subsystems are required because the processor
model reads the FPGA signal values at a different time than it writes them.
Therefore, the scaling of the output signals must be processed at a different time
than the scaling of the input signals.

FPGA subsystem The FPGA subsystem includes the functionality that is

processed on the FPGA. You implement the subsystem with the FPGA
Programming blockset and the blocksets for FPGA modeling, such as the HDL
library of the AMD Vitis Model Composer.

Processor model (behavior model) The processor model (behavior model in

ConfigurationDesk) includes the functionality that is processed on the real-time
processor.

Benefits of scaling subsystems A scaling subsystem supports the iterative development of a real-time
application:
§ Scaling subsystems separate the development of the FPGA functionality and
the functionality of the processor interface.
Changes or complex adaptions in the processor communication can be
processed in the scaling subsystem.
§ Scaling subsystems can be changed and developed without changing the
FPGA subsystem or the processor model. This significantly reduces the build
time during the development process.
§ You can automatically update changes in the scaling subsystems in all
instances of the FPGA custom function in ConfigurationDesk.

Related topics Basics

Limitations Concerning Scaling Subsystems............................................................................ 160

HowTos

How to Implement the Interfaces of Scaling Subsystems......................................................... 164

How to Prepare FPGA Models to Use Scaling Subsystems........................................................ 162

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Characteristics of Scaling Subsystems

Features of scaling subsystems These are the main features of scaling subsystems:
§ In ConfigurationDesk, scaling subsystems belong to the FPGA custom function
block type. This has the following advantages:
§ You can use the same scaling subsystems with different applications.
§ You can instantiate the function block type multiple times.
§ An update of the FPGA container automatically updates the instantiated
function blocks and their scaled interfaces.
§ Scaling subsystems can be updated independently from the FPGA subsystem.
Modifications do not require an FPGA build.
§ Mask parameters of a scaling subsystem can be used to adjust scaling
subsystems in ConfigurationDesk and in ControlDesk at run time.

Representation in In ConfigurationDesk, FPGA custom function blocks represent an instance of the

ConfigurationDesk build FPGA function. The following illustration shows an FPGA custom function
block and the naming of the elements.

Element Naming
1 The default function block name is the FPGA application name.
You specify the FPGA application name when you build the FPGA
application.
2 The function name is the name of the scaling subsystem in Simulink.
3 The function port name is the signal name of the model port block
that provides the interface to the processor model (behavior model).

Representation of FPGA models with several FPGA functions If your

FPGA model includes several FPGA functions, each FPGA function is represented
by its own FPGA custom function block type in ConfigurationDesk. The following
illustration is an example.

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Simulink ConfigurationDesk

FPGA model
FPGA function A

Scaling subsystem FPGA subsystem Scaling subsystem

signal1 signal1

From processor To processor

FPGA function B

Scaling subsystem FPGA subsystem Scaling subsystem

signal1 signal1

From processor To processor

For more information, refer to Representation of FPGA Applications in

ConfigurationDesk (ConfigurationDesk I/O Function Implementation Guide ).

Tuning scaling subsystems of You can use mask parameters for scaling subsystems to make the scaling
built FPGA applications subsystem tunable, for example, to support different processor models (behavior
models) in ConfigurationDesk. In ConfigurationDesk, the mask parameters are
provided as function block properties. In ControlDesk, the mask parameters are
tunable parameters that can be changed at run time.

Mask Dialog in Simulink Properties Browser in ConfigurationDesk

The support of mask parameters by ConfigurationDesk and ControlDesk

is limited. For more information, refer to Limitations Concerning Scaling
Subsystems on page 160.

Tagging the subsystems to use The FPGA model consists of several subsystems that are executed on the FPGA or
scaling subsystems the real-time processor. Tags are used to distinguish the different subsystems:
§ Scaling subsystems must be tagged to make clear that they are not part of the
FPGA application.
§ FPGA functions are tagged to make clear that the subsystem is represented in
ConfigurationDesk by one function block type.

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The following illustration shows the Tag property in the Block Properties dialog
of a subsystem.

Tag Value Description

direction=0 The scaling subsystem processes input signals.
direction=1 The scaling subsystem processes output signals.
fpgafunction=1 The FPGA function is represented in ConfigurationDesk by
one function block type.

You can tag the subsystems manually or you can use templates. For instructions
on using templates, refer to How to Prepare FPGA Models to Use Scaling
Subsystems on page 162.

Related topics Basics

Basics on Preprocessing and Postprocessing the Processor Communication............................. 156

Limitations Concerning Scaling Subsystems

Limitations Observe the following limitations when you implement a scaling subsystem:
§ A scaling subsystem executes either input signals or output signals. You cannot
use the same scaling subsystem for input and output signals.
§ A scaling subsystem can exchange data only with the processor model, the
FPGA subsystem, and other scaling subsystems within an FPGA function. At
least one connection to the FPGA subsystem must be implemented. Data
exchange between scaling subsystems of different FPGA functions is not

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allowed. The following illustration shows allowed and prohibited connections

between scaling subsystems.
Simulink

FPGA model

FPGA function A

Scaling subsystem FPGA subsystem Scaling subsystem

signal1 signal1

From processor To processor

FPGA function B

Scaling subsystem FPGA subsystem Scaling subsystem

signal1 signal1

From processor To processor

However, on the FPGA a data exchange between the FPGA subsystems of the
FPGA functions can be implemented.
§ A scaling subsystem does not support ungrouped registers, i.e., registers
whose Register group ID is set to zero.
§ A scaling subsystem must include all registers of a register group, i.e., all
registers with the same Register group ID and the same data direction
(Register In or Register Out) must be handled by the same scaling
subsystem.
§ Scaling subsystems must be independent from the sample time, because
model ports of the processor model can use different sample times.
To build the scaling subsystem without a specific sample time, the FPGA
Programming Blockset sets the solver type to Fixed-step and the periodic
sample time constraint to Ensure sample time independent. This limits the use
of certain blocks, e.g., you cannot use Simulink Integrator blocks.
If the scaling subsystem does not satisfy the specified constraints, Simulink
displays an error message during the build process.
§ The function ports of a function block can be mapped only to the same
application process of the processor model (behavior model). Therefore, the
interface of an FPGA subsystem must provide signals only for one processor
application process.
For more information on processor application processes, refer to Terms and
Definitions for Building Executable Applications (ConfigurationDesk Real-Time
Implementation Guide ).
§ The following limitations apply for mask parameters that are provided as
function block properties in ConfigurationDesk and as tunable parameters in
ControlDesk:
§ Only the edit and checkbox mask parameter types are supported.
§ The Evaluate parameter attribute must be selected.
§ The mask parameter must be tunable.
§ The mask parameter value must not be modified in the block's mask
initialization.

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§ In ConfigurationDesk, only mask parameters of the following data types are

available as function block properties:
§ Scalars
§ Vectors
§ Two-dimensional matrices
a b
a c ⋯
or c d
b d ⋯
⋮ ⋮
§ Enumerations

Related topics HowTos

How to Implement the Interfaces of Scaling Subsystems......................................................... 164

How to Prepare FPGA Models to Use Scaling Subsystems

Objective Creating subsystems in the FPGA model to implement scaling subsystems.

Basics To distinguish the scaling subsystem from the FPGA subsystem, you have to
tag the subsystem with the direction tag. Refer to Characteristics of Scaling
Subsystems on page 158.

Methods You can use the following methods to prepare an FPGA model:
§ If you model an FPGA model from scratch, use templates to prepare the FPGA
model. Refer to Method 1.
§ If you adapt an existing FPGA model, prepare the existing FPGA model. Refer
to Method 2.

Method 1 To prepare an FPGA model using templates

1 Open the FPGA Interface sublibrary of the FPGA Programming Blockset.

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2 Drag & drop the FPGA Function subsystem of the Model Structure
Templates to the FPGA model.

Method 2 To prepare an existing FPGA model

1 Add the FPGA functionalities that form an FPGA function to a subsystem.
The FPGA functionalities must include the FPGA interface to the processor
model. For an animated graphic, refer to dSPACE Help.
You can group the FPGA functionalities and distribute them among several
subsystems. This results in several FPGA functions. Keep in mind that the
processor interface of an FPGA subsystem must provide signals for only one
processor core (one application process in ConfigurationDesk).
2 Open the FPGA Interface sublibrary of the FPGA Programming Blockset.

3 Drag & drop the Scale In and Scale Out subsystems of the Model
Structure Templates to the FPGA model.
Add at least one Scale In or Scale Out subsystem for each FPGA subsystem.
4 Add the FPGA subsystem of step 1 and the scaling subsystems of step 3 to
one subsystem (FPGA function).
5 Open the block dialog of the FPGA function subsystem and add
fpgafunction=1 to the Tag property.
6 If necessary, repeat steps 1 to 5 for other FPGA functions.

Result You prepared the FPGA model to implement scaling subsystems.

By using templates for preparing the subsystems, the subsystems are tagged with
the matching tags. Refer to Characteristics of Scaling Subsystems on page 158.

Related topics Basics

Basics on Preprocessing and Postprocessing the Processor Communication............................. 156

Characteristics of Scaling Subsystems..................................................................................... 158
Limitations Concerning Scaling Subsystems............................................................................ 160

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How to Implement the Interfaces of Scaling Subsystems

Objective Adding the interface blocks to scaling subsystems that provide the interfaces to
the processor model and the FPGA subsystem.

Precondition The FPGA_XDATA_READ_BL, FPGA_XDATA_WRITE_BL and FPGA_INT_BL

blocks in the FPGA subsystem are completely configured before generating the
corresponding blocks for the scaling subsystem. Refer to Modeling Processor
Model Access on page 130.

Workflow This workflow consists of the following parts:

§ To add the blocks that provide the interface to the FPGA subsystem. Refer to
Part 1 on page 164.
§ In the scaling subsystems, implement the functionality to scale the processor
signals. To do this, use the Simulink blockset and note the limitations on
scaling subsystems. For the limitations, refer to Limitations Concerning Scaling
Subsystems on page 160.
§ To add the blocks that provide the interface to the processor model. Refer to
Part 2 on page 166.

Part 1 To add the blocks that provide the interface to the FPGA subsystem
1 In the FPGA model, double-click the FPGA_SETUP_BL block to open its
dialog.
2 On the Interface tab, click Generate corresponding processor blocks for
FPGA XDATA blocks to generate the model port blocks required for the
interface.
3 Open the FPGA function subsystem.

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4 Drag the generated Data Outport blocks to the Scale In subsystem and the
generated Data Inport blocks to the Scale Out subsystem.

For special use cases, you can add a Data Inport block to the Scale In
subsystem instead of the Scale Out subsystem. This way the processor does
not write the processor signal to the FPGA application at the end of a
processor task as usual, but only at the beginning. The same applies to the
Data Outport blocks.

Interim result You added the interface blocks to the FPGA subsystem.

Before you add the interface blocks to the processor model, implement the
functionality to scale the processor signals.

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Part 2 To add the blocks that provide the interface to the processor model
1 Open the Model Interface Blockset.

2 Add at least one Data Inport block to the Scale In subsystem and connect
it to the scaling functionality.
3 Configure the added Data Inport block. Refer to How to Configure Data
Port Blocks (Model Interface Package for Simulink - Modeling Guide ).
4 Add at least one Data Outport block to the Scale Out subsystem and
connect it to the scaling functionality.
5 Select the added Data Outport block and select Model Port Blocks -
Update All Selected Outport Blocks from Input Signals.

Result You added the interfaces to the scaling subsystems. The following illustration
shows a simple example of a Scale In subsystem.

Note

The generated hardware-triggered runnable function blocks (counterpart of

the FPGA_INT_BL blocks) must be added to the processor model.

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Related topics Basics

Basics on Preprocessing and Postprocessing the Processor Communication............................. 156

Limitations Concerning Scaling Subsystems............................................................................ 160

How to Implement Data Exchange Between Scaling Subsystems

Objective Directly exchanging signal values between scaling subsystems. The data
exchange takes place on the real-time processor and does not use any FPGA
resources.

Limitation You can exchange data only between scaling subsystems of the same FPGA
function. Refer to Limitations Concerning Scaling Subsystems on page 160.

Precondition You prepared the FPGA model to use scaling subsystems. Refer to How to
Prepare FPGA Models to Use Scaling Subsystems on page 162.

Method To implement data exchange between scaling subsystems

1 Add Simulink inports and/or outports to the scaling subsystems and connect
signals to the added ports.
2 Connect the inports and outports of the scaling subsystems.

Result The FPGA application exchanges signal values between the scaling subsystems.

Related topics Basics

Basics on Preprocessing and Postprocessing the Processor Communication............................. 156

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How to Implement the Interfaces for Offline Simulation

Objective Connecting the processor model (behavior model) with the scaling subsystems
for offline simulation.

Precondition In the scaling subsystems, the model port blocks providing the interface to the
processor model are added and configured. Refer to How to Implement the
Interfaces of Scaling Subsystems on page 164.

Method To implement the interfaces for offline simulation

1 In the scaling subsystem, select a model port block that provides the
interface to the processor model. This is a model port block that has no
block connection to the FPGA subsystem.

2 Open the block dialog and select the Signal Configuration page.

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3 Enter a unique connection tag for each port in order to connect it to a

model port of the processor model.

4 If the scaling subsystems has further model port blocks that form the
interface to the processor model, repeat steps 1 … 3 with these model port
blocks.
5 Select all model port blocks that form the interface to the processor model.
6 Select Model Ports Blocks - Create Inverse Model Port Block.
7 Add the generated model port blocks to the processor model (behavior
model).

Result You added the processor interface in the processor model (behavior model).

The Signal Configuration page of the model port block dialog displays the
Connection Tag and the corresponding model port blocks. The model ports
with the same Connection Tag correspond to each other.

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Related topics Basics

Basics on Preprocessing and Postprocessing the Processor Communication............................. 156

Simulating a Processor Model................................................................................................. 175
Simulating an FPGA Subsystem............................................................................................... 174

How to Update an FPGAC File with Modified Scaling Subsystems

Objective Updating the scaling subsystems of an FPGAC file without rebuilding the FPGA
application.

Basics The FPGA build process adds all build result files to an FPGAC file. The
building of the FPGA application takes a long time. If you changed only scaling
subsystems, you do not have to rebuild the FPGA subsystem.

The FPGA build process inserts all build result files into an FPGAC file. Building
the FPGA application takes a lot of time. If you have changed only scaling
subsystems, you do not need to rebuild the FPGA subsystem.

To save time, you can replace the scaling subsystem only to update the
preprocessing and/or postprocessing of the processor signals. The FPGA
application remains unchanged.

Preconditions The following preconditions must be fulfilled:

§ An FPGAC file is available.
§ The modifications do not affect the FPGA functionality or the FPGA interface
blocks (FPGA_XDATA_READ_BL and FPGA_XDATA_WRITE_BL blocks).

Possible methods Use one of the following methods:

§ Update the FPGAC file of the last FPGA build process with menu commands.
Refer to Method 1 on page 170.
§ Update any FPGAC file with the script interface. Refer toMethod 2 on
page 171

Method 1 To update an FPGAC file with a menu command

1 Open the subsystem of the FPGA model with the FPGA Setup block.

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2 Click dSPACE FPGA - Update All Scaling Subsystems for Last Build.

To update only selected scaling subsystems, right-click on a selected

scaling subsystem and select dSPACE FPGA - Update Selected Scaling
Subsystems for Last Build.

Method 2 To update an FPGAC file with the script interface

1 In the MATLAB Command Window, for example, enter the following
command:
rtifpga_scriptinterface('ReplaceScalingSubsystems','<FPGACpath>',
'<SubsystemPath>')

Placeholder Description
<FPGACpath> File path to the FPGAC file to be updated. For example:
C:\FPGAApplications\
DemoFPGApipt1_E97E9F7D35F047.fpgac.
<SubsystemPath> Path to the modified scaling subsystem
in the Simulink model. For example:
DemoFPGApipt1/DemoFPGApipt1/
FPGA Function.
The script rebuilds all scaling subsystems that exist at
the specified path and replaces the build result files in
the specified FPGAC file. This means that if the path to
the FPGA model is specified, all scaling subsystems will
be updated.
To save time, update only a specific scaling subsystem
by specifying the path to the modified subsystem.

Result You updated the scaling subsystems of an FPGAC file.

§ The menu command updates the FPGAC file without changing its ID.
§ The script generates a new FPGAC file with a unique ID.

Next step To update the function blocks in ConfigurationDesk, replace the FPGAC file in
the ConfigurationDesk search path folder.

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Related topics Basics

Basics on Preprocessing and Postprocessing the Processor Communication............................. 156

Update All Scaling Subsystems for Last Build (FPGA Programming Blockset - FPGA
Interface Reference )
Update Selected Scaling Subsystems for Last Build (FPGA Programming Blockset -
FPGA Interface Reference )

References

ReplaceScalingSubsystems (FPGA Programming Software Script Interface

Reference )

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Simulating and Debugging Processor and FPGA

Applications

Introduction You can run the processor model and its FPGA subsystems in different simulation
modes.

Where to go from here Information in this section

Running Processor Models and FPGA Subsystems in Simulink

Simulation Mode................................................................................... 174
You can run the processor model and its FPGA subsystems in Simulink
simulation mode (offline simulation) to test the model behavior.

Debugging Processor Models and FPGA Subsystems.............................. 177

Simulink and AMD Vitis Model Composer provide several tools for
analyzing a model.

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Running Processor Models and FPGA Subsystems in Simulink

Simulation Mode
Introduction You can run the processor model and its FPGA subsystems in Simulink simulation
mode (offline simulation) to test the model behavior.

Where to go from here Information in this section

Simulating an FPGA Subsystem.............................................................. 174

Before you execute the FPGA application on the real-time hardware, you
should test its behavior in a simulated I/O environment.

Simulating a Processor Model................................................................ 175

Before you execute the processor application on the real-time hardware,
you should test its behavior in a simulated environment.

Simulating an FPGA Subsystem

Introduction Before you execute the FPGA application on the real-time hardware, you should
test its behavior in a simulated I/O environment.

Providing ports for simulation In a Simulink simulation (also called offline simulation), the implemented FPGA
data subsystem runs without connection to the external hardware. The simulation is
based on the Simulink model and not on the generated model code. The input
signals and output signals of the model interface must be simulated within the
model. For this purpose, the FPGA Interface blocks provide simulation ports
that you can enable for simulation. The simulation ports and their connected
model components are ignored when you build the FPGA application.

The enabled simulation ports of the FPGA_IO_READ_BL and

FPGA_IO_WRITE_BL blocks can be connected to an I/O model that simulates
the expected real input and output signals applied to the I/O pins of the FPGA
board.

The enabled simulation ports of the FPGA_XDATA_READ_BL and

FPGA_XDATA_WRITE_BL blocks can be connected to Simulink Source and Sink
blocks to simulate the FPGA model independently from the processor model.
There is no need to implement the corresponding processor interface blocks for
simulation.

Specifying the offline In the Analysis tab of the FPGA_SETUP_BL block dialog, you can specify the
simulation period offline simulation period. This is the step size that will be used for the simulation.

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If you have specified fixed step size, the offline simulation period must be an
integer multiple of the fixed step size specified in the Simulink Configuration
Parameters. Officially, the AMD Vitis Model Composer supports only variable
step size.
Example If you have specified a fixed step size of 1 µs in the Simulink
Configuration Parameters, the offline simulation period can be greater than or
equal to 1 µs, for example 1 ms.

Note

There are some blocks from the HDL library of the AMD Vitis Model
Composer, for example, the Constant and Counter blocks, for which you
can specify a sampling rate in their block dialogs.
If there is a difference between the specified offline simulation period and
the block's explicit period, the block period is calculated by:
HWBlockPeriod = SimulinkBlockPeriod · HWClockPeriod /
OfflineSimulationPeriod
For example, if you have specified the explicit period of a Counter block
with 10 µs and the offline simulation period with 1 µs, the hardware block
period is 100 ns for a hardware clock period of 10 ns.

Starting the simulation You can start the simulation in the model window of the FPGA subsystem by
clicking the Start simulation toolbar button, choosing Simulation - Run from
the menu bar or using the Ctrl+T shortcut.

The simulation is executed for the specified simulation time or until you stop it.

Related topics Basics

Initializing the DDR4 RAM of the DS6602 for Offline Simulation............................................... 92

Simulating and Debugging Processor and FPGA Applications.................................................. 173

Simulating a Processor Model

Introduction Before you execute the processor application on the real-time hardware, you
should test its behavior in a simulated environment.

Simulating a MicroLabBox II, You can simulate the interaction between the processor model and the FPGA
MicroAutoBox III, or a model in offline mode without modifying the models. The simulation data is
SCALEXIO systems delivered by the specified simulation ports or, if these ports are not available, by
the corresponding interface blocks in the model.

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Simulating a MicroAutoBox II If you simulate the processor model of a MicroAutoBox II or a MicroLabBox, you
or MicroLabBox can do this in different model modes.

Simulating in FPGA-Build / Offline simulation model mode The processor

model and its FPGA subsystems are simulated (see also Simulating an FPGA
Subsystem on page 174).
You can simulate the interaction between the processor model and the FPGA
model in offline mode without modifying the models. The simulation data is
delivered by the specified simulation ports or, if these ports are not available, by
the corresponding interface blocks in the model.

Simulating in Processor-Build model mode The processor model only

contains the blocks from the processor model. The FPGA subsystems are
removed from the model. The simulation can therefore be used only to test
the behavior of the processor model, and there is no simulated data exchange
with the FPGA subsystems.

Starting the simulation You can start the simulation in the model window of the processor model by
clicking the Start simulation toolbar button, choosing Simulation - Run from
the menu bar or using the Ctrl+T shortcut.

The simulation is executed for the specified simulation time or until you stop it.

Related topics Basics

Simulating and Debugging Processor and FPGA Applications.................................................. 173

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Debugging Processor Models and FPGA Subsystems

Introduction There are a lot of standard tools in Simulink that help you find mistakes in
your processor model, for example, unconnected signals or incorrect data type
conversions. The AMD Vitis Model Composer provides special tools for analyzing
FPGA systems.

Where to go from here Information in this section

Analyzing FPGA Models......................................................................... 177

AMD Vitis Model Composer and dSPACE provide tools for timing
analysis, resource utilization analysis, and HDL simulation.

Features of the dSPACE Timing Analyzer................................................ 179

The dSPACE Timing Analyzer helps you fix timing errors that are detected
during the build process.

Features of the dSPACE Utilization Analyzer........................................... 181

The dSPACE Utilization Analyzer helps you to analyze the utilization of
the FPGA resources.

Analyzing FPGA Models

Introduction AMD Vivado and dSPACE provide tools for timing analysis, resource utilization
analysis, and HDL simulation.

Timing analysis If the build process for your FPGA subsystem has detected timing problems, use
the Vivado timing analysis tool or the dSPACE Timing Analyzer.

Timing analysis of the entire FPGA application The build process

automatically starts a timing analysis of the entire FPGA application including
the framework for the used platform. In the MATLAB Command Window, the
build process outputs links to the results of the analysis.
Depending on your preferences and the build FPGA model, click one of the
following links to the results of the timing analysis:
§ Show Timing Report of complete FPGA:
Opens the Vivado Timing Analyzer to show the results. The Vivado Timing
Analyzer shows only the signal paths that are modeled with the HDL library of
the AMD Vitis Model Composer. The Vivado Timing Analyzer does not show
signal paths that are modeled with Simulink blocks.
§ dSPACE Timing Analyzer:
Opens the dSPACE Timing Analyzer to show FPGA timing failures
independently of the used blockset, including FPGA subsystems based on

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Simulink blocks (HDL coder subsystems). For more information, refer to

Features of the dSPACE Timing Analyzer on page 179.
For building the FPGA application, refer to Building FPGA and Processor
Applications on page 185.

Timing analysis of the custom FPGA model On the Analysis tab of the
FPGA_SETUP_BL block, you can click Timing Analysis to start the timing
analysis of the FPGA model. This timing analysis considers only the FPGA model
that is modeled with blocks from the HDL library of the AMD Vitis Model
Composer. FPGA model parts that are modeled with Simulink blocks and the
dSPACE platform framework are not considered.
The result of the analysis is displayed in VivadoTiming Analyzer and saved to
the <ModelName>_timing folder in the working folder.
To show the last report, click Show Last Timing Report on the Analysis tab of
the FPGA_SETUP_BL block.

Tip

Use the timing analysis of the custom FPGA model to fix timing problems
with model parts that use the HDL library of the AMD Vitis Model
Composer.

Resource utilization analysis If the build process for your FPGA subsystem has detected FPGA resource
problems, use the resource utilization analysis tool from the AMD Vitis Model
Composer.

Resource analysis of the entire FPGA application The build process

automatically starts a resource analysis of the entire FPGA application including
the framework for the used platform. In the MATLAB Command Window, the
build process outputs links to the results of the analysis.
Depending on your preferences and the build FPGA model, click one of the
following links to the results of the resource analysis:
§ Show Resource Utilization Report of complete FPGA:
Opens the Vivado Resource Analyzer to show the results. The Vivado
Resource Analyzer shows only the subsystems and blocks that are modeled
with the HDL library of the AMD Vitis Model Composer. The Vivado Resource
Analyzer does not show subsystems that are modeled with Simulink blocks.
§ dSPACE Utilization Viewer:
Opens the dSPACE FPGA Resource Utilization Viewer to show the used
resources for the build FPGA application, including subsystems based on
Simulink blocks (HDL coder subsystems).
For more information, refer to Features of the dSPACE Utilization Analyzer on
page 181.

Resource analysis of the custom FPGA model You can start the resource
analysis on the Analysis tab of the FPGA_SETUP_BL block by clicking Resource
Analysis. This resource analysis considers only the custom FPGA model without
the framework of the platform that is automatically added to your FPGA model
during the build process.

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The result of the analysis is displayed in the Resource Analyzer and saved to the
<ModelName>_resource folder in the working folder. To show the last report,
click Show Last Timing Report on the Analysis tab of the FPGA_SETUP_BL
block.

HDL simulation If you completed a Simulink simulation and are satisfied with the behavior of the
model, the next step is to compare the simulation data from the FPGA model
with the simulation data from generated HDL code. To do so, you can start the
HDL Simulation on the Analysis tab of the FPGA_SETUP_BL block.

Note

The HDL simulation only starts if the simulation time is not infinite.

When the simulation has finished, you can look at a textual report. The results
are also stored in the HDLAnalysis folder in the working folder.

Further information For more information on timing analysis, resource utilization analysis, and HDL
simulation, refer to the Vivado Design Suite User Guide.

Related topics Basics

Detecting and Fixing Timing Problems (FPGA Programming Blockset Getting

Started )
Simulating and Debugging Processor and FPGA Applications.................................................. 173

Features of the dSPACE Timing Analyzer

Introduction The dSPACE Timing Analyzer helps you fix timing errors that are detected during
the build process.

The timing analyzer helps you with the following features:

§ Shows the most critical FPGA signal paths of the built FPGA application
independently of the used block libraries (HDL library of the AMD Vitis Model
Composer and/or standard Simulink library (HDL Coder subsystems)).
The number of FPGA signal paths is limited to 1,000 bits of signals. For
example, 50 20-bit wide data paths can be displayed.
§ Provides details on the used blocks within a failed signal path.
§ Opens a selected block of a failed signal path in the FPGA model. This gives
you a fast access to fix the error.
§ Provides the timing report with details on the selected signal path. The details
help to fix errors that require detailed analysis.

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Opening the dSPACE Timing After the build process finishes, click dSPACE Timing Analyzer in the MATLAB
Analyzer Command Window to open the analyzer.

User interface elements The dSPACE Timing Analyzer has the following elements.

Element Name Description

1 Status Shows the result of the timing analysis:
§ Green: Timing passed.
§ Red: Timing failed.
2 Signal Shows the most critical FPGA signal paths of the built FPGA application:
paths § Slack: Timing reserve of the signal paths. Negative values indicate the lack of time.
table
§ Source: Block at the starting point of the timing path.
§ Destination: Block at the end point of the timing path.
If the Source and Destination blocks of the signal path are <…>/FPGA_SETUP_BL1, the
path is in the dSPACE framework. Paths with little slack can be located there. However, the
framework should not generate timing errors (Slack < 0 ns) below 70% FPGA utilization.
3 Details Details on the selected path in the signal paths table.
pane § Slack: Timing reserve of the signal paths. Negative values indicate the lack of time.
§ Requirement: Maximum possible delay of the signal path.
§ Delay: Sum of logic delay and routing delay.
§ Logic Delay: Delay caused by the block logic.
§ Route Delay: Delay caused by routing of the signal in the FPGA.

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Element Name Description

4 Path tab Details on the blocks of the selected signal path.
§ Parent Subsystem: Path to the subsystem that includes all blocks of the selected signal path.
§ Delay: Logic and routing delay of a block in the FPGA model.
§ Block: Path to the block in the FPGA model relative to the parent subsystem.

Tip

Double-click a block to highlight the block in the FPGA model.

5 Report Detailed timing report on the selected signal path.

tab

Related topics Basics

Detecting and Fixing Timing Problems (FPGA Programming Blockset Getting

Started )

Features of the dSPACE Utilization Analyzer

Introduction The dSPACE Utilization Analyzer provides information on the utilization of FPGA
resources for the complete FPGA application:
§ Resources for the FPGA model part that is modeled with blocks of the HDL
library of the AMD Vitis Model Composer.
§ Resources for the FPGA model part that is modeled with blocks of the Simulink
blockset (HDL coder subsystems).
§ Resources used by the dSPACE framework.

Opening the dSPACE After the build process finishes, click dSPACE Utilization Viewer in the
Utilization Analyzer MATLAB Command Window to open the viewer.

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User interface elements The dSPACE Utilization Analyzer has the following elements.

Element Name Description

1 Details pane Displays the name of analyzed FPGA application and the used framework.
2 Display pane Lets you specify the displayed values
§ Expand all button: Lets you expand all rows in the table.
§ Collapse all button: Lets you collapse all rows in the table.
§ Show Percentages checkbox: Lets you display the relative utilization instead of the
absolute utilization.
§ Show Zeros checkbox: Lets you display the value zero instead of an empty cell.
3 Report table Displays the utilization sorted by subsystems and blocks. The listed resource parameters
are platform-dependent and can differ depending on the used platform.
§ Block: Displays the subsystems and blocks of the FPGA model.
§ Total LUTs: Displays the utilization of all look-up tables.
§ LUTRAMs: Displays the utilization of look-up tables implemented as synchronous RAM
resource.
§ SRLs: Displays the utilization of look-up tables implemented as shift registers.
§ FFs: Displays the utilization of flip-flops.
§ RAMB36: Displays the utilization of RAM with 36 kB block size.
§ RAMB18: Displays the utilization of RAM with 18 kB block size.
§ DSP Blocks: Displays the utilization of digital signal processors.

Tip

§ Double-click a row to highlight the element in the FPGA model.

§ The + and – signs let you expand and collapse the rows.

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Element Name Description

4 Clear Clears the highlighting in the FPGA model.
Highlight
button
5 Close button Close the viewer.
6 Help button Opens this help topic.

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Building FPGA and Processor Applications

Introduction If the behavior of your model in Simulink simulation fulfills your requirements,
you can generate the model code and build the executable files from the
processor model and the FPGA subsystems.

Where to go from here Information in this section

Building the Applications (MicroLabBox II, MicroAutoBox III,

SCALEXIO)............................................................................................. 186
The FPGA Programming Blockset manages the build process of
the FPGA application for dSPACE hardware that is supported by
ConfigurationDesk.

Building the Applications (MicroAutoBox II, MicroLabBox)...................... 195

The FPGA Programming Blockset manages the build process of the FPGA
application and the processor application.

Achieving Successful Builds at High FPGA Utilization.............................. 205

Reusing build results increases the likelihood of successful FPGA builds
and reduces build times for rather small changes in the FPGA model.

Using an FPGA Build Server................................................................... 207

The dSPACE FPGA Build Server can take over the build process from the
FPGA Programming Blockset.

Monitoring the Build Process................................................................. 216

The FPGA Build Monitor displays status information and the build
progress of different FPGA builds.

Backing Up the Build Results.................................................................. 225

You can back up the build results, reports, and the entire model.

Information in other sections

Accessing FPGA Applications with your Experiment Software........ ........ 233

You can build FPGA applications that provide access to FPGA signals and
constants with your experiment software.

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Building the Applications (MicroLabBox II, MicroAutoBox III,

SCALEXIO)
Introduction The FPGA Programming Blockset manages the build process of the FPGA
application for a MicroLabBox II, MicroAutoBox III, or a SCALEXIO system. To
build the real-time application, you have to use ConfigurationDesk.

Where to go from here Information in this section

How to Build FPGA Applications (MicroLabBox II,

MicroAutoBox III, SCALEXIO)................................................................. 186
Before you can execute the FPGA model on the real-time hardware, you
must build an application from its generated code.

How to Prepare the Processor Models for Separating

(MicroLabBox II, MicroAutoBox III, SCALEXIO)........................................ 189
You have to specify the processor models in the entire model so that the
framework can automatically separate the processor models from other
parts of the entire model, such as the FPGA model.

How to Export Build Results and Processor Models to

ConfigurationDesk Projects.................................................................... 191
You have to add the processor model and the FPGA application to
a ConfigurationDesk application before you can build the real-time
application.

How to Build Processor Applications (MicroLabBox II,

MicroAutoBox III, SCALEXIO)................................................................. 193
Before you can execute the behavior model on the real-time hardware,
you must build an application from its generated code.

How to Build FPGA Applications (MicroLabBox II, MicroAutoBox III,

SCALEXIO)

Objective Before you can execute the FPGA model on a MicroLabBox II, MicroAutoBox III,
or SCALEXIO system, you must build an application from its generated code.

Basics The code generation and the build process are managed by the FPGA
Programming Blockset. It uses the AMD Vitis Model Composer to generate VHDL
code and starts the FPGA implementation process, including synthesis, mapping,
routing and generating the bitstream file.

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 Building the Applications (MicroLabBox II, MicroAutoBox III, SCALEXIO)

Even if no errors occurred during modeling, simulating, and building, your FPGA
application is not guaranteed to work correctly. Some combination of factors
might prohibit the execution of your FPGA application, e.g., combinations of the
operating temperature, the power of the entire hardware system, technological
limitations of the FPGA, the sample rate, etc. Some FPGA applications do not
start at all, others start correctly but fail during operation.

Due to the complexity of FPGA applications and their dependency on the used
FPGA hardware, the AMD Design Tools cannot ensure that all possible design
problems are detected during the analysis and simulation of the FPGA model.

To solve the problem, you have to modify the FPGA model and make sure that
you consider generally accepted FPGA design rules to ensure a stable and reliable
FPGA application (refer to Audience profile on page 9). For more information,
contact dSPACE Support.

Backing up build results Before you build an FPGA application, you can enable and configure the
automatic backup of the build FPGA application, models, and reports that are
generated and used during the build process. Refer to Backing Up the Build
Results on page 225.

Preconditions § Your platform is a MicroLabBox II, MicroAutoBox III, or a SCALEXIO system.

§ The FPGA subsystem that you want to build must be implemented correctly,
for example, the FPGA Interface blocks must be configured correctly.
§ If you use Black Box blocks from the HDL library of the AMD Vitis Model
Composer to incorporate hardware description language models, the files
of the incorporated models are located in the model root folder or in an
Includes subfolder in the model root folder. The Includes subfolder and
optional subfolders must be added to the MATLAB search paths as relative
paths. For more information, refer to Implementing the FPGA Functionality on
page 67.
§ The build process is executed only if the versions of the installed AMD tools
are suitable for the FPGA Programming Blockset. For suitable software tools,
refer to Software Tools for Working with the FPGA Programming Blockset on
page 19.

Note

An FPGA application must be build with a variable-step solver.

If you have specified a fixed‑step solver it is automatically switched.

Possible methods You can build an FPGA application in different ways:

§ In the FPGA_SETUP_BL block, you can start the build process for the FPGA
subsystem it belongs to. Refer to the method below.
§ You can use an FPGA Build Server to build the FPGA application. Refer to
Using an FPGA Build Server on page 207.

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Method To build an FPGA application via FPGA_SETUP_BL block

1 Double-click the FPGA_SETUP_BL block in the FPGA subsystem to open the
block's dialog and switch to its Build tab.
2 Check and specify the general settings on the tab.
3 Select Local Build as build process and click Start Build to start the build
process.

Result The FPGA Build Monitor opens that displays status information and the build
progress. For more information, refer to FPGA Build Monitor 2024-A Reference
on page 218.

During the build, the FPGA Programming Blockset opens a temporary model
<FPGAModelName>_rtiFPGAtmp and closes the temporary model when the
FPGA application is built.

You will find the FPGAC file according to the settings

on the Analysis tab of the FPGA_SETUP_BL block in
<FPGABuildFolder>/<ModelName>_rtiFPGA/FPGA_Custom_Functions/
<FPGAApplicationName>_<ApplicationID>.fpgac. ApplicationID is a 56-bit
identifier which is uniquely created at each build process.

For a troubleshooting on common problems during the build, refer to Building

an FPGA application on page 262.

Next step You have the following options to further process the build results:
§ You can prepare the entire model to export the build results and the processor
model to ConfigurationDesk. Refer to How to Prepare the Processor Models
for Separating (MicroLabBox II, MicroAutoBox III, SCALEXIO) on page 189.
§ You can directly use the build results in ConfigurationDesk, for example, to
update an existing FPGA custom function block type without changing the
processor model.
Click the publish link in the MATLAB Command Window or press the Publish
button on the Interface tab of the FPGA Setup block dialog to publish
the path of the built FPGA container file to the global user location file of
ConfigurationDesk.

Related topics Basics

Achieving Successful Builds at High FPGA Utilization............................................................... 205

Backing Up the Build Results................................................................................................... 225
Building FPGA and Processor Applications.............................................................................. 185
Troubleshooting...................................................................................................................... 259

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 Building the Applications (MicroLabBox II, MicroAutoBox III, SCALEXIO)

How to Prepare the Processor Models for Separating (MicroLabBox II,

MicroAutoBox III, SCALEXIO)

Objective You have to prepare the processor models in the entire model so that the
framework can automatically separate the processor models from other parts of
the entire model, such as the FPGA model.

Required preparations Before the framework can export the processor models, you have to specify the
following:
§ Specify the processor models in the entire model.
In a ConfigurationDesk project, the processor interfaces are a part of the
behavior model. Other parts of the entire model, such as the FPGA application
or stimulus signals of external I/O signals, are not part of the behavior model.
Therefore, the framework separates the processor models from the entire
model. To do this, you have to specify the processor models in the entire
model.
§ Specify a name and a folder for the separated processor models.
In ConfigurationDesk, the separated processor models are implemented
outside ConfigurationDesk in a Simulink model. When the framework
exports the processor models to ConfigurationDesk, it implements the
separated processor models that are saved at the specified location to
ConfigurationDesk.

Separating multicore For more information on separating multicore processor models, refer to
processor models Workflow for Creating a Multicore Real-Time Application Using One Overall
Behavior Model (ConfigurationDesk Real-Time Implementation Guide ).

Precondition Your platform is a MicroLabBox II, MicroAutoBox III, or a SCALEXIO system.

Method To prepare the processor model for separating

1 On the top-level of the entire model, add the Model Separation Setup
block from the dSPACE Model Interface Package for Simulink block library.
2 Open the block dialog.
The Model Separation Setup block analyzes the entire model and displays
all top-level subsystems that can be separated as models.

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3 Click to add a new model entry in the Models tree.

List of unassigned subsystems Models tree

4 In the Model name edit field, enter a name for the Simulink model that
includes a processor model that must be separated.
5 In the Model folder edit field, enter a folder name or path for the separated
processor model to be saved when the framework exports the processor
model.
If you do not enter a folder or path, the framework saves the separated
processor model to the folder of the entire model.
6 From the Unassigned subsystems list, select the subsystems of the

processor model and click to assign the subsystems to the model entry.
7 If the entire model includes more than one processor model to be separated,
repeat steps 3 ... 6.
8 Click Save to save the configuration to the source model.
9 Click Close to close the dialog.

Result Now the model is prepared for separating. The framework is able to process the
following steps when you export the processor model:
§ To separate the processor models from the entire model.
§ To save the separated processor models as Simulink models with the specified
name to the specified folder.

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Next step Now you can export the FPGA build results and the processor models to
ConfigurationDesk. Refer to How to Export Build Results and Processor Models
to ConfigurationDesk Projects on page 191.

Related topics Basics

Building FPGA and Processor Applications.............................................................................. 185

How to Export Build Results and Processor Models to ConfigurationDesk

Projects

Objective You have to add the processor model and the FPGA application to a
ConfigurationDesk application before you can build the real-time application.

Steps of the export process The framework mainly performs the following steps when it exports the build
results and the processor model to ConfigurationDesk:
§ Opens ConfigurationDesk.
§ Creates a new project in ConfigurationDesk.
§ Adds the file path of the current build results to the global user location file.
The global user location file is located at
%LOCALAPPDATA%\dSPACE\ConfigurationDesk\Settings\<ReleaseVersion>
(<ProductVersion>)
When you add the file paths to the global user location file, the
FPGA application is available as FPGA custom function block types in all
ConfigurationDesk projects.
Different versions of FPGAC files differ only in the application ID
(<FPGAApplicationName>_<ApplicationID>.fpgac). When updating the
FPGAC file, the FPGA Programming Blockset adds an application ID so that
ConfigurationDesk can find the latest version first and ignores the other
FPGAC files. In ConfigurationDesk, the Message Viewer displays the found
FPGAC files and the ignored FPGAC files.
The following illustration shows messages of the Message Viewer concerning
the registration of FPGA custom function block types.

§ Adds instances of the added custom function block types to the signal chain.

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The framework performs the following steps only if the processor model can be
separated and the processor interface is implemented:
§ Separates and saves the processor models according to the settings of the
Model Separation Setup block.
In ConfigurationDesk, the processor models are implemented outside
ConfigurationDesk in Simulink models.
§ Exports the model interface of the processor models to ConfigurationDesk.
§ Maps the function ports of the added FPGA custom function blocks to the
model ports of the processor model (behavior model).

Preconditions § Your platform is a MicroLabBox II, MicroAutoBox III or a SCALEXIO system.

§ The FPGA application is built. Refer to How to Build FPGA Applications
(MicroLabBox II, MicroAutoBox III, SCALEXIO) on page 186.
§ The processor interface is implemented. Missing parts of the processor
interface cannot be automatically mapped in ConfigurationDesk. Refer to How
to Generate a Processor Interface on page 148.
§ The Model Separation Setup block is added to the entire model and
configured. Refer to How to Prepare the Processor Models for Separating
(MicroLabBox II, MicroAutoBox III, SCALEXIO) on page 189.

Result You exported all build FPGA applications of the entire model and the processor
model to ConfigurationDesk. In ConfigurationDesk, the processor model is a part
of the behavior model.

If the processor interface is implemented, the model port mapping is done

automatically. Otherwise you have to do this manually.

Tip

§ In ConfigurationDesk, click to rearrange the blocks of a signal chain

so that as many mapping lines as possible are horizontal.
§ To map the ports of Simulink buses, drag & drop the model port group to
the FPGA custom function.

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Note

You can access a register group by one task only.

For more information on the representation of FPGA applications in

ConfigurationDesk, refer to Representation of FPGA Applications in
ConfigurationDesk (ConfigurationDesk I/O Function Implementation Guide ).

Next step You can map the device ports of the external devices to the signal ports of
the FPGA function blocks, assign the hardware resources, enable the angular
processing unit, and specify the task priority of interrupts. Refer to Handling
FPGA Custom Function Blocks in ConfigurationDesk (ConfigurationDesk I/O
Function Implementation Guide ).

Related topics Basics

Building FPGA and Processor Applications.............................................................................. 185

Representation of FPGA Applications in ConfigurationDesk (ConfigurationDesk I/O
Function Implementation Guide )

References

ExportToNewProject (FPGA Programming Software Script Interface Reference )

ExportToRecentProject (FPGA Programming Software Script Interface Reference )

How to Build Processor Applications (MicroLabBox II, MicroAutoBox III,

SCALEXIO)

Objective Before you can execute the behavior model including the processor model on the
real-time hardware, you must build an application from its generated code.

Basics The code generation and the build process are managed by ConfigurationDesk.

For general information, refer to Building Real-Time Applications

(ConfigurationDesk Real-Time Implementation Guide ).

Note

Before you start the build process for the processor application, you must
set the Fixed-step size setting on the Solver page to a value, which is the
multiple of the offline simulation period specified in the FPGA_SETUP_BL
block. Check also the compatibility of the solver settings used for FPGA-
based offline simulation, for example, the solver type.

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Preconditions § Your platform is a MicroLabBox II, MicroAutoBox III, or a SCALEXIO system.

§ The working folder must be set to the model path.
§ If you want to download the real-time application after the build process, the
platform must be registered via the Platform Manager in ConfigurationDesk.

Method To build a processor application when using a MicroLabBox II,

MicroAutoBox III, or a SCALEXIO system
1 Prepare the behavior model for the build process.
2 Only if you do not export the build results to ConfigurationDesk via the
FPGA_SETUP_BL block:
§ In ConfigurationDesk, execute the Analyze Model (Complete
Analysis) command, to make all the required Runnable Functions
(used for FPGA_interrupts) available to the behavior model.
§ Execute the Create Preconfigured Application Process command
to initialize the application process.
3 In ConfigurationDesk, configure the build options.
4 Click Build in ConfigurationDesk's Build Manager to start the build process.

Result If the build process finished successfully, you will find the build results,
such as the processor application file and the variable description file, in
ConfigurationDesk's Build Results folder. The FPGA application is automatically
programmed to the RAM of the FPGA when the processor application is loaded.

For example, if you built the MyDemo application for a MicroLabBox II,
MicroAutoBox III, or a SCALEXIO system, you will find the executable RTA file
called MyDemo.rta in the Build Results folder.

Related topics Basics

Building Real-Time Applications (ConfigurationDesk Real-Time Implementation

Guide )

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Building the Applications (MicroAutoBox II, MicroLabBox)

Introduction The FPGA Programming Blockset manages the build process of the FPGA
application and the processor application for a MicroAutoBox II or a
MicroLabBox.

Where to go from here Information in this section

How to Build FPGA Applications (MicroAutoBox II, MicroLabBox)........... 195

Before you can execute the FPGA model on the real-time hardware, you
must build an application from its generated code.

Basics on Building the Processor Application (MicroAutoBox II,

MicroLabBox)........................................................................................ 198
Notes and required settings to build the processor application.

How to Build Single-Core Processor Applications (MicroAutoBox II,

MicroLabBox)........................................................................................ 200
To build a single-core processor application that includes and supports
your FPGA application.

How to Build Multicore Processor Applications for MicroLabBox............ 201

To build a multicore processor application that includes and supports
your FPGA application.

How to Create Burn Applications for MicroAutoBox II............................ 203

You can explicitly program the FPGA with a burn application.

How to Build FPGA Applications (MicroAutoBox II, MicroLabBox)

Objective Before you can execute the FPGA model on the real-time hardware, you must
build an application from its generated code.

Basics The code generation and the build process are managed by the FPGA
Programming Blockset. It uses the AMD Vitis Model Composer to generate
VHDL code and starts the FPGAlinx implementation process, including synthesis,
mapping, routing and generating the bitstream file.

Even if no errors occurred during modeling, simulating, and building, your FPGA
application is not guaranteed to work correctly. Some combination of factors
might prohibit the execution of your FPGA application, e.g., combinations of the
operating temperature, the power of the entire hardware system, technological
limitations of the FPGA, the sample rate, etc. Some FPGA applications do not
start at all, others start correctly but fail during operation.

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Due to the complexity of FPGA applications and their dependency on the used
FPGA hardware, the AMD Design Tools cannot ensure that all possible design
problems are detected during the analysis and simulation of the FPGA model.

To solve the problem, you have to modify the FPGA model and make sure that
you consider generally accepted FPGA design rules to ensure a stable and reliable
FPGA application (refer to Audience profile on page 9). For more information,
contact dSPACE Support.

Backing up build results Before you build an FPGA application, you can enable and configure the
automatic backup of the build FPGA application, models, and reports that are
generated and used during the build process. Refer to Backing Up the Build
Results on page 225.

Using the script interface for The FPGA Programming Blockset provides a script interface that you can use to
building an FPGA application start the FPGA build process in the MATLAB Command Window.

The syntax for the FPGA build is:

[listOfAppIDs, listOfiniFileRefs, pModelPath, errorcode] =
rtifpga_scriptinterface('FPGABuild',<SimulinkHandle>)

The script considers all subsystems that are contained in the model/subsystem
which is specified by the Simulink handle.

Preconditions § Your platform is a MicroAutoBox II or MicroLabBox.

§ The FPGA subsystem that you want to build must be implemented correctly,
for example, the FPGA Interface blocks must be configured correctly.
§ If you use Black Box blocks from the HDL library of the AMD Vitis Model
Composer to incorporate hardware description language models, the files
of the incorporated models are located in the model root folder or in an
Includes subfolder in the model root folder. The Includes subfolder and
optional subfolders must be added to the MATLAB search paths as relative
paths. For more information, refer to Implementing the FPGA Functionality on
page 67.
§ The build process is executed only if the versions of the installed AMD tools
are suitable for the FPGA Programming Blockset. For suitable software tools,
refer to Software Tools for Working with the FPGA Programming Blockset on
page 19.
§ Switching to the Processor-Build model mode is only possible if all the
specified FPGA subsystems has been built before.

Note

An FPGA application must be build with a variable-step solver.

If you have specified a fixed‑step solver it is automatically switched.

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Possible methods You can build an FPGA application in different ways:

§ In the FPGA_SETUP_BL block, you can start the build process for the FPGA
subsystem it belongs to. Refer to Method 1.
§ Only MicroAutoBox II: In the PROC_SETUP_BL block, you can start the build
process for a specified set of FPGA subsystems. Refer to Method 2.
§ In the MATLAB Command Window, you can use the script interface from the
FPGA Programming Blockset to build all the available FPGA subsystems from
the specified Simulink model handle. Refer to Method 3.
§ You can use an FPGA Build Server to build the FPGA application. Refer to
Using an FPGA Build Server on page 207.

Method 1 To build an FPGA application via FPGA_SETUP_BL block

1 Open the FPGA_SETUP_BL block dialog and switch to its Build tab.
2 Check and specify the general settings on the tab.
3 Select Local Build as build proces and click Start Build to start the build
process.

Method 2 To build an FPGA application via PROC_SETUP_BL block

1 Open the PROC_SETUP_BL block dialog.
2 On the Unit page, set the Include option from the FPGA build column for
each FPGA subsystem which you want to build an FPGA application for.
The Include option is disabled if:
§ You specified an FPGA model INI file.
The FPGA application was already built.
§ The model mode is set to Processor-Build.
In this mode, you can only build the processor application. To allow
the building of FPGA applications, you must switch to the FPGA-Build /
Offline Simulation mode on the Model Configuration page.
3 Click Build to start the build processes for the selected FPGA subsystems.
The build processes are executed sequentially.

Method 3 To build an FPGA application via script interface

1 Use the script interface and execute the FPGABuild script function by
entering it directly in the command line of the MATLAB Command Window
or referencing an M-file that contains the script function.
Example: The following script will start an FPGA build process for any FPGA
subsystems found in the processor model that is called MyProcModel.
ProcModelHandle = get_param('MyProcModel','handle')
rtifpga_scriptinterface('FPGABuild',ProcModelHandle)

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Result The FPGA Build Monitor opens that displays status information and the build
progress. For more information, refer to FPGA Build Monitor 2024-A Reference
on page 218.

During the build, the FPGA Programming Blockset opens a temporary model
<FPGAModelName>_rtiFPGAtmp and closes the temporary model when the
FPGA application is built.

You will find the FPGAC file according to the settings

on the Analysis tab of the FPGA_SETUP_BL block in
<FPGABuildFolder>/<ModelName>_rtiFPGA/FPGA_Custom_Functions/
<FPGAApplicationName>_<ApplicationID>.fpgac. ApplicationID is a 56-bit
identifier which is uniquely created at each build process.

For a troubleshooting on common problems during the build, refer to Building

an FPGA application on page 262.

Related topics Basics

Achieving Successful Builds at High FPGA Utilization............................................................... 205

Backing Up the Build Results................................................................................................... 225
Introduction to the Script Interface of the FPGA Programming Software (FPGA
Programming Software Script Interface Reference )
Troubleshooting...................................................................................................................... 259

Basics on Building the Processor Application (MicroAutoBox II, MicroLabBox)

Used coder The code generation and the build process are managed by the Simulink Coder.
For general information, refer to Building and Downloading the Model (RTI and
RTI-MP Implementation Guide ).

Note

Before you start the build process for the processor application, you must
set the Fixed-step size setting on the Solver page to a value that is the
multiple of the offline simulation period specified in the FPGA_SETUP_BL
block.

Model separation The processor model that you want to build must not contain an FPGA
subsystem. Otherwise the build process will terminate with an error message.

The FPGA Programming Blockset provides two methods to remove an FPGA

subsystem from the processor model only for the time of building the processor
application.

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Switching the model mode On the Model Configuration page of

the PROC_SETUP_BL block, you can choose between the FPGA-Build /
Offline Simulation and the Processor-Build model modes. If you switch
to the Processor-Build model mode, a copy of the processor model is
created before the FPGA subsystems are removed. The copy is saved as
<ProcModelName>_rtiFPGASeparationFile.mdl in the same folder as the
original model. If you switch back to the FPGA-Build / Offline Simulation
model mode, the copy is used to restore the model. The copy is not deleted in
the file system.

Note

§ You cannot switch to the Processor-Build model mode without having

built the FPGA application beforehand.
§ If you want to give the model to another person, you must provide both
models: the model that was saved in the Processor-Build model mode
and its separation file. Alternatively, you can switch to the FPGA-Build /
Offline Simulation model mode before you transmit the MDL file of the
processor model.
§ If you save the model in the Processor-Build model mode with a new
path or a new name, restoring the original model will not work.

Using the script interface for separating the processor model The script
interface of the FPGA Programming Blockset can be used to separate the
processor model before you start the build process. It works in the same way
as the model mode switch via the PROC_SETUP_BL block dialog.
The syntax for separation is:
[errorcode, path] = rtifpga_scriptinterface('Separation',
<ProcModelHandle>)
§ errorcode = 0: Operation finished successfully
§ errorcode != 0: Operation terminated with an error
§ path: Returns the path of the separation file
You can get the handle of the processor model by using:
ProcModelHandle = get_param(<ProcessorModelName>,'handle')
You can restore the processor model by using Deseparation instead of
Separation as the first argument.
The syntax for deseparation is:
[errorcode] = rtifpga_scriptinterface('Deseparation',
<ProcModelHandle>)
§ errorcode = 0: Operation finished successfully
§ errorcode != 0: Operation terminated with an error
The script interface can also be used for building the FPGA application (see How
to Build FPGA Applications (MicroAutoBox II, MicroLabBox) on page 195).

INI files used with the FPGA There are two kinds of initialization files:
Programming Blockset § Framework INI file
A framework INI file contains the interface definitions for the FPGA, the FPGA
board's I/O and the processor. It also contains the function-specific settings

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that are displayed in the dialogs of the FPGA interface blocks according to
the specified function. It is therefore mainly used for configuring the FPGA
interface blocks.
§ FPGA model INI file
An FPGA model INI file is created when you build an FPGA application. It
allows you to include built FPGA applications in your processor application
without specifying the corresponding FPGA model. For example, in the setup
block for the processor model, you can specify either an FPGA subsystem or an
FPGA model INI file for further actions.
FPGA model INI files are only used for build results of MicroLabBox and
MicroAutoBox II.

Related topics HowTos

How to Build Multicore Processor Applications for MicroLabBox............................................. 201

How to Build Single-Core Processor Applications (MicroAutoBox II, MicroLabBox)................... 200

How to Build Single-Core Processor Applications (MicroAutoBox II,

MicroLabBox)

Objective To build a single-core processor application that includes and supports your FPGA
application.

Basics For information on building the processor application, refer to Basics on Building
the Processor Application (MicroAutoBox II, MicroLabBox) on page 198.

Preconditions § Your platform is a MicroAutoBox II or MicroLabBox.

§ The FPGA model INI file must be available before you start the build process.
§ The working folder must be set to the model path.
§ The processor model to be built must be opened in MATLAB.
§ If you want to download the processor application after the build process, the
real-time hardware must be registered, for example, via the Platform Manager
in ControlDesk.

Method To build a single-core processor application

1 Prepare the processor model for the build process. Either switch the model
mode to Processor-Build in the PROC_SETUP_BL block or use the script
interface to separate the FPGA subsystems from the processor model. For
details, see above.
2 On the Unit page of the PROC_SETUP_BL block, select the required
programming option. If you specify not to program the related FPGA

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application into flash or RAM, the FPGA application must be available in

the FPGA board's flash memory. Otherwise, the processor application will
terminate after the FPGA board's initialization phase.
3 Open the Code Generation dialog, specify the build options and check the
configuration, for example, the selected target file and the specified fixed
step size.
4 Click Build in the Code Generation dialog to start the build process.

Result If the build process finishes successfully, you will find the build results, such as
the processor application file and the variable description file, in the working
folder. If you have specified to program the FPGA application into flash or
RAM, the flash or the FPGA is automatically programmed when the processor
application is loaded. For more information on programming the FPGA, refer to
How to Create Burn Applications for MicroAutoBox II on page 203.

For example, if you built the MyDemo application for a MicroLabBox, you
will find the executable PPC file in the working folder and a subfolder called
MyDemo_rti1202 containing the generated code and all the intermediate build
results.

Related topics HowTos

How to Build Processor Applications (MicroLabBox II, MicroAutoBox III, SCALEXIO)................. 193

References

AddIniFile (FPGA Programming Software Script Interface Reference )

Deseparation (FPGA Programming Software Script Interface Reference )
GetFPGABlocks (FPGA Programming Software Script Interface Reference )
RemoveIniFile (FPGA Programming Software Script Interface Reference )
Separation (FPGA Programming Software Script Interface Reference )

How to Build Multicore Processor Applications for MicroLabBox

Objective To build a multicore processor application that includes and supports your FPGA
application.

Basics For information on building the processor application, refer to Basics on Building
the Processor Application (MicroAutoBox II, MicroLabBox) on page 198.

Effects on FPGA signal tracing The processor model that programs the FPGA triggers the data acquisition
of FPGA signals with the task period of the subsystem in which the

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PROC_SETUP_BL block is located. You can specify which processor model

programs the FPGA when you configure the build process.

Preconditions § The FPGA model INI file must be available before you start the build process.
§ The master model and the slave model must contain the PROC_SETUP_BL
block.
§ The working folder must be set to the model path.
§ The processor model to be built must be opened in MATLAB.
§ If you want to download the processor application after the build process, the
real-time hardware must be registered, for example, via the Platform Manager
in ControlDesk.

Method To build a multicore processor application for MicroLabBox

1 Prepare the processor model including the FPGA subsystem for the
build process. Either switch the model mode to Processor-Build in the
PROC_SETUP_BL block or use the script interface to separate the FPGA
subsystems from the processor model. For more information, refer to Model
separation on page 198.
2 Open the PROC_SETUP_BL block dialog of the processor model that you
want to program the FPGA. This could be the PROC_SETUP_BL block dialog
of the master model or of the slave model.
3 On the Unit page, select the FPGA model INI file. If the file is not selectable,
add the FPGA model INI file to the Advanced page.
4 Select the programming option into ram or into flash and click OK.
5 Open the PROC_SETUP_BL block dialog of the other processor model.
6 On the Unit page, select the FPGA model INI file. If the file is not selectable,
add the FPGA model INI file to the Advanced page.
7 Clear the programming option (select - - -) and click OK.
8 Start the build process with the Multiprocessor Setup dialog. For more
information, refer to Basics on the Build and Download (RTI and RTI-MP
Implementation Guide ).

Result If the build process finishes successfully, you will find the build results, such as
the processor application file and the variable description file, in the working
folder. The FPGA is automatically programmed when the processor application is
loaded.

Related topics Basics

Details on MP Systems (RTI and RTI-MP Implementation Guide )

Modeling Aspects for Multicore Processor Applications........................................................... 151

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How to Create Burn Applications for MicroAutoBox II

Objective You can explicitly program the FPGA of the MicroAutoBox II with a burn
application.

Basics A burn application is used to load an FPGA application to the FPGA. Usually, the
FPGA programming is included in the processor application and there is no need
to use a burn application. But in some cases, it is useful to program the FPGA
explicitly.

Note

If you load a processor application that was built without specifying a

programming option for the real-time hardware, and there is no application
running on the FPGA, the processor application is terminated after the
initialization phase of the FPGA board.

Programming into flash If you use the flash memory of the FPGA board,
you must execute the burn application only once. Each time you start the FPGA
board, the FPGA application is loaded to the FPGA automatically. In this case, the
processor application should be built without specifying a programming option.
This gives you the shortest startup time for your system. If you want to load a
new FPGA application to the flash, you must execute the burn application to
replace the flash contents and restart the system to program the FPGA from the
flash with the new application.

Note

When programming into flash, you must consider the Autoboot features of
your hardware.
§ The Autoboot feature can be enabled and
disabled via the MicroAutoBox Configuration Tool
(<RCP_HIL_InstallationPath>/Exe/DS1401_ConfigGUI.exe) or via
RTLib, refer to fpga_tp1_enable_autoboot (MicroAutoBox II RTLib
Reference ) and fpga_tp1_disable_autoboot (MicroAutoBox II RTLib
Reference ).

Programming into RAM If you use the RAM memory of the FPGA board,
the FPGA must be programmed every time you start the system. It is therefore
recommended to build the processor application with the RAM programming
option to program the FPGA application automatically when loading the
processor application. A burn application for the RAM is useful if you want
to test the FPGA application only. If you program into the RAM memory, any
running FPGA application is immediately stopped and replaced with the new
FPGA application, unlike flash programming, where you must restart the board
to activate the new FPGA application.

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Preconditions § Your platform is a MicroAutoBox II.

§ The model must be in the Processor-Build model mode.

Method To create a burn application

1 Double-click the PROC_SETUP_BL block in the processor model to open its
dialog.
2 On the Unit page, choose a programming option for each of the specified
FPGA applications.
3 Click Create burn application to start the build process for the burn
application. The Simulink Coder is used to manage the build process.

Result If the build process succeeded, the build result can be found in
<ModelName>_rtiFPGA/burnapplication. The executable is not
automatically downloaded to the processor board. The intermediate build results
can be found in
<ModelName>_rtiFPGA/burnapplication/<ModelName>_burnapplication
_rti1401.

For example, if you built the burn application for the

MyDemo model, you will find the executable PPC file in
MyDemo_rtiFPGA/burnapplication and the intermediate build results in
MyDemo_rtiFPGA/burnapplication/MyDemo_burnapplication_rti1401.

For information how to load a burn application, refer to Experimenting with an

FPGA Application on page 229.

Related topics Basics

Experimenting with an FPGA Application................................................................................ 229

References

CreateBurnApplication (FPGA Programming Software Script Interface Reference )

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Achieving Successful Builds at High FPGA Utilization

Introduction Reusing build results increases the likelihood of successful FPGA builds and
reduces build times for rather small changes in the FPGA model.

How to Build FPGA Applications Incrementally

Objective Consistently achieving successful builds at high FPGA utilizations.

Basics The FPGA Programming Blockset lets you enable the incremental build feature of
Vivado to help in consistently achieving successful builds at high FPGA utilization.
A known good reference build is used as a starting point for implementation
so that new builds can use a working FPGA configuration and only the actual
changes have to be implemented. An incremental build increases the likelihood
of successful FPGA builds and reduces build times for rather small changes in the
FPGA model.

Precondition Build results of an FPGA application are available.

Method To build an FPGA application incrementally

1 Open the Build tab of the FPGA_SETUP_BL block.
2 Select Enable incremental build.

3 Click Find latest build result for reference.

The FPGA Programming Blockset searches the current build directory for
the last design checkpoint file (DCP file). If the FPGA Programming Blockset
finds a DCP file, it writes the file path to the Incremental Build Reference
parameter. The DCP file is used as reference to the build results.
Alternatively, you can enter the path of a DCP file, for example, to reference
the results of an older build.
4 Build the FPGA application.

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Result The FPGA Programming Blockset builds the FPGA application based on the
results of the referenced build results.

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Using an FPGA Build Server

Introduction The dSPACE FPGA Build Server can take over the build process from the FPGA
Programming Blockset.

Where to go from here Information in this section

Basics on the FPGA Build Server............................................................. 207

The dSPACE FPGA Build Server can execute the FPGA build that was
started with the FPGA Programming Blockset.

How to Prepare the Computer for the FPGA Build Server....................... 209
To install the software and exchange folder required to run the FPGA
Build Server.

How to Install and Start the FPGA Build Server....................................... 211

The FPGA Build Server must be configured and run before you start the
build process.

How to Build FPGA Applications via a Server.......................................... 212

To provide the files for the FPGA build process.

FPGA Build Server Configuration File Reference..................................... 214

Description of the parameters.

Basics on the FPGA Build Server

Introduction The dSPACE FPGA Build Server can execute the FPGA build that was started with
the FPGA Programming Blockset.

Use cases Main use cases for the FPGA Build Server:
§ To continue modeling after you started the build process.
The FPGA Build Server can run on the same PC as the FPGA Programming
Blockset.
§ To provide high computing capacity to build FPGA applications faster for
several modeling workstations.

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One computer with optimized computing capacity builds the FPGA application
for several modeling workstations.

Modeling workstation Modeling workstation

Modeling workstation Modeling workstation

FPGA Build
Server

Modeling workstation Modeling workstation

Principle of operation The following illustration shows the principle of operation:

Source files Source files

FPGA build FPGA build

FPGA Programming file Build folder file FPGA Build
Blockset Server

Monitor the build progress

FPGA Build Monitor

A common build folder is used to exchange the source files to build the FPGA
application and the resulting FPGA build file.
§ The FPGA Programming Blockset provides the source files for building the
FPGA application.
§ The FPGA Build Server builds the FPGA application and provides the FPGA
build file.
The FPGA Build Server can build multiple FPGA applications at the same time.
§ The FPGA Build Monitor displays the build progress of all builds that are
executed in the build folder.

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Tip

If one computer is used as the build server for several modeling

workstations, you can use a separate build folder for each modeling
workstation.
To use separate build directories, install multiple FPGA Build Servers on the
computer.

Modeling workstation Build folder

3 FPGA Build
Servers on one
computer

Modeling workstation Build folder

Modeling workstation Build folder

Related topics HowTos

How to Build FPGA Applications via a Server........................................................................... 212

How to Install and Start the FPGA Build Server........................................................................ 211
How to Monitor the Build Process........................................................................................... 216

How to Prepare the Computer for the FPGA Build Server

Objective To install the software and exchange folder required to run the FPGA Build
Server.

Required software The following software is required to run the FPGA Build Server.
§ Windows operating system that is supported by the RCP and HIL software of
the current Release.
For a list of supported operating systems, refer to Operating System (New
Features and Migration ). The listed Windows Server operating systems are
not supported by AMD.
§ The Vivado version that is used for FPGA modeling. Refer to Software Tools for
Working with the FPGA Programming Blockset on page 19.

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§ Python 3.11
It is recommended that you use the Python distribution provided
by the dSPACE Release. This Python distribution contains the latest
packages with some bugfixes and security updates. For information on
avoiding or solving conflicts with other Python distributions, refer to
https://www.dspace.com/faq?094.
§ Microsoft .NET Framework 4.7.2

Precondition You have access to the source media of the required software.

Method To prepare the computer for the FPGA Build Server

1 Install the required software.

Tip

If the FPGA Programming Blockset is installed on the same computer,

the required software is already installed.

2 Create an exchange folder as a common build folder. The folder must meet
the following requirements:
§ The build server and the modeling workstations have read/write access to
exchange the files for the build process.
§ The path to the build folder is the same for the FPGA Build Server and for
the modeling workstations.
The same path is required, because absolute paths are used in the FPGA
models.
§ The path length of the build folder is short to avoid errors during the build
process.
During the build process, the path length can exceed the maximum path
length specified by Windows. This might lead to error messages during
file system operations. For more information, refer to AMD Answer Record
52787 (https://support.xilinx.com/s/article/52787?language=en_US).
For information on creating an exchange folder with read/write access, refer
to the documentation of the operating system.

Result You prepared the computer for running the FPGA Build Server.

Related topics Basics

Basics on the FPGA Build Server.............................................................................................. 207

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How to Install and Start the FPGA Build Server

Objective The FPGA Build Server must be configured and run before you start the build
process in the FPGA_SETUP_BL block.

Precondition The computer for the FPGA Build Server must be prepared. Refer to How to
Prepare the Computer for the FPGA Build Server on page 209.

Method To install and start the FPGA Build Server

1 Copy the complete FPGABuildServer installation folder to the computer
that will run the FPGA Build Server. The installation folder is located in the
following folder:
<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\RTIFPGA\bin\

2 Use an ASCII text editor to open the FpgaBuildServerConfig.json

configuration file:
<ServerFolder>\FPGABuildServer\FpgaBuildServerConfig.json

3 Enter the path of the build folder. Use one of the following characters to
separate the directories of the path.
§ Use / to enter the path:
"BuildDirectory" : "<root>/.../<BuildFolder>"
§ Use \\ to enter the path:
"BuildDirectory" : "<root>\\...\\<BuildFolder>"
The other configuration parameters are optionally. Refer to FPGA Build
Server Configuration File Reference on page 214.
4 Save the configuration file.
5 Execute the FpgaBuildServer.exe batch file to start the FPGA Build
Server. Location of the batch file:
<ServerFolder>\FPGABuildServer\FPGABuildServer\

Result You configured and started the FPGA Build Server.

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Tip

§ To make sure that the server is automatically available after a restart,

configure Windows to start the FPGA Build Server when Windows
starts. For more information, refer to https://support.microsoft.com/en-
us/help/4026268/windows-10-change-startup-apps.
§ To use multiple build directories, you can run multiple FPGA Build Servers
in parallel: Repeat step 1 ... 5 with other installation and build directories
to use more than one FPGA Build Server.

Related topics Basics

Basics on the FPGA Build Server.............................................................................................. 207

HowTos

How to Prepare the Computer for the FPGA Build Server........................................................ 209

References

FPGA Build Server Configuration File Reference...................................................................... 214

How to Build FPGA Applications via a Server

Objective To provide the files for the FPGA build process.

Basics You start the build process with the FPGA_SETUP_BL block of the FPGA model.
The build process is automatically started and managed by the FPGA Build Server.
The FPGA Build Server starts the implementation process, including synthesizing,
mapping, routing and generating the bitstream file.

Even if no errors occurred during modeling, simulating, and building, your FPGA
application is not guaranteed to work correctly. Some combination of factors
might prohibit the execution of your FPGA application, e.g., combinations of the
operating temperature, the power of the entire hardware system, technological
limitations of the FPGA, the sample rate, etc. Some FPGA applications do not
start at all, others start correctly but fail during operation.

Due to the complexity of FPGA applications and their dependency on the used
FPGA hardware, the AMD Design Tools cannot ensure that all possible design
problems are detected during the analysis and simulation of the FPGA model.

To solve the problem, you have to modify the FPGA model and make sure that
you consider generally accepted FPGA design rules to ensure a stable and reliable

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FPGA application (refer to Audience profile on page 9). For more information,
contact dSPACE Support.

Preconditions The following preconditions must be fulfilled:

§ The FPGA model that you want to build must be correctly implemented. For
example, the FPGA Interface blocks must be correctly configured.
§ If you use Black Box blocks from the HDL library of the AMD Vitis Model
Composer to incorporate hardware description language models, the files
of the incorporated models are located in the model root folder or in an
Includes subfolder in the model root folder. The Includes subfolder and
optional subfolders must be added to the MATLAB search paths as relative
paths. For more information, refer to Implementing the FPGA Functionality on
page 67.
§ The FPGA_SETUP_BL block has read/write access to the build folder.
§ The FPGA Build Server must be running. Refer to How to Install and Start the
FPGA Build Server on page 211.

Method To build an FPGA application via a server

1 Open the FPGA_SETUP_BL block dialog and switch to the Build tab.
2 Specify a specific custom function name that is used for the the FPGA
custom function blocks in ConfigurationDesk.
3 In Build directory, enter the path to the build folder.

Note

The FPGA Build Server must use the same path for the build folder,
because the FPGA model uses absolute paths.

4 Select Remote Build as build process.

5 Click Start Build to start start the build process.

Result The FPGA Build Monitor opens that displays status information and the build
progress. For more information, refer to FPGA Build Monitor 2024-A Reference
on page 218.

The FPGA Programming Blockset starts the AMD Vitis Model Composer and
a temporary model: <FPGAModelName>_rtiFPGAtmp. The AMD Vitis Model
Composer generates and synthesizes the files for the build process and saves
them to the build folder. The temporary model automatically closes.

You can continue FPGA modeling after the required files for the build process are
available and saved to the build folder. The FPGA Build Server automatically starts
the build process after the server detected the new build job.

Next step The build process can take a long time. You can use the FPGA Build Monitor
to monitor the build progress. Refer to How to Monitor the Build Process on
page 216.

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Related topics Basics

Basics on the FPGA Build Server.............................................................................................. 207

HowTos

How to Monitor the Build Process........................................................................................... 216

FPGA Build Server Configuration File Reference

Introduction Parameters in the FpgaBuildServerConfig.json configuration file lets you

configure the FPGA Build Server.

File location Location of the configuration file:

<ServerDirectory>\FPGABuildServer\FpgaBuildServerConfig.json

Syntax The following example shows the syntax of the configuration file.
{
"BuildDirectory" : "<root>\\...\\<BuildFolder>",
"ConcurrentJobs" : 4,
"LogFile" : "FpgaBuildServer.log"
}

BuildDirectory parameter Lets you enter the path of the build folder. This parameter must be set.

Use one of the following characters to separate the folders of the path.
§ Use / to enter the path:
"BuildDirectory" : "<root>/.../<BuildFolder>"
§ Use \\ to enter the path:
"BuildDirectory" : "<root>\\...\\<BuildFolder>"

ConcurrentJobs parameter Lets you set the maximum number of concurrent build jobs. If the maximum
number has been reached, new jobs are not started until old jobs are completed.

If this parameter is not used, the maximum number of concurrent build jobs is
set to four.

The ConcurrentJobs parameter affects only the number of build jobs and not
the number of build threads that are set via the FPGA_SETUP_BL block.

LogFile parameter Lets you enter a file name of a log file in the build folder to record status
information on the build server and build error messages.

The FPGA Build Server adds a new file with the entered name to the build folder
if the entered file does not exist.

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If this parameter is not used, the FPGA Build Server does not use a log file.

Related topics HowTos

How to Install and Start the FPGA Build Server........................................................................ 211

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Monitoring the Build Process

Introduction The FPGA Build Monitor displays status information and the build progress of
different FPGA builds.

Where to go from here Information in this section

How to Monitor the Build Process.......................................................... 216

To configure and start the FPGA Build Monitor.

FPGA Build Monitor 2024-A Reference.................................................. 218

Description of the FPGA Build Monitor user interface.

How to Monitor the Build Process

Objective To configure and start the FPGA Build Monitor.

Basics The FPGA Build Monitor monitors build processes that are available in the
selected build folder. The FPGA Build Monitor displays status information and
the build progress. For more information, refer to FPGA Build Monitor 2024-A
Reference on page 218.

Method To monitor the build process

1 On the Start menu, select All Programs ‑ dSPACE RCP and HIL <Release>
‑ dSPACE FPGA Build Monitor.
The FPGA Build Monitor starts.

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2 Drag & drop the build folder to the FPGA Build Monitor.
The FPGA Build Monitor displays all build processes that are available in the
selected folder.

Result The FPGA Build Monitor displays information on the monitored build processes.

For a troubleshooting on common problems during the build, refer to Building

an FPGA application on page 262.

Next step When the FPGA build is complete, you can build the processor application.
Refer to Building the Applications (MicroAutoBox II, MicroLabBox) on page 195
or Building the Applications (MicroLabBox II, MicroAutoBox III, SCALEXIO) on
page 186.

Related topics Basics

Basics on the FPGA Build Server.............................................................................................. 207

Troubleshooting...................................................................................................................... 259

HowTos

How to Build FPGA Applications via a Server........................................................................... 212

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FPGA Build Monitor 2024-A Reference

Basic user interface elements The following illustration shows the basic elements of the FPGA Build Monitor
user interface.

1 2

5 4

Element Name Description

1 Current build Displays and lets you specify the current build folder. After you specified a folder, the
folder working area displays status information on all builds that use the build folder.
2 Open button Lets you open the file explorer to select the build folder to be monitored.
3 Menu button Lets you open/close the command menu.
4 Command Gives you access to the following commands:
menu § Clear Caches: Lets you clear all build caches of the monitored build folder.
§ Sort by: Lets you sort the monitored builds by date, name, or state.
§ Help: Opens the FPGA Programming Blockset Guide PDF. The document provides
information on using the FPGA Build Server and FPGA Build Monitor.
§ About: Opens a dialog with information on the version.
5 Working area Lets you drag & drop a build folder to be monitored. After you drop a folder, the
working area displays status information on all builds that use the build folder.
The following status information can be displayed:
§ Build canceled on page 219
§ Build complete on page 219
§ Build complete with warnings on page 220
§ Build failed with errors on page 221
§ Build not yet started on page 222
§ Build stage on page 223
§ Waiting for code generation on page 223

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Build canceled The FPGA build was canceled.

Expand/ Collapse Lets you expand/collapse the status information.

MATLAB messages Displays the steps and messages that the MATLAB®
Command Window outputs during the build process.

Reset button Lets you reset the build state to not yet started.

Build complete The build file is available. Depending on the platform, the build file is an FPGA
model INI file or an FPGAC file.

Expand/ Collapse Lets you expand/collapse the status information.

FPGA utilization Displays information on the FPGA utilization:

§ LUTs: Number of used Look-up tables (LUTs) in comparison to the available
LUTs.

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§ Registers: Number of used registers in comparison to the available registers.

§ Block RAMs: Number of used block RAM in comparison to the available block
RAM.

MATLAB messages Displays the steps and messages that the MATLAB®
Command Window outputs during the build process.

Build performance Displays performance information that is measured

during the build process.
§ Build stage: Stages to complete an FPGA build.
§ Cache: Availability of the build stage in the cache.
§ Hit: The build process uses the cached build stage.
§ Miss: The build stage is not cached and has to be processed.
§ Duration: Duration required to finish the process step.
§ Avg. CPU: Average processor utilization required to complete the build stage.
The percentage value refers to one processor core, i.e., values greater than
100% can be achieved in a multicore system.
This information might not be available if the build is not performed by an
FPGA build server.
§ Peak RAM: Peak RAM usage in the build stage.
This information might not be available if the build is not performed by an
FPGA build server.

Build complete with warnings The build file is available, but warning messages were output during the build
process.

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Expand/ Collapse Lets you expand/collapse the status information.

FPGA utilization Displays information on the FPGA utilization:

§ LUTs: Number of used Look-up tables (LUTs) in comparison to the available
LUTs.
§ Registers: Number of used registers in comparison to the available registers.
§ Block RAMs: Number of used block RAM in comparison to the available block
RAM.

MATLAB messages Displays the steps and messages that the MATLAB®
Command Window outputs during the build process.

Build performance Displays performance information that is measured

during the build process.
§ Build stage: Stages to complete an FPGA build.
§ Cache: Availability of the build stage in the cache.
§ Hit: The build process uses the cached build stage.
§ Miss: The build stage is not cached and has to be processed.
§ Duration: Duration required to finish the process step.
§ Avg. CPU: Average processor utilization required to complete the build stage.
The percentage value refers to one processor core, i.e., values greater than
100% can be achieved in a multicore system.
This information might not be available if the build is not performed by an
FPGA build server.
§ Peak RAM: Peak RAM usage in the build stage.
This information might not be available if the build is not performed by an
FPGA build server.

Build failed with errors The build process cannot be finished due to errors.

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Expand/ Collapse Lets you expand/collapse the status information.

MATLAB messages Displays the steps and messages that the MATLAB®
Command Window outputs during the build process.

Build performance Displays performance information that is measured

during the build process.
§ Build stage: Stages to complete an FPGA build.
§ Cache: Availability of the build stage in the cache.
§ Hit: The build process uses the cached build stage.
§ Miss: The build stage is not cached and has to be processed.
§ Duration: Duration required to finish the process step.
§ Avg. CPU: Average processor utilization required to complete the build stage.
The percentage value refers to one processor core, i.e., values greater than
100% can be achieved in a multicore system.
This information might not be available if the build is not performed by an
FPGA build server.
§ Peak RAM: Peak RAM usage in the build stage.
This information might not be available if the build is not performed by an
FPGA build server.

Reset button Lets you reset the build state to not yet started.

Build not yet started The files for building the FPGA application are available in the build folder, but
the FPGA Build Server has not started building the FPGA application.

If the build does not start, the FPGA Build Server might not be running or is
observing another build folder. Check the settings and restart the server. Refer to
How to Install and Start the FPGA Build Server on page 211.

Expand/ Collapse Lets you expand/collapse the status information.

MATLAB messages Displays the steps and messages that the MATLAB®
Command Window outputs during the build process.

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Build stage The Build server executes the build process and the Build Monitor displays the
current build stage.

Expand/ Collapse Lets you expand/collapse the status information.

MATLAB messages Displays the steps and messages that the MATLAB®
Command Window outputs during the build process.

Build performance Displays performance information that is measured

during the build process.
§ Build stage: Stages to complete an FPGA build.
§ Cache: Availability of the build stage in the cache.
§ Hit: The build process uses the cached build stage.
§ Miss: The build stage is not cached and has to be processed.
§ Duration: Duration required to finish the process step.
§ Avg. CPU: Average processor utilization required to complete the build stage.
The percentage value refers to one processor core, i.e., values greater than
100% can be achieved in a multicore system.
This information might not be available if the build is not performed by an
FPGA build server.
§ Peak RAM: Peak RAM usage in the build stage.
This information might not be available if the build is not performed by an
FPGA build server.

Cancel Build button Lets you cancel the build process before it has been
completed.

Waiting for code generation The FPGA build process waits until the AMD Vitis Model Composer generates
and synthesizes the files for the build process and saves them to the build folder.
The MATLAB messages show the preparatory steps for code generation.

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Expand/ Collapse Lets you expand/collapse the status information.

MATLAB messages Displays the steps and messages that the MATLAB®
Command Window outputs during the build process.

Related topics HowTos

How to Monitor the Build Process........................................................................................... 216

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 Backing Up the Build Results

Backing Up the Build Results

Where to go from here Information in this section

Configuring the Backing Up of Build Results.......................................... 225

Backing up the built FPGA application, models, and reports generated
and used during the build process.

How to Open Backed Up Vivado Reports............................................... 227

Opening backed-up timing reports and utilization reports.

Configuring the Backing Up of Build Results

Introduction Before you build an FPGA application, you can enable and configure the
automatic backup of the build FPGA application, models, and reports that are
generated and used during the build process.

Backup items You can back up the following items:

§ FPGAC file
§ Entire Simulink model
§ Used data dictionaries
§ Model report of the used FPGA channels, software, and tools.
§ Build report of the FPGA utilization and build duration.
§ Vivado reports of the timing and utilization
§ Optionally an HTML model of the entire Simulink model

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Configuring the backup The Build tab of the FPGA_SETUP_BL block dialog lets you configure the
options backup of the build results.

Configuring the backup The FPGA_SETUP_BL block dialog lets you enter a file path to back up the build
directory results.

To use different directories for each backup, you can add the following wildcards
to the file path:
§ %APPID adds a directory with the name of the application ID.
§ %TIMESTAMP adds a directory with the current time. The name format is
yyyy-mm-dd_HH-MM-SS.

If you do not use a wildcard, the backup process uses the same directory for all
backups.

Backing up the Simulink The backup process can automatically back up the Simulink model of the entire
model model. In addition, you can configure to generate a web view (HTML model) of
the Simulink model to display the entire model with any Internet browser.

Preconditions The following preconditions must be fulfilled to back up the

model:
§ The Simulink Report GeneratorTM is required to generate the HTML model.
§ If a build server performs the build process, you must enable the copying of
the model to the build directory.

Note

Before you select Copy model to build directory, make sure that all
users with read permission to the common build directory are entitled to
see the model.

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A copy of the model is required to enable the build server to generate reports
and to back up the model.

Cleaning the build directory It can be useful to save memory, for example, if you use a build server. Therefore
you can enable the cleaning of the build directory after the FPGA application
is built and backed up. Then, the FPGA Programming Blockset removes all
deletable files from the build directory.

Related topics HowTos

How to Open Backed Up Vivado Reports................................................................................ 227

How to Open Backed Up Vivado Reports

Introduction M-scripts are provided in the backup folder to open the backed-up timing and
utilization reports.

Method To open a backed-up Vivado report

1 Open the <backup folder>\Reports folder.
2 Open the TimingReport.m or UtilizationReport.m script in MATLAB.
3 Run the script.
4 If the MATLAB Editor dialog opens, click Change Folder.

Result The selected report opens.

Related topics Basics

Configuring the Backing Up of Build Results........................................................................... 225

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 Running Processor and FPGA Applications on the Real-Time Hardware

Running Processor and FPGA Applications on the

Real-Time Hardware

Introduction When you have built the executable applications for the processor and the FPGA
board, you can load them to the real-time hardware for experimenting.

Experimenting with an FPGA Application

Introduction You can observe the behavior of the real-time application and change
application‑specific parameters by using ControlDesk.

Downloading processor and To run a processor application, the built executable file must only be
FPGA application downloaded to the real-time hardware. The real-time hardware must be
registered beforehand, for example, via the Platform Manager in ControlDesk
or ConfigurationDesk. Any running application is stopped and overwritten by the
newly loaded application. If the processor application contains the programming
of the FPGA, the FPGA application is loaded to the FPGA automatically. If it does
not, and there is no FPGA application running, you must first download the burn
application to program the FPGA and afterwards the processor application.

Note

Before you download the processor application, the flash process started
by the burn application must be finished. For more information on burn
applications, refer to How to Create Burn Applications for MicroAutoBox II
on page 203.

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Note

Even if no errors occurred during modeling, simulating, and building, your

FPGA application is not guaranteed to work correctly. Some combination
of factors might prohibit the execution of your FPGA application, e.g.,
combinations of the operating temperature, the power of the entire
hardware system, technological limitations of the FPGA, the sample rate,
etc. Some FPGA applications do not start at all, others start correctly but fail
during operation.
Due to the complexity of FPGA applications and their dependency on the
used FPGA hardware, the AMD Design Tools cannot ensure that all possible
design problems are detected during the analysis and simulation of the
FPGA model.
To solve the problem, you have to modify the FPGA model and make sure
that you consider generally accepted FPGA design rules to ensure a stable
and reliable FPGA application (refer to Audience profile on page 9). For
more information, contact dSPACE Support.

Required files For experimenting, i.e., changing application-specific parameters during run time
and displaying the behavior, you need files that are created during the build
process, for example, the processor application (.x86, .ppc or .rta), the variable
description file (.trc), the system description file (.sdf), and the mapping file
(.map).

Accessing FPGA signals with You use the SDF file to access the FPGA signals and constants with your
an experiment software experiment software, for example, with ControlDesk.

In ControlDesk, you can access the signals and constants for FPGA tracing and
FPGA scaling in the Variables controlbar under
Signal Chain/IO Function View/FPGA Custom Functions/FPGA Applic
ation Name/….

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Limitations For limitations, refer to Basics on Tracing FPGA Signals on

page 237.

Note

Running applications might stop, if too many FPGA signals are traced
If you trace more than 100 signals with 32-bit values (or 50 signals with 64-
bit values) every millisecond with your experiment software, tracing might
cause a task overrun that stops the application.
These measures reduce the number of traced FPGA signals per millisecond:
§ Disable signal tracing if there is no need to trace FPGA signals.
§ Reduce the number of traceable signals. Refer to Basics on Tracing FPGA
Signals on page 237.
§ Reduce the number of signals that that you trace with the experiment
software. Only the values of signals traced with an experiment software
are sent to the real-time processor and can cause a task overrun.

Triggering the data acquisition The data acquisition of all traceable FPGA
signals is triggered by one trigger source, so all signals of an FPGA application
are captured at the same time. It is not possible to capture signals at different
points in time.
The experiment software can trace only FPGA signals with integer multiples of
the trigger period for tracing FPGA signals.
For the MicroLabBox II, MicroAutoBox III, and SCALEXIO systems, you must map
the Trigger inport of the FPGA custom function block (FPGA Setup block) to
the behavior model. This enables the triggering of the data acquisition with the
shortest task period of the mapped behavior model. Refer to Basics on Tracing
FPGA Signals on page 237.
For MicroAutoBox II and MicroLabBox, the data acquisition is automatically
triggered with the task period of the subsystem in which the FPGA_SETUP_BL
block is located. If you implement a multicore processor application for the
MicroLabBox, the data acquisition is triggered with the task period of the
subsystem in which the FPGA_SETUP_BL block is located that programs the
FPGA.

Related documents § ControlDesk Introduction and Overview for information on working with
ControlDesk.
§ ConfigurationDesk Real-Time Implementation Guide for detailed
information on working with ConfigurationDesk.

Related topics Basics

Accessing FPGA Applications with your Experiment Software.................................................. 233

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Accessing FPGA Applications with your Experiment

Software

Introduction You can build FPGA applications that provide access to FPGA signals and
constants with your experiment software.

Where to go from here Information in this section

Accessing Elements of FPGA Applications.............................................. 234

You can use different methods to access FPGA signals and constants.

Tracing FPGA Signals............................................................................. 237

You can make FPGA signals traceable to trace FPGA signals with your
experiment software.

Adjusting Values of FPGA Constants...................................................... 244

You can adjust tunable FPGA constants with your experiment software.

Enabling the FPGA Test Access and Scaling............................................ 248

You can enable the FPGA test access and scaling to substitute or scale
interface signals.

Displaying FPGA Signals in ControlDesk................................................. 256

You can add FPGA Scope blocks to the FPGA model to display FPGA
signals in ControlDesk.

Information in other sections

Displaying FPGA Signals in ControlDesk................................................. 256

You can add FPGA Scope blocks to the FPGA model to display FPGA
signals in ControlDesk.

Characteristics of Scaling Subsystems.................................................... 158

Features and limitations of scaling subsystems and their representation in
ConfigurationDesk.

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Accessing Elements of FPGA Applications

Introduction You can use different methods to access FPGA signals and constants.

Introduction to Access FPGA Applications

Use cases To access an FPGA application with your experiment software is useful in the
following cases, for example:
§ To trace signals and adjust control parameters for optimization.
§ To use the FPGA application with various settings, e.g., you can scale analog
I/O signals to support different sensors and actors.
§ To debug the application, e.g., you can test the cable harness by switching the
I/O interface to defined values.

Possible elements to access You can access elements of the FPGA logic that includes the FPGA functionality
and elements of the FPGA interface.

Accessing elements of the FPGA logic You can access FPGA signals and
tunable FPGA signals. The illustration below show you the possible methods to
access the elements.

1
Adjusting tunable FPGA FPGA signal FPGA
FPGA constant block tracing block

FPGA signal
tracing

Method Description Further Information

FPGA signal tracing Gives you read access to FPGA signals. Tracing FPGA Signals on page 237
Adjusting tunable FPGA Gives you read/write access to FPGA Adjusting Values of FPGA Constants on
constants constants. page 244

Accessing the FPGA interface You can access the signals of the FPGA
interface to scale and or substitute them. The illustration below show you the
possible methods to access the elements.

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I/O logic

board-specific bus
FPGA test access

FPGA_XDATA_WRITE_BL

I/O logic

FPGA test access

FPGA_XDATA_READ_BL

Analog output
I/O logic
channel
Scaling
FPGA test access Saturation
and offset

FPGA_IO_WRITE_BL

Analog input
I/O logic
channel
Scaling
Saturation FPGA test access
and offset

FPGA_IO_READ_BL

Digital output
I/O logic
channel
Inverting FPGA test access

FPGA_IO_WRITE_BL

Digitial input
I/O logic
channel
FPGA test access Inverting

FPGA model FPGA_IO_READ_BL

Method Description Further Information

FPGA test access Lets you replace signal values. Enabling the FPGA Test Access and Scaling on
Scaling and offset Lets you scale and add an offset to analog page 248
I/O signals.
Saturation Lets you saturate analog I/O signals.
Inverting Lets you invert the polarity of digital I/O
signals and RS232/485 signals.

Methods to access the FPGA The following methods to trace and tune FPGA signals are supported:
application § FPGA signal tracing.
§ SCALEXIO systems only: Scope for FPGA signals.
§ Tunable FPGA constants.

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§ FPGA test access.

§ FPGA scaling:
§ Scaling of analog I/O signals.
§ Inverting digital I/O signals.
§ Inverting RS232/485 signals.

The following table gives you an overview of the platforms that support the
access of FPGA applications and the methods that are supported.

Platform FPGA Scaling

Inverting Digital I/O Signals

Inverting RS232/485 Signals

Scaling Analog I/O Signals
Tunable FPGA Constants
FPGA Signal Tracing

FPGA Test Access

FPGA Scope
SCALEXIO ✓1) ✓ ✓ ✓ ✓ ✓ ✓
MicroLabBox ✓ ✓ ✓ ✓ ✓ – –
MicroLabBox II ✓ ✓ ✓ ✓ ✓ – –
MicroAutoBox II ✓ ✓ ✓ ✓ ✓ – –
MicroAutoBox III ✓ ✓ ✓ ✓ ✓ – –
1) ✓ = Supported, – = Not supported

Related topics Basics

Adjusting Values of FPGA Constants....................................................................................... 244

Displaying FPGA Signals in ControlDesk.................................................................................. 256
Enabling the FPGA Test Access and Scaling............................................................................. 248
Tracing FPGA Signals.............................................................................................................. 237

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Tracing FPGA Signals

Introduction You can make FPGA signals traceable to trace FPGA signals with your experiment
software.

Where to go from here Information in this section

Basics on Tracing FPGA Signals.............................................................. 237

Background information on the tracing mechanism, the limitations, and
the excluding of model parts from tracing.

How to Make FPGA Signals Traceable.................................................... 240

If you want to build an FPGA application that support the tracing
of FPGA signals, you must enable the feature before you build the
application.

How to Exclude FPGA Signals from Tracing............................................ 242

You can reduce the number of traceable signals by excluding parts of the
model from tracing.

Basics on Tracing FPGA Signals

Basics on FPGA tracing FPGA signals can be traced via FPGA variables that are added to the FPGA
application during the build process. These variables provide the read access for
the experiment software. The implementation of FPGA variables uses resources
of the FPGA (flip-flops). Building the FPGA application with traceable signals also
takes more time. Keep in mind that 1000 traceable FPGA signals increase the
build time for about 10%, 4000 traceable FPGA signals roughly doubles the
build time.

Tracing mechanism To trace an FPGA signal, the values of the FPGA

variables must be requested by the experiment software. That is, if the
experiment software does not request values, no values are sent to the
experiment software. The FPGA application sends requested values of traced
FPGA signals via the board-specific bus to the processor application. Then, the
processor application sends the values to your host PC. This takes time and limits
the number of traceable FPGA signals.

Tracing the signals with the experiment software A system description

file (SDF file) containing additional information for tracing variables of the FPGA
application and the processor model is generated during the build process of the
processor application. You can use the SDF file with your experiment software
to access the FPGA variables. For details, refer to Experimenting with an FPGA
Application on page 229.

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Limitations There are limitations for tracing signals of FPGA applications:

§ Every millisecond, the following number of FPGA signals can be traced:
§ At most 100 signals with up to 32-bit values.
§ At most 50 signals with up to 64-bit values.
Running applications might stop, if too many FPGA signals are traced.
§ Signals with floating-point variables can be traced only if the values are in the
single or double precision floating-point formats (IEEE 754 standard). Other
floating-point formats are not supported.
§ Signals with fixed-point variables can be traced only if the data width is 1 bit ...
64 bit.
§ The data acquisition of all traced signals is triggered by one trigger source. So
all signals are captured at the same time. It is not possible to capture signals at
different points in time.
The experiment software can trace FPGA signals only with integer multiples of
the trigger period from within the behavior model.
For details on the trigger source, refer to Trigger source for tracing on
page 240.
§ When the experiment software traces FPGA signals, it takes one task period
until the traced signals are provided to the experiment software. If you start a
new measurement, the first two measurements are not valid.
§ Traced FPGA signals cannot be used for the experiment software as trigger
condition for data acquisition or to stimulate variables.
§ Real-Time Testing is supported with the following limitations:
§ Support of fixed-point data types up to a data width of 32 bit.
§ No support of fixed-point data types for MicroLabBox II, MicroAutoBox III,
and SCALEXIO systems.
§ Use of API libraries, such as XIL API libraries or Test Automation Python
Modules, is not fully supported.
MicroAutoBox II only: No support of XIL API libraries.
§ Flight recording of traced FPGA signals is not supported.
§ SCALEXIO systems only: Tracing of FPGA signals is not supported for
application processes containing a task configured in ConfigurationDesk as
'No jitter, low latency'.

Selecting signals for tracing The number of signals that can be traced with your experiment software is
limited (refer to Limitations on page 238).

There are two ways to reduce the number of traceable FPGA signals and both
can be used at the same time:
§ Tracing of selected model parts only.
§ Excluding model parts from tracing.

Tracing of selected model parts You can enable FPGA tracing for selected
subsystems of the entire FPGA model via the FPGA_SETUP_BL block. For
instructions, refer to How to Make FPGA Signals Traceable on page 240.

Excluding model parts from tracing You can exclude a subsystem from
the TRC file by using the subsystem omission tag (DsVdOmit). You must enter

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DsVdOmit=1 in the Tag edit field in the Block Properties dialog of the
subsystem.
Exclusion is applied recursively through the model hierarchy. To reinclude
subsystems, you can enter DsVdOmit=0. By this, you can include the variables
of a specific subsystem hierarchy. You can set the DsVdOmit tag by using
workspace variables. For example, if WSVar1 is a workspace variable, you
can use set_param(subsystemHandle,'Tag','DsVdOmit=$(WSVar1)') to
let the DsVdOmit tag value being evaluated during build process.
If you set DsVdOmit=-1, the DsVdOmit settings in the included subsystems are
ignored.

Setting Description
DsVdOmit tag is The subsystem contents including all blocks beneath this subsystem do not appear in the
set to 1 generated SDF file. Use set_param(gcb,'Tag', 'DsVdOmit=1').
DsVdOmit tag is The subsystem contents including all blocks beneath this subsystem appear in the generated
set to 0 SDF file, even if a subsystem above this subsystem has set the DsVdOmit tag to 1. Use
set_param(gcb,'Tag', 'DsVdOmit=0').
DsVdOmit tag is The subsystem contents including all blocks beneath this subsystem do not appear in the
set to -1 generated SDF file. DsVdOmit settings of subsystems included in this subsystem are ignored.
Use set_param(gcb,'Tag', 'DsVdOmit=-1').

The following example shows how the DsVdOmit tags can control the exclusion
of subsystem variables. The variables of the grayed subsystems are not generated
in the SDF file.
Model Root
Subsystem1

Subsystem2 (DsVdOmit = 1)
Subsystem3
Subsystem4 (DsVdOmit = 0)
Subsystem5
Subsystem6 (DsVdOmit = 1)
Subsystem7
Subsystem8
Subsystem9
Subsystem10

For instructions, refer to How to Exclude FPGA Signals from Tracing on page 242.

Making FPGA signals Before you can trace FPGA signals with your experiment software, you must
traceable enable the generation of FPGA variables so that the FPGA signals are traceable.
You enable the tracing mechanisms via the FPGA_SETUP_BL block. For
instructions, refer to How to Make FPGA Signals Traceable on page 240.

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Trigger source for tracing The data acquisition of traced signals is triggered with the task period of the
processor application.

Platform Trigger Source

§ MicroLabBox II The FPGA custom function block (FPGA Setup block) provides a Trigger inport in
§ MicroAutoBox III ConfigurationDesk. When you map this port, you specify the task that triggers the data
§ SCALEXIO acquisition.
To provide the trigger signal, you can connect the model port to a constant in the behavior
model. Each read process triggers the FPGA application. The read value itself has no influence
on the triggering.

MicroLabBox The processor application of the processor core that programs the FPGA triggers the data
acquisition. You specify this processor application during the build configuration. Refer to How
to Build Multicore Processor Applications for MicroLabBox on page 201.
MicroAutoBox II The processor application triggers the data acquisition.

Related topics Basics

Accessing the FPGA Application with the Experiment Software (ConfigurationDesk

I/O Function Implementation Guide )

HowTos

How to Make FPGA Signals Traceable..................................................................................... 240

References

GetTraceSubsystems (FPGA Programming Software Script Interface Reference )

SetTraceSubsystems (FPGA Programming Software Script Interface Reference )

How to Make FPGA Signals Traceable

Objective If you want to build an FPGA application that support the tracing of FPGA
signals, you must enable the feature before you build the application.

Limitations For limitations on tracing FPGA signals, refer to Basics on Tracing FPGA Signals
on page 237.

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Method To make FPGA signals traceable

1 Double-click the FPGA_SETUP_BL block and open the Tracing tab.

2 On the Tracing tab, select Tracing.

3 Select the FPGA signal types to be traced:
§ Select Subsystem ports to specify that incoming and outgoing signals of
subsystems inside the selected FPGA subsystems are traceable.
§ Select Subsystem contents to specify that all signals internally used in the
selected FPGA subsystems are traceable.
§ Select Busses to specify that output signals of Simulink Bus Creator blocks
and Bus Selector blocks of the selected FPGA subsystems can be traced
directly.
4 In the tree view, select the subsystems to be accessed by clicking the
subsystem's name. If you click on a name, you select or clear the system
and its subelements.

Tip

Update lets you trigger the analysis of the number of elements that will
be accessable for the current FPGA model.The Summary area display
the result of the analysis.
For analyzing, the dialog opens a temporary model
<FPGAModelName>_rtiFPGAtmp. The dialog closes the temporary
model at the end of the analysis.

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Note

Running applications might stop, if too many FPGA signals are

traced
If you trace more than 100 signals with 32-bit values (or 50 signals with
64-bit values) every millisecond with your experiment software, tracing
might cause a task overrun that stops the application.
These measures reduce the number of traced FPGA signals per
millisecond:
§ Disable signal tracing if there is no need to trace FPGA signals.
§ Reduce the number of traceable signals. Refer to Basics on Tracing
FPGA Signals on page 237.
§ Reduce the number of signals that that you trace with the experiment
software. Only the values of signals traced with an experiment
software are sent to the real-time processor and can cause a task
overrun.

Result You enabled that the FPGA application will provide variables for tracing FPGA
signals. The variables will be added during the build process of the FPGA
application.

Related topics Basics

Accessing the FPGA Application with the Experiment Software (ConfigurationDesk

I/O Function Implementation Guide )
Basics on Tracing FPGA Signals............................................................................................... 237

HowTos

How to Exclude FPGA Signals from Tracing............................................................................. 242

How to Exclude FPGA Signals from Tracing

Objective You can reduce the number of traceable signals by excluding parts of the model
from tracing.

Method To exclude FPGA signals from tracing

1 Open the subsystem from which you want to start the exclusion.

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2 Open the Block Properties dialog of the subsystem and enter DsVdOmit=1 in
the Tag edit field.

For more information on the DsVdOmit tag, refer to Basics on Tracing FPGA
Signals on page 237.

Result You reduced the number of traceable FPGA signals. The signals of the excluded
subsystems cannot be traced with an experiment software.

Related topics Basics

Basics on Tracing FPGA Signals............................................................................................... 237

HowTos

How to Make FPGA Signals Traceable..................................................................................... 240

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Adjusting Values of FPGA Constants

Introduction You can adjust tunable FPGA constants with your experiment software.

Where to go from here Information in this section

Basics on Tunable FPGA Constants................................................ ........ 244

Background information on the adjusting mechanism and the limitations
for tunable FPGA constants.

How to Make FPGA Constants Tunable......................................... ........ 245

If you want to build an FPGA application that supports tunable FPGA
constants, you must enable the feature before you build the application.

Basics on Tunable FPGA Constants

Adjusting tunable FPGA If you enable the tracing of FPGA signals, you can also enable that tunable FPGA
constants constants are provided.

Tunable FPGA constants FPGA constants are tunable only if they are added
to a subsystem that you selected for FPGA signal tracing. If you enable
that tunable FPGA constants are provided, the FPGA constants inside these
subsystems are tunable.
For more information on selecting subsystems for tracing, refer to Basics on
Tracing FPGA Signals on page 237.

Adjusting mechanism The adjusting mechanism is similar to the tracing

mechanism: FPGA constants can be adjusted via FPGA variables that are added
to the FPGA application during the build process. These variables provide the
read access for the experiment software. The implementation of FPGA variables
uses resources of the FPGA (flip-flops).

Adjusting values of FPGA constants with the experiment software A

system description file (SDF file) containing additional information for tunable
FPGA constants is generated during the build process of the processor
application in ConfigurationDesk. You can use the SDF file with your experiment
software to access and adjust the tunable FPGA constants. For details, refer to
Experimenting with an FPGA Application on page 229.

Limitations There are limitations for adjusting tunable FPGA constants:

§ Floating-point constants can be adjusted only if the values are in the single
or double precision floating-point formats (IEEE 754 standard). Other floating-
point formats are not supported.

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§ Fixed-point constants can be adjusted with an experiment software only if the

data width is 1 bit ... 64 bit.
If you use Real-Time Testing for adjusting, fixed-point constants can be
adjusted only with the following data types:
§ Real-Time Testing is supported with the following limitations:
§ Support of fixed-point data types up to a data width of 32 bit.
§ No support of fixed-point data types for the MicroLabBox II,
MicroAutoBox III, and SCALEXIO systems.
§ The data acquisition of tunable FPGA constants is triggered by the trigger
source for the tracing mechanism. The experiment software can change FPGA
constants only with integer multiples of the trigger source period.
For details on the trigger source, refer to Basics on Tracing FPGA Signals on
page 237.
§ When the experiment software changes FPGA constant values, it takes at least
one task period until the new values are provided to the FPGA application.
§ Adjusting FPGA constants is not supported for application processes
containing a task configured in ConfigurationDesk as 'No jitter, low latency'.
§ MicroAutoBox II only: No support of XIL API libraries.

Making FPGA constants Before you can tune FPGA constants with your experiment software, you
tunable must enable the generation of additional FPGA variables to support tunable
FPGA constants. You enable this feature via the FPGA_SETUP_BL block. For
instructions, refer to How to Make FPGA Constants Tunable on page 245.

Related topics Basics

Accessing the FPGA Application with the Experiment Software (ConfigurationDesk

I/O Function Implementation Guide )

HowTos

How to Make FPGA Constants Tunable................................................................................... 245

How to Make FPGA Constants Tunable

Objective If you want to build an FPGA application that supports tunable FPGA constants,
you must enable the feature before you build the application.

Supported platforms For platforms that can provide tunable FPGA constants, refer to Methods to
access the FPGA application on page 235.

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Limitations For limitations on adjusting tunable FPGA constants, refer to Basics on Tunable
FPGA Constants on page 244.

Method To make FPGA constants tunable

1 Double-click the FPGA_SETUP_BL block and open the Tracing tab.

2 On the Tracing tab, select Tracing.

3 Select Tunable Constants.
4 In the tree view, select the subsystems including the FPGA constants that
you want to be tunable by clicking the subsystem's name. If you click on a
name, you select or clear the system and its subelements.

FPGA constants are tunable only if they reside in a subsystem that you
selected for FPGA signal tracing. For more information on selecting signals
for FPGA signal tracing, refer to Selecting signals for tracing on page 238.

Tip

Update lets you trigger the analysis of the number of elements that will
be accessable for the current FPGA model.The Summary area display
the result of the analysis.
For analyzing, the dialog opens a temporary model
<FPGAModelName>_rtiFPGAtmp. The dialog closes the temporary
model at the end of the analysis.

Result You enabled that the FPGA application will provide variables for tuning FPGA
constants. The variables will be added during the build process of the FPGA
application.

Example for tunable FPGA The following example shows you the SDF file of a DemoFPGApipt1 demo
constants project in ControlDesk. The FPGA constants Ki and Kp are added to the demo to

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replace the values that are sent from the processor model. The demo is built with
tunable FPGA constants.

Related topics Basics

Accessing the FPGA Application with the Experiment Software (ConfigurationDesk

I/O Function Implementation Guide )
Basics on Tunable FPGA Constants.......................................................................................... 244
Experimenting with an FPGA Application................................................................................ 229

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Enabling the FPGA Test Access and Scaling

Introduction You can enable the FPGA test access and scaling to substitute or scale interface
signals.

Where to go from here Information in this section

Basics on FPGA Test Access and Scaling................................................. 248

Gives you access to modify the interface signals of the FPGA application.

How to Enable FPGA Test Access and Scaling......................................... 252

If you want to build an FPGA application with FPGA test access
and scaling, you must enable the feature before you build the FPGA
application.

How to Change the Data Type of Analog Signals................................... 253

To scale and use analog signals with the required precision and value
range.

How to Specify Scaling Presettings......................................................... 254

To specify scaling presettings for offline simulation and for the build
FPGA application.

Basics on FPGA Test Access and Scaling

Introduction FPGA test access and scaling are two methods to access and modify the interface
signals of the FPGA application. If you enable FPGA test access and scaling, the
build process adds additional FPGA variables to the FPGA application to support
the features.

FPGA test access An FPGA application with FPGA test access provides intervention points at the
FPGA interface. These intervention points let you substitute values that are
exchanged with the FPGA interface.

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FPGA interface Processor interface

Interface logic PROC_XDATA_READ_BL

board-specific bus
Replace value

FPGA_XDATA_WRITE_BL Processor
model

Interface logic PROC_XDATA_WRITE_BL

Replace value
FPGA logic
FPGA_XDATA_READ_BL

Interface logic
Replace value

FPGA_IO_WRITE_BL I/O channel

Interface logic
Replace value

FPGA_IO_READ_BL

With the experiment software, you can set a value that replaces the original
signal. A replace value becomes active when you switch the input or output from
the original signal to the replace value.

FPGA Scaling FPGA scaling lets you modify the signal of the FPGA interface as follows:
§ Scaling of analog signals with a scaling factor.
§ Adding signal offsets to analog signals.
§ Saturating analog signals.
§ Inverting digital I/O signals, including RS232/485 signals.

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Analog output
I/O logic
channel
Scaling
FPGA test access Saturation
and offset

FPGA_IO_WRITE_BL

Analog input
I/O logic
channel
Scaling
Saturation FPGA test access
and offset

FPGA_IO_READ_BL

Digital output
I/O logic
channel
Inverting FPGA test access

FPGA_IO_WRITE_BL

Digitial input
I/O logic
channel
FPGA test access Inverting

FPGA model FPGA_IO_READ_BL

With the experiment software, you can set variables to scale the I/O signals.

Methods to scale analog signals There are two methods to scale analog
signals with different intentions:
§ To access and modify the analog signals with your experiment software, you
enable FPGA test access and scaling.

§ To conveniently handle the analog values, you scale the Bit values of the
analog converter to the physical unit millivolt.

This scaling is not intended to modify analog signals.

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Using the experiment The following table shows you the types of FPGA variables that are added to the
software for access SDF file to support FPGA test access and scaling:

Access Method Variable Description

FPGA test access <FPGASignal> - TA_Switchvalue Lets you switch between the actual values used
as input or output for the FPGA interface and
the substitute value.
§ 0: The actual values are used.
§ 1: The substitute value is used.
<FPGASignal> - TA_Replacevalue Lets you specify the substitute value that can
be used instead the actual values.
FPGA Analog signal <FPGASignal> - Scaling factor Lets you specify the scaling factor. The scaling
scaling modification factor amplifies the signal before it is saturated
or replaced via FPGA test access.
<FPGASignal> - Scaling offset Lets you add an offset after the signal is scaled.
<FPGASignal> - Saturation Lets you set the minimum and maximum values
minimum value to which the signals are saturated.
<FPGASignal> - Saturation
maximum value
Digital signal <FPGASignal> - Invert polarity Lets you invert the digital I/O signal.
inverting § 0: The signal is not inverted: A high-level
voltage or a low-high transition represents a
1 and vice versa.
§ 1: The signal is inverted: A high-level voltage
or a low-high transition represents a 0 and
vice versa.
RS232/485 signal <FPGASignal> - Invert polarity Lets you invert RS232/485 signals.
inverting § 0: The signal is not inverted.
§ 1: The signal is inverted.

ControlDesk instruments Intruments to modify analog signals of an FPGA application at run time are
available in ControlDesk. Refer to ControlDesk Instrument Handling .

Related topics Basics

Accessing the FPGA Application with the Experiment Software (ConfigurationDesk

I/O Function Implementation Guide )

HowTos

How to Change the Data Type of Analog Signals.................................................................... 253

How to Enable FPGA Test Access and Scaling.......................................................................... 252
How to Specify Scaling Presettings.......................................................................................... 254

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How to Enable FPGA Test Access and Scaling

Objective If you want to build an FPGA application with FPGA test access and scaling, you
must enable the feature before you build the FPGA application.

Method To enable FPGA test access and scaling

1 Double-click the FPGA_SETUP_BL block and open the Tracing tab.

2 On the Tracing tab, select Tracing.

3 Select Tunable Constants.
4 Select Test Access and I/O Scaling.

Tip

Update lets you trigger the analysis of the number of elements that will
be accessable for the current FPGA model.The Summary area display
the result of the analysis.
For analyzing, the dialog opens a temporary model
<FPGAModelName>_rtiFPGAtmp. The dialog closes the temporary
model at the end of the analysis.

Result You enabled that the FPGA application includes variables to provide the signal
ports and function ports with FPGA test access and scaling. The variables will be
added during the build process of the FPGA application.

To access the variables for FPGA test access and scaling, you use the SDF file that
is generated when you build the real-time application.

For an overview of the added FPGA variables, refer to Using the experiment
software for access on page 251.

Example for FPGA test access The following example shows you the added variables for the
and scaling FPGA_XDATA_READ_BL1 interface block for FPGA test access and scaling in
ControlDesk. The example application is built with FPGA test access and scaling.

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Related topics Basics

Accessing the FPGA Application with the Experiment Software (ConfigurationDesk

I/O Function Implementation Guide )
Basics on FPGA Test Access and Scaling.................................................................................. 248

How to Change the Data Type of Analog Signals

Objective To scale and use analog signals with the required precision and value range.

Precondition FPGA test access and scaling must be enabled. Refer to How to Enable FPGA Test
Access and Scaling on page 252.

Method To change the data type of an analog signal

1 Double-click the FPGA I/O interface block (FPGA_IO_WRITE_BL or
FPGA_IO_READ_BL) and open the Scaling page.

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The Scaling page displays the scaling parameters that are supported for the
selected I/O function.
2 On the Scaling page, specify the format and the bit width of analog signal
values.

For more information on the parameters, open the Description page and
click the Help for <block name> button.

Result You changed the data type that is used by the selected I/O function for analog
signal values.

The new data type is used as follows:

§ New data type for the following scaling parameters:
§ Scaling factor
§ Scaling offset
§ Saturation minimum value
§ Saturation maximum value
§ New data type for the Data port of the selected I/O function to support the
new precision and value range.

Related topics Basics

Basics on FPGA Test Access and Scaling.................................................................................. 248

How to Specify Scaling Presettings

Objective To specify scaling presettings for offline simulation and for the build FPGA
application.

Supported platforms For platforms that support the scaling of I/O signals, refer to Methods to access
the FPGA application on page 235.

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Precondition FPGA test access and scaling must be enabled. Refer to How to Enable FPGA Test
Access and Scaling on page 252.

Method To specify the scaling presettings

1 Double-click the FPGA I/O interface block (FPGA_IO_WRITE_BL or
FPGA_IO_READ_BL) and open the Scaling page.

The Scaling page displays the scaling parameters that are supported for the
selected I/O function.
2 On the Scaling page, specify the settings for the scaling parameters.

Note

Scaling of analog Signals

It is not checked whether the specified and displayed values for analog
I/O signals are supported by the data type or hardware. The values
will be executed with the maximum accuracy and saturated to the
minimum and maximum values that are supported by the data type and
the hardware.
For specifying the data type, refer to How to Change the Data Type of
Analog Signals on page 253.

For more information on the parameters, open the Description page and
click the Help for <block name> button.

Result You specified the scaling presettings for the selected I/O function. The settings
are used for offline simulation and for the build of the FPGA application.

Related topics Basics

Basics on FPGA Test Access and Scaling.................................................................................. 248

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Displaying FPGA Signals in ControlDesk

Introduction You can add FPGA Scope blocks to the FPGA model to display FPGA signals in
ControlDesk.

Capturing FPGA Signals for Display in ControlDesk

Introduction The FPGA Scope block lets you connect up to 16 FPGA signals that can be
captured. Nevertheless, only 8 FPGA signals can be displayed in ControlDesk at
the same time. You can select the signals to be displayed in ControlDesk.

Limitations You must observe the following limitations.

§ The platform must be a SCALEXIO system.
§ The data type must be signed integer, unsigned integer, or single precision
floating‑point (XFloat_8_24).
The Boolean data type is not supported. As an alternative, you can use
UFix_1_0.
§ The maximum bit width of signals that can be captured is 32 bit.

Basics on capturing If a trigger event occurs, the FPGA Scope block captures a time sequence of
the connected FPGA signals. The scope depth indicates the number of captured
data values. As an alternative, you can use the video mode to capture the FPGA
signals without triggering.

Time sequence length The scope depth limits the number of signal
values in a captured time sequence. The highest time resolution
to capture the FPGA signal is the FPGA clock period. You can
downsample the signal capturing to capture a longer time sequence
with a reduced time resolution. The length of a time sequence is
tsequence = Scope deptℎ ⋅ Downsampling factor ⋅ FPGA clock period

Configuring the scope You can specify the scope depth in the block dialog. Refer to FPGA Scope (FPGA
Programming Blockset - FPGA Interface Reference ).

The FPGA Scope instrument in ControlDesk lets you configure the signal
capturing at run time, such as the trigger conditions and downsampling factor.
Refer to FPGA Scope (ControlDesk Instrument Handling ).

After you build the FPGA application, the FPGA custom function lets you
specify an initial scope configuration in ConfigurationDesk. Refer to Configuring
the Basic Functionality (FPGA) (ConfigurationDesk I/O Function Implementation
Guide ).

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Related topics References

FPGA Scope (FPGA Programming Blockset - FPGA Interface Reference )

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Troubleshooting

Introduction When working with the FPGA Programming Software there are some problems
which can arise.

Problems and Their Solutions

Overview Known problems and their solution are grouped by their occurrence:
§ General modeling issues on page 259
§ Implementing the FPGA model on page 260
§ Building an FPGA application on page 262
§ Building a processor application on page 266
§ Running the FPGA application on a dSPACE system on page 267

General modeling issues Copying of model parts takes a long time Copying the FPGA
Programming Blockset's function blocks might take too long. As of FPGA
Programming Blockset 3.3, the blockset automatically analyzes the FPGA model
and reassigns new hardware resources. The analysis might take too long.
You can speed up the copy & paste process for the current session by
deactivating the automatic reassignment of new hardware resources:
§ Open the Advanced Preferences dialog and set the
PASTE_KEEP_CHANNEL_NUM preference to false. Refer to Dialog Settings
of the Advanced Preferences Dialog (FPGA Programming Blockset - FPGA
Interface Reference ).

No FPGA model actions (Vitis Model Composer Hub) The FPGA

Programming Blockset cannot perform model actions because the System
Generator block is migrated to the Vitis Model Composer Hub block.
Measure if the Vitis Model Composer Hub block is part of the FPGA model:
§ Delete the Vitis Model Composer Hub block.
§ Open the Platform tab of the FPGA Setup block.

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§ Simulate a a change of a setting: Select a different platform and then select

the correct platform again.
§ Click OK.
The FPGA Programming Blockset adds the System Generator block.

Implementing the FPGA The following errors might occur in implementing the FPGA model via the HDL
model library of the AMD Vitis Model Composer and trying to perform actions like
offline simulation or FPGA build. The messages appear in the MATLAB command
prompt and/or in a MATLAB or Simulink error dialog box.

Incorrect display of sample time information When you use Simulink's

Sample Time Display, the displayed sample time colors might be wrong when the
model is in the compiled state, for example, during the offline simulation. This is
caused by a display problem when using the HDL library of the AMD Vitis Model
Composer.
§ Always update your model (Ctrl+D) before you interpret the colors. After the
model update, the colors are correct.

Error message (Solver types)

The periodic sample time ... is not allowed because the ratio
of this sample time over base rate (...) is greater than the
maximum value of uint32.
or
Invalid setting for fixed-step size (...) in model '...'.
All sample times in your model must be an integer multiple of
the fixed-step size.
This message might appear in updating the Simulink model including an FPGA
subsystem (Update Diagram, Ctrl-D) if the solver options are configured as a
Fixed-step type. AMD Vitis Model Composer supports solver options configured
as a Variable-step type only. The diagram update can be launched explicitly or
triggered implicitly when you run an offline simulation, an FPGA build process,
etc.
§ If FPGA subsystems are part of the model, always choose a Variable step solver
to perform an offline simulation, an FPGA build process, etc. (model mode:
FPGA-Build/Offline Simulation).
§ Choose a Fixed-step solver only if there are no more FPGA subsystems in the
model (model mode: Processor-Build).

Error message (Signal periods)

The period of the signal driving the enable of this block is
inappropriate. The period must be an integer multiple of the
gcd of signals driving the following input ports:
d : ...
enable period: ...
This message might appear in updating the Simulink model including an FPGA
subsystem (Update Diagram, Ctrl-D). The diagram update can be launched
explicitly or triggered implicitly when you run an offline simulation, an FPGA

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 Problems and Their Solutions

build process, etc. The error message is reported by an FPGA interface block of
the FPGA Programming Blockset.
§ Control the data path driving the reporting FPGA interface block.
§ If a Down Sample block from the HDL library of the AMD Vitis Model
Composer was used in this path, make sure that there is always a
corresponding Up Sample block before driving the FPGA interface block.
§ Make sure that the downsampling factor of the whole path exactly matches
the upsampling factor. For example, there could be two cascaded Down
Sample blocks each with factor 2 and one Up Sample block with factor 4.
§ If a block of teh HDL library of the AMD Vitis Model Composer defining
its own sample period, for example, a Counter block, drives the FPGA
interface block, make sure that the defined sample period matches the offline
simulation period specified in the FPGA_SETUP_BL block.
§ If the sample period must be higher than the system period, for example, if the
counter has to run at a lower rate to count slower, use an Up Sample block
before driving the FPGA interface block. The factor by which the driving block
runs slower must be upsampled precisely.

Error message (FPGA_SETUP_BL block)

All Xilinx Blocks must be contained in a level of hierarchy
with a System Generator Token.
This error might appear if there is no block on the same hierarchy level as the
FPGA_SETUP_BL block within the FPGA subsystem. This happens, for example, if
all the other blocks in the FPGA model are encapsulated by subsystems, i.e., only
subsystems are on the same level as the FPGA_SETUP_BL block.
1. Place at least one block on the same hierarchy level as the FPGA_SETUP_BL
block. This might be a dummy block, for example, a Constant block
from the HDL library of the AMD Vitis Model Composer or an
FPGA_IO_READ_BL block from the FPGA Programming Blockset.
2. Restart the MATLAB session.
3. Restart the offline simulation.

Error message (Resource Estimator block)

Error using ==>resourceestimatoraction>checkForSysgenToken at 51
The Resource Estimator requires instancing of a Sysgen Token
in the same Subsystem
This error might appear if you try to use a AMD Resource Estimator block in an
FPGA subsystem.
§ Use the Update Diagram command (Ctrl-D) in the model to instantiate a
System Generator Setup block (Sysgen Token).
§ Restart the resource estimation.

Error message (Offline simulation)

No data is transmitted to and from an FPGA subsystem during
an offline simulation although the corresponding interface
blocks are modelled and parameterized correctly.
This error appears if the FPGA subsystem has been replaced by an FPGA model
INI file in the Processor Setup block. FPGA Model INI files cannot be simulated.
§ Check the settings in the Processor Setup block and make sure that the
affected FPGA subsystem is assigned to the FPGA board you want to simulate.
It is not enough to include the FPGA subsystem in the model.

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Warning message (Sample time inheritance)

Warning: Source '.../FPGA_XDATA_WRITE_BL1/phs_write_register/
phs//rtlib_sim_model/Data Store Read' specifies that its sample
time (-1) is back-inherited. You should explicitly specify the
sample time of sources.
This warning appears if the offline simulation model of an FPGA block tries to
inherit the sample time of its corresponding block in the processor model.
§ This is the intended behavior of the FPGA interface blocks, specified by the
default settings. The message can be ignored.
§ You can suppress the message:
§ You can disable this diagnostic by setting the Source block specifies
-1 sample time diagnostic to none in the Sample Time group on the
Diagnostics pane of the Configuration Parameters dialog box.
§ You can explicitly set the Simulation ports sample time to a value other
than -1 for each affected FPGA interface block on its Parameters page.

Error message (Invalid Simulink handle)

Trouble running xlUpdateIcon(3617,0003662109375,-1,-1,-1,
{'\fontsize{11pt}\bf In ',},{' ',},{'',},'','bc55d28f');;
Error was: Error using ==> get_param
This error might appear if the AMD Vitis Model Composer uses an invalid
Simulink handle format due to specific regional settings.
§ Change your Windows regional settings to English
or
§ Change your Windows settings for the decimal point to point instead of
comma.

Warning message (Broken connections)

Warning: Matching "Goto" for "From" '...' not found
This warning appears if the offline simulation connections of corresponding
blocks in the FPGA subsystem and the processor model are broken. This might
happen if you simulate an FPGA subsystem in a processor model and then
change the assignment in the Processor Setup block from the FPGA subsystem to
the FPGA model INI file with the FPGA subsystem remaining in the model.
§ This warning can be ignored for FPGA interface blocks because the broken
connections are restored whenever they are required for offline simulation.
When the warning appears no offline simulation is performed with the
affected blocks.
§ You can eliminate this warning by regenerating the FPGA interface block
structures.
§ For blocks of the Processor Interface, perform an Update Diagram command
(Ctrl-D)
§ For blocks of the FPGA Interface, open the FPGA Setup block, reselect the
current FPGA framework and close the dialog by clicking OK.

Building an FPGA application The following errors might occur in building an FPGA application. They appear in
the MATLAB Command Window and/or in a MATLAB or Simulink error dialog.

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Path length exceeds maximum length During the build process the path
length can get unpredictably long, as shown by the following example:
<model_folder>\<modelname>_rtiFPGA\
<modelname>_<ApplicationID\sysgen\hdl_netlist\cm.runs\
cm_c_counter_binary_v12_0_0_synth_1\
cm_c_counter_binary_v12_0_0*.*
It is not possible to specify a maximum build path length that is guaranteed to
work.
The windows operating system limits the maximum path length to
260 characters. This limitation might lead to miscellaneous error messages
during file system operations.
1. Minimize the total length of the working folder, the FPGA build
folder, the model name, and the name of the FPGA subsystem
to be built. For details on specifying the FPGA build folder, refer
to Parameters Page (FPGA_SETUP_BL) (FPGA Programming Blockset -
FPGA Interface Reference ). For details on minimizing the total
length of the working folder, refer to AMD Answer Record 52787
(https://support.xilinx.com/s/article/52787?language=en_US).
2. Restart the build process.

Error message (Build path)

RTI Build Error
An error occurred in the build of the Xilinx System Generator
Error in compiling/generating the netlist.
… and …
Standard exception: XNetlistEngine:
An exception was raised:
com.xilinx.sysgen.netlist.NetlistInternal: couldn't run
/coregen.exe:
There are several reasons for this error:
§ One typical reason for this error is a too-long build path, which leads to
problems when the AMD tools perform file system operations. For details,
refer to Path length exceeds maximum length on page 263.
§ The AMD CORE Generator might run into memory problems when using the
Java virtual machine. The reason might be either not enough or too much
reserved memory.
1. Check the CORE Generator log file to determine the exact error reason.
§ Use a file search to find the log file second_pass_coregen.txt
in the subfolders of the FPGA interface build folder
<WorkingDir>/<ModelName>_rtiFPGA/...
§ Open the log file and find the following error: ERROR:coreutil:195 -
Could not create Java virtual machine – JVM
2. Increase the memory size available for Java objects in MATLAB.
§ Set the Java Heap Size value to at least 768 MB in the General - Java
Heap Memory page of MATLAB's Preferences dialog.
3. See AMD Answer Records 20708 and 20780 for further details
(https://support.xilinx.com/s/article/52787?language=en_US).
§ The AMD CORE Generator fails to generate a core for a Constant Multiplier
(CMult) configured with a factor of 1 and a bit width of 1.

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1. Check the CORE Generator log file to determine the exact error reason.
§ Use a file search to find the log file second_pass_coregen.txt
in the subfolders of the FPGA interface build folder
<WorkingDir>/<ModelName>_rtiFPGA/...
§ Open the log file and find the following error: ERROR:sim -
PortBWidth: Value '1' is out of range '[2..64]'
2. Replace all CMult blocks configured as described above by Delay blocks.
This results in the same behavior, but a Delay block only needs one register
entry, whereas a CMult block allocates a DSP block.

Error message (Lack of resources)

Starting mapping...
------------------------------------------------------------
RTI Build Error
Mapping failed because of overmapping. Your design is probably
too large for the FPGA you use. For further details, refer to
the Xilinx log file, which is located in:
...
This error appears if the FPGA application does not fit on the FPGA due to a lack
of resources. The application is too large for the FPGA device.
§ Reduce the resource requirements by removing parts of the FPGA model if
applicable.
§ Check the bit widths of the signals used in the design. The higher the bit
widths, the higher the resource requirements.
§ Change the implementation-specific settings for each block of the HDL library
of the AMD Vitis Model Composer. Several blocks, for example, the Mult,
Counter, CMult or AddSub blocks, provide an Implementation page in
their block dialogs:
§ Try using embedded multipliers/DSP48 blocks or not.
§ Try using behavioral HDL or Cores.
§ Try using distributed RAM or Block RAM.
§ Try using optimization for area instead of speed.
§ Reduce the resource-dependent settings in the FPGA interface blocks, for
example, the buffer depth.
§ Reduce the overall number of FPGA interface blocks used.
§ Use the AMD Resource Estimator block to quickly check which decisions
save resources. For Resource Estimator usage, see Error message (Resource
Estimator block) on page 261.

Error message (Timing constraints)

RTI Build Error
At least one timing constraint of your system was not met.
You can analyze your design with the Timing Analyzer.
For further details, refer to the log file located in:
...
or
RTI Build Error
Mapping was not successful. For further details, refer to
the Xilinx log file, which is located in:
...

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This error appears if the FPGA application cannot run on the FPGA due to timing
issues. The design cannot run at the FPGA’s clock frequency.
§ Run a Timing Analysis to determine exactly which data path of your model
does not meet timing constraints.
§ Make the path a multicycle path by downsampling. Use the Down Sample
and Up Sample blocks of the HDL library of the AMD Vitis Model Composer
in the data path.
§ When using DSPs in a multicycle path, refer to Notes on Using Multicycle Paths
on page 71.
§ Add additional latency to the data path by:
§ Inserting dedicated Register or Delay blocks in the data path.
§ Increasing the Latency parameter of blocks within the data path.
§ Change the implementation-specific settings for each FPGA block. Several
blocks, for example, the Mult, Counter, CMult or AddSub blocks, provide an
Implementation page in their block dialogs:
§ Use Cores instead of behavioral HDL.
§ Use optimization for speed instead of area.
§ Enable pipelining.

Error message (Vivado clock interaction report detected unsafe clock

interactions)
Vivado clock interaction report detected unsafe clock interactions.
(…)
This error appears when Vivado detects problems concerning the decoupling of
subsystems with different clock periods. For example: Using registers to decouple
data words increases metastability.
However, Vivado incorrectly detects the use of registers to decouple the
transmission of bit values (UFix_1_0) as an error.
§ Fix the reported clock interactions problems to build a reliable FPGA
application.
§ You can disable the check if you are sure that the detected problems will not
lead to an unreliable FPGA application. For example, if you used registers to
decouple the transmission of bit values.
Open the Advanced Preferences dialog and set the
IGNORE_CLOCK_INTERACTION_PROBLEMS preference to true. Refer to
Dialog Settings of the Advanced Preferences Dialog (FPGA Programming
Blockset - FPGA Interface Reference ).

Warning message (Too much asynchronous logic detected)

CRITICAL WARNING: Too much asynchronous logic detected!
This may cause unstable operation. Please revise your design. (…)
This warning appears when 30% of the total FPGA logic is used in signal paths
that are downsampled with a sample time less than 100 ns by using the Down
Sample and Up Sample blocks of the HDL library of the AMD Vitis Model
Composer. Such designs do not comply with the generally accepted FPGA design
rules that ensure a stable and reliable FPGA application.
Replace the downsampled signal paths with signal paths using registers/flip-
flops.

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When asynchronous logic is replaced by synchronous logic, the following items

are important:
§ Ensure the timing constraints.
In FPGA logic, timing is always measured between two flip-flops. This means
that if a signal does not make its way through combinatorial logic (i.e., all
operations with latency 0) between two flip-flops in the FPGA clock period,
the timing is violated and the FPGA build is aborted.

§ When processing different signals, ensure that the signal transmission time is
the same.
For example: Three values of an analog converter are processed to one signal.
To process the values of the same point in time, the delay of the signals must
be the same.

Building a processor The following errors might occur when performing a Simulink Coder build
application to generate a processor application. They appear in the MATLAB Command
Window and/or in a MATLAB or Simulink error dialog.

Error message (Wrong model mode)

Model contains dSPACE FPGA blocks.

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This error appears when you try to start a Simulink Coder build process for a
model that still contains FPGA subsystems.
§ Switch the model mode from FPGA-Build / Offline Simulation to Processor-
Build by using the Processor Setup block (PROC_SETUP_BLx). This step
temporarily removes all FPGA blocks from the model.

Running the FPGA application The following errors might occur in running the built FPGA application on a
on a dSPACE system dSPACE system. You can find the source of the errors by experimenting with
dSPACE's ControlDesk.

Error message (No FPGA application loaded)

<FPGA hardware>_init(0x00): No FPGA application loaded. (302)
This error appears when you download a processor application that tries to
access an FPGA application but no FPGA application is running on the FPGA
board/module.
§ Choose the programming options into ram or into flash for the FPGA
application in the Processor Setup block (PROC_SETUP_BLx) before performing
a Simulink Coder build process to download the processor application.
§ If you have chosen the into flash programming option, the autoboot option
from the FPGA board’s/module’s flash memory has to be enabled and the
dSPACE hardware has to be switched off and on once to start programming
the FPGA from the flash.

Error message (Incompatible FPGA model INI file)

<FPGA hardware>_program(0x00): The model ini-File you use is
incompatible to your Hardware! (332)
This error appears when you try to use an FPGA model INI file to program an
FPGA board or FPGA module the INI file is not intended for.
§ Choose the correct FPGA framework for your hardware configuration. There
are FPGA frameworks available for each possible combination of FPGA boards
or FPGA modules and I/O modules (piggyback boards).
§ Adapt your hardware system, by mounting the correct I/O module on the
FPGA board or FPGA module. The FPGA model INI file might be correct but
not suitable to the hardware configuration.
§ Check your dSPACE installation. If you try to use a new FPGA board or module
with an old dSPACE installation, the new board or module might not be
recognized as compatible by the software. Refer to the user documentation
of the FPGA Programming Blockset to get information on the supported
hardware.

Error (Simulation results)

The online simulation results do not match the offline
simulation results from the Simulink model.
This error might appear for several reasons:
§ Synchronous vs. asynchronous FPGA and processor applications:
§ In a Simulink simulation, the communication between the FPGA model and
the processor model is deterministic. Both applications run synchronously on
a common time base.

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§ On the dSPACE hardware, the FPGA application runs independently of the

processor model. Each application runs asynchronously with its own time
base.
§ The values of the Simulink offline simulation and the online simulation on
dSPACE hardware should match, but not the timing of the communication
between FPGA and processor application.
§ Offline simulation period vs. FPGA period
§ To guarantee precise results, the offline simulation period must match the
FPGA's period. (This is in contrast to online simulation, which can run at a
higher sample period because simulating the FPGA's period takes a lot of
computing power).
§ If the FPGA application contains timing-dependent parts such as discrete
integrators that accumulate by a time factor, you must be sure to adapt the
time factor to the FPGA’s period before building the FPGA application if the
offline simulation was performed at a different sample period and therefore
with a different time factor.

General note Even if no errors occurred during modeling, simulating, and

building, your FPGA application is not guaranteed to work correctly. Some
combination of factors might prohibit the execution of your FPGA application,
e.g., combinations of the operating temperature, the power of the entire
hardware system, technological limitations of the FPGA, the sample rate, etc.
Some FPGA applications do not start at all, others start correctly but fail during
operation.
Due to the complexity of FPGA applications and their dependency on the used
FPGA hardware, the AMD Design Tools cannot ensure that all possible design
problems are detected during the analysis and simulation of the FPGA model.
To solve the problem, you have to modify the FPGA model and make sure that
you consider generally accepted FPGA design rules to ensure a stable and reliable
FPGA application (refer to Audience profile on page 9). For more information,
contact dSPACE Support.

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 Index

I
Index
feature overview 25
A DS2655 FPGA Base Board
I/O access 73
feature overview 27
accessing FPGA signals I/O mapping of input channels 74
DS2655M1 Multi-I/O Module
experiment software 230 I/O mapping of output channels 75
feature overview 28
SDF file 230 I/O modules
DS2655M2 Digital I/O Module
adjusting FPGA constants for MicroAutoBox II 25
feature overview 28
adjusting mechanism 244 for MicroAutoBox III 25
DS6601 FPGA Base Board
basics 244 for SCALEXIO DS2655 28
feature overview 27
limitations 244 input channel number 73
DS6602 FPGA Base Board
AMD Design Suite 20 input channel types 73
feature overview 27
AMD Vitis Model Composer 20
DS6651 Multi-I/O Module
feature overview 28 L
B Local Program Data folder 11
best practise 54 E
building FPGA application
effects of modeling external I/O access 75 M
FPGA Build Server
exchanging data with the processor model 55, MAP file 230
basics 212
130 MicroAutoBox II
MicroAutoBox II 195
experimenting with FPGA application 229 building FPGA application 195
MicroAutoBox III 186
exporting to ConfigurationDesk feature overview 24
separating the processor model 189
build result 191 MicroAutoBox III
MicroLabBox 195
processor model 191 feature overview 24
MicroLabBox II 186
MicroLabBox
SCALEXIO system 186
separating the processor model 189 F building FPGA application 195
feature overview 22
building multicore processor application features
MicroLabBox II
MicroLabBox 201 new features 32
feature overview 23
building processor application Release 2021-A 39
migrating
MicroAutoBox III 193 Release 2021-B 39
framework 43
MicroLabBox II 193 Release 2022-A 38
platform 43
SCALEXIO system 193 Release 2022-B 37
modeling
building single-core processor application Release 2023-A 34
multiple clock domains 81
MicroAutoBox II 200 Features
user clock domains 84
MicroLabBox 200 Release 2023-B 33
burnapplication folder 204 FPGA application name 55
FPGA architecture 13 N
C FPGA board assignment 54 new features
FPGA data synchronization 56 FPGA Programming Blockset 32
clock domain
FPGA interface 16
multiple 81
FPGA Programming Blockset
user clock 84 O
components 16
clock period output channel number 74
hardware support 22
multiple clock domains 81 output channel types 74
new features 32
user clock domains 84
FPGA scaling
Common Program Data folder 11
basics 249 P
components of the FPGA Programming
FPGA test access Parameters page
Blockset 16
basics 248 empty 52
creating a burn application 203
enabling 252 processor communication
FPGA tracing MicroAutoBox II 131
D basics 237 MicroAutoBox III 131
Description page enabling 240 MicroLabBox 131
empty 52 excluding signals 242 MicroLabBox II 131
deseparating a model 199 limitations 238 SCALEXIO 132
Documents folder 11 processor interface 16
downloading FPGA application 229 G implementing 148
downloading processor application 229 programming FPGA 203
generating a processor interface 148
DS1514 programming into flash 203
feature overview 24 programming into RAM 203
DS1552 Multi-I/O Module H providing simulation ports 174
feature overview 25 hardware support 22
DS1552B1 Multi-I/O Module
R
feature overview 25
DS1554 Engine Control I/O Module reading an FPGA signal 47

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 Index

reading from an external input channel 73

replacing Gateway blocks 47
resetting FPGA framework 48
rtiFGPASeparationFile 199

S
SCALEXIO FPGA base board
feature overview 27
SDF file 230
separating a model 199
simulating FPGA subsystem 174
simulating processor model 175
specifying offline simulation period 174
supported AMD design tools 21
supported MATLAB versions 21
supported operating systems 21
switching model mode 199

T
tracing FPGA signals
basics 237
excluding model parts 238
limitations 238
subsystem omission tag (DsVdOmit) 238
tracing mechanism 237
TRC file 230
troubleshooting 259
building FPGA application 262
building processor application 266
copying FPGA model 259
implementing FPGA model 260
no FPGA model actions 259
path length 263
running FPGA application 267
too much asynchronous logic 265
unsafe clock interactions 265
viewing sample time information 260
Vitis Model Composer Hub 259
tunable FPGA constants
basics 244
enabling 245
limitations 244

U
updating FPGA framework 42

W
workflow 57
using a MicroAutoBox II 60
using a MicroAutoBox III 58
using a MicroLabBox 60
using a MicroLabBox II 58
using a SCALEXIO system 58
writing an FPGA signal 48
writing to output channels 74

X
Xilinx System Generator for DSP 20

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