FPGA Programming Blockset

FPGA Interface Reference

For FPGA Programming Blockset 2024-A

Release 2024-A – May 2024

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If possible, always provide the serial number of the hardware, the relevant dSPACE License
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© 2009 - 2024 by:

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This publication and the contents hereof are subject to change without notice.

AURELION, AUTERA, ConfigurationDesk, ControlDesk, MicroAutoBox, MicroLabBox,

SCALEXIO, SIMPHERA, SYNECT, SystemDesk, TargetLink, and VEOS are registered
trademarks of dSPACE GmbH in the United States or other countries, or both. Other
brand names or product names are trademarks or registered trademarks of their respective
companies or organizations.
 Contents

Contents

About This Reference 11

General Information on the FPGA Interface of the FPGA

Programming Blockset 15
Overview of the FPGA Programming Blockset................................................ 15
Features of the FPGA Programming Blockset................................................. 19

Common FPGA Blocks of the FPGA Programming

Blockset 23
FPGA_SETUP_BL..................................................................................................... 24
Block Description (FPGA_SETUP_BL).............................................................. 24
Unit Page (FPGA_SETUP_BL).......................................................................... 25
Parameters Page (FPGA_SETUP_BL)............................................................... 26
Subsystem Clocks Page (FPGA_SETUP_BL)..................................................... 30
FPGA Access Page (FPGA_SETUP_BL)............................................................. 31
ConfigurationDesk Interface Page (FPGA_SETUP_BL)..................................... 33

FPGA Scope........................................................................................................... 37
Block Description (FPGA Scope)..................................................................... 37
General Page (FPGA Scope)........................................................................... 39

HDL Coder Gateways............................................................................................. 40

Intramodel Out and Intramodel In................................................................. 40

FPGA Interface Blocks (Common Settings) 43

FPGA_XDATA_READ_BL......................................................................................... 44
Block Description (FPGA_XDATA_READ_BL)................................................... 45
Unit Page (FPGA_XDATA_READ_BL).................................................. ............ 46
Description Page (FPGA_XDATA_READ_BL).................................................... 48

FPGA_XDATA_WRITE_BL........................................................................................ 49
Block Description (FPGA_XDATA_WRITE_BL).................................................. 50
Unit Page (FPGA_XDATA_WRITE_BL)............................................................. 51
Description Page (FPGA_XDATA_WRITE_BL)...................................... ............ 53

FPGA_IO_READ_BL................................................................................................. 54
Block Description (FPGA_IO_READ_BL).......................................................... 54

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Unit Page (FPGA_IO_READ_BL)...................................................................... 55

Description Page (FPGA_IO_READ_BL)........................................................... 56

FPGA_IO_WRITE_BL............................................................................................... 58
Block Description (FPGA_IO_WRITE_BL)......................................................... 59
Unit Page (FPGA_IO_WRITE_BL)..................................................................... 60
Description Page (FPGA_IO_WRITE_BL).......................................................... 60

FPGA_INT_BL......................................................................................................... 62
Block Description (FPGA_INT_BL)................................................................... 63
Unit Page (FPGA_INT_BL).................................................................. ............ 64
Description Page (FPGA_INT_BL).................................................................... 64

Dialog Settings to Edit Simulink Bus Signals............................................................ 66

Bus Editor Dialog - FPGA_XDATA_READ_BL/FPGA_XDATA_WRITE_BL............ 66

Block Settings for the MicroLabBox Frameworks 69

FPGA_XDATA_READ_BL (DS1202 FPGA I/O Type 1 Settings)................................... 70
Parameters Page (FPGA_XDATA_READ_BL).................................................... 70
Description Page (FPGA_XDATA_READ_BL).................................................... 77

FPGA_XDATA_WRITE_BL (DS1202 FPGA I/O Type 1 Settings).................................. 79

Parameters Page (FPGA_XDATA_WRITE_BL)................................................... 79
Description Page (FPGA_XDATA_WRITE_BL)...................................... ............ 86

FPGA_IO_READ_BL (DS1202 FPGA I/O Type 1 Settings)........................................... 88

Parameters Page (FPGA_IO_READ_BL)........................................................... 88
Scaling Page (FPGA_IO_READ_BL)................................................................. 95
Description Page (FPGA_IO_READ_BL)........................................................... 98

FPGA_IO_WRITE_BL (DS1202 FPGA I/O Type 1 Settings)............................. .......... 100

Parameters Page (FPGA_IO_WRITE_BL)........................................................ 100
Scaling Page (FPGA_IO_WRITE_BL).............................................................. 117
Description Page (FPGA_IO_WRITE_BL)........................................................ 121

FPGA_INT_BL (DS1202 FPGA I/O Type 1 Settings)....................................... .......... 122

Parameters Page (FPGA_INT_BL).................................................................. 122
Description Page (FPGA_INT_BL).................................................................. 123

Block Settings for the MicroLabBox II Framework 125

FPGA_XDATA_READ_BL (MicroLabBox II).............................................................. 126
Parameters Page (FPGA_XDATA_READ_BL).................................................. 126

FPGA_XDATA_WRITE_BL (MicroLabBox II)............................................................. 135

Parameters Page (FPGA_XDATA_WRITE_BL)................................................. 135

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FPGA_IO_READ_BL (MicroLabBox II)..................................................................... 147

Parameters Page (FPGA_IO_READ_BL)......................................................... 147
Scaling Page (FPGA_IO_READ_BL)............................................................... 165

FPGA_IO_WRITE_BL (MicroLabBox II).................................................................... 169

Parameters Page (FPGA_IO_WRITE_BL)........................................................ 169
Scaling Page (FPGA_IO_WRITE_BL).............................................................. 188

FPGA_INT_BL (MicroLabBox II).............................................................................. 192

Parameters Page (FPGA_INT_BL).................................................................. 192

Block Settings for the SCALEXIO Frameworks 195

Block Settings for the DS2655 FPGA Base Board Framework...................... .......... 196

FPGA_XDATA_READ_BL (DS2655 FPGA Base Board Settings)........................... 196

Parameters Page (FPGA_XDATA_READ_BL).................................................. 197

FPGA_XDATA_WRITE_BL (DS2655 FPGA Base Board Settings).......................... 206

Parameters Page (FPGA_XDATA_WRITE_BL)................................................. 206

FPGA_IO_READ_BL (DS2655 FPGA Base Board Settings).................................. 217

Parameters Page (FPGA_IO_READ_BL)......................................................... 218
Scaling Page (FPGA_IO_READ_BL)............................................................... 229

FPGA_IO_WRITE_BL (DS2655 FPGA Base Board Settings)................................. 229

Parameters Page (FPGA_IO_WRITE_BL)........................................................ 230
Scaling Page (FPGA_IO_WRITE_BL).............................................................. 238

FPGA_INT_BL (DS2655 FPGA Base Board Settings)........................................... 239

Parameters Page (FPGA_INT_BL).................................................................. 239

Block Settings for the DS6601 FPGA Base Board Framework...................... .......... 241

FPGA_XDATA_READ_BL (DS6601 FPGA Base Board Settings)........................... 241

Parameters Page (FPGA_XDATA_READ_BL).................................................. 242

FPGA_XDATA_WRITE_BL (DS6601 FPGA Base Board Settings).......................... 251

Parameters Page (FPGA_XDATA_WRITE_BL)................................................. 251

FPGA_IO_READ_BL (DS6601 FPGA Base Board Settings).................................. 262

Parameters Page (FPGA_IO_READ_BL)......................................................... 263
Scaling Page (FPGA_IO_READ_BL)............................................................... 275

FPGA_IO_WRITE_BL (DS6601 FPGA Base Board Settings)................................. 276

Parameters Page (FPGA_IO_WRITE_BL)........................................................ 276
Scaling Page (FPGA_IO_WRITE_BL).............................................................. 285

FPGA_INT_BL (DS6601 FPGA Base Board Settings)........................................... 286

Parameters Page (FPGA_INT_BL).................................................................. 286

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Block Settings for the DS6602 FPGA Base Board Framework...................... .......... 288

FPGA_XDATA_READ_BL (DS6602 FPGA Base Board Settings)........................... 288

Parameters Page (FPGA_XDATA_READ_BL).................................................. 289

FPGA_XDATA_WRITE_BL (DS6602 FPGA Base Board Settings).......................... 298

Parameters Page (FPGA_XDATA_WRITE_BL)................................................. 298

FPGA_IO_READ_BL (DS6602 FPGA Base Board Settings).................................. 309

Parameters Page (FPGA_IO_READ_BL)......................................................... 310
Scaling Page (FPGA_IO_READ_BL)............................................................... 322

FPGA_IO_WRITE_BL (DS6602 FPGA Base Board Settings)................................. 323

Parameters Page (FPGA_IO_WRITE_BL)........................................................ 323
Scaling Page (FPGA_IO_WRITE_BL).............................................................. 342

FPGA_INT_BL (DS6602 FPGA Base Board Settings)........................................... 342

Parameters Page (FPGA_INT_BL).................................................................. 343

Block Settings for the DS2655M1 I/O Module Framework.......................... .......... 344

FPGA_IO_READ_BL (DS2655M1 I/O Module Settings)...................................... 344

Parameters Page (FPGA_IO_READ_BL)......................................................... 345
Scaling Page (FPGA_IO_READ_BL)............................................................... 350

FPGA_IO_WRITE_BL (DS2655M1 I/O Module Settings)..................................... 353

Parameters Page (FPGA_IO_WRITE_BL)........................................................ 354
Scaling Page (FPGA_IO_WRITE_BL).............................................................. 363

Block Settings for the DS2655M2 I/O Module Framework.......................... .......... 368

FPGA_IO_READ_BL (DS2655M2 I/O Module Settings)...................................... 368

Parameters Page (FPGA_IO_READ_BL)......................................................... 369
Scaling Page (FPGA_IO_READ_BL)............................................................... 377

FPGA_IO_WRITE_BL (DS2655M2 I/O Module Settings)..................................... 378

Parameters Page (FPGA_IO_WRITE_BL)........................................................ 378
Scaling Page (FPGA_IO_WRITE_BL).............................................................. 397

Block Settings for the DS6651 Multi-I/O Module Framework...................... .......... 400

FPGA_IO_READ_BL (DS6651 Multi-I/O Module Settings).................................. 400

Parameters Page (FPGA_IO_READ_BL)......................................................... 401
Scaling Page (FPGA_IO_READ_BL)............................................................... 413

FPGA_IO_WRITE_BL (DS6651 Multi-I/O Module Settings)................................. 416

Parameters Page (FPGA_IO_WRITE_BL)........................................................ 416
Scaling Page (FPGA_IO_WRITE_BL).............................................................. 445

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Block Settings for the DS660X_MGT Framework.................................................. 450

FPGA_IO_READ_BL (MGT In Settings).................................................... .......... 450

Parameters Page (FPGA_IO_READ_BL)......................................................... 451
Scaling Page (FPGA_IO_READ_BL)............................................................... 457

FPGA_IO_WRITE_BL (MGT Out Settings).......................................................... 457

Parameters Page (FPGA_IO_WRITE_BL)........................................................ 458
Scaling Page (FPGA_IO_WRITE_BL).............................................................. 463

Block Settings for the Inter-FPGA Interface Framework......................................... 464

FPGA_IO_READ_BL (Inter-FPGA Interface Settings)........................................... 464

Parameters Page (FPGA_IO_READ_BL)......................................................... 465
Scaling Page (FPGA_IO_READ_BL)............................................................... 469

FPGA_IO_WRITE_BL (Inter-FPGA Interface Settings).......................................... 470

Parameters Page (FPGA_IO_WRITE_BL)........................................................ 471
Scaling Page (FPGA_IO_WRITE_BL).............................................................. 475

Block Settings for the MicroAutoBox II Frameworks 477

Block Settings for the FPGA1401Tp1 with Multi-I/O Module Frameworks............. 478

FPGA_XDATA_READ_BL (FPGA1401Tp1 with Multi-I/O Module

Settings).......................................................................................................... 478
Parameters Page (FPGA_XDATA_READ_BL).................................................. 479
Description Page (FPGA_XDATA_READ_BL).................................................. 486

FPGA_XDATA_WRITE_BL (FPGA1401Tp1 with Multi-I/O Module

Settings).......................................................................................................... 487
Parameters Page (FPGA_XDATA_WRITE_BL)................................................. 488
Description Page (FPGA_XDATA_WRITE_BL)...................................... .......... 495

FPGA_IO_READ_BL (FPGA1401Tp1 with Multi-I/O Module Settings)...... .......... 496

Parameters Page (FPGA_IO_READ_BL)......................................................... 496
Scaling Page (FPGA_IO_READ_BL)............................................................... 509
Description Page (FPGA_IO_READ_BL)......................................................... 512

FPGA_IO_WRITE_BL (FPGA1401Tp1 with Multi-I/O Module Settings)............... 513

Parameters Page (FPGA_IO_WRITE_BL)........................................................ 513
Scaling Page (FPGA_IO_WRITE_BL).............................................................. 531
Description Page (FPGA_IO_WRITE_BL)........................................................ 534

FPGA_INT_BL (FPGA1401Tp1 with Multi-I/O Module Settings)......................... 534

Parameters Page (FPGA_INT_BL).................................................................. 535
Description Page (FPGA_INT_BL).................................................................. 536

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Block Settings for the FPGA1401Tp1 with Engine Control I/O Module
Framework........................................................................................................... 538

FPGA_XDATA_READ_BL (FPGA1401Tp1 with Engine Control I/O

Module Settings)................................................................................... .......... 538
Parameters Page (FPGA_XDATA_READ_BL).................................................. 539
Description Page (FPGA_XDATA_READ_BL).................................................. 546

FPGA_XDATA_WRITE_BL (FPGA1401Tp1 with Engine Control I/O

Module Settings)................................................................................... .......... 547
Parameters Page (FPGA_XDATA_WRITE_BL)................................................. 547
Description Page (FPGA_XDATA_WRITE_BL)...................................... .......... 554

FPGA_IO_READ_BL (FPGA1401Tp1 with Engine Control I/O Module

Settings).......................................................................................................... 555
Parameters Page (FPGA_IO_READ_BL)......................................................... 556
Scaling Page (FPGA_IO_READ_BL)............................................................... 566
Description Page (FPGA_IO_READ_BL)......................................................... 570

FPGA_IO_WRITE_BL (FPGA1401Tp1 with Engine Control I/O Module

Settings).......................................................................................................... 570
Parameters Page (FPGA_IO_WRITE_BL)........................................................ 571
Scaling Page (FPGA_IO_WRITE_BL).............................................................. 577
Description Page (FPGA_IO_WRITE_BL)........................................................ 578

FPGA_INT_BL (FPGA1401Tp1 with Engine Control I/O Module Settings)........... 579

Parameters Page (FPGA_INT_BL).................................................................. 579
Description Page (FPGA_INT_BL).................................................................. 580

Block Settings for the MicroAutoBox III Frameworks 583

Block Settings for the FPGA1403Tp1 with Multi‑I/O Module Frameworks............. 584

FPGA_XDATA_READ_BL (FPGA1403Tp1 with Multi-I/O Module

Settings).......................................................................................................... 584
Parameters Page (FPGA_XDATA_READ_BL).................................................. 585

FPGA_XDATA_WRITE_BL (FPGA1403Tp1 with Multi-I/O Module

Settings).......................................................................................................... 594
Parameters Page (FPGA_XDATA_WRITE_BL)................................................. 594

FPGA_IO_READ_BL (FPGA1403Tp1 with Multi-I/O Module Settings)...... .......... 603

Parameters Page (FPGA_IO_READ_BL)......................................................... 603
Scaling Page (FPGA_IO_READ_BL)............................................................... 620

FPGA_IO_WRITE_BL (FPGA1403Tp1 with Multi-I/O Module Settings)............... 623

Parameters Page (FPGA_IO_WRITE_BL)........................................................ 623
Scaling Page (FPGA_IO_WRITE_BL).............................................................. 642

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FPGA_INT_BL (FPGA1403Tp1 with Multi-I/O Module Settings)......................... 645

Parameters Page (FPGA_INT_BL).................................................................. 645

Block Settings for the FPGA1403Tp1 with Engine Control I/O Module
Framework........................................................................................................... 647

FPGA_XDATA_READ_BL (FPGA1403Tp1 with Engine Control I/O

Module Settings)................................................................................... .......... 647
Parameters Page (FPGA_XDATA_READ_BL).................................................. 648

FPGA_XDATA_WRITE_BL (FPGA1403Tp1 with Engine Control I/O

Module Settings)................................................................................... .......... 657
Parameters Page (FPGA_XDATA_WRITE_BL)................................................. 657

FPGA_IO_READ_BL (FPGA1403Tp1 with Engine Control I/O Module

Settings).......................................................................................................... 666
Parameters Page (FPGA_IO_READ_BL)......................................................... 666
Scaling Page (FPGA_IO_READ_BL)............................................................... 679

FPGA_IO_WRITE_BL (FPGA1403Tp1 with Engine Control I/O Module

Settings).......................................................................................................... 683
Parameters Page (FPGA_IO_WRITE_BL)........................................................ 683
Scaling Page (FPGA_IO_WRITE_BL).............................................................. 690

FPGA_INT_BL (FPGA1403Tp1 with Engine Control I/O Module Settings)........... 691

Parameters Page (FPGA_INT_BL).................................................................. 691

Enhancements to the Simulink Menus 693

Menu Commands for FPGA Programming............................................................ 694
Advanced Preferences................................................................................. 694
Generate Corresponding Block.................................................................... 695
Show Corresponding Block......................................................................... 695
Update All Scaling Subsystems for Last Build............................................... 696
Update Selected Scaling Subsystems for Last Build....................................... 697
Word Length Calculator.............................................................................. 698

Advanced Preferences Dialog..................................................................... .......... 699

Opening the Advanced Preferences Dialog.................................................. 699
Dialog Settings of the Advanced Preferences Dialog.................................... 700

Word Length Calculator....................................................................................... 706

Opening the Word Length Calculator.......................................................... 706
Dialog Settings of the Word Length Calculator............................................ 707

Index 709

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 About This Reference

About This Reference

Content This reference is a description of FPGA interface blocks and their settings
provided by the FPGA Interface sublibrary of the FPGA Programming Blockset.
The common block settings and the framework-specific block settings are
described in separate sections.

You can use this blockset to integrate an FPGA model in your dSPACE
system. For the supported dSPACE hardware, refer to Overview of the FPGA
Programming Blockset on page 15.

Audience profile It is assumed that you have good knowledge in:

§ Applying generally accepted FPGA design rules to ensure a stable and reliable
FPGA application.
§ The architectural structure of FPGAs (CLB architecture, slice flip-flops, memory
resources, DSP resources, clocking resources) with a verifiable experience on
digital designs (structural mapping, tool-flow knowledge, synthesis options,
timing analysis).
§ Modeling with Simulink®.
§ Modeling with the HDL library of the AMD® VitisTM Model Composer
§ Using the AMD design tools for simulation and debugging.

Symbols dSPACE user documentation uses the following symbols:

Symbol Description
Indicates a hazardous situation that, if not avoided,
V DANGER
will result in death or serious injury.
Indicates a hazardous situation that, if not avoided,
V WARNING could result in death or serious injury.
Indicates a hazardous situation that, if not avoided,
V CAUTION could result in minor or moderate injury.
Indicates a hazard that, if not avoided, could result in
NOTICE
property damage.

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 About This Reference

Symbol Description
Indicates important information that you should take
Note
into account to avoid malfunctions.
Indicates tips that can make your work easier.
Tip
Indicates a link that refers to a definition in the
glossary, which you can find at the end of the
document unless stated otherwise.
Follows the document title in a link that refers to
another document.

Naming conventions dSPACE user documentation uses the following naming conventions:

%name% Names enclosed in percent signs refer to environment variables for

file and path names.

<> Angle brackets contain wildcard characters or placeholders for variable

file and path names, etc.
Examples:
§ Where you find terms such as rti<XXXX> replace them by the RTI platform
support you are using, for example, rti1202.
§ Where you find terms such as <model> or <submodel> in this document,
replace them by the actual name of your model or submodel. For example,
if the name of your Simulink model is smd_1202_sl.slx and you are
asked to edit the <model>_usr.c file, you actually have to edit the
smd_1202_sl_usr.c file.

RTI block name conventions All I/O blocks have default names based on
dSPACE's board naming conventions:
§ Most RTI block names start with the board name.
§ A short description of functionality is added.
§ Most RTI block names also have a suffix.

Suffix Meaning
M Module number (for MicroAutoBox II)
C Channel number
G Group number
CON Converter number
BL Block number
P Port number
I Interrupt number

A suffix is followed by the appropriate number. For example,

DS1202SER_INT_C2_I1 represents an interrupt block located on a
MicroLabBox. The suffix indicates channel number 2 and interrupt number
1 of the block. For more general block naming, the numbers are replaced by
variables (for example, DS1202SER_INT_Cx_Iy).

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FPGA Programming Blockset - FPGA Interface Reference May 2024
 About This Reference

Special Windows folders Windows‑based software products use the following special folders:

Common Program Data folder A standard folder for application-specific

program data that is used by all users.
%PROGRAMDATA%\dSPACE\<InstallationGUID>\<ProductName>
or
%PROGRAMDATA%\dSPACE\<ProductName>\<VersionNumber>

Documents folder A standard folder for application‑specific files that are

used by the current user.
%USERPROFILE%\Documents\dSPACE\<ProductName>\<VersionNumber>

Local Program Data folder A standard folder for application-specific

program data that is used by the current user.
%USERPROFILE%\AppData\Local\dSPACE\<InstallationGUID>\
<ProductName>

Accessing dSPACE Help and After you install and decrypt Windows‑based dSPACE software, the
PDF files documentation for the installed products is available in dSPACE Help and as PDF
files.

dSPACE Help (local) You can open your local installation of dSPACE Help:
§ On its home page via Windows Start Menu
§ On specific content using context-sensitive help via F1

PDF files You can access PDF files via the icon in dSPACE Help. The PDF
opens on the first page.

dSPACE Help (Web) Independently of the software installation, you can

access the Web version of dSPACE Help at https://www.dspace.com/go/help.
To access the Web version, you must have a mydSPACE account.
For more information on the mydSPACE registration process, refer to
https://www.dspace.com/faq?097.

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 About This Reference

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FPGA Programming Blockset - FPGA Interface Reference May 2024
 General Information on the FPGA Interface of the FPGA Programming Blockset

General Information on the FPGA Interface of the

FPGA Programming Blockset

Where to go from here Information in this section

Overview of the FPGA Programming Blockset.......................................... 15

Provides a short description of the blockset's components and how to
access them.

Features of the FPGA Programming Blockset............................................ 19

The FPGA Programming Blockset provides dynamically configured dialog
settings and an interface to some development features of the AMD Vitis
Model Composer Blockset.

Overview of the FPGA Programming Blockset

Introduction To provide a short description of the blockset's components and how to access
them.

FPGA Programming Blockset The FPGA Programming Blockset is a Simulink® blockset for using an FPGA
model with a dSPACE system.

The blockset provides Simulink blocks for implementing and simulating the
interface between the FPGA mounted on a dSPACE I/O board and the board's
I/O, and the interface between the dSPACE I/O board and its processor board.
The following table shows the supported FPGA hardware.

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 General Information on the FPGA Interface of the FPGA Programming Blockset

Platform Supported Hardware Framework Notes

MicroLabBox MicroLabBox DS1202 FPGA I/O Remaining I/O channels cannot be used by
Type 1 RTI/RTLib.
DS1202 FPGA I/O Can be used together with the RTI1202 and the
Type 1 (Flexible I/O) RTI Electric Motor (EMC) blocksets.
MicroLabBox II DS1303 Multi-I/O Board DS1303 (KU15P) Remaining I/O channels cannot be used for
Multi-I/O Board function blocks in ConfigurationDesk.
MicroAutoBox II § MicroAutoBox II FPGA1401Tp1 Supports the DS1552 Multi-I/O Module.
1401/1511/1514 (7K325) with Multi-
§ MicroAutoBox II I/O Module (DS1552)
1401/1513/1514 FPGA1401Tp1 Supports the DS1552B1 Multi-I/O Module.
(7K325) with
Multi-I/O Module
(DS1552B1)
FPGA1401Tp1 Supports the DS1554 Engine Control I/O
(7K325) with Engine Module.
Control I/O Module
(DS1554)
MicroAutoBox III DS1514 FPGA Base FPGA1403Tp1 Supports the DS1552 Multi-I/O Module.
Board (7K325) with Multi-
I/O Module (DS1552)
FPGA1403Tp1 Supports the DS1552B1 Multi-I/O Module.
(7K325) with
Multi-I/O Module
(DS1552B1)
FPGA1403Tp1 Supports the DS1554 Engine Control I/O
(7K325) with Engine Module.
Control Module
(DS1554)
SCALEXIO DS2655 FPGA Base DS2655 (7K160) The SCALEXIO FPGA base boards provide 5 slots
Board (7K160) FPGA Base Board to extend the I/O capability with DS2655M1
DS2655 FPGA Base DS2655 (7K410) Multi-I/O Modules, DS2655M2 Digital I/O
Board (7K410) FPGA Base Board Modules, and DS6551 Multi-I/O Modules. The
assembly has no slot dependencies. With the
DS6601 FPGA Base DS6601 (KU035) Inter-FPGA Interface framework, you can use
Board FPGA Base Board I/O module slots of the SCALEXIO FPGA base
DS6602 FPGA Base DS6602 (KU15P) boards as inter-FPGA interfaces.
Board FPGA Base Board
DS2655M1 Multi-I/O DS2655M1 I/O Can be used after you load one of the
Module Module SCALEXIO FPGA base board frameworks.
DS2655M2 Digital I/O DS2655M2 I/O
Module Module
DS6651 Multi-I/O DS6651 Multi-I/O
Module Module
Inter-FPGA connection Inter-FPGA Interface
MGT communication DS660X_MGT An MGT module can be plugged into the
bus DS6601 and DS6602 FPGA base boards.

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 Overview of the FPGA Programming Blockset

Library access To open the library, execute one of the following methods:
§ In the MATLAB Command Window, enter rtifpga.
§ To access the Simulink blocks of the library separately:
In the Simulink Library Browser, navigate to the dSPACE FPGA Programming
Blockset folder.
§ For MicroAutoBox II:
In the RTI1401 Blockset, click one of the following blocksets:
§ MicroAutoBox II DS1511/DS1514
§ MicroAutoBox II DS1513/DS1514
Then click FPGA Type 1.
§ For MicroLabBox:
In the DS1202 MicroLabBox FPGA I/O Type 1 blockset, Click FPGA Class 1.

If you open the block library, the blockset is displayed.

Note

The FPGA Interface library and the Demo model are only available, if you
have the full license for the FPGA Programming Blockset.
If you have the standard RTI license only, the blockset looks like this:

Library components The following components are available in the FPGA Programming Blockset:

FPGA Interface The Simulink blocks of the FPGA Iinterface sublibrary are
used on the dSPACE I/O board that provides an FPGA, for example, the DS6602

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FPGA Base Board. They let you configure the interface to external I/O and to a
processor board, for example, a SCALEXIO Processing Unit.

The FPGA INTERFACE sublibrary provides the following Simulink blocks:

§ Setup
§ FPGA_SETUP_BL on page 24
§ Processor board access
§ FPGA_XDATA_READ_BL on page 44
§ FPGA_XDATA_WRITE_BL on page 49
§ FPGA_INT_BL on page 62
§ External I/O access
§ FPGA_IO_READ_BL on page 54
§ FPGA_IO_WRITE_BL on page 58
§ FPGA signal capturing
§ FPGA Scope on page 37
§ Model structure templates
§ The templates let you structure your FPGA model to use scaling subsystems.
For more information, refer to Preprocessing and Postprocessing the Signals
Between the FPGA and the Processor Model (FPGA Programming Blockset
Guide ).
The following templates can be used:
§ FPGA Function
An FPGA function template that includes an FPGA subsystem, a scaling
subsystem to preprocess processor signals (Scale In), and a scaling
subsystem to postprocess processor signals (Scale Out).
§ Scale In
Scaling subsystem to preprocess processor signals.
§ Scale Out
Scaling subsystem to postprocess processor signals.
§ HDL Coder Gateways
§ Intramodel Out and Intramodel In on page 40

Processor Interface The Simulink blocks of the Processor Interface library

are used on the dSPACE processor board to implement the communication with
the I/O board. The model on the I/O board that you want to access, for example,
the DS1514 FPGA Base Board, must contain the related FPGA interface blocks.

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For more information, refer to FPGA Programming Blockset - Processor Interface

Reference .

Note

If you use a MicroLabBox II, MicroAutoBox III, or a SCALEXIO system, the

processor interface is implemented within the behavior model using blocks
of the Model Port Block library.

Demo model If you have the full license for the FPGA Programming Blockset, Simulink models
are available that show how to use the blocks of the FPGA Programming
Blockset. Double-click the Demo button in the blockset to open the library
containing the demo models. In the next step you have to choose the demo
model for the framework which you have in use. A demo model prepared
for a different framework will not work. You can also find the model files at
<RCP_HIL_InstallationPath>\Demos\RTIFPGA.

Related topics Basics

Features of the FPGA Programming Blockset............................................................................. 19

Features of the FPGA Programming Blockset

Introduction The FPGA Programming Blockset provides dynamically configured dialog settings
and an interface to some development features of the AMD Vitis Model
Composer Blockset.

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Supported third party For modeling the FPGA functionality, the following third-party blockstes are
blocksets supported:
§ The AMD Vitis Model Composer Blockset.
The AMD Vitis Model Composer Blockset is a Simulink block library that lets
you graphically model FPGA applications. The AMD Vitis Model Composer
Blockset requires a separate license.
The FPGA Programming Blockset supports only the HDL library of the AMD
Vitis Model Composer.
§ Simulink blocks to model parts of the FPGA model.
To use Simulink blocks, the Mathworks HDL Coder is required and
the used Simulink blocks must be supported by the HDL Coder.
Refer to https://www.mathworks.com/help/comm/ug/find-blocks-and-system-
objects-supporting-hdl-code-generation.html.
The use of Simulink blocks to model parts of the FPGA model requires
special handling, refer to How to Use Simulink Blocks for Modeling the FPGA
Functionality (FPGA Programming Blockset Guide ).

Hardware-specific settings You can specify the hardware to be used in the block dialog of
the FPGA_SETUP_BL block. After you selected the hardware, the FPGA
Programming Blockset loads the hardware-specific framework. The framework
provides the following interfaces:
§ Communication with the real-time processor via the hardware-specific bus,
such as IOCNET.
§ Access to the I/O channels of the FPGA board.
§ Interrupt handling.

The following illustration shows the features of a framework.

FGPA
IOCNET

ADC unit
dSPACE
User application framework DAC unit

Digital I/O unit

Frame work ID and
configuration data

Function-specific settings The block dialogs have several pages. The Parameters and the Description
pages are empty until you select a function by specifying the access type for
board communication or specifying the I/O type for an I/O access on the Unit
page of a block dialog. These pages are dynamically filled with text and settings
according to the selected function.

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Flexible signal handling To model data exchange via the external I/O pins,
you must only add the I/O block for a specific access direction (read or write)
to the model. The signal type (analog or digital) can be configured in the block
dialog. The availability of the signal types depends on the selected framework.

Interaction with the AMD If you implemented the required functionality of the FPGA application by using
Vitis Model Composer the HDL library of the AMD Vitis Model Composer only, you have direct access
to all its features for configuring, debugging and building the application. If you
want to integrate the FPGA model in a dSPACE system, certain blocks of the
HDL library must be replaced by blocks from the FPGA Programming Blockset.
Most of the above-mentioned features are now available indirectly by using the
blocks from the FPGA Programming Blockset, for example, the timing analysis for
debugging purposes.

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Common FPGA Blocks of the FPGA Programming

Blockset

Introduction Common FPGA blocks are available for FPGA models independently of a
hardware-specific framework.

Where to go from here Information in this section

FPGA_SETUP_BL...................................................................................... 24
To specify general settings for the FPGA model and to support the
modeling and building of the FPGA application.

FPGA Scope............................................................................................. 37
To capture up to 16 FPGA signals with the time resolution of the FPGA
clock. 8 of the 16 signals can be displayed in ControlDesk.

HDL Coder Gateways.............................................................................. 40

To provide a gateway for signals and buses to a subsystem that is
modeled with Simulink blocks.

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FPGA_SETUP_BL
Purpose To specify general settings for the FPGA model and to support the modeling and
building of the FPGA application.

Where to go from here Information in this section

Block Description (FPGA_SETUP_BL)......................................................... 24

To specify general settings for the FPGA model and to support the
modeling and building of the FPGA application.

Unit Page (FPGA_SETUP_BL).................................................................... 25

To specify the FPGA framework.

Parameters Page (FPGA_SETUP_BL).......................................................... 26

To specify general settings for all the FPGA Interface blocks used and to
perform several FPGA model actions.

Subsystem Clocks Page (FPGA_SETUP_BL)............................................... 30

To use multiple clock domains for modeling parts of the FPGA design
with individual clock periods.

FPGA Access Page (FPGA_SETUP_BL)....................................................... 31

To make FPGA signals traceable for experiment software.

ConfigurationDesk Interface Page (FPGA_SETUP_BL)............................... 33

To implement the processor interface designed with a framework of a
SCALEXIO FPGA base board, MicroAutoBox III, or MicroLabBox II.

Block Description (FPGA_SETUP_BL)

Block overview

Description The FPGA_SETUP_BL block lets you select the appropriate frameworks for the
FPGA hardware and provides the following features to support the modeling of
the FPGA application.
§ Setting build parameters and starting the build process.
§ Starting analysis such as timing analysis to fix failures in an early stage.
§ Enabling FPGA tracing to capture and scale signals.

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§ Specifying multiple clock domains to use different clock periods in an

application.
§ Supporting the implementation of the processor interface (Simulink model
interface) in ConfigurationDesk.

An FPGA model must contain one FPGA_SETUP_BL block at its top level. More
FPGA_SETUP_BL blocks in the FPGA model will lead to an error when you try to
configure interface blocks or to build the model code.

The settings in the FPGA_SETUP_BL block overwrite the settings in an existing

System Generator block of the AMD® VitisTM Model Composer.

Unit Page (FPGA_SETUP_BL)

Purpose To specify the FPGA framework.

Dialog settings Board number Displays the board number in the range 1 … 16.
For SCALEXIO systems, you can set a board number to distinguish between
multiple FPGA boards during modeling.

Framework / piggyback Lets you select a framework that is delivered with

your hardware. The framework provides the definitions for the implemented
on-board I/O features and processor-bus access features. If you want to use
other boards or a piggyback plugged to the board, you must select the related
framework.
The framework of a piggyback board provides the I/O features of the base board
and additionally the I/O extensions of the piggyback board.

Note

The framework consists of a framework INI file. The definitions in this file
control the settings that are displayed in the hardware-specific dialog pages.

Framework author Displays the author of the framework INI file that you
selected by the Framework / piggyback setting.

I/O module 1 … 5 Lets you select the I/O modules that are installed to the I/O
module slots of a SCALEXIO FPGA base board. The FPGA Programming Blockset
automatically loads the frameworks to support the selected modules.
The number of the I/O module indicates the used I/O module slot. For example:
I/O module 1 is connected to the I/O module slot 1 of the FPGA base board.
You can select the following I/O modules:
§ DS2655M1 I/O Module
§ DS2655M2 I/O Module
§ DS6651 Multi-I/O Module
§ Inter-FPGA Interface

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In ConfigurationDesk, you can assign the hardware only if the connected

hardware matches module type and module slot. For example, if you have
selected a DS2655M1 I/O Module for I/O module 1 and a DS2655M2 I/O Module
for I/O module 3, the hardware registered in ConfigurationDesk must provide
at least a DS2655M1 Multi-IO Module on I/O module slot 1 and a DS2655M2
Digital IO Module on I/O module slot 3.

MGT module Lets you select the framework to support MGT modules. MGT
modules can be used only with the MicroLabBox II, DS6601 FPGA Base Board,
and DS6602 FPGA Base Board.
You can select the following frameworks:
§ SCALEXIO: Samtex FireFly ECUO-B04 (QSFP+)
The FPGA Programming Blockset automatically loads the DS660X_MGT
framework to support the MGT interface of a SCALEXIO system.
§ MicroLabBox II: DS1303 QSFP
The FPGA Programming Blockset automatically loads the DS1303_MGT
framework to support the MGT interface of the MicroLabBox II.
To use MGTs, an MGT module must be connected to the MGT connector of the
dSPACE real-time hardware. For more information, refer to Basic Structure of the
MGT Interface (FPGA Programming Blockset Guide ).

Author Displays the author of the framework INI file that you selected by the
I/O module setting.

Related topics Basics

Features of the FPGA Programming Blockset............................................................................. 19

Implementing Inter-FPGA Communication via I/O Module Slots (FPGA Programming
Blockset Guide )

Parameters Page (FPGA_SETUP_BL)

Purpose To specify general settings for all the FPGA interface blocks used and to perform
several FPGA model actions.

Dialog settings Application name Lets you specify the name of the FPGA application if
Same as subsystem / model is cleared. The name is used as a description for
the built FPGA application and can be displayed in your experiment software,
such as ControlDesk. For the MicroLabBox II, MicroAutoBox III, and SCALEXIO
systems, the FPGA application name is used as custom function block type.
If you use the same FPGA application name for variants of the FPGA model
for the MicroLabBox II, MicroAutoBox III, or SCALEXIO systems, all the variants
have the same custom function block type. This helps you reuse FPGA variants
in ConfigurationDesk, because you can exchange the FPGA application without
changing the custom function block in the signal chain.

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Same as subsystem/model Lets you use the name of the subsystem that
contains the FPGA model as FPGA application name. The FPGA model is the
subsystem to which the FPGA_SETUP block is added to. FPGA application
name displays the current name.

Build directory Lets you specify the directory for the build process and the
build results if Current directory is cleared.

Note

During the build process, the path length can exceed the maximum path
length specified by Windows. This might lead to error messages during
file system operations. For more information, refer to AMD Answer Record
52787 (https://support.xilinx.com/s/article/52787?language=en_US).
§ Keep the path length of the FPGA build directory short to avoid errors
during the build process.

Current directory Lets you use the current MATLAB working folder as FPGA
build directory. Build directory displays the current build directory.

Incremental build reference Lets you specify the path to the design
checkpoint file (DCP file) as reference for the next incremental build process.
Vivado generates the DCP file during the FPGA build process.
You can enter the path to the reference file if Enable incremental build is
selected.

Enable incremental build Lets you enable the reuse of build results for the
next build to make build results more predictable and to reduce build effort.
Incremental Build Reference displays the DCP file that is used as a reference
for the incremental build.

Find latest build result for reference Searches the current build directory
for the last DCP file. If the FPGA Programming Blockset finds a suitable DCP file,
it writes the path of the DCP file to Incremental Build Reference.

Backup directory Lets you enter a path to back up the build results if Enable
backup is selected.
To use different directories for each backup, you can add the following wildcards
to the file path:
§ %APPID adds a directory with the name of the application ID.
§ %TIMESTAMP adds a directory with the current time. The name format is
yyyy-mm-dd_HH-MM-SS.
If you do not use a wildcard, the backup process uses the same directory for all
backups.

Enable backup Lets you enable the backup of the build results, reports, and
models.

Copy model to build directory Lets you enable the copying of the entire
model to the build directory.
If a build server performs the build process, a copy of the FPGA model is required
to enable the build server to generate the HTML model and to back up the
model.

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Note

Before you select this option, make sure that all users with read permission
to the common build directory are entitled to see the model.

Generate WebView Lets you enable the generation of an HTML model to

display the entire model with any Internet browser.
The Simulink Report GeneratorTM is required to generate the HTML model.

Clean up build directory Lets you enable the removal of deletable files after
the FPGA application is built and backed up.

Interface down-sample factor Lets you specify the sampling rate of all the
FPGA Interface blocks in the subsystem. The sampling rate is the ratio of the
hardware clock frequency and the given number of cycles. The value must be a
positive integer.

Note

In offline simulation mode, the sample period is the product of the offline
simulation period times the given number of cycles.

Offline simulation period Lets you specify the simulation period to be used
in offline simulation mode. The value must be greater than or equal to the FPGA
clock period.

FPGA clock period Displays the hardware clock period of the FPGA in
seconds. The value is specified in the framework INI file.
For example, DS6602 FPGA Base Board: 8e-9 s (8·10-9 s = 8 ns) corresponds to
125 MHz clock rate.

Description Lets you enter a description of the FPGA model.

The description will be saved in the FPGA model INI file. When you specify
the processor interface, the description can be displayed on the Advanced
page of the processor setup block (PROC_SETUP_BL). When you add the FPGA
model INI file to ConfigurationDesk, the FPGA description property of the FPGA
custom function block displays the description.

FPGA model action Lets you select an action that you want to perform on
the FPGA model. The selected action is executed when you click Execute.
You can choose between the following model actions:
§ FPGA Build
Starts the build process for the FPGA model. See the
MATLAB Command Window to follow the progress of the build
process. You will find the resulting FPGA model INI file in
<FPGABuilddirectory>/<ModelName>_rtiFPGA/ini. The name of a FPGA
model INI file is <FPGAApplicationName>_<ApplicationID>.ini.
The build process opens a temporary model <FPGAModelName>_rtiFPGAtmp
to build the application. The build process closes the temporary model at the
end.

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§ Remote FPGA Build

Lets you start the build process to use the dSPACE FPGA Build Server for
building the FPGA application. Refer to Using an FPGA Build Server (FPGA
Programming Blockset Guide ).
The FPGA Programming Blockset opens a temporary model
<FPGAModelName>_rtiFPGAtmp and closes the temporary model before the
FPGA Build Server starts to build the FPGA application.
§ HDL Simulation (Model only)
Starts the offline simulation of the entire Simulink model based on generated
HDL code. The simulation itself uses utilities from the AMD Vitis Model
Composer to create an HDL test bench. The test bench compares Simulink
simulation results for the FPGA subsystem to those of Vivado Simulator based
on the generated HDL code for the FPGA subsystem and therefore checks the
correctness of the generated code. The simulation results are presented as text
and waveform. For more information, refer to the Vivado Design Suite User
Guide.
§ Timing Analysis (Model only)
If the build process has detected timing problems, you can execute the timing
analysis to analyze the timing behavior of your FPGA subsystem. This timing
analysis considers the custom FPGA model without the dSPACE framework of
the platform and the signal paths of HDL Coder subsystems. Timing Analysis
starts the timing analysis utility from the AMD Vitis Model Composer. For more
information, refer to the Vivado Design Suite User Guide.
§ Resource Analysis (Model only)
If the build process detected resource problems, you can execute the resource
analysis to analyze the FPGA utilization of the FPGA subsystem. This resource
analysis considers the custom FPGA model without the framework of the
platform and the resources required by HDL Coder subsystems. Resource
Analysis starts the resource analysis utility from the AMD Vitis Model
Composer. For more information, refer to the Vivado Design Suite User Guide.
§ Show Last Timing Report
Opens the Vivado Timing Analyzer to show the last timing analysis including
the timing analysis that is executed during the build process.
The Vivado Timing Analyzer shows only the signal paths that are modeled
with the HDL library of the AMD Vitis Model Composer
§ Show Last Resource Utilization Report
Opens the resource utilization report of the last resource analysis inclusive the
resource utilization analyses that is executed during the build process.
§ Generate Model Report
Generates a report of the used FPGA channels, software, and tools.

Thread(s) Lets you accelerate the build process by performing the FPGA build
process in parallel with multiple build threads.
A parallel build needs more RAM than a serial build. If your PC slows down due
to a lack of RAM and multiple build threads, you can decrement the number of
build threads.

Automatic bus (re-)analysis for FPGA_XDATA blocks Lets you save time by
deactivating the analysis of the buses that are connected to the Buffer64 Out

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and Buffer64 In blocks. The bus analysis checks if the connected bus topology
matches the bus topology of the Data port.
If you use FPGA_XDATA blocks in the bus transfer mode, the bus analysis is
recommended. The bus transfer mode is supported only by the MicroLabBox II,
MicroAutoBox III, and SCALEXIO systems.

Related topics Basics

Achieving Successful Builds at High FPGA Utilization (FPGA Programming Blockset

Guide )
Backing Up the Build Results (FPGA Programming Blockset Guide )
Using an FPGA Build Server (FPGA Programming Blockset Guide )

Subsystem Clocks Page (FPGA_SETUP_BL)

Purpose To use multiple clock domains for modeling parts of the FPGA design with
individual clock periods.

Dialog settings Subsystem 1 ... 10 Lets you select the subsystem to specify an individual
clock period and offline simulation period. The subsystem must be a part of the
FPGA model.
If you select a subsystem, the FPGA model use multiple clock domains. To use
multiple clock domains, the FPGA design must be partitioned into subsystems.
Each subsystem has an individual clock period. For more information, refer to
How to Use Multiple Clock Domains for FPGA Modeling (FPGA Programming
Blockset Guide ).

Clock period Lets you specify an individual clock period for the selected
subsystem. A common value for the clock period is in the range 20 ns ... 4 ns
(50 MHz ... 250 MHz).
After entering the clock period, the dialog recalculates all clock periods for a
clock setup with a minimum error for all clock periods. After recalculation, the
dialog immediately updates the clock period's values to the calculated values in
double precision.

Offl. sim. period Lets you specify the simulation period to be used in offline
simulation mode for the selected subsystem. The value must be greater than or
equal to the clock period of the selected subsystem.

Related topics Basics

Using Multiple Clock Domains for FPGA Modeling (FPGA Programming Blockset
Guide )

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HowTos

How to Use Multiple Clock Domains for FPGA Modeling (FPGA Programming
Blockset Guide )

FPGA Access Page (FPGA_SETUP_BL)

Purpose To make FPGA signals accessible for experiment software.

Platform support The following table gives you an overview of the platforms that support the
access of FPGA applications and the methods that are supported.

Platform FPGA Scaling

Inverting Digital I/O Signals

Inverting RS232/485 Signals

Scaling Analog I/O Signals
Tunable FPGA Constants
FPGA Signal Tracing

FPGA Test Access

FPGA Scope
SCALEXIO ✓1) ✓ ✓ ✓ ✓ ✓ ✓
MicroLabBox ✓ ✓ ✓ ✓ ✓ – –
MicroLabBox II ✓ ✓ ✓ ✓ ✓ – –
MicroAutoBox II ✓ ✓ ✓ ✓ ✓ – –
MicroAutoBox III ✓ ✓ ✓ ✓ ✓ – –
1) ✓ = Supported, – = Not supported

For more information on FPGA Scope, refer to Displaying FPGA Signals in

ControlDesk (FPGA Programming Blockset Guide ).

Dialog settings Enable FPGA tracing Lets you specify that FPGA signals are traceable in the
FPGA application.
Traceable signals require FPGA resources, build time, and there are some
limitations to experimenting with FPGA variables. Refer to Basics on Tracing
FPGA Signals (FPGA Programming Blockset Guide ).

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Note

Running applications might stop, if too many FPGA signals are traced
If you trace more than 100 signals with 32-bit values (or 50 signals with 64-
bit values) every millisecond with your experiment software, tracing might
cause a task overrun that stops the application.
These measures reduce the number of traced FPGA signals per millisecond:
§ Disable signal tracing if there is no need to trace FPGA signals.
§ Reduce the number of traceable signals. Refer to Basics on Tracing FPGA
Signals (FPGA Programming Blockset Guide ).
§ Reduce the number of signals that that you trace with the experiment
software. Only the values of signals traced with an experiment software
are sent to the real-time processor and can cause a task overrun.

Enable tunable FPGA constants Lets you enable that tunable FPGA
constants are provided and their values can be changed in the experiment
software.
This setting can be selected only if FPGA tracing is enabled.

Enable FPGA test access and scaling Lets you enable FPGA test access and
FPGA scaling.
FPGA test access enables intervention points for the experiment software. The
intervention points let you set values for the I/O interface and for data values
that are exchanged with the processor interface.
FPGA scaling includes scaling, saturating, and inverting FPGA I/O signals with
your experiment software. The Scaling page of the FPGA_IO_READ_BL and
FPGA_IO_WRITE_BL blocks dialogs provide parameters to specify FPGA scaling.

Note

Scaling of analog I/O signals also effects the signal path:

§ If you use the parameters of the Scaling page to scale analog signals, the
data type of the Data port is set to the specified data format for scaling.
For more information, refer to How to Change the Data Type of Analog
Signals (FPGA Programming Blockset Guide ).
§ FPGA scaling of analog I/O signals might cause additional latency. If
the latency can be calculated during the modeling, analog I/O functions
display the total latency.

This setting is selectable only if FPGA tracing and tunable FPGA constants are
enabled.

Select subsystems to be accessed Lets you select the subsystems that can
be accessed with your experiment software by clicking the subsystem's name
in the tree view. If you click a name, you select or clear the subsystem and its
subelements.

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The selection affects only FPGA signal tracing and the adjusting of tunable FPGA
constants.

Trace input and output ports of subsystem Lets you specify that incoming
and outgoing signals of FPGA subsystems are traceable.

Trace all subsystem internal signals Lets you specify that all signals used
internally in FPGA subsystems are traceable.

Trace buses Lets you specify that all signals of Simulink Bus Creator blocks
and Bus Selector blocks are traceable.

Analyze model Displays the last analysis of the following points:

§ The number of signals that will be traceable in the FPGA application and the
number of flip-flops that are additionally required to make the signal traceable
via variables.
§ The number of tunable constants and the number of flip-flops that are
additionally required to make the constants tunable.
§ The number of ports that support FPGA test access and scaling and the
number of flip-flops that are additionally required for FPGA test access and
scaling.

Analyze Lets you analyze the current FPGA model on the number of signals
and constants that will be accessible with your experiment software.
For analysis, the dialog opens the temporary model
<FPGAModelName>_rtiFPGAtmp. The dialog closes the temporary model at the
end of the analysis.

Added FPGA variables for For an overview of the types of FPGA variables that are added to the SDF file to
FPGA test access and scaling support FPGA test access and scaling, refer to Using the experiment software for
access (FPGA Programming Blockset Guide ).

Related topics Basics

Accessing FPGA Applications with your Experiment Software (FPGA Programming

Blockset Guide )

ConfigurationDesk Interface Page (FPGA_SETUP_BL)

Purpose To implement the processor interface designed with a framework of a SCALEXIO

FPGA base board, MicroAutoBox III, or MicroLabBox II.

Export all build results to Build result to export Displays the name of the latest FPGA build results and
ConfigurationDesk settings the date and time the build was executed.

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The latest FPGAC file includes the build results. The file is located at
<build folder>\<application name>_rtiFPGA\
FPGA_Custom_Functions.
If the entire model contains additional FPGA models for other FPGA boards, the
framework provides an FPGAC file for each FPGA model.

Publish Publishes the path of the built FPGA container file to the global
user location file of ConfigurationDesk. This makes the build FPGA application
available as FPGA custom function block types in the Function Browser of
ConfigurationDesk.

Name of (new) project Lets you enter the name of the ConfigurationDesk
project to which the build results will be exported.
The name you enter must not contain a dot or whitespace as the first or last
character.

Export to new project Lets you export the build results to the specified
ConfigurationDesk project. If the specified project does not exist, the framework
adds a new project to ConfigurationDesk.
The framework mainly performs the following steps when it exports the build
results and the processor model to ConfigurationDesk:
§ Opens ConfigurationDesk.
§ Creates a new project in ConfigurationDesk.
§ Adds the file path of the current build results to the global user location file.
The global user location file is located at
%LOCALAPPDATA%\dSPACE\ConfigurationDesk\Settings\<ReleaseVersion>
(<ProductVersion>)
When you add the file paths to the global user location file, the
FPGA application is available as FPGA custom function block types in all
ConfigurationDesk projects.
Different versions of FPGAC files differ only in the application ID
(<FPGAApplicationName>_<ApplicationID>.fpgac). When updating the
FPGAC file, the FPGA Programming Blockset adds an application ID so that
ConfigurationDesk can find the latest version first and ignores the other
FPGAC files. In ConfigurationDesk, the Message Viewer displays the found
FPGAC files and the ignored FPGAC files.
The following illustration shows messages of the Message Viewer concerning
the registration of FPGA custom function block types.

§ Adds instances of the added custom function block types to the signal chain.
The framework performs the following steps only if the processor model can be
separated and the processor interface is implemented:
§ Separates and saves the processor models according to the settings of the
Model Separation Setup block.
In ConfigurationDesk, the processor models are implemented outside
ConfigurationDesk in Simulink models.
§ Exports the model interface of the processor models to ConfigurationDesk.

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§ Maps the function ports of the added FPGA custom function blocks to the
model ports of the processor model (behavior model).
For instructions, refer to How to Export Build Results and Processor Models to
ConfigurationDesk Projects (FPGA Programming Blockset Guide ).

Select recent project Lets you select an existing ConfigurationDesk project

to which the build result will be exported.
If no projects are selectable, click Refresh list.

Export to recent project Lets you export the build result to the selected
ConfigurationDesk project to add the FPGA application to the signal chain of the
selected project and to perform the model port mapping.
For instructions, refer to How to Export Build Results and Processor Models to
ConfigurationDesk Projects (FPGA Programming Blockset Guide ).

Refresh list Lets you refresh the list with the projects that were recently used
in ConfigurationDesk.
If clicked, the framework starts ConfigurationDesk for importing the recently
used ConfigurationDesk projects.

Import parameters Lets you import the settings of an instantiated FPGA

application (FPGA custom function block). The FPGA application must be added
to the ConfigurationDesk project that the Export to recent project displays.
The framework imports the following settings:
§ Settings of the electrical interface.
§ Settings of the scaling parameters.
Clicking the framework starts ConfigurationDesk to import the settings. If several
FPGA custom function blocks are added to the signal chain of the project, a
dialog lets you select the FPGA custom function block from which you import
the settings.
For instructions, refer to How to Update FPGA Models with Imported Parameter
Settings (FPGA Programming Blockset Guide ).

Processor Interface settings Generate Lets you generate model port blocks to implement the processor
interface.
If you click Generate, the related FPGA model is analyzed and a corresponding
processor interface model is created with the blocks of the Model Interface
Package for Simulink.
The model port blocks are automatically configured with the corresponding
channel numbers, channel names, access type, and format parameters.
After you copy the generated model port blocks to the processor model or
scaling subsystem, you can close the generated interface model without saving.

Select subsystems for Lets you select the subsystems that can be accessed by different application
function block types in processes in ConfigurationDesk, for example, to support a multicore processor
ConfigurationDesk application. For instructions, refer to How to Select Subsystems for Multicore
Support (MicroLabBox II, MicroAutoBox III, SCALEXIO) (FPGA Programming
Blockset Guide ).

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Resulting function block types Displays the resulting number and types
of function blocks after you exported the build results to ConfigurationDesk.
For more information on function block types supporting multicore processor
applications, refer to Aspects on FPGA Applications Supporting Multicore
Processor Applications (FPGA Programming Blockset Guide ).

Included scaling subsystems Displays the number and names of scaling

subsystems:
§ In [>]: Scaling subsystem that preprocesses the signals coming from the
processor model.
§ Out [<]: Scaling subsystem that postprocesses the signals coming from the
FPGA subsystem.

Related topics HowTos

How to Generate a Processor Interface (FPGA Programming Blockset Guide )

How to Prepare the Processor Models for Separating (MicroLabBox II,
MicroAutoBox III, SCALEXIO) (FPGA Programming Blockset Guide )

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FPGA Scope
Purpose To capture up to 16 FPGA signals with the time resolution of the FPGA clock. 8
of the 16 signals can be displayed in ControlDesk.

Where to go from here Information in this section

Block Description (FPGA Scope)............................................................... 37

To capture FPGA signals that can be displayed in ControlDesk.

General Page (FPGA Scope)..................................................................... 39

To specify general settings for the FPGA Scope block.

Block Description (FPGA Scope)

Block overview The following illustration shows the block.

Purpose To capture FPGA signals that can be displayed in ControlDesk.

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Description The FPGA Scope block lets you connect up to 16 FPGA signals that can be
captured. Nevertheless, only 8 FPGA signals can be displayed in ControlDesk at
the same time. You can select the signals to be displayed in ControlDesk.

Limitations You must observe the following limitations.

§ The platform must be a SCALEXIO system.
§ The data type must be signed integer, unsigned integer, or single precision
floating‑point (XFloat_8_24).
The Boolean data type is not supported. As an alternative, you can use
UFix_1_0.
§ The maximum bit width of signals that can be captured is 32 bit.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Signal 1 … 16 Captures up to 16 signal values. Nevertheless, only
the values of 8 FPGA signals can be displayed in
ControlDesk at the same time. You can select the
signals to be displayed in ControlDesk.
You can leave the ports unconnected if you do not
need them.
Data type: Signed integer, unsigned integer, and
XFloat_8_24
Bit width: Up to 32 bit
Data width: 1
External Triggers the signal capturing if the external trigger is
trigger used as trigger source.
You can leave the port unconnected if you do not
need it.
Data type: UFix_1_0
Data width: 1
A rising edge triggers the signal capturing.
Output
Trigger Outputs the trigger event to trigger other FPGA
Scope blocks, for example.
Data type: UFix_1_0
§ 0: No trigger event
§ 1: A trigger event occurs. This value is set for one
clock cycle.

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Related topics Basics

Displaying FPGA Signals in ControlDesk (FPGA Programming Blockset Guide )

References

General Page (FPGA Scope)...................................................................................................... 39

General Page (FPGA Scope)

Purpose To specify general settings for the FPGA Scope block.

Dialog settings Scope depth Lets you specify the number of data values that are captured
when a trigger event occurs. A new trigger event is not evaluated until all data
values have been captured and processed by the processor application.

Related topics Basics

Displaying FPGA Signals in ControlDesk (FPGA Programming Blockset Guide )

References

Block Description (FPGA Scope)................................................................................................ 37

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HDL Coder Gateways

Purpose To provide a gateway for signals and buses to a subsystem that is modeled with
Simulink blocks.

Intramodel Out and Intramodel In

Purpose The Intramodel Out and Intramodel In blocks let you separate a subsystem
to model parts of the FPGA model with blocks of the MathWorks© Simulink
blockset.

Precondition The MathWorks HDL CoderTM must be installed to build an FPGA model with
a subsystem that uses blocks of the MathWorks Simulink blockset (HDL coder
subsystems). Refer to Software Tools for Working with the FPGA Programming
Blockset (FPGA Programming Blockset Guide ).

Intramodel Out The Intramodel Out block connects the output of a AMD Vitis Model
Composer block to the input of an HDL Coder subsystem.

The Intramodel Out block automatically adapts its signal/bus type to the
connected input signal/bus type.

Intramodel In The Intramodel In block connects the output of an HDL Coder subsystem to the
input of a AMD Vitis Model Composer block.

The Intramodel In block automatically adapts its signal type to the connected
input signal/bus type.

Using Simulink blocks for For instructions on using Simulink blocks for modeling, refer to How to
FPGA modeling Use Simulink Blocks for Modeling the FPGA Functionality (FPGA Programming
Blockset Guide ).

For Simulink blocks that can be used to model the FPGA functionality, refer
to https://www.mathworks.com/help/comm/ug/find-blocks-and-system-objects-
supporting-hdl-code-generation.html.

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Related topics HowTos

How to Use Simulink Blocks for Modeling the FPGA Functionality (FPGA
Programming Blockset Guide )

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FPGA Interface Blocks (Common Settings)

Introduction The common settings of the interface blocks are independently of a hardware-
specific framework.

Where to go from here Information in this section

FPGA_XDATA_READ_BL.......................................................................... 44
To implement read access to processor-bus data in the FPGA model.

FPGA_XDATA_WRITE_BL......................................................................... 49
To implement write access to processor-bus data in the FPGA model.

FPGA_IO_READ_BL.................................................................................. 54
To provide read access to an external device via a physical input channel.

FPGA_IO_WRITE_BL................................................................................. 58
To provide write access to an external device via a physical output
channel.

FPGA_INT_BL........................................................................................... 62
To provide interrupts generated in the FPGA model to the processor
model.

Dialog Settings to Edit Simulink Bus Signals............................................. 66

The FPGA frameworks of SCALEXIO, MicroAutoBox III, and
MicroLabBox II support Simulink buses for processor communication. A
dialog lets you edit the bus topology.

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FPGA_XDATA_READ_BL
Purpose To implement read access to processor-bus data in the FPGA model.

Where to go from here Information in this section

Block Description (FPGA_XDATA_READ_BL)............................................. 45

To specify read access by the FPGA model to the processor model via
processor bus.

Unit Page (FPGA_XDATA_READ_BL)......................................................... 46

To specify the general configuration for the FPGA board's processor bus
read access.

Description Page (FPGA_XDATA_READ_BL).............................................. 48

To provide detailed information about the selected access type.

Information in other sections

Block Settings for the MicroLabBox Frameworks...................................... 69

The block dialogs provide hardware-specific settings after you load one
of the DS1202 FPGA I/O Type 1 frameworks.

Block Settings for the MicroLabBox II Framework................................... 125

The block dialogs provide hardware-specific settings after you load the
DS1303 (KU15P) Multi-I/O Board framework.

Block Settings for the SCALEXIO Frameworks........................................ 195

The block dialogs provide hardware-specific settings after you load one
of the frameworks supporting SCALEXIO systems.

Block Settings for the MicroAutoBox II Frameworks............................... 477

The block dialogs provide hardware-specific settings after you load one
of the frameworks supporting MicroAutoBox II.

Block Settings for the MicroAutoBox III Frameworks.............................. 583

The block dialogs provide hardware-specific settings after you load one
of the frameworks supporting MicroAutoBox III.

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Block Description (FPGA_XDATA_READ_BL)

Block overview The figure below shows the block in unconfigured state.

Purpose To specify read access by the FPGA model to the processor model via processor
bus.

Description The FPGA_XDATA_READ_BL block is used to model communication between

the FPGA model and the processor model via processor bus. For further
information on the processor bus, refer to Modeling Processor Model Access
(FPGA Programming Blockset Guide ). This block can read data from the
processor bus. The number of available channels and their configurations
depend on the specified framework or piggyback module. The related
framework INI file contains the definitions for the available access types and
channel numbers on the Unit page and their settings on the Parameters page.

I/O characteristics The following table describes the ports of the block:

Port Description
Output
From XDATA Represents the outport until the access type and
channel number are defined.

Hardware-specific settings For hardware-specific settings after you select the access type in the block dialog,
refer to the following topics:
§ Block Settings for the MicroLabBox Frameworks on page 69
§ Block Settings for the MicroLabBox II Framework on page 125
§ Block Settings for the SCALEXIO Frameworks on page 195
§ Block Settings for the MicroAutoBox II Frameworks on page 477
§ Block Settings for the MicroAutoBox III Frameworks on page 583

Related topics Basics

Modeling Processor Model Access (FPGA Programming Blockset Guide )

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Unit Page (FPGA_XDATA_READ_BL)

Purpose To specify the general configuration for the FPGA board's processor bus read
access.

Dialog settings Board number Displays the board number in the range 1 … 16.
For SCALEXIO systems, you can set a board number to distinguish between
multiple FPGA boards during modeling.

Access type Lets you select the storage you want to read from. The
available access types are defined in the specified framework INI file. For more
information, refer to Details on the access types on page 46.
The settings on the Parameters page depend on the specified access type.

Channel number Lets you specify a channel number that corresponds to the
storage. The available channel numbers are defined in the specified framework
INI file and depend on the specified access type.

Subchannel number Lets you specify a subchannel to use Simulink buses

for data exchange. Up to 256 subchannels can be used for each channel.
Subchannel number 1 of a buffer channel must always be used, the other
subchannels can be used in any order.
For more information on subchannels, refer to Using Subchannels for Data
Exchange (FPGA Programming Blockset Guide ).
This setting is configurable only if the bus transfer mode is supported by
the platform and enabled on the Parameters page. For more information,
refer to How to Use Simulink Buses of the FPGA Model to Model Processor
Communication (FPGA Programming Blockset Guide ).

Channel name Lets you specify a user-specific name for the specified
channel. The name is displayed in this block and in its corresponding
PROC_XDATA_WRITE_BL block in the processor model.

Show Lets you see where the corresponding processor interface block of the
selected block is used in the processor model.

Generate Lets you generate a processor interface block that corresponds to

the register or buffer.
The block is added to the FPGA model. Move the block to the processor model
to use it as a processor interface.

Details on the access types The FPGA framework contains the definition of the data storage areas. It
specifies one data storage type as register (implemented as Flip-Flop) and one
data storage type as buffer (implemented in the FPGA RAM). With the access
type, you can choose the data storage that you want to use for the data
exchange.

Register access Register access lets you access a scalar value in the register.
The data is identified by the specified channel number. The values are
transmitted element by element.

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Register group access You can group registers to a register group via a
common Register Group ID. All the values that belong to the same Register
Group ID are synchronously updated in the FPGA subsystem.
For read access, the registers of a register group are read from the board-specific
bus sequentially and then provided to the FPGA application simultaneously. For
write access, the registers of a register group are sampled simultaneously in the
FPGA application. These values form a consistent data group that is written to
the board-specific bus.

Buffer access Buffer access lets you access a vector value in the data buffer.
One specific value of the data is identified by the specified channel number and
the position within the buffer.
Data exchange is implemented via a FIFO buffer that works as a swinging buffer.
This means that there are two separate buffers for reading and writing, and
one buffer that switches between reading and writing. Only the pointer has to
be changed to switch the buffer so that no buffer has to be copied from one
position to another.

Free buffer

Application Read buffer Write buffer FPGA application

running on the
processor board

Bus access Bus access lets you use Simulink buses to model the data
exchange between the processor and the FPGA. The data exchange is
implemented via a FIFO buffer in the same way as the buffer access type.
Bus access is supported only by the blocksets of MicroLabBox II, MicroAutoBox III,
and SCALEXIO.

Hardware-specific settings For hardware-specific settings after you select the access type in the block dialog,
refer to the following topics:
§ Block Settings for the MicroLabBox Frameworks on page 69
§ Block Settings for the MicroLabBox II Framework on page 125
§ Block Settings for the SCALEXIO Frameworks on page 195
§ Block Settings for the MicroAutoBox II Frameworks on page 477
§ Block Settings for the MicroAutoBox III Frameworks on page 583

Related topics Basics

Modeling Processor Model Access (FPGA Programming Blockset Guide )

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Description Page (FPGA_XDATA_READ_BL)

Purpose To provide detailed information about the selected access type.

Description The Description page provides a function-specific Help for <...> button after
you selected a function on the corresponding Unit page.

Click Help for <...> to get function-specific information.

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FPGA_XDATA_WRITE_BL
Purpose To implement write access to processor-bus data in the FPGA model.

Where to go from here Information in this section

Block Description (FPGA_XDATA_WRITE_BL)............................................ 50

To specify write access by the FPGA model to the processor model via
processor bus.

Unit Page (FPGA_XDATA_WRITE_BL)............................................. .......... 51

To specify the general configuration for the FPGA board's processor bus
write access.

Description Page (FPGA_XDATA_WRITE_BL)............................................. 53

To provide detailed information about the selected access type.

Information in other sections

Block Settings for the MicroLabBox Frameworks...................................... 69

The block dialogs provide hardware-specific settings after you load one
of the DS1202 FPGA I/O Type 1 frameworks.

Block Settings for the MicroLabBox II Framework................................... 125

The block dialogs provide hardware-specific settings after you load the
DS1303 (KU15P) Multi-I/O Board framework.

Block Settings for the SCALEXIO Frameworks........................................ 195

The block dialogs provide hardware-specific settings after you load one
of the frameworks supporting SCALEXIO systems.

Block Settings for the MicroAutoBox II Frameworks............................... 477

The block dialogs provide hardware-specific settings after you load one
of the frameworks supporting MicroAutoBox II.

Block Settings for the MicroAutoBox III Frameworks.............................. 583

The block dialogs provide hardware-specific settings after you load one
of the frameworks supporting MicroAutoBox III.

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Block Description (FPGA_XDATA_WRITE_BL)

Block overview The figure below shows the block in unconfigured state.

Purpose To specify write access by the FPGA model to the processor model via processor
bus.

Description The FPGA_XDATA_WRITE_BL block is used to model communication between

the FPGA model and the processor model via processor bus. For further
information on the processor bus, refer to Modeling Processor Model Access
(FPGA Programming Blockset Guide ). This block can write data to the
processor bus. The number of available channels and their configurations
depends on the specified framework or piggyback module. The settings on the
Parameters page depend on the specified access type.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
To XDATA Represents the inport until the access type and the
channel number are defined.

Hardware-specific settings For hardware-specific settings after you select the access type in the block dialog,
refer to the following topics:
§ Block Settings for the MicroLabBox Frameworks on page 69
§ Block Settings for the MicroLabBox II Framework on page 125
§ Block Settings for the SCALEXIO Frameworks on page 195
§ Block Settings for the MicroAutoBox II Frameworks on page 477
§ Block Settings for the MicroAutoBox III Frameworks on page 583

Related topics Basics

Modeling Processor Model Access (FPGA Programming Blockset Guide )

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 FPGA_XDATA_WRITE_BL

Unit Page (FPGA_XDATA_WRITE_BL)

Purpose To specify the general configuration for the FPGA board's processor bus write
access.

Dialog settings Board number Displays the board number in the range 1 … 16.
For SCALEXIO systems, you can set a board number to distinguish between
multiple FPGA boards during modeling.

Access type Lets you select the storage you want to write to. The
available access types are defined in the specified framework INI file. For more
information, refer to Details on the access types on page 51.
The settings on the Parameters page depend on the specified access type.

Channel number Lets you specify a channel number that corresponds to the
storage. The available channel numbers are defined in the specified framework
INI file and depend on the specified access type.

Subchannel number Lets you specify a subchannel to use Simulink buses

for data exchange. Up to 256 subchannels can be used for each channel.
Subchannel number 1 of a buffer channel must always be used, the other
subchannels can be used in any order.
For more information on subchannels, refer to Using Subchannels for Data
Exchange (FPGA Programming Blockset Guide ).
This setting is configurable only if the bus transfer mode is supported by
the platform and enabled on the Parameters page. For more information,
refer to How to Use Simulink Buses of the FPGA Model to Model Processor
Communication (FPGA Programming Blockset Guide ).

Channel name Lets you specify a user-specific name for the specified
channel. The name is displayed in this block and in its corresponding block in
the processor model.

Show Lets you see where the corresponding processor interface block of the
selected block is used in the entire model.

Generate Lets you generate a processor interface block that correspond to

the register or buffer.
The blocks are added to the FPGA model. Move the blocks to the processor
model to use them as a processor interface.

Details on the access types The FPGA framework contains the definition of the data storage areas. It
specifies one data storage type as register (implemented as Flip-Flop) and one
data storage type as buffer (implemented in the FPGA RAM). With the access
type, you can choose the data storage that you want to use for the data
exchange.

Register access Register access lets you access a scalar value in the register.
The data is identified by the specified channel number. The values are
transmitted element by element.

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Register group access You can group registers to a register group via a
common Register Group ID. All the values that belong to the same Register
Group ID are synchronously updated in the FPGA subsystem.
For read access, the registers of a register group are read from the board-specific
bus sequentially and then provided to the FPGA application simultaneously. For
write access, the registers of a register group are sampled simultaneously in the
FPGA application. These values form a consistent data group that is written to
the board-specific bus.

Buffer access Buffer access lets you access a vector value in the data buffer.
One specific value of the data is identified by the specified channel number and
the position within the buffer.
Data exchange is implemented via a FIFO buffer that works as a swinging buffer.
This means that there are two separate buffers for reading and writing, and
one buffer that switches between reading and writing. Only the pointer has to
be changed to switch the buffer so that no buffer has to be copied from one
position to another.

Free buffer

Application Read buffer Write buffer FPGA application

running on the
processor board

Bus access Bus access lets you use Simulink buses to model the data
exchange between the processor and the FPGA. The data exchange is
implemented via a FIFO buffer in the same way as the buffer access type.
Bus access is supported only by the blocksets of MicroLabBox II, MicroAutoBox III,
and SCALEXIO.

Hardware-specific settings For hardware-specific settings after you select the access type in the block dialog,
refer to the following topics:
§ Block Settings for the MicroLabBox Frameworks on page 69
§ Block Settings for the MicroLabBox II Framework on page 125
§ Block Settings for the SCALEXIO Frameworks on page 195
§ Block Settings for the MicroAutoBox II Frameworks on page 477
§ Block Settings for the MicroAutoBox III Frameworks on page 583

Related topics Basics

Modeling Processor Model Access (FPGA Programming Blockset Guide )

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 FPGA_XDATA_WRITE_BL

Description Page (FPGA_XDATA_WRITE_BL)

Purpose To provide detailed information about the selected access type.

Description The Description page provides a function-specific Help for <...> button after
you selected a function on the corresponding Unit page.

Click Help for <...> to get function-specific information.

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FPGA_IO_READ_BL
Purpose To provide read access to an external device via a physical input channel.

Where to go from here Information in this section

Block Description (FPGA_IO_READ_BL).................................................... 54

To implement read access to a physical input channel in the FPGA model.

Unit Page (FPGA_IO_READ_BL)................................................................ 55

To specify the I/O type and channel to be used for read access.

Description Page (FPGA_IO_READ_BL)..................................................... 56

To provide detailed information about the selected I/O function.

Information in other sections

Block Settings for the MicroLabBox Frameworks...................................... 69

The block dialogs provide hardware-specific settings after you load one
of the DS1202 FPGA I/O Type 1 frameworks.

Block Settings for the MicroLabBox II Framework................................... 125

The block dialogs provide hardware-specific settings after you load the
DS1303 (KU15P) Multi-I/O Board framework.

Block Settings for the SCALEXIO Frameworks........................................ 195

The block dialogs provide hardware-specific settings after you load one
of the frameworks supporting SCALEXIO systems.

Block Settings for the MicroAutoBox II Frameworks............................... 477

The block dialogs provide hardware-specific settings after you load one
of the frameworks supporting MicroAutoBox II.

Block Settings for the MicroAutoBox III Frameworks.............................. 583

The block dialogs provide hardware-specific settings after you load one
of the frameworks supporting MicroAutoBox III.

Block Description (FPGA_IO_READ_BL)

Block overview The figure below shows the block in unconfigured state.

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Purpose To implement read access to a physical input channel in the FPGA model.

Description You can use this block to read data from external devices. The number of
available input channels and their configurations depends on the specified
framework or piggyback module.

I/O mapping For information on the I/O mapping, refer to the description of the framework-
specific Parameters page of this block.

I/O characteristics The following table describes the ports of the block:

Port Description
Output
From IO Represents the outport until the I/O channel is
defined.

Hardware-specific settings For hardware-specific settings after you select the access type in the block dialog,
refer to the following topics:
§ Block Settings for the MicroLabBox Frameworks on page 69
§ Block Settings for the MicroLabBox II Framework on page 125
§ Block Settings for the SCALEXIO Frameworks on page 195
§ Block Settings for the MicroAutoBox II Frameworks on page 477
§ Block Settings for the MicroAutoBox III Frameworks on page 583

Related topics Basics

Modeling External I/O Access (FPGA Programming Blockset Guide )

Unit Page (FPGA_IO_READ_BL)

Purpose To specify the I/O type and channel to be used for read access.

Dialog settings Board number Displays the board number in the range 1 … 16.
For SCALEXIO systems, you can set a board number to distinguish between
multiple FPGA boards during modeling.

Channel name Lets you specify a user‑specific name for the specified
channel.

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I/O type Lets you filter the available input channels.

§ All: The list contains all available input channels.
§ All other selectable I/O types are defined in the specified framework or
piggyback module.
The list below the I/O type setting displays all the available channels of the
specified I/O type. Channels that were already assigned to other blocks are not
displayed in the list.

Note

The dialog settings on the Parameters page depend on the selected I/O
function.

Hardware-specific settings For hardware-specific settings after you select the access type in the block dialog,
refer to the following topics:
§ Block Settings for the MicroLabBox Frameworks on page 69
§ Block Settings for the MicroLabBox II Framework on page 125
§ Block Settings for the SCALEXIO Frameworks on page 195
§ Block Settings for the MicroAutoBox II Frameworks on page 477
§ Block Settings for the MicroAutoBox III Frameworks on page 583

Related topics Basics

Modeling External I/O Access (FPGA Programming Blockset Guide )

Description Page (FPGA_IO_READ_BL)

Purpose To provide detailed information about the selected I/O function.

Description The Description page provides a function-specific Help for <...> button after
you selected a function on the corresponding Unit page.

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Click Help for <...> to get function-specific information.

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FPGA_IO_WRITE_BL
Purpose To provide write access to an external device via a physical output channel.

Where to go from here Information in this section

Block Description (FPGA_IO_WRITE_BL)................................................... 59

To implement write access to a physical output channel in the FPGA
model.

Unit Page (FPGA_IO_WRITE_BL)............................................................... 60

To specify the I/O type and channel to be used for write access.

Description Page (FPGA_IO_WRITE_BL).................................................... 60

To provide detailed information about the selected I/O function.

Information in other sections

Block Settings for the MicroLabBox Frameworks...................................... 69

The block dialogs provide hardware-specific settings after you load one
of the DS1202 FPGA I/O Type 1 frameworks.

Block Settings for the MicroLabBox II Framework................................... 125

The block dialogs provide hardware-specific settings after you load the
DS1303 (KU15P) Multi-I/O Board framework.

Block Settings for the SCALEXIO Frameworks........................................ 195

The block dialogs provide hardware-specific settings after you load one
of the frameworks supporting SCALEXIO systems.

Block Settings for the MicroAutoBox II Frameworks............................... 477

The block dialogs provide hardware-specific settings after you load one
of the frameworks supporting MicroAutoBox II.

Block Settings for the MicroAutoBox III Frameworks.............................. 583

The block dialogs provide hardware-specific settings after you load one
of the frameworks supporting MicroAutoBox III.

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Block Description (FPGA_IO_WRITE_BL)

Block overview The figure below shows the block in unconfigured state.

Purpose To implement write access to a physical output channel in the FPGA model.

Description You can use this block to write data to external devices. The number of available
output channels and their configurations depends on the specified framework or
piggyback module.

I/O mapping For information on the I/O mapping, refer to the description of the framework-
specific Parameters page of this block.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
To IO Represents the inport until the I/O channel is
defined.

Hardware-specific settings For hardware-specific settings after you select the access type in the block dialog,
refer to the following topics:
§ Block Settings for the MicroLabBox Frameworks on page 69
§ Block Settings for the MicroLabBox II Framework on page 125
§ Block Settings for the SCALEXIO Frameworks on page 195
§ Block Settings for the MicroAutoBox II Frameworks on page 477
§ Block Settings for the MicroAutoBox III Frameworks on page 583

Related topics Basics

Modeling External I/O Access (FPGA Programming Blockset Guide )

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Unit Page (FPGA_IO_WRITE_BL)

Purpose To specify the I/O type and channel to be used for write access.

Dialog settings Board number Displays the board number in the range 1 … 16.
For SCALEXIO systems, you can set a board number to distinguish between
multiple FPGA boards during modeling.

Channel name Lets you specify a user‑specific name for the specified
channel.

I/O type Lets you filter and select the available output channels according to
I/O type.
§ All: The list contains all available output channels.
§ All other selectable I/O types are defined in the specified framework or
piggyback module.
The list below the I/O type setting displays all the available channels of the
specified I/O type. Channels that were already assigned to other blocks are not
displayed in the list.

Note

The dialog settings on the Parameters page depend on the selected I/O
function.

Hardware-specific settings For hardware-specific settings after you select the access type in the block dialog,
refer to the following topics:
§ Block Settings for the MicroLabBox Frameworks on page 69
§ Block Settings for the MicroLabBox II Framework on page 125
§ Block Settings for the SCALEXIO Frameworks on page 195
§ Block Settings for the MicroAutoBox II Frameworks on page 477
§ Block Settings for the MicroAutoBox III Frameworks on page 583

Related topics Basics

Modeling External I/O Access (FPGA Programming Blockset Guide )

Description Page (FPGA_IO_WRITE_BL)

Purpose To provide detailed information about the selected I/O function.

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Description The Description page provides a function-specific Help for <...> button after
you selected a function on the corresponding Unit page.

Click Help for <...> to get function-specific information.

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FPGA_INT_BL
Purpose To provide interrupts generated in the FPGA model to the processor model.

Where to go from here Information in this section

Block Description (FPGA_INT_BL)............................................................. 63

To provide an interrupt for triggering a task in the processor model.

Unit Page (FPGA_INT_BL)......................................................................... 64

To specify the interrupt channel used to trigger a task in the processor
model.

Description Page (FPGA_INT_BL).............................................................. 64

To provide detailed information about the selected I/O function.

Information in other sections

Block Settings for the MicroLabBox Frameworks...................................... 69

The block dialogs provide hardware-specific settings after you load one
of the DS1202 FPGA I/O Type 1 frameworks.

Block Settings for the MicroLabBox II Framework................................... 125

The block dialogs provide hardware-specific settings after you load the
DS1303 (KU15P) Multi-I/O Board framework.

Block Settings for the SCALEXIO Frameworks........................................ 195

The block dialogs provide hardware-specific settings after you load one
of the frameworks supporting SCALEXIO systems.

Block Settings for the MicroAutoBox II Frameworks............................... 477

The block dialogs provide hardware-specific settings after you load one
of the frameworks supporting MicroAutoBox II.

Block Settings for the MicroAutoBox III Frameworks.............................. 583

The block dialogs provide hardware-specific settings after you load one
of the frameworks supporting MicroAutoBox III.

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Block Description (FPGA_INT_BL)

Block overview The figure below shows the block in unconfigured state.

Purpose To provide an interrupt for triggering a task in the processor application.

Description The block provides interrupt lines from the FPGA board that you can use
to asynchronously trigger a task in the processor application. An interrupt is
handled internally and transmitted via interrupt line on the processor bus. For
further information on the processor bus, refer to Modeling Processor Model
Access (FPGA Programming Blockset Guide ).

The Parameters page of the dialog is empty until you specify an interrupt
channel number.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Int Represents the inport until the channel number is
defined.

Hardware-specific settings For hardware-specific settings after you select the access type in the block dialog,
refer to the following topics:
§ Block Settings for the MicroLabBox Frameworks on page 69
§ Block Settings for the MicroLabBox II Framework on page 125
§ Block Settings for the SCALEXIO Frameworks on page 195
§ Block Settings for the MicroAutoBox II Frameworks on page 477
§ Block Settings for the MicroAutoBox III Frameworks on page 583

Related topics HowTos

How to Trigger Interrupt-Driven Processor Tasks (FPGA Programming Blockset

Guide )

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Unit Page (FPGA_INT_BL)

Purpose To specify the interrupt channel used to trigger a task in the processor model.

Dialog settings Board number Displays the board number in the range 1 … 16.
For SCALEXIO systems, you can set a board number to distinguish between
multiple FPGA boards during modeling.

Channel number Lets you select a channel number. The range of the
selectable interrupt channels depend on the specified framework or piggyback
module.
Channels that were already assigned to other blocks are not displayed in the list.

Channel name Lets you specify a user-specific name for the specified
channel. The name is displayed in this block and in the corresponding
PROC_INT_BL block in the processor model.

Show Lets you see where the corresponding processor interface block of the
selected block is used in the processor model.

Generate Lets you generate a processor interface block that corresponds to

the register or buffer.
The block is added to the FPGA model. Move the block to the processor model
to use it as an processor interface.

Hardware-specific settings For hardware-specific settings after you select the access type in the block dialog,
refer to the following topics:
§ Block Settings for the MicroLabBox Frameworks on page 69
§ Block Settings for the MicroLabBox II Framework on page 125
§ Block Settings for the SCALEXIO Frameworks on page 195
§ Block Settings for the MicroAutoBox II Frameworks on page 477
§ Block Settings for the MicroAutoBox III Frameworks on page 583

Related topics HowTos

How to Trigger Interrupt-Driven Processor Tasks (FPGA Programming Blockset

Guide )

Description Page (FPGA_INT_BL)

Purpose To provide detailed information about the selected I/O function.

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Description The Description page provides a function-specific Help for <...> button after
you selected a function on the corresponding Unit page.

Click Help for <...> to get function-specific information.

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Dialog Settings to Edit Simulink Bus Signals

Introduction The frameworks of SCALEXIO, MicroAutoBox III, and MicroLabBox II support
Simulink buses to implement the communication between the FPGA
and the processor board. The FPGA_XDATA_READ_BL block and the
FPGA_XDATA_WRITE_BL block let you open a dialog to display and edit the
bus topology.

Bus Editor Dialog - FPGA_XDATA_READ_BL/FPGA_XDATA_WRITE_BL

Purpose To display and edit a Simulink bus topology between the FPGA and the processor
board.

Supported hardware Simulink buses between the FPGA and the processor board are supported only
by SCALEXIO, MicroAutoBox III, and MicroLabBox II.

Precondition The Bus access type is selected on the Unit page of the
FPGA_XDATA_READ_BL or FPGA_XDATA_WRITE_BL block dialog.

Opening the dialog On the Parameters page of the FPGA_XDATA_READ_BL or

FPGA_XDATA_WRITE_BL block dialog, click Edit bus topology.

Signals
Lets you add a new signal to the root level or to a selected signal of the
FPGABus tree. If you add a new signal to a signal in the FPGABus tree, the data
type of that signal changes to Bus automatically, if required.

Lets you delete a signal.

Lets you cut a signal and copy it to the Clipboard of the dialog.

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Lets you copy a signal to the Clipboard of the dialog.

Lets you paste a signal from the Clipboard of the dialog to the selected
signal. If you selected the Ports (root) node, you create a new block port. If you
selected a bus signal, you create a new bus element.

Note

Copy & paste of signals is only possible within the same block dialog.

Lets you move the selected signal up one position.

Lets you move the selected signal down one position.

Signal properties The following signal properties are available:

Name Lets you enter a name for the signal selected in the signal tree. The
name of the root signal is used as a variable name in the generated variable
description file after the real-time application is built.
The name must fulfill the following conditions:
§ The name must not begin or end with /.
§ The names of signals on the same structure level must be unique. They are
case-sensitive.

Description Not supported for FPGA bus topologies.

Unit Not supported for FPGA bus topologies.

Type Lets you specify the data type of the selected signal:
§ Signed
The signal values are in a signed fixed‑point format.
§ Unsigned
The signal values are in a unsigned fixed‑point format.
§ Floating-point
The signal values are in a floating‑point format.
§ Boolean
The signal values are 1 or 0.

Bitwidth Lets you specify the number of bits used to represent the selected
signal. The maximum number is 64 bits.

Binary Point This setting depends on the format selected in the Type setting.
§ signed/unsigned
You can specify the binary point position of the signal data type. 0 represents
the lowest bit position.
§ floating‑point
You can specify the fraction width of the signal data type.

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Related topics HowTos

How to Change the Bus Topology of a Simulink Bus (FPGA Programming Blockset
Guide )
How to Specify the Data Type Conversion for Processor Communication (FPGA
Programming Blockset Guide )

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Block Settings for the MicroLabBox Frameworks

Introduction The block dialogs provide hardware-specific settings after you load one of the
following frameworks:
§ DS1202 FPGA I/O Type 1
§ DS1202 FPGA I/O Type 1 (Flexible I/O)

Where to go from here Information in this section

FPGA_XDATA_READ_BL (DS1202 FPGA I/O Type 1 Settings).......... .......... 70

To configure read access to the local bus data in the FPGA model when
using one of the DS1202 FPGA I/O Type 1 frameworks.

FPGA_XDATA_WRITE_BL (DS1202 FPGA I/O Type 1 Settings)................... 79

To configure write access to local bus data in the FPGA model when
using one of the DS1202 FPGA I/O Type 1 frameworks.

FPGA_IO_READ_BL (DS1202 FPGA I/O Type 1 Settings)............................ 88

To configure read access to analog and digital input signals in the FPGA
model when using one of the DS1202 FPGA I/O Type 1 frameworks.

FPGA_IO_WRITE_BL (DS1202 FPGA I/O Type 1 Settings)......................... 100

To configure write access to analog and digital output signals in
the FPGA model when using one of the DS1202 FPGA I/O Type 1
frameworks.

FPGA_INT_BL (DS1202 FPGA I/O Type 1 Settings)................................... 122

To configure the FPGA interrupt channel when using one of the DS1202
FPGA I/O Type 1 frameworks.

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FPGA_XDATA_READ_BL (DS1202 FPGA I/O Type 1 Settings)

Purpose To configure read access to the local bus data in the FPGA model when using
one of the following frameworks:
§ DS1202 FPGA I/O Type 1
§ DS1202 FPGA I/O Type 1 (Flexible I/O)

Where to go from here Information in this section

Parameters Page (FPGA_XDATA_READ_BL).............................................. 70

To specify the data format and specific settings for the selected access
type.

Description Page (FPGA_XDATA_READ_BL).............................................. 77

To provide detailed information about the selected access type.

Information in other sections

Common settings
Block Description (FPGA_XDATA_READ_BL)............................................. 45
To specify read access by the FPGA model to the processor model via
processor bus.

Unit Page (FPGA_XDATA_READ_BL)......................................................... 46

To specify the general configuration for the FPGA board's processor bus
read access.

Related FPGA blocks

PROC_XDATA_WRITE_BL (FPGA Programming Blockset -
Processor Interface Reference )
To write data from the processor model to the FPGA model via the
board-specific bus.

FPGA_XDATA_WRITE_BL......................................................................... 49
To implement write access to processor-bus data in the FPGA model.

FPGA_XDATA_WRITE_BL (DS1202 FPGA I/O Type 1 Settings)................... 79

To configure write access to local bus data in the FPGA model when
using one of the DS1202 FPGA I/O Type 1 frameworks.

Parameters Page (FPGA_XDATA_READ_BL)

Purpose To specify the data format and specific settings for the selected access type.

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Description The DS1202 FPGA I/O Type 1 frameworks provide the following access types that
you can select on the Unit page of the block's dialog:
§ Register/Register64
If you select Register or Register64 as the access type, the data is read from a
local bus register. 256 registers are available with a data width of 32 bits each
and 256 registers with a data width of 64 bits each. The values are transmitted
element by element.
If you want to access data from several registers simultaneously, you can group
these registers by specifying the same group identifier for them.
Ungrouped registers are automatically combined into one register group with
group ID Ungrouped to optimize data transfer. Since register groups can be
only accessed by one task, you have to explicitly group registers which are
used by different tasks.
§ Buffer/Buffer64
If you select Buffer or Buffer64 as the access type, the data is read from a
local bus buffer. 32 buffers are available that provides elements with a data
width of 32 bits each and 32 buffers that provides elements with a data
width of 64 bits each. Each buffer has a variable buffer size of 1 up to 32768
elements.

There are settings that are common to both access types and settings that are
specific to each access type.

For more information, refer to Details on the access types on page 46.

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_XDATA_READ_BL block.

Binary point position (or fraction width) This setting depends on the
format selected in the Format setting.
§ signed/unsigned
The values of the Data outport are in fixed‑point format.
You can specify the binary point position of the 32‑bit value in the range
0 … 32 and the binary point position of the 64‑bit value in the range 0 … 64.
0 represents the lowest bit position, 32 or 64 the highest bit position.
§ floating‑point
The values of the Data outport are in floating‑point format. The fraction width
is displayed.

Format Lets you select the data format of the Data outport.
§ signed/unsigned
The values of the Data outport are in fixed‑point format with or without one
bit reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
64-bit fixed-point data types are converted to double. Therefore, the fixed-
point resolution of fixed-point data types is restricted to 53 bits.
§ floating‑point
The values of the Data outport are in floating‑point format.

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The 32‑bit data value supports the single-precision floating‑point format with a
fraction width of 24, which complies with the IEEE 754 standard (single).
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is displayed in the Binary point position (or fraction
width) setting.

Enable simulation port Lets you enable an inport for offline simulation data.
The Sim_Data inport is added to the block to connect it to any Simulink signal
used for simulation.

Simulation ports sample time Lets you specify the sample time of the
ports used for simulation, for example, Sim_Data. By default, the sample time
is inherited. You must only specify the sample time explicitly, if the modeling
situation inhibits to inherit the sample time, for example, if the corresponding
PROC block is part of an asynchronous task or is used for multiple access to the
same channel.

Register In description Block display If you specify the register access type, the block display
changes. The simulation ports are optionally displayed.

I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Sim_Data Simulates a local bus data exchange including
floating-point to fixed-point data conversion.
Available only if Enable simulation port is set on
the Parameters page.
Data type: Double
Data width: 1
Output
Data Outputs a 32-bit data value to be read from a
local bus register. The data format depends on the
related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary
point position>
§ Floating‑point format
XFloat_8_24
Data New Outputs a flag that indicates the changes of the
register status. If the flag changes from 0 to 1 and

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Port Description
then to 0 again, the requested register contains a
new value. The flag is set to 1 only within one clock
cycle.
Data type: UFix_1_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register In settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 71.

Register group ID Lets you specify a number in the range 1 … 63 to create

register groups. Registers which you specified with the same group ID are read
from the local bus sequentially and then provided to the FPGA application
simultaneously.
Specify 0 for ungrouped read access.

Buffer In description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Sim_Data Simulates a local bus data exchange including floating-point to fixed-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768
Address Specifies an element in the buffer you want to read. The block requires 3 clock
cycles to update the value of the Data outport according to the specified address.
The maximum port range depends on the specified buffer size in the Parameters
page. The valid port range depends on the number of elements currently in the
buffer (see Data Count outport). If you request data from an address that is greater

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Port Description
than the Data Count value, the output of the Data outport is undefined. The first
element of a buffer is addressed by 0.
Data type: UFix_16_0
Output
Data Outputs a 32-bit data value to be read from a local bus buffer. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Data New Outputs a flag that indicates the changes of the buffer status. If the flag changes
from 0 to 1 and then to 0 again, the requested buffer contains new values and is
ready to be read. The flag is set to 1 only within one clock cycle.
Data type: UFix_1_0
Data Count Outputs the number of elements in the current buffer.
The maximum range depends on the specified buffer size. You can use the value to
define the valid range for the Address inport of 0 … (Data Count -1).
Data type: UFix_16_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Buffer In settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 71.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.
The maximum range of the Address inport depends on the buffer size.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 32-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

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Register64 In description Block display If you specify the register access type, the block display
changes. The simulation ports are optionally displayed.

I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Sim_Data Simulates a local bus data exchange including
floating-point to fixed-point data conversion.
Available only if Enable simulation port is set on
the Parameters page.
Data type: Double
Data width: 1
Output
Data Outputs a 64-bit data value to be read from a
local bus register. The data format depends on the
related dialog settings.
Data type:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary
point position>
64-bit fixed-point data types are converted to
double. Therefore, the fixed-point resolution of
fixed-point data types is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Data New Outputs a flag that indicates the changes of the
register status. If the flag changes from 0 to 1 and
then to 0 again, the requested register contains a
new value. The flag is set to 1 only within one clock
cycle.
Data type: UFix_1_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

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Register64 In settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 71.

Register group ID Lets you specify a number in the range 1 … 63 to create

register groups. All registers – 32‑bit and 64‑bit registers – which you specified
with the same group ID are read from the local bus sequentially and then
provided to the FPGA application simultaneously.
Specify 0 for ungrouped read access.

Buffer64 In description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Sim_Data Simulates a local bus data exchange including floating-point to fixed-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768
Address Specifies an element in the buffer you want to read. The block requires 3 clock
cycles to update the value of the Data outport according to the specified address.
The maximum port range depends on the specified buffer size in the Parameters
page. The valid port range depends on the number of elements currently in the
buffer (see Data Count outport). If you request data from an address that is greater
than the Data Count value, the output of the Data outport is undefined. The first
element of a buffer is addressed by 0.
Data type: UFix_16_0
Output
Data Outputs a 64-bit data value to be read from a local bus buffer. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double. Therefore, the fixed-point
resolution of fixed-point data types is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53

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Port Description
Data New Outputs a flag that indicates the changes of the buffer status. If the flag changes
from 0 to 1 and then to 0 again, the requested buffer contains new values and is
ready to be read. The flag is set to 1 only within one clock cycle.
Data type: UFix_1_0
Data Count Outputs the number of elements in the current buffer.
The maximum range depends on the specified buffer size. You can use the value to
define the valid range for the Address inport of 0 … (Data Count -1).
Data type: UFix_16_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Buffer64 In settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 71.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.
The maximum range of the Address inport depends on the buffer size.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Related topics References

Description Page (FPGA_XDATA_READ_BL)............................................................................... 77

FPGA_XDATA_READ_BL........................................................................................................... 44
FPGA_XDATA_READ_BL (DS1202 FPGA I/O Type 1 Settings)...................................................... 70

Description Page (FPGA_XDATA_READ_BL)

Purpose To provide detailed information about the selected access type.

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Description The Description page provides detailed information about the access type that
you selected on the corresponding Unit page. The information is either in the
text field itself or in an external help document that you can open by clicking the
function-specific Help button on this page.

The description of the access type that is provided by the standard DS1202 FPGA
I/O Type 1 frameworks is included in this user documentation. The description of
the access type of customized frameworks or mounted piggybacks is available as
a separate document.

Related topics References

FPGA_XDATA_READ_BL........................................................................................................... 44
FPGA_XDATA_READ_BL (DS1202 FPGA I/O Type 1 Settings)...................................................... 70
Parameters Page (FPGA_XDATA_READ_BL)............................................................................... 70

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FPGA_XDATA_WRITE_BL (DS1202 FPGA I/O Type 1 Settings)

Purpose To configure write access to the local bus data in the FPGA model when using
one of the following frameworks:
§ DS1202 FPGA I/O Type 1
§ DS1202 FPGA I/O Type 1 (Flexible I/O)

Where to go from here Information in this section

Parameters Page (FPGA_XDATA_WRITE_BL)............................................. 79

To specify the data format and specific settings for the selected access
type.

Description Page (FPGA_XDATA_WRITE_BL)............................................. 86

To provide detailed information about the selected access type.

Information in other sections

Common settings
Block Description (FPGA_XDATA_WRITE_BL)............................................ 50
To specify write access by the FPGA model to the processor model via
processor bus.

Unit Page (FPGA_XDATA_WRITE_BL)............................................. .......... 51

To specify the general configuration for the FPGA board's processor bus
write access.

Related FPGA blocks

FPGA_XDATA_READ_BL.......................................................................... 44
To implement read access to processor-bus data in the FPGA model.

FPGA_XDATA_READ_BL (DS1202 FPGA I/O Type 1 Settings).......... .......... 70

To configure read access to the local bus data in the FPGA model when
using one of the DS1202 FPGA I/O Type 1 frameworks.

Parameters Page (FPGA_XDATA_WRITE_BL)

Purpose To specify the data format and specific settings for the selected access type.

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Description The DS1202 FPGA I/O Type 1 frameworks provide the following access types that
you can select in the Unit page of the block's dialog:
§ Register/Register64
If you select Register or Register64 as the access type, the data is written
to a local bus register. 256 registers are available with a data width of 32
bits each and 256 registers with a data width of 64 bits each. The values
are transmitted element by element. If you want to access data from several
registers simultaneously, you can group these registers by specifying the same
group identifier for them.
§ Buffer/Buffer64
If you select Buffer or Buffer64 as the access type, the data is written to a
local bus buffer. 32 buffers are available that provides elements with a data
width of 32 bits each and 32 buffers that provides elements with a data
width of 64 bits each. Each buffer has a variable buffer size of 1 up to 32768
elements.

There are settings that are common to both access types and settings that are
specific to each access type.

For more information, refer to Details on the access types on page 51.

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_XDATA_WRITE_BL block.

Binary point position (or fraction width) This setting depends on the
format selected in the Format setting.
§ signed/unsigned
The values of the Data outport are in fixed‑point format.
You can specify the binary point position of the 32‑bit value in the range
0 … 32 and the binary point position of the 64‑bit value in the range 0 … 64.
0 represents the lowest bit position, 32 or 64 the highest bit position.
§ floating‑point
The values of the Data outport are in floating‑point format. The fraction width
is displayed.

Format Lets you select the data format of the Data inport.
§ signed/unsigned
The values of the Data inport are in fixed‑point format with or without one bit
reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
64-bit fixed-point data types are converted to double. Therefore, the fixed-
point resolution of fixed-point data types is restricted to 53 bits.
§ floating‑point
The values of the Data inport are in floating‑point format.
The 32‑bit data value supports the single-precision floating‑point format with a
fraction width of 24, which complies with the IEEE 754 standard (single).
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).

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The fraction width is displayed in the Binary point position (or fraction
width) setting.

Enable simulation data port Lets you enable an outport for offline
simulation data. The Sim_Data outport is added to the block to connect it to
any Simulink signal used for simulation.

Simulation ports sample time Lets you specify the sample time of the ports
used for simulation, for example, Sim_Data and Sim_Status. By default, the
sample time is inherited. You must only specify the sample time explicitly, if
the modeling situation inhibits to inherit the sample time, for example, if the
corresponding PROC block is part of an asynchronous task or is used for multiple
access to the same channel.

Register Out description Block display If you specify the register access type, the block display
changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Data Specifies a 32-bit data value to be written to a local bus register. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Output
Sim_Data Simulates a local bus data exchange including fixed-point to floating-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1

Note

The range can be exceeded for the Data inport. The inport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

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Register Out settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 80.

Register group ID Lets you specify a number in the range 1 … 63 to

create register groups. Registers which you specified with the same group ID are
sampled simultaneously in the FPGA application. The values form a consistent
data group that is written to the local bus.

Buffer Out description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a 32-bit data value to be written to a local bus buffer. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Enable Specifies the current valid Data port value.
Data type: UFix_1_0
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.
Ready Explicitly specifies the buffer state as ready to send immediately, even if the buffer
is not completely filled. The data values are written to a new buffer in the following
clock cycle. While the port value is 1, the buffer switches every clock cycle. You are
therefore recommended to set the value for only one clock cycle. If the buffer is
completely filled, it is automatically switched, and the data values are stored in a
new buffer.
Data type: UFix_1_0
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready to send, even if it is not completely filled. The
buffer is switched and the data values are accessible via local bus in the following
clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.
Output

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Port Description
Sim_Data Simulates a local bus data exchange including fixed-point to floating-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768. The vector width depends on the specified buffer size.
Overflow Outputs a flag that indicates that a buffer overflow occurred. An overflow occurs if
the old buffer is not read completely before a new buffer is ready to be read.
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.
Data type: UFix_1_0
Sim_Status Outputs information about the simulated data exchange on the Sim_Data outport.
Available only if the access type is specified as Buffer and Enable simulation port
is set on the Parameters page.
Data type: UInt32
Data width: 3
§ Sim_Status[0]: Contains the number of valid elements in the Sim_Data vector.
§ Sim_Status[1]: Indicates whether the current buffer contains new or old values. It
is 1 if the buffer contains new values.
§ Sim_Status[2]: Indicates whether a buffer overflow occurred. At least one buffer
was not read and its data was lost before the currently read buffer was filled.

Buffer Out settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 80.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 32-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation status port Lets you enable an outport to get status
information about the simulation data that is available when you have enabled
the simulation data port. The Sim_Status outport is added to the block.

Register64 Out description Block display If you specify the register access type, the block display
changes. The simulation ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Data Specifies a 64-bit data value to be written to a local bus register. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double. Therefore, the fixed-point
resolution of fixed-point data types is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Output
Sim_Data Simulates a local bus data exchange including fixed-point to floating-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1

Note

The range can be exceeded for the Data inport. The inport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register64 Out settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 80.

Register group ID Lets you specify a number in the range 1 … 63 to create

register groups. All registers – 32‑bit and 64‑bit registers – which you specified
with the same group ID are sampled simultaneously in the FPGA application. The
values form a consistent data group that is written to the local bus.

Buffer64 Out description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a 64-bit data value to be written to a local bus buffer. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double. Therefore, the fixed-point
resolution of fixed-point data types is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Enable Specifies the current valid Data port value.
Data type: UFix_1_0
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.
Ready Explicitly specifies the buffer state as ready to send immediately, even if the buffer
is not completely filled. The data values are written to a new buffer in the following
clock cycle. While the port value is 1, the buffer switches every clock cycle. You are
therefore recommended to set the value for only one clock cycle. If the buffer is
completely filled, it is automatically switched, and the data values are stored in a
new buffer.
Data type: UFix_1_0
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready o send, even if it is not completely filled. The
buffer is switched and the data values are accessible via local bus in the following
clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.
Output
Sim_Data Simulates a local bus data exchange including fixed-point to floating-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768. The vector width depends on the specified buffer size.
Overflow Outputs a flag that indicates that a buffer overflow occurred. An overflow occurs if
the old buffer is not read completely before a new buffer is ready to be read.
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.
Data type: UFix_1_0
Sim_Status Outputs information about the simulated data exchange on the Sim_Data outport.
Available only if the access type is specified as Buffer and Enable simulation port
is set on the Parameters page.
Data type: UInt32

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Port Description
Data width: 3
§ Sim_Status[0]: Contains the number of valid elements in the Sim_Data vector.
§ Sim_Status[1]: Indicates whether the current buffer contains new or old values. It
is 1 if the buffer contains new values.
§ Sim_Status[2]: Indicates whether a buffer overflow occurred. At least one buffer
was not read and its data was lost before the currently read buffer was filled.

Buffer64 Out settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 80.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64 bits in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation status port Lets you enable an outport to get status
information about the simulation data that is available when you have enabled
the simulation data port. The Sim_Status outport is added to the block.

Related topics References

Description Page (FPGA_XDATA_WRITE_BL).............................................................................. 86

FPGA_XDATA_WRITE_BL.......................................................................................................... 49
FPGA_XDATA_WRITE_BL (DS1202 FPGA I/O Type 1 Settings).................................................... 79

Description Page (FPGA_XDATA_WRITE_BL)

Purpose To provide detailed information about the selected access type.

Description The Description page provides detailed information about the access type that
you selected on the corresponding Unit page. The information is either in the
text field itself or in an external help document that you can open by clicking the
function-specific Help button on this page.

The description of the access type that is provided by the standard DS1202 FPGA
I/O Type 1 frameworks is included in this user documentation. The description of
the access type of customized frameworks or mounted piggybacks is available as
a separate document.

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Related topics References

FPGA_XDATA_WRITE_BL.......................................................................................................... 49
FPGA_XDATA_WRITE_BL (DS1202 FPGA I/O Type 1 Settings).................................................... 79
Parameters Page (FPGA_XDATA_WRITE_BL).............................................................................. 79

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FPGA_IO_READ_BL (DS1202 FPGA I/O Type 1 Settings)

Purpose To configure read access to analog and digital input signals in the FPGA model
when using one of the following frameworks:
§ DS1202 FPGA I/O Type 1
§ DS1202 FPGA I/O Type 1 (Flexible I/O)

Where to go from here Information in this section

Parameters Page (FPGA_IO_READ_BL)..................................................... 88

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_READ_BL)............................................................ 95

To specify the inverting, scaling, and saturation settings for the selected
I/O function.

Description Page (FPGA_IO_READ_BL)..................................................... 98

To provide detailed information about the selected I/O function.

Information in other sections

Common settings
Block Description (FPGA_IO_READ_BL).................................................... 54
To implement read access to a physical input channel in the FPGA model.

Unit Page (FPGA_IO_READ_BL)................................................................ 55

To specify the I/O type and channel to be used for read access.

Related FPGA blocks

FPGA_IO_WRITE_BL................................................................................. 58
To provide write access to an external device via a physical output
channel.

FPGA_IO_WRITE_BL (DS1202 FPGA I/O Type 1 Settings)......................... 100

To configure write access to analog and digital output signals in
the FPGA model when using one of the DS1202 FPGA I/O Type 1
frameworks.

Parameters Page (FPGA_IO_READ_BL)

Purpose To specify relevant settings for the selected I/O function.

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Description The frameworks provide different I/O types, which you can select on the
Unit page of the block. The number of the available physical connections on
MicroLabBox's DS1302 determines the I/O functions that you can select:
§ ADC 1 (Class 1) … ADC 24 (Class 1)
§ ADC 1 (Class 2) … ADC 8 (Class 2)
§ Resolver 1 ... Resolver 2
§ Status In
§ Proc App Status

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_IO_READ_BLx block, except
for the Status In function.

Enable simulation port Lets you enable an inport for offline simulation data.
The Sim_Data inport is added to the block to connect it to simulation data
coming from a Simulink-based I/O environment model.

ADC (Class 1) description Block display If you select an ADC (Class 1) channel from the channel list,
the block display changes. The simulation ports are displayed optionally.

I/O characteristics The scaling between the analog input voltage and the
output of the block is:

Input Voltage Range Simulink Output

‑10 V … +10 V The output port range is: ‑32767 … +32767

The following table describes the ports of the block for analog input channels:

Port Description
Input
Convert Triggers the sampling of the A/D converter. When the value is set to 1 for at least
one clock cycle, the ADC starts the conversion. The port allows a precise definition
of the starting point of ADC sampling. The Busy outport signals the end of the
conversion process.
Setting this value permanently to 1 results in continuous sampling.
Data type: UFix_1_0
Range: 0 or 1

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Port Description
Sim Data Simulates an input signal in the same range as that specified for the real input
signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Input voltage range: ‑10 V … +10 V
Output
Data Outputs the current results of the A/D conversions on the current channel.
Data type: Fix_16_0 1)
Range: ‑32767 … +32767
Update rate: 1 Msps
Busy Outputs an end of conversion signal if the conversion result is available. If the flag
changes from 1 to 0, the ADC data contains a new value. The flag is set to 0 for
only one clock cycle.
Data type: UFix_1_0
Range: 0 or 1
1) You can change the data type of the Data port with the Scaling format parameter
on the Scaling page. Refer to How to Change the Data Type of Analog Signals (FPGA
Programming Blockset Guide ).
If the hardware input signal or the value of the Sim_Data inport exceeds
the specified input voltage range, Data outport is saturated to minimum or
maximum range value.

I/O mapping The signals are available at the Analog In connector.

MicroLabBox has static mapping between I/O signals and I/O pins. The signal
name is also printed on the housing of MicroLabBox. You have to consider only
the connector panel type.
For a detailed connector pinout, refer to:
§ Analog I/O A Connector (Sub-D) (MicroLabBox Hardware Installation and
Configuration )
§ Analog In and Analog Out Connectors (BNC) (MicroLabBox Hardware
Installation and Configuration )
§ Analog In Class 1 Connectors (Spring-Cage) (MicroLabBox Hardware
Installation and Configuration )
For detailed information on the channel characteristics, refer to Analog Class 1
Inputs (MicroLabBox Hardware Installation and Configuration ).

ADC (Class 1) settings Only common dialog settings. Refer to Common settings on page 89.

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ADC (Class 2) description Block display If you select an ADC (Class 2) channel from the channel list,
the block display changes. The simulation ports are displayed optionally.

I/O characteristics The scaling between the analog input voltage and the
output of the block is:

Input Voltage Range Simulink Output

–10 V … +10 V The output port range is: –32768 … +32767

The following table describes the ports of the block for analog input channels:

Port Description
Input
Sim Data Simulates an input signal in the same range as that specified for the real input
signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Input voltage range: -10 V … +10 V
Output
Data Outputs the current results of the A/D conversions on the current channel.
Data type: Fix_16_0 1)
Range: -32768 … +32767
Update rate: 10 Msps
1) You can change the data type of the Data port with the Scaling format parameter
on the Scaling page. Refer to How to Change the Data Type of Analog Signals (FPGA
Programming Blockset Guide ).
If the hardware input signal or the value of the Sim_Data inport exceeds
the specified input voltage range, Data outport is saturated to minimum or
maximum range value.

I/O mapping The signals are available at the Analog In connector.

MicroLabBox has static mapping between I/O signals and I/O pins. The signal
name is also printed on the housing of MicroLabBox. You have to consider only
the connector panel type.
For a detailed connector pinout, refer to:
§ Analog I/O A Connector (Sub-D) (MicroLabBox Hardware Installation and
Configuration )
§ Analog In and Analog Out Connectors (BNC) (MicroLabBox Hardware
Installation and Configuration )
§ Analog In Class 2 Connectors (Spring-Cage) (MicroLabBox Hardware
Installation and Configuration )

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For detailed information on the channel characteristics, refer to Analog Class 2

Inputs (MicroLabBox Hardware Installation and Configuration ).

ADC (Class 2) settings Only common dialog settings. Refer to Common settings on page 89.

Resolver description Basics on the resolver interface Refer to Resolver Interface (MicroLabBox
Features ).

Block display If you select Resolver 1 or Resolver 2 channel from the channel
list, the block display changes.

I/O characteristics The following table describes the ports of the block for
resolver input channels:

Port Description
Input
Enable Enables the excitation voltage:
§ 0: The resolver interface provides no excitation voltage.
§ 1: The resolver interface provides the excitation voltage that you set on the
Parameters page.
Data type: UFix_1_0
Data width: 1
Reset Resets the fault status of the resolver interface that is provided at the Fault port to
0:
§ 0: No reset.
§ 1: Resets the fault status.
Data type: UFix_1_0
Data width: 1
Output
Mechanical Outputs the position of the resolver sensor as a 16-bit angle value. The 16-bit range
Position of 0 … +65535 corresponds to 0° ... (360 - 2-16)°.
Formula for angle calculation: alpha[°] = Mechanical Position * 360°/216.
Data type: UFix_16_0
Range: 0 … +65535
Data width: 1
Valid Outputs whether the angle position and fault status that are provided by the
resolver sensor are valid.

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Port Description
This port is used to evaluate whether the resolver interface is ready to receive data
from the input signals:
§ 0: The hardware cannot get data from the input signals. The current values are
not valid.
§ 1: Data values for the position and the fault status has been received. The current
values are valid.
Data type: UFix_1_0
Data width: 1
Update Outputs a flag that indicates that a new position value or fault status is available.
A high level acknowledges the update. The flag is set high in only one clock cycle.
Data type: UFix_1_0
Data width: 1
Fault Outputs the fault status of the resolver interface. The measured position might be
valid only if no error is found.
Each bit in the 8‑bit value represents a specific fault if its value is 1:
§ Bit 0 (LSB): Configuration parity error
§ Bit 1: Phase lock
§ Bit 2: Velocity too high
§ Bit 3: Loss of tracking
§ Bit 4: Degradation of signal mismatch
§ Bit 5: Degradation of signal overrange
§ Bit 6: Inputs loss of signal
§ Bit 7: Inputs clipped
Data type: UFix_1_0
Data width: 8
For more information on the status information, refer to Resolver Interface
(MicroLabBox Features ).

I/O mapping The signals are available at the Resolver connector.

MicroLabBox has static mapping between I/O signals and I/O pins. The signal
name is also printed on the housing of MicroLabBox. You have to consider only
the connector panel type.
Each interface provides six signals:
§ 2 differential analog output signals for EXC and EXC
§ 4 differential analog input signals for SIN, SIN, COS and COS
For a detailed connector pinout, refer to:
§ Resolver Connectors (Sub-D) (MicroLabBox Hardware Installation and
Configuration )
§ Resolver Connectors (Spring-Cage) (MicroLabBox Hardware Installation and
Configuration )
For a detailed information on the channel characteristics, refer to Resolver
Interfaces (MicroLabBox Hardware Installation and Configuration ).

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Resolver settings The Parameters page provides the following dialog settings.

Desired excitation frequency Lets you select the frequency of the sine
signal to be used for the excitation of the resolver rotor in the range 2,000 Hz …
20,000 Hz in steps of 250 Hz.

Excitation RMS voltage Lets you select the voltage level of the excitation
output signal:
§ 3.0 VRMS
§ 7.0 VRMS
§ 10.0 VRMS

Input RMS voltage Lets you select the voltage level of the sine and cosine
input signals:
§ 1.5 VRMS
§ 3.5 VRMS
§ 5.0 VRMS

Maximum speed Lets you select the maximum speed to be measured in

revolutions per minute. By selecting the speed range, you specify the related
resolution.
§ 150000 rpm (10 Bit): Specifies a maximum speed of 150,000 rpm and a
resolution of 10 bits.
§ 60000 rpm (12 Bit): Specifies a maximum speed of 60,000 rpm and a
resolution of 12 bits.
§ 30000 rpm (14 Bit): Specifies a maximum speed of 30,000 rpm and a
resolution of 14 bits.
§ 7500 rpm (16 Bit): Specifies a maximum speed of 7500 rpm and a resolution
of 16 bits.

Status In description Block display If you select the Status In channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Output
Init Done Outputs the state of the initialization sequence that is started after programming
the FPGA.
Data type: UFix_1_0
§ 0: Initialization sequence is in progress.
§ 1: Initialization sequence has finished.

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I/O mapping No external connection.

Status In settings None

Proc App Status description Block display If you select the Proc App Status channel from the channel list,
the block display changes.

I/O characteristics The following table describes the ports of the block:

Port Description
Output
Status Outputs the state of the processor application. The state can be used to control the
FPGA application.
Data type: UFix_1_0
§ 0: Processor application is stopped.
§ 1: Processor application is running.

I/O mapping No external connection.

Proc App Status settings None

Related topics References

Description Page (FPGA_IO_READ_BL)...................................................................................... 98

FPGA_IO_READ_BL................................................................................................................... 54
FPGA_IO_READ_BL (DS1202 FPGA I/O Type 1 Settings)............................................................. 88
Scaling Page (FPGA_IO_READ_BL)............................................................................................. 95

Scaling Page (FPGA_IO_READ_BL)

Purpose To specify the inverting, scaling, and saturation settings for the selected I/O
function.

Description You can modify the I/O signal of the selected I/O function if you select the
Enable FPGA test access and scaling parameter on the FPGA Access page

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of the FPGA_SETUP_BL block dialog. The possible modifications depend on the

selected I/O function.

Common settings The following settings on the Scaling page are common to the I/O functions that
you can select on the Unit page.

Enable FPGA test access and scaling for this block Lets you disable FPGA
test access and scaling for the selected I/O function.

ADC (class 1 and class 2) The following settings on the Scaling page are specific to the ADC I/O function.
settings
Note

Scaling of analog I/O signals also effects the signal path:

§ If you use the parameters of the Scaling page to scale analog signals, the
data type of the Data port is set to the specified data format for scaling.
For more information, refer to How to Change the Data Type of Analog
Signals (FPGA Programming Blockset Guide ).
§ FPGA scaling of analog I/O signals might cause additional latency. If
the latency can be calculated during the modeling, analog I/O functions
display the total latency.

Scaling format Lets you select the data format for scaling and saturation.
§ Signed/Unsigned:
The values of the parameters for scaling and saturation are in fixed‑point
format. The signed fixed-point format reserves one bit for the sign.
You can specify the number of bits and the binary point position with the
Number of bits and Binary point (fraction width) parameters.
§ Single:
The values of the parameters for scaling and saturation are 32-bit values in
the single-precision floating‑point format with a fraction width of 24, which
complies with the IEEE 754 standard (single).
§ Double:
The values of the parameters for scaling and saturation are 64-bit values in
the double-precision floating‑point format with a fraction width of 53, which
complies with the IEEE 754 standard (double).

Number of bits This setting depends on the Scaling format setting.

§ Fixed-point format:
Lets you specify the bit width of the scaling parameters and the Data port in
the range 1 ... 64.
§ Floating-point format:
Displays the bit width of the scaling parameters and the Data port.

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Binary point (fraction width) This setting depends on the Scaling format
setting.
§ Fixed-point format:
Lets you specify the binary point position of the scaling parameters and the
Data port. The position 0 represents the lowest bit position
§ Floating-point format:
Displays the fraction width of the scaling parameters and the Data port.

Scaling factor Lets you specify the scaling factor. The scaling factor gains the
signal of the Data port before it is saturated or replaced via FPGA test access.
You must check whether the specified and displayed value is supported by
the specified scaling format. The value of the Scaling factor parameter will
be executed with the maximum accuracy of the specified scaling format
and saturated to the minimum and maximum values that the scaling format
supports.

Scaling offset Lets you add a signal offset after the signal of the Data port is
scaled with the scaling factor.
You must check whether the specified and displayed value is supported by
the specified scaling format. The value of the Scaling offset parameter will
be executed with the maximum accuracy of the specified scaling format
and saturated to the minimum and maximum values that the scaling format
supports.

Saturation minimum value Lets you specify the minimum value to which
the measured and scaled signal is saturated before it is output via the Data port.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation minimum
value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

Saturation maximum value Lets you specify the maximum value to which
the measured and scaled signal is saturated before it is output via the Data port.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation maximum
value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

Multiplier latency Lets you specify the latency that is caused by the
multiplier for scaling. The multiplier is used to multiply the signal with the value
of the Scaling factor parameter.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The multiplication will be implemented without latency.
§ 1 ... 20: The multiplication will be implemented with the specified latency.
Use this value range in the exceptional case that the optimized latency cause
timing problems during the build process.

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Adder latency Lets you specify the latency that is caused by the offset adder.
The offset adder is used to add the value of the Scaling offset parameter to the
signal.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The adding will be implemented without latency.
§ 1 ... 20: The adding will be implemented with the specified latency.
Use this value range in the exceptional case that the optimized latency causes
timing problems during the build process.

Status In settings The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

Proc App Status settings The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

Resolver settings The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

Related topics Basics

Basics on FPGA Test Access and Scaling (FPGA Programming Blockset Guide )

References

Description Page (FPGA_IO_READ_BL)...................................................................................... 98

FPGA_IO_READ_BL................................................................................................................... 54
FPGA_IO_READ_BL (DS1202 FPGA I/O Type 1 Settings)............................................................. 88
Parameters Page (FPGA_IO_READ_BL)...................................................................................... 88

Description Page (FPGA_IO_READ_BL)

Purpose To provide detailed information about the selected I/O function.

Description The Description page provides detailed information about the access type that
you selected on the corresponding Unit page. The information is either in the
text field itself or in an external help document that you can open by clicking the
function-specific Help button on this page.

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The description of the access type that is provided by the standard DS1202 FPGA
I/O Type 1 frameworks is included in this user documentation. The description of
the access type of customized frameworks or mounted piggybacks is available as
a separate document.

Related topics References

FPGA_IO_READ_BL................................................................................................................... 54
FPGA_IO_READ_BL (DS1202 FPGA I/O Type 1 Settings)............................................................. 88
Parameters Page (FPGA_IO_READ_BL)...................................................................................... 88
Scaling Page (FPGA_IO_READ_BL)............................................................................................. 95

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FPGA_IO_WRITE_BL (DS1202 FPGA I/O Type 1 Settings)

Purpose To configure write access to analog and digital output signals in the FPGA model
when using one of the following frameworks:
§ DS1202 FPGA I/O Type 1
§ DS1202 FPGA I/O Type 1 (Flexible I/O)

Where to go from here Information in this section

Parameters Page (FPGA_IO_WRITE_BL).................................................. 100

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_WRITE_BL)........................................................ 117

To specify the inverting, scaling, and saturation settings for the selected
I/O function.

Description Page (FPGA_IO_WRITE_BL).................................................. 121

To provide detailed information about the selected I/O function.

Information in other sections

Common settings
Block Description (FPGA_IO_WRITE_BL)................................................... 59
To implement write access to a physical output channel in the FPGA
model.

Unit Page (FPGA_IO_WRITE_BL)............................................................... 60

To specify the I/O type and channel to be used for write access.

Related FPGA blocks

FPGA_IO_READ_BL.................................................................................. 54
To provide read access to an external device via a physical input channel.

FPGA_IO_READ_BL (DS1202 FPGA I/O Type 1 Settings)............................ 88

To configure read access to analog and digital input signals in the FPGA
model when using one of the DS1202 FPGA I/O Type 1 frameworks.

Parameters Page (FPGA_IO_WRITE_BL)

Purpose To specify relevant settings for the selected I/O function.

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Description The frameworks provide the three I/O types Analog, Digital, and Other, which
you can select on the Unit page of the block. The number of the available
physical connections on MicroLabBox's DS1302 board determines the I/O
functions that you can select:
§ DAC 1 (Class 1) … DAC 16 (Class 1)
§ Buzzer
§ Digital InOut 1 (Class 1) … Digital InOut 48 (Class 1)
§ Digital InOut 1 (Class 2) … Digital InOut 12 (Class 2)
§ LED Out 1 … LED Out 4
§ UART 1 (RS232) … UART 2 (RS232)
§ UART 1 (RS422/485) … UART 2 (RS422/485)

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_IO_WRITE_BL block, except
for the LED Out function.

Enable simulation port Lets you enable an outport for offline simulation
data. The Sim Data outport is added to the block to connect it to a Simulink-
based I/O environment model.
§ If you have selected one of the UART functions, this setting is replaced by
function-specific simulation settings.
§ For the Digital InOut functions, there are separate settings for enabling the
input and output simulation ports.

DAC (Class 1) description Block display If you select a DAC channel from the channel list, the block
display changes. The simulation ports are displayed optionally.

I/O characteristics The scaling between the analog output voltage and the
input of the block is:

Output Voltage Range Simulink Input

‑10 V … +10 V The input port range is: ‑32767 … +32767

The following table describes the ports of the block:

Port Description
Input
Data Outputs a signal in the specified range.
Data type: Fix_16_0 1)
Output voltage range: ‑32767 … +32767

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Port Description
The range can be exceeded, and saturation is performed to a minimum or maximum
value.
Hardware update rate: 2.78 Msps
If the values are updated at a higher FPGA model rate, intermediate values are not
updated by the DAC.
Convert Triggers the sampling of the D/A converter. When the value is set to 1 for at least
one clock cycle, the DAC starts the conversion. The port allows a precise definition
of the starting point of DAC sampling. The Busy outport signals the end of the
conversion process.
Setting this value permanently to 1 results in continuous sampling.
Data type: UFix_1_0
Range: 0 or 1
Output
Busy Outputs an end of conversion signal if the conversion result is available. If the flag
changes from 0 to 1, the DAC data contains a new value. The flag is set to 1 for
only one clock cycle.
Data type: UFix_1_0
Range: 0 or 1
Sim Data Simulates an output signal in the same range as that specified for the real output
signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Output voltage range: ‑10 V … +10 V
1) You can change the data type of the Data port with the Scaling format parameter
on the Scaling page. Refer to How to Change the Data Type of Analog Signals (FPGA
Programming Blockset Guide ).

I/O mapping The signals are available at the Analog Out connector.
MicroLabBox has static mapping between I/O signals and I/O pins. The signal
name is also printed on the housing of MicroLabBox. You have to consider only
the connector panel type.
For a detailed connector pinout, refer to:
§ Analog I/O B Connector (Sub-D) (MicroLabBox Hardware Installation and
Configuration )
§ Analog In and Analog Out Connectors (BNC) (MicroLabBox Hardware
Installation and Configuration )
§ Analog Out Class 1 Connectors (Spring-Cage) (MicroLabBox Hardware
Installation and Configuration )
For detailed information on the channel characteristics, refer to Analog Class 1
Outputs (MicroLabBox Hardware Installation and Configuration ).

DAC (Class 1) settings Only common dialog settings. Refer to Common settings on page 101.

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Buzzer description Block display If you select Buzzer from the channel list, the block display
changes.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Frequency Specifies the period of the acoustic signal in steps of 40 µs. You calculate the
frequency as follows:
frequency [Hz] = 1 / period [s]
Data type: UFix8_0
Value range: 0 … 255
§ 0 : No acoustic signal
§ 1: 40 µs (25 kHz)
§ ...
§ 255: 10200 µs (98 Hz)
Beep Specifies the duration of one beep of the acoustic signal in steps of 10 ms.
Duration Data type: UFix8_0
Value range: 0 … 255
§ 0: No acoustic signal
§ 1 ... 254: 10 ms ... 2540 ms
§ 255: Beep is generated permanently
Pause Specifies the duration of a pause between two beeps of the buzzer in steps of
Duration 10 ms.
Data type: UFix8_0
Value range: 0 … 255: 0 ms ... 2550 ms
Beep Count Specifies the number of beeps to be generated.
Data type: UFix8_0
Value range: 0 … 255
§ 0: No acoustic signal
§ 255: The number of beeps is infinite
Start Starts the buzzer if the value is 1 for one clock cycle. The started buzzer outputs
the specified acoustic signal. New values of the Frequency, Beep Duration, Pause
Duration, and Beep Count ports take effect immediately. For example: If you
change the data value of the Frequency port to 0, the buzzer stops the generation
of an acoustic signal immediately.
Data type: UFix1_0
Range: 0 or 1

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I/O mapping No external connection

Buzzer settings None

Digital InOut (Class 1) Block display If you select a Digital InOut (Class 1) channel from the channel
description list, the block display changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Out Outputs a signal in the specified range.
If driven with 0, the hardware output is 0 V. If driven with 1, the hardware output
is set to the specified high-supply voltage.
The hardware output is only driven if the Enable port is set to 1, otherwise the
output is set to high impedance (High-Z).
Data Type: UFix_1_0
Update rate: 100 MHz

Note

The frequency that can be generated is much smaller than the update rate.
For information on the electrical characteristics of the DS1302 board, refer
to Digital Class 1 I/O (Bidirectional) (MicroLabBox Hardware Installation and
Configuration ).

Enable Controls the hardware output.

Data values if the channel is used as digital input:
§ 0: The Data In outport is disabled.
§ 1: The Data In outport outputs the current results of the digital input channel.
Data values if the channel is used as digital output:
§ 0: The hardware is set to High-Z.
§ 1: The hardware output reacts to the Data Out inport.
Data type: UFix_1_0
Direction Controls the direction of the digital channel.
Data type: UFix_1_0
§ 0: The channel is used as digital input channel.
§ 1: The channel is used as digital output channel.

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Port Description
Sim Data In Simulates an input signal in the same range as that specified for the real input
signal.
Available only if Enable digital in simulation port is set on the Parameters
page.
Data type: Double
Data width: 1
Threshold level: 2 V
Output
Data In Outputs the current results of the digital input channel.
Data type: UFix_1_0
The Data In outport is enabled only if the Enable port is set to 1.
§ 0: Input voltage falled below the threshold low voltage of 0.8 V.
§ 1: Input voltage exceeded the threshold high voltage of 2 V.
Update rate: 100 MHz

Note

The frequency that can be generated is much smaller than the update rate.
For information on the electrical characteristics of the DS1302 board, refer
to Digital Class 1 I/O (Bidirectional) (MicroLabBox Hardware Installation and
Configuration ).

Sim Data Out Simulates an output signal in the same range as that specified for the real output
signal.
Available only if Enable digital out simulation port is set on the Parameters
page.
Data type: Double
Data width: 1
Output voltage: 0 V, 2.5 V, 3.3 V, or 5 V

If the value of the Data In inport exceeds the specified data width, only the
lowest bit is used.

I/O mapping The signals are available at the Digital I/O connector.
MicroLabBox has static mapping between I/O signals and I/O pins. The signal
name is also printed on the housing of MicroLabBox. You have to consider only
the connector panel type.
For a detailed connector pinout, refer to:
§ Digital I/O A Connector (Sub-D) (MicroLabBox Hardware Installation and
Configuration )
DIO1 ch 1 … DIO1 ch 32
§ Digital I/O B Connector (Sub-D) (MicroLabBox Hardware Installation and
Configuration )
DIO1 ch 33 … DIO1 ch 48
§ Digital I/O Class 1 Connectors (Spring-Cage) (MicroLabBox Hardware
Installation and Configuration )
DIO1 ch 1 … DIO1 ch 48

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For detailed information on the channel characteristics, refer to:

§ Digital Class 1 I/O (Bidirectional) (MicroLabBox Hardware Installation and
Configuration )

Digital InOut (Class 1) settings The Parameters page provides the following dialog settings.

Invert values Lets you select whether to invert the input and output values of
the digital channel.

Input filter Lets you specify the minimum pulse length for detecting a valid
input in the range 0 … 10,000,000 ns.

High supply Lets you specify the high-level voltage for the digital outputs.
You can select 2.5 V, 3.3 V or 5 V.

Rising edge delay Lets you specify whether to use a delay for the rising edge
detection. The delay can be specified in the range 0 … 65500 ns.

Enable digital out simulation port Lets you enable an outport for offline
simulation data. The Sim Data Out outport is added to the block to connect it
to a Simulink-based I/O environment model.

Enable digital in simulation port Lets you enable an inport for offline
simulation data. The Sim Data In inport is added to the block to connect it to
simulation data coming from a Simulink-based I/O environment model. This port
is relevant only if the signal direction is in.

Digital InOut (Class 2) Block display If you select a Digital InOut (Class 2) channel from the channel
description list, the block display changes. The simulation ports are displayed optionally.

I/O characteristics The I/O characteristics for the Digital InOut (Class 2)
function are the same as for the Digital InOut (Class 1) function, refer to I/O
characteristics on page 104.

I/O mapping The signals are available at the Digital I/O connector.
MicroLabBox has static mapping between I/O signals and I/O pins. The signal
name is also printed on the housing of MicroLabBox. You have to consider only
the connector panel type.
For a detailed connector pinout, refer to:
§ Digital I/O B Connector (Sub-D) (MicroLabBox Hardware Installation and
Configuration )
§ Digital I/O Class 2 Connectors (Spring-Cage) (MicroLabBox Hardware
Installation and Configuration )

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For detailed information on the channel characteristics, refer to:

§ Digital Class 2 I/O (Bidirectional) (MicroLabBox Hardware Installation and
Configuration )

Digital InOut (Class 2) settings The Parameters page provides the following dialog settings.

Invert values Lets you select whether to invert the input and output values of
the digital channel.

Input filter Lets you specify the minimum pulse length for detecting a valid
input in the range 0 … 10,000,000 ns.

Rising edge delay Lets you specify whether to use a delay for the rising edge
detection. The delay can be specified in the range 0 … 65500 ns.

Enable digital out simulation port Lets you enable an outport for offline
simulation data. The Sim Data Out outport is added to the block to connect it
to a Simulink-based I/O environment model.

Enable digital in simulation port Lets you enable an inport for offline
simulation data. The Sim Data In inport is added to the block to connect it to
simulation data coming from a Simulink-based I/O environment model. This port
is relevant only if the signal direction is in.

LED Out description Block display If you select an LED Out channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Intensity Red Controls the color of one of the four FPGA status LEDs placed near the
connectors. With this inport you specify the red component of the RGB color
value.
Data type: UFix_8_0
Value range: 0 … 255
Intensity Green Controls the color of one of the four FPGA status LEDs placed near the
connectors. With this inport you specify the green component of the RGB color
value.
Data type: UFix_8_0
Value range: 0 … 255

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Port Description
Intensity Blue Controls the color of one of the four FPGA status LEDs placed near the
connectors. With this inport you specify the blue component of the RGB color
value.
Data type: UFix_8_0
Value range: 0 … 255

If the value of the Data inport exceeds the specified data width, only the lowest
8 bits are used.

I/O mapping No external connection.

LED Out settings None

UART (RS232) description Block display If you select an UART (RS232) channel from the channel list,
the block display changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Read_Enable Specifies to start receiving a value.
After three clock cycles, the value is available and can be read from the RX
FIFO buffer. The value remains valid until the next Read_Enable signal.
Before you read data from the RX FIFO buffer, you should check the
Read_Fifo_Empty signal not to be set. The Read_Fifo_Empty signal
switches one clock cycle after the RX FIFO value has been read.
Do not use the Read_Data_Count signal (Read_Data_Count < 0) to check
the RX FIFO buffer, because it requires one additional clock cycle to get the
count value.
You can read one value per clock cycle from the UART.
Data Type: UFix_1_0
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.
Write_Enable Specifies to start sending a value.
The Write_Data value is written to the TX FIFO buffer, from which it is
automatically send to the TX output pin of the I/O connector using the
specified UART communication settings.

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Port Description
Write_Enable must be set to 1 for only one clock cycle.
Before you write data to the TX FIFO buffer, you should check the
Write_Fifo_Full signal not to be set. The Write_Fifo_Full signal switches
one clock cycle after the Write_Enable signal has been set.
Do not use the Write_Data_Count signal (Write_Data_Count < 2047) to
check the TX FIFO buffer, because it requires one additional clock cycle to
get the count value.
Data type: UFix_1_0
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.
The hardware output port is driven with the values from the TX FIFO buffer.
It is synchronously running to the UART clock defined by the UART baud
rate. The hardware port has inverted voltage levels of ‑6 V (logical high)
and +6 V (logical low).
Write_Data Specifies the value to be send.
The Write_Data signal is transferred at each clock cycle with Write_Enable
set to 1.
Data type: UFix_9_0
Data width: 1
Range: 0 … 511
Range exceeding is possible. Then, only the lowest bits 5 … 9 will be used.
Because of the unsigned data type, negative values will be interpreted as
positive values and the saturation will always be towards the maximum
value.
RTS Specifies the Ready‑To‑Send (RTS) signal.
The RTS/CTS handshake is handled by the user, the RTS signal is just passed
through and adapted to the physical layer.
Data type: UFix_1_0
Data width: 1
The hardware port is synchronously running to the UART clock defined by
the UART baud rate. The hardware port has voltage levels of +6 V (active,
logical high) and ‑6 V (inactive).
Sim_RX Simulates an RX value in the RX FIFO buffer.
Available only if Enable simulation RX port is set on the Parameters page.
Data type: Double
Data width: 1
The signal has to be in logical format with 1 as high and 0 as low, and
not in the inverted values of the physical layer (‑12 V high, +12 V low).
The format of this serial bitstream has to correspond to the specified UART
communication settings.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.
Sim_CTS Simulates the Clear‑To‑Send (CTS) hardware signal.
Available only if Enable simulation CTS port is set on the Parameters page.
The RTS/CTS handshake is handled by the user. The Sim_CTS signal is just
passed through to CTS.
Data type: Double
Data width: 1

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Port Description
Range:
§ 0: CTS inactive
§ 1: CTS active
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.
Output
Read_Data_Count Outputs the number of new entries in the RX FIFO buffer.
Two clock cycles are required to return the number of entries.
If you only want to check whether a value is available in the RX FIFO buffer,
use the Read_Fifo_Empty signal instead of this.
Data type: UFix_11_0
Data width: 1
Range: 0 … 2047
The range can be exceeded, and saturation is performed to a minimum or
maximum value.
Read_Data Outputs the last read data from the RX FIFO buffer.
The read_data is available after three clock cycles after the Read_Enable
signal. The return value is 0, if the data is read before anything has been
received by the RX hardware input.
Data type: UFix_9_0
Data width: 1
Range: 0 … 511
It is not possible to exceed the range.
The hardware input receives serial data for the UART RX FIFO buffer using
inverted voltage levels of ‑6 V (logical high) and +6 V (logical low).
Read_Fifo_Empty Outputs the status of the RX FIFO buffer.
If the status of the buffer is not empty, then you can start reading the data
using the Read_Enable signal.
The Read_Fifo_Empty signal switches one clock cycle after the FIFO value
has been read.
Do not use the Read_Data_Count signal to check the status of the buffer
(Read_Data_Count>0), because this requires one additional clock cycle
before its value is valid.
Data type: UFix_1_0
Data width: 1
Range:
§ 0: The RX FIFO buffer is not empty.
§ 1: The RX FIFO buffer is empty.
It is not possible to exceed the range.
CTS Outputs the state of the Clear‑To‑Send (CTS) hardware port.
RTS/CTS handshake is handled by the user. CTS is just passed through with
conversion to logical 1 and 0.
Data type: UFix_1_0
Data width: 1

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Port Description
Range:
§ 0: CTS inactive
§ 1: CTS active
The CTS hardware port is synchronously running to the UART clock defined
by the UART baud rate. The hardware port has voltage levels of +6 V (active,
logical high) and ‑6 V (inactive).
It is not possible to exceed the range.
Write_Data_Count Outputs the number of values in the TX FIFO buffer.
The values in the TX FIFO buffer has not been sent already.
Do not use the Write_Data_Count signal to check the status of the buffer
(Write_Data_Count<2047), because this requires two clock cycles before its
value is valid, instead of one clock cycle when using the Write_Fifo_Full
signal.
Data type: UFix_11_0
Data width: 1
Range: 0 … 2047
It is not possible to exceed the range.
Write_Fifo_Full Outputs the status of the TX FIFO buffer.
You can use the signal to check the TX FIFO buffer before you start writing
data to the buffer. The Write_Fifo_Full signal switches one clock cycle after
the Write_Enable signal has been set.
Data type: UFix_1_0
Data width: 1
Range:
§ 0: The TX FIFO buffer is not full.
§ 1: The TX FIFO buffer is full.
It is not possible to exceed the range.
Sim_TX Simulates the TX hardware signal.
Available only if Enable simulation TX port is set on the Parameters page.
The signal is in logical format and not in inverted values from the physical
layer (‑6 V high, +6 V low). The format of the serial bitstream corresponds to
the specified UART communication settings.
Data type: Double
Data width: 1
Range:
§ 0: Low
§ 1: High
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.
Sim_RTS Simulates the Ready‑To‑Send (RTS) hardware signal.
Available only if Enable simulation RTS port is set on the Parameters page.
The signal is in logical format and only passed through to the RTS signal.
Data type: Double
Data width: 1

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Port Description
Range:
§ 0: RTS inactive
§ 1: RTS active
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.

I/O mapping The signals are available at the RS232 (422/485) connector.
MicroLabBox has static mapping between I/O signals and I/O pins. The signal
name is also printed on the housing of MicroLabBox. You have to consider only
the connector panel type.
For a detailed connector pinout, refer to:
§ RS232 (422/485) Connector (Sub-D) (MicroLabBox Hardware Installation and
Configuration )
For detailed information on the channel characteristics, refer to:
§ Communication Interfaces (MicroLabBox Hardware Installation and
Configuration )

UART (RS232) settings The Parameters page provides the following dialog settings.

Baud rate Lets you select the baud rate in the range 50 … 1,000,000 baud
(bits per second) from the given list.

Word length Lets you select the word length in the range 5 … 9 bits. The
word length includes the number of data bits and the optional parity bit.
For example, if a message consists of 8 data bits and the parity bit, you have to
set the word length to 9.

Note

The parity bit cannot be controlled via dialog setting. You have to consider
an optional parity bit in your own model implementation.

The Write_Data and Read_Data ports handle raw bits. If you want to use
a parity bit with the Write_Data port, you have to explicitly generate it and
provide it as the last bit of the port. If you want to use a parity bit with the
Read_Data port, you have to explicitly check it and read it as the last bit of the
port.

Stop bits Lets you select the number of stop bits in the range 1, 1.5 and 2.

Enable simulation RX port Lets you enable an inport for offline simulation
data. The Sim_RX inport is added to the block to connect it to simulation data
coming from a Simulink-based I/O environment model.

Enable simulation CTS port Lets you enable an inport for offline simulation
data. The Sim_CTS inport is added to the block to connect it to simulation data
coming from a Simulink-based I/O environment model.

Enable simulation TX port Lets you enable an outport for offline simulation
data. The Sim_TX outport is added to the block to connect it to a Simulink-based
I/O environment model.

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Enable simulation RTS port Lets you enable an outport for offline
simulation data. The Sim_RTS outport is added to the block to connect it to
a Simulink-based I/O environment model.

UART (RS422/485) description Block display If you select an UART (RS422/485) channel from the channel
list, the block display changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Read_Enable Specifies to start receiving a value.
After three clock cycles, the value is available and can be read from the RX
FIFO buffer. The value remains valid until the next Read_Enable signal.
Before you read data from the RX FIFO buffer, you should check the
Read_Fifo_Empty signal not to be set. The Read_Fifo_Empty signal
switches one clock cycle after the RX FIFO value has been read.
Do not use the Read_Data_Count signal (Read_Data_Count < 0) to check
the RX FIFO buffer, because it requires one additional clock cycle to get the
count value.
You can read one value per clock cycle from the UART.
Data Type: UFix_1_0
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.
Write_Enable Specifies to start sending a value.
The Write_Data value is written to the TX FIFO buffer, from which it is
automatically send to the TX output pin of the I/O connector using the
specified UART communication settings.
Write_Enable must be set to 1 for only one clock cycle.
Before you write data to the TX FIFO buffer, you should check the
Write_Fifo_Full signal not to be set. The Write_Fifo_Full signal switches
one clock cycle after the Write_Enable signal has been set.
Do not use the Write_Data_Count signal (Write_Data_Count < 2047) to
check the TX FIFO buffer, because it requires one additional clock cycle to get
the count value.
Data type: UFix_1_0
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.

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Port Description
The hardware output port is driven with the values from the TX FIFO buffer. It
is synchronously running to the UART clock defined by the UART baud rate.
The hardware port has inverted voltage levels of ‑6 V (logical high) and +6 V
(logical low).
Write_Data Specifies the value to be send.
The Write_Data signal is transferred at each clock cycle with Write_Enable
set to 1.
Data type: UFix_9_0
Data width: 1
Range: 0 … 511
Range exceeding is possible. Then, only the lowest bits 5 … 9 will be used.
Because of the unsigned data type, negative values will be interpreted as
positive values and the saturation will always be towards the maximum
value.
Driver_Enable Specifies to enable the output driver in the transceiver for data transmission.
If you use the UART (RS485/422) function in half-duplex mode, the output
driver must be disabled while receiving data.
Data type: UFix_1_0
Data width: 1
Sim_RX Simulates an RX value in the RX FIFO buffer.
Available only if Enable simulation RX port is set on the Parameters page.
Data type: Double
Data width: 1
The signal has to be in logical format with 1 as high and 0 as low, and
not in the inverted values of the physical layer (‑12 V high, +12 V low).
The format of this serial bitstream has to correspond to the specified UART
communication settings.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.
Output
Read_Data_Count Outputs the number of new entries in the RX FIFO buffer.
Two clock cycles are required to return the number of entries.
If you only want to check whether a value is available in the RX FIFO buffer,
use the Read_Fifo_Empty signal instead of this.
Data type: UFix_11_0
Data width: 1
Range: 0 … 2047
The range can be exceeded, and saturation is performed to a minimum or
maximum value.
Read_Data Outputs the last read data from the RX FIFO buffer.
The read_data is available after three clock cycles after the Read_Enable
signal. The return value is 0, if the data is read before anything has been
received by the RX hardware input.
Data type: UFix_9_0
Data width: 1
Range: 0 … 511
It is not possible to exceed the range.

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Port Description
The hardware input receives serial data for the UART RX FIFO buffer using
inverted voltage levels of ‑6 V (logical high) and +6 V (logical low).
Read_Fifo_Empty Outputs the status of the RX FIFO buffer.
If the status of the buffer is not empty, then you can start reading the data
using the Read_Enable signal.
The Read_Fifo_Empty signal switches one clock cycle after the FIFO value
has been read.
Do not use the Read_Data_Count signal to check the status of the
buffer (Read_Data_Count>0), because this requires one additional clock cycle
before its value is valid.
Data type: UFix_1_0
Data width: 1
Range:
§ 0: The RX FIFO buffer is not empty.
§ 1: The RX FIFO buffer is empty.
It is not possible to exceed the range.
Write_Data_Count Outputs the number of values in the TX FIFO buffer.
The values in the TX FIFO buffer has not been sent already.
Do not use the Write_Data_Count signal to check the status of the buffer
(Write_Data_Count<2047), because this requires two clock cycles before its
value is valid, instead of one clock cycle when using the Write_Fifo_Full
signal.
Data type: UFix_11_0
Data width: 1
Range: 0 … 2047
It is not possible to exceed the range.
Write_Fifo_Full Outputs the status of the TX FIFO buffer.
You can use the signal to check the RX FIFO buffer before you start writing
data to the buffer. The Write_Fifo_Full signal switches one clock cycle after
the Write_Enable signal has been set.
Data type: UFix_1_0
Data width: 1
Range:
§ 0: The TX FIFO buffer is not full.
§ 1: The TX FIFO buffer is full.
It is not possible to exceed the range.
Sim_TX Simulates the TX hardware signal.
Available only if Enable simulation TX port is set on the Parameters page.
The signal is in logical format and not in inverted values from the physical
layer (‑6 V high, +6 V low). The format of the serial bitstream corresponds to
the specified UART communication settings.
Data type: Double
Data width: 1
Range:
§ 0: Low
§ 1: High

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Port Description
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.

I/O mapping The signals are available at the RS232 (422/485) connector.
MicroLabBox has static mapping between I/O signals and I/O pins. The signal
name is also printed on the housing of MicroLabBox. You have to consider only
the connector panel type.
For a detailed connector pinout, refer to:
§ RS232 (422/485) Connector (Sub-D) (MicroLabBox Hardware Installation and
Configuration )
For detailed information on the channel characteristics, refer to:
§ Communication Interfaces (MicroLabBox Hardware Installation and
Configuration )

UART (RS422/485) settings The Parameters page provides the following dialog settings.

Baud rate Lets you select the baud rate in the range 50 … 10,000,000 baud
(bits per second) from the given list.

Word length Lets you select the word length in the range 5 … 9 bits. The
word length includes the number of data bits and the optional parity bit.
For example, if a message consists of 8 data bits and the parity bit, you have to
set the word length to 9.

Note

The parity bit cannot be controlled via dialog setting. You have to consider
an optional parity bit in your own model implementation.

The Write_Data and Read_Data ports handle raw bits. If you want to use
a parity bit with the Write_Data port, you have to explicitly generate it and
provide it as the last bit of the port. If you want to use a parity bit with the
Read_Data port, you have to explicitly check it and read it as the last bit of the
port.

Stop bits Lets you select the number of stop bits in the range 1, 1.5 and 2.

Mode Lets you select the mode for receiving messages.

§ Full duplex mode
You can simultaneously send and receive signals on the UART channel.
§ Half duplex mode
You can send or receive signals on the UART channel, but you cannot do both
at the same time.

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Termination Lets you enable an internal termination between RX‑ and RX+
and between TX‑ and TX+.

Setting Meaning
Open No termination
Terminated The RX and TX signals are terminated via an
internal 120 Ω resistor.

Enable simulation RX port Lets you enable an inport for offline simulation
data. The Sim_RX inport is added to the block to connect it to simulation data
coming from a Simulink-based I/O environment model.

Enable simulation TX port Lets you enable an outport for offline simulation
data. The Sim_TX outport is added to the block to connect it to a Simulink-based
I/O environment model.

Related topics References

Description Page (FPGA_IO_WRITE_BL)................................................................................... 121

FPGA_IO_WRITE_BL.................................................................................................................. 58
FPGA_IO_WRITE_BL (DS1202 FPGA I/O Type 1 Settings).......................................................... 100
Scaling Page (FPGA_IO_WRITE_BL)......................................................................................... 117

Scaling Page (FPGA_IO_WRITE_BL)

Purpose To specify the inverting, scaling, and saturation settings for the selected I/O
function.

Description You can modify the I/O signal of the selected I/O function if you select the
Enable FPGA test access and scaling parameter on the FPGA Access page
of the FPGA_SETUP_BL block dialog. The possible modifications depend on the
selected I/O function.

Common settings The following settings on the Scaling page are common to the I/O functions that
you can select on the Unit page.

Enable FPGA test access and scaling for this block Lets you disable FPGA
test access and scaling for the selected I/O function.

Digital InOut settings The following settings on the Scaling page are specific to the Digital InOut I/O
function.

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Invert input polarity Lets you invert the measured values of the electrical
input signal:
§ Disabled:
The Data port outputs the signals as measured: A high-level voltage results in
a 1 and vice versa.
§ Enabled:
The output of the Data port is inverted: A low-level voltage results in a 0 and
vice versa.

Invert output polarity Lets you adapt the electrical output signal:
§ Disabled:
If driven with 1, the I/O function outputs the high-level voltage as selected
with the High supply parameter on the Parameters page.
If driven with 0, the I/O function outputs the low-level voltage.
§ Enabled:
If driven with 1, the I/O function outputs the low-level voltage (0 V).
If driven with 0, the I/O function outputs the high-level voltage.

DAC settings The following settings on the Scaling page are specific to the DAC I/O function.

Note

Scaling of analog I/O signals also effects the signal path:

§ If you use the parameters of the Scaling page to scale analog signals, the
data type of the Data port is set to the specified data format for scaling.
For more information, refer to How to Change the Data Type of Analog
Signals (FPGA Programming Blockset Guide ).
§ FPGA scaling of analog I/O signals might cause additional latency. If
the latency can be calculated during the modeling, analog I/O functions
display the total latency.

Scaling format Lets you select the data format for scaling and saturation.
§ Signed/Unsigned:
The values of the parameters for scaling and saturation are in fixed‑point
format. The signed fixed-point format reserves one bit for the sign.
You can specify the number of bits and the binary point position with the
Number of bits and Binary point (fraction width) parameters.
§ Single:
The values of the parameters for scaling and saturation are 32-bit values in
the single-precision floating‑point format with a fraction width of 24, which
complies with the IEEE 754 standard (single).

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§ Double:
The values of the parameters for scaling and saturation are 64-bit values in
the double-precision floating‑point format with a fraction width of 53, which
complies with the IEEE 754 standard (double).

Number of bits This setting depends on the Scaling format setting.

§ Fixed-point format:
Lets you specify the bit width of the scaling parameters and the Data port in
the range 1 ... 64.
§ Floating-point format:
Displays the bit width of the scaling parameters and the Data port.

Binary point (fraction width) This setting depends on the Scaling format
setting.
§ Fixed-point format:
Lets you specify the binary point position of the scaling parameters and the
Data port. The position 0 represents the lowest bit position
§ Floating-point format:
Displays the fraction width of the scaling parameters and the Data port.

Scaling factor Lets you specify the scaling factor. The scaling factor gains
the signal of the Data port or the replace value (FPGA test access) before it is
saturated.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Scaling factor parameter
will be saturated to the minimum and maximum values that the scaling format
and the hardware supports.

Scaling offset Lets you add a signal offset after the signal of the Data port is
scaled with the scaling factor.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Scaling offset parameter
will be saturated to the minimum and maximum values that the scaling format
and the hardware supports.

Saturation minimum value Lets you specify the minimum value to which
the scaled Data inport signal is saturated before it is output via an analog output
channel.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation minimum
value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

Saturation maximum value Lets you specify the maximum value to which
the scaled Data inport signal is saturated before it is output via an analog output
channel.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation maximum
value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

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Multiplier latency Lets you specify the latency that is caused by the
multiplier for scaling. The multiplier is used to multiply the signal with the value
of the Scaling factor parameter.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The multiplication will be implemented without latency.
§ 1 ... 20: The multiplication will be implemented with the specified latency.
Use this value range in the exceptional case that the optimized latency cause
timing problems during the build process.

Adder latency Lets you specify the latency that is caused by the offset adder.
The offset adder is used to add the value of the Scaling offset parameter to the
signal.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The adding will be implemented without latency.
§ 1 ... 20: The adding will be implemented with the specified latency.
Use this value range in the exceptional case that the optimized latency causes
timing problems during the build process.

UART settings The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

LED Out settings The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

Buzzer settings The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

Related topics Basics

Basics on FPGA Test Access and Scaling (FPGA Programming Blockset Guide )

References

Description Page (FPGA_IO_WRITE_BL)................................................................................... 121

FPGA_IO_WRITE_BL.................................................................................................................. 58
FPGA_IO_WRITE_BL (DS1202 FPGA I/O Type 1 Settings).......................................................... 100

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Description Page (FPGA_IO_WRITE_BL)

Purpose To provide detailed information about the selected I/O function.

Description The Description page provides detailed information about the access type that
you selected on the corresponding Unit page. The information is either in the
text field itself or in an external help document that you can open by clicking the
function-specific Help button on this page.

The description of the access type that is provided by the standard DS1202 FPGA
I/O Type 1 frameworks is included in this user documentation. The description of
the access type of customized frameworks or mounted piggybacks is available as
a separate document.

Related topics References

FPGA_IO_WRITE_BL.................................................................................................................. 58
FPGA_IO_WRITE_BL (DS1202 FPGA I/O Type 1 Settings).......................................................... 100
Parameters Page (FPGA_IO_WRITE_BL)................................................................................... 100
Scaling Page (FPGA_IO_WRITE_BL)......................................................................................... 117

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FPGA_INT_BL (DS1202 FPGA I/O Type 1 Settings)

Purpose To configure the FPGA interrupt channel when using one of the following
frameworks:
§ DS1202 FPGA I/O Type 1
§ DS1202 FPGA I/O Type 1 (Flexible I/O)

Where to go from here Information in this section

Parameters Page (FPGA_INT_BL)............................................................ 122

To enable the simulation port for an interrupt.

Description Page (FPGA_INT_BL)............................................................ 123

To provide detailed information about the selected I/O function.

Information in other sections

Common settings
Unit Page (FPGA_INT_BL)......................................................................... 64
To specify the interrupt channel used to trigger a task in the processor
model.

Other interface blocks

PROC_INT_BL (FPGA Programming Blockset - Processor Interface
Reference )
To receive an interrupt from the FPGA model to trigger an asynchronous
task in the processor model.

Parameters Page (FPGA_INT_BL)

Purpose To enable the simulation port for an interrupt.

Description The DS1202 FPGA I/O Type 1 frameworks provide 32 interrupt lines.

An interrupt is requested if the Int port is set to 1 for at least one clock cycle. If
you set the Int port to 0, the last interrupt is not released but saved. An interrupt
is edge-triggered.

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Int description Block display The figure below shows the block display with the optional
simulation port.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Int Provides the interrupt request line.
Data type: UFix_1_0
0 to 1: Interrupt is requested (edge-triggered).
0: No interrupt is requested. Last requested interrupt is saved.
Output
Sim_Int Simulates an interrupt by performing a function call to enable a function-call
subsystem.
Available only if Enable simulation port is set on the Parameters page.
Data type: Function call

Int settings Enable simulation port Lets you enable an outport for a simulated interrupt.
The Sim_Int outport is added to the block to connect it to a function-call
subsystem in the processor model.

Related topics References

Description Page (FPGA_INT_BL)............................................................................................. 123

FPGA_INT_BL............................................................................................................................ 62
FPGA_INT_BL (DS1202 FPGA I/O Type 1 Settings).................................................................... 122

Description Page (FPGA_INT_BL)

Purpose To provide detailed information about the selected I/O function.

Description The Description page provides detailed information about the access type that
you selected on the corresponding Unit page. The information is either in the
text field itself or in an external help document that you can open by clicking the
function-specific Help button on this page.

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The description of the access type that is provided by the standard DS1202 FPGA
I/O Type 1 frameworks is included in this user documentation. The description of
the access type of customized frameworks or mounted piggybacks is available as
a separate document.

Related topics References

FPGA_INT_BL............................................................................................................................ 62
FPGA_INT_BL (DS1202 FPGA I/O Type 1 Settings).................................................................... 122
Parameters Page (FPGA_INT_BL)............................................................................................. 122

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Block Settings for the MicroLabBox II Framework

Introduction The block dialogs provide hardware-specific settings after you load the DS1303
(KU15P) Multi-I/O Board framework.

Where to go from here Information in this section

FPGA_XDATA_READ_BL (MicroLabBox II)............................................... 126

To configure read access to data provided by a processor application
when using the DS1303 (KU15P) Multi-I/O Board framework.

FPGA_XDATA_WRITE_BL (MicroLabBox II).............................................. 135

To configure write access to data provided by a processor application
when using the DS1303 (KU15P) Multi-I/O Board framework.

FPGA_IO_READ_BL (MicroLabBox II)...................................................... 147

To configure read access to I/O signals when using the DS1303 (KU15P)
Multi-I/O Board framework.

FPGA_IO_WRITE_BL (MicroLabBox II)..................................................... 169

To configure write access to I/O signals when using the DS1303 (KU15P)
Multi-I/O Board framework.

FPGA_INT_BL (MicroLabBox II)............................................................... 192

To configure the FPGA interrupt channel when using the DS1303
(KU15P) Multi-I/O Board framework.

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FPGA_XDATA_READ_BL (MicroLabBox II)

Purpose To configure read access to data provided by a processor application when using
the DS1303 (KU15P) Multi-I/O Board framework.

Where to go from here Information in this section

Parameters Page (FPGA_XDATA_READ_BL)............................................ 126

To specify the data format and specific settings for the selected access
type.

Information in other sections

Common settings
Block Description (FPGA_XDATA_READ_BL)............................................. 45
To specify read access by the FPGA model to the processor model via
processor bus.

Unit Page (FPGA_XDATA_READ_BL)......................................................... 46

To specify the general configuration for the FPGA board's processor bus
read access.

Parameters Page (FPGA_XDATA_READ_BL)

Purpose To specify the data format and specific settings for the selected access type.

Description The processor application can provide data to the FPGA application via the
I/O carrier network (IOCNET). IOCNET is a dSPACE-specific high-speed serial
communication bus that connects the boards in the MicroLabBox II.

The DS1303 (KU15P) Multi-I/O Board framework provides the following access
types that you can select on the Unit page of the block's dialog:
§ Register/Register64
If you select Register or Register64 as the access type, the data is read from
an IOCNET register. 256 registers are available with a data width of 32 bits
each and 256 registers with a data width of 64 bits each. The values are
transmitted element by element.
If you want to access data from several registers simultaneously, you can group
these registers by specifying the same group identifier for them.
Ungrouped registers are automatically combined into one register group with
group ID Ungrouped to optimize data transfer. Since register groups can be

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only accessed by one task, you have to explicitly group registers which are
used by different tasks.
§ Buffer/Buffer64
If you select Buffer or Buffer64 as the access type, the data is read from
an IOCNET buffer. 32 buffers are available that provides elements with a data
width of 32 bits each and 32 buffers that provides elements with a data
width of 64 bits each. Each buffer has a variable buffer size of 1 up to 32768
elements.
§ Bus
If you select Bus as the access type, the data is read from an IOCNET buffer.
The bus access type lets you use Simulink buses to model the data exchange
between the processor and the FPGA.

For more information, refer to Details on the access types on page 46.

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_XDATA_READ_BL block.

Binary point position (or fraction width) This setting depends on the
format selected in the Format setting.
§ signed/unsigned
The values of the Data outport are in fixed‑point format.
You can specify the binary point position of the 32‑bit value in the range
0 … 32 and the binary point position of the 64‑bit value in the range 0 … 64.
0 represents the lowest bit position, 32 or 64 the highest bit position.
§ floating‑point
The values of the Data outport are in floating‑point format. The fraction width
is displayed.

Format Lets you select the data format of the Data outport.
§ signed/unsigned
The values of the Data outport are in fixed‑point format with or without one
bit reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
64-bit fixed-point data types are converted to double, except the data
type without a binary point (binary point position = 0). Therefore, the fixed-
point resolution of fixed-point data types with a binary point (binary point
position > 0) is restricted to 53 bits.
§ floating‑point
The values of the Data outport are in floating‑point format.
The 32‑bit data value supports the single-precision floating‑point format with a
fraction width of 24, which complies with the IEEE 754 standard (single).
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is displayed in the Binary point position (or fraction
width) setting.

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Enable simulation port Lets you enable an inport for offline simulation data.
The Sim_Data inport is added to the block to connect it to any Simulink signal
used for simulation.

Simulation ports sample time Lets you specify the sample time of the
ports used for simulation, for example, Sim_Data. By default, the sample time
is inherited. You must only specify the sample time explicitly, if the modeling
situation inhibits to inherit the sample time, for example, if the corresponding
PROC block is part of an asynchronous task or is used for multiple access to the
same channel.

Buffer In description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Sim_Data Simulates a data exchange including floating-point to fixed-point data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768
Address Specifies an element in the buffer you want to read. The block requires 3 clock
cycles to update the value of the Data outport according to the specified address.
The maximum port range depends on the specified buffer size in the Parameters
page. The valid port range depends on the number of elements currently in the
buffer (see Data Count outport). If you request data from an address that is greater
than the Data Count value, the output of the Data outport is undefined. The first
element of a buffer is addressed by 0.
Data type: UFix_16_0
Output
Data Outputs a 32-bit data value to be read from an IOCNET buffer. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24

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Port Description
Data New Outputs a flag that indicates the changes of the buffer status. If the flag changes
from 0 to 1 and then to 0 again, the requested buffer contains new values and is
ready to be read. The flag is set to 1 only within one clock cycle.
Data type: UFix_1_0
Data Count Outputs the number of elements in the current buffer.
The maximum range depends on the specified buffer size. You can use the value to
define the valid range for the Address inport of 0 … (Data Count -1).
Data type: UFix_16_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Buffer In settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 127.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.
The maximum range of the Address inport depends on the buffer size.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 32-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Buffer64 In description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Sim_Data Simulates a data exchange including floating-point to fixed-point data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768
Address Specifies an element in the buffer you want to read. The block requires 3 clock
cycles to update the value of the Data outport according to the specified address.
The maximum port range depends on the specified buffer size in the Parameters
page. The valid port range depends on the number of elements currently in the
buffer (see Data Count outport). If you request data from an address that is greater
than the Data Count value, the output of the Data outport is undefined. The first
element of a buffer is addressed by 0.
Data type: UFix_16_0
Output
Data Outputs a 64-bit data value to be read from an IOCNET buffer. The data format
depends on the related dialog settings.
Data type if the bus transfer mode is disabled on the Parameters page:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double, except the data type
without a binary point (binary point position = 0). Therefore, the fixed-point
resolution of fixed-point data types with a binary point (binary point position > 0)
is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Data New Outputs a flag that indicates the changes of the buffer status. If the flag changes
from 0 to 1 and then to 0 again, the requested buffer contains new values and is
ready to be read. The flag is set to 1 only within one clock cycle.
Data type: UFix_1_0
Data Count Outputs the number of elements in the current buffer.
The maximum range depends on the specified buffer size. You can use the value to
define the valid range for the Address inport of 0 … (Data Count -1).
Data type: UFix_16_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

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Buffer64 In settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 127.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.
The maximum range of the Address inport depends on the buffer size.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Bus In description Block display If you specify the access type, the block display changes. The
simulation port is optionally displayed.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Sim_Data Simulates a bus data exchange including floating-point to fixed-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768
Output
Data Outputs the signals of the Simulink bus. The data types of the signals depend
on the bus topology that is copied via Copy bus topology from corresponding
processor block or Copy bus topology from gcb on the Parameters page. The
maximum bit wide is 64 bits.
The resolution of the data types is restricted to 53 bits, because the data type of the
received bus signals from the processor application is double and the block converts
the signals to the signal data types.
Data New Outputs a flag that indicates the changes of the buffer status. If the flag changes
from 0 to 1 and then to 0 again, the requested buffer contains new values and is
ready to be read. The flag is set to 1 only within one clock cycle.
Data type: UFix_1_0

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Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Bus In settings The following dialog settings are specific for the Bus access type. For common
dialog settings, refer to Common settings on page 127.

Buffer size Displays the size of the buffer in the range 1 … 32,768. The
buffer size depends on the number of bus signals.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1,024
words. For example, a buffer with a buffer size of 1 allocates a memory
block of 1,024 words with a data width of 64-bit in the FPGA memory. This
applies to any buffer and the related swinging buffer.

Edit bus topology Opens a dialog to display and configure the

bus signals. For more information, refer to Bus Editor Dialog -
FPGA_XDATA_READ_BL/FPGA_XDATA_WRITE_BL on page 66.

Copy bus topology from corresponding processor block Lets you copy an
existing bus topology from the corresponding processor block in the processor
model. For more information, refer to How to Use Simulink Buses of the
Processor Model to Model the Processor Communication (FPGA Programming
Blockset Guide ).

Copy bus topology from gcb Lets you copy an existing FPGA bus topology
from the selected Simulink Bus Creator block, subsystem inport block, or
subsystem outport block to the Data port of the Bus In block.
You cannot copy a bus topology from the processor model, because these
topologies do not include the FPGA data types. For instructions, refer to How
to Use Simulink Buses of the FPGA Model to Model Processor Communication
(FPGA Programming Blockset Guide ).

Reset bus topology Lets you clear the bus topology of the Data port.

Register In description Block display If you specify the register access type, the block display
changes. The simulation ports are optionally displayed.

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I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Sim_Data Simulates a data exchange including floating-point to fixed-point data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Output
Data Outputs a 32-bit data value to be read from an IOCNET register. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Data New Outputs a flag that indicates the changes of the register status. If the flag changes
from 0 to 1 and then to 0 again, the requested register contains a new value. The
flag is set to 1 only within one clock cycle.
Data type: UFix_1_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register In settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 127.

Register group ID Lets you specify a number in the range 1 … 63 to

create register groups. Registers which you specified with the same group ID are
read from the IOCNET sequentially and then provided to the FPGA application
simultaneously.
Specify 0 for ungrouped read access.

Register64 In description Block display If you specify the register access type, the block display
changes. The simulation ports are optionally displayed.

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I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Sim_Data Simulates a data exchange including floating-point to fixed-point data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Output
Data Outputs a 64-bit data value to be read from an IOCNET register. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double, except the data type
without a binary point (binary point position = 0). Therefore, the fixed-point
resolution of fixed-point data types with a binary point (binary point position > 0)
is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Data New Outputs a flag that indicates the changes of the register status. If the flag changes
from 0 to 1 and then to 0 again, the requested register contains a new value. The
flag is set to 1 only within one clock cycle.
Data type: UFix_1_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register64 In settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 127.

Register group ID Lets you specify a number in the range 1 … 63 to

create register groups. All registers – 32‑bit and 64‑bit registers – which you
specified with the same group ID are read from the IOCNET sequentially and
then provided to the FPGA application simultaneously.
Specify 0 for ungrouped read access.

Related topics References

Block Settings for the MicroLabBox II Framework.................................................................... 125

FPGA_XDATA_READ_BL........................................................................................................... 44

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FPGA_XDATA_WRITE_BL (MicroLabBox II)

Purpose To configure write access to data provided by a processor application when using
the DS1303 (KU15P) Multi-I/O Board framework.

Where to go from here Information in this section

Parameters Page (FPGA_XDATA_WRITE_BL)........................................... 135

To specify the data format and specific settings for the selected access
type.

Information in other sections

Common settings
Block Description (FPGA_XDATA_WRITE_BL)............................................ 50
To specify write access by the FPGA model to the processor model via
processor bus.

Unit Page (FPGA_XDATA_WRITE_BL)............................................. .......... 51

To specify the general configuration for the FPGA board's processor bus
write access.

Parameters Page (FPGA_XDATA_WRITE_BL)

Purpose To specify the data format and specific settings for the selected access type.

Description The processor application can read data provided by the FPGA application via
the I/O carrier network (IOCNET). IOCNET is a dSPACE-specific high-speed serial
communication bus that connects the boards in the MicroLabBox II.

The DS1303 (KU15P) Multi-I/O Board framework provides the following access
types that you can select in the Unit page of the block's dialog:
§ Register/Register64
If you select Register or Register64 as the access type, the data is written
to an IOCNET register. 256 registers are available with a data width of 32
bits each and 256 registers with a data width of 64 bits each. The values
are transmitted element by element. If you want to access data from several
registers simultaneously, you can group these registers by specifying the same
group identifier for them.
§ Buffer/Buffer64
If you select Buffer or Buffer64 as the access type, the data is written to
an IOCNET buffer. 32 buffers are available that provides elements with a data

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width of 32 bits each and 32 buffers that provides elements with a data
width of 64 bits each. Each buffer has a variable buffer size of 1 up to 32768
elements.
§ Bus
If you select Bus as the access type, the data is written to an IOCNET buffer.
The bus access type lets you use Simulink buses to model the data exchange
between the processor and the FPGA.

There are settings that are common and settings that are specific to each access
type.

For more information, refer to Details on the access types on page 51.

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_XDATA_WRITE_BL block.

Binary point position (or fraction width) This setting depends on the
format selected in the Format setting.
§ signed/unsigned
The values of the Data inport are in fixed‑point format.
You can specify the binary point position of the 32‑bit value in the range
0 … 32 and the binary point position of the 64‑bit value in the range 0 … 64.
0 represents the lowest bit position, 32 or 64 the highest bit position.
§ floating‑point
The values of the Data inport are in floating‑point format. The fraction width
is displayed.

Format Lets you select the data format of the Data inport.
§ signed/unsigned
The values of the Data inport are in fixed‑point format with or without one bit
reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
64-bit fixed-point data types are converted to double, except the data
type without a binary point (binary point position = 0). Therefore, the fixed-
point resolution of fixed-point data types with a binary point (binary point
position > 0) is restricted to 53 bits.
§ floating‑point
The values of the Data inport are in floating‑point format.
The 32‑bit data value supports the single-precision floating‑point format with a
fraction width of 24, which complies with the IEEE 754 standard (single).
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is displayed in the Binary point position (or fraction
width) setting.

Enable simulation data port Lets you enable an outport for offline
simulation data. The Sim_Data outport is added to the block to connect it to
any Simulink signal used for simulation.

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Simulation ports sample time Lets you specify the sample time of the ports
used for simulation, for example, Sim_Data and Sim_Status. By default, the
sample time is inherited. You must only specify the sample time explicitly, if
the modeling situation inhibits to inherit the sample time, for example, if the
corresponding PROC block is part of an asynchronous task or is used for multiple
access to the same channel.

Buffer Out description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a 32-bit data value to be written to an IOCNET buffer. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Enable Specifies the current valid Data port value.
Data type: UFix_1_0
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.
Ready Explicitly specifies the buffer state as ready to send immediately, even if the buffer
is not completely filled. The data values are written to a new buffer in the following
clock cycle. While the port value is 1, the buffer switches every clock cycle. You are
therefore recommended to set the value for only one clock cycle. If the buffer is
completely filled, it is automatically switched, and the data values are stored in a
new buffer.
Data type: UFix_1_0
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready to send, even if it is not completely filled. The
buffer is switched and the data values are accessible via IOCNET in the following
clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.
Send_Ack Triggers a data transmission to IOCNET. With Send_Ack and Read_Req you can
trigger a processor synchronous data exchange.

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Port Description
A data transmission is always requested at the beginning of a task, before the
processor model is computed. Each time a new data transmission is requested by
Read_Req, Send_Ack must explicitly acknowledge the Data values for transmission
within one task period. To send current data, you can delay the transmission. After a
new data transmission is requested, you write the current data values to the buffer.
Then you must acknowledge the new data for transmission.
Available only if Enable Read_Req and Send_Ack ports for explicit data
transmit is set on the Parameters page. If Enable Read_Req and Send_Ack
ports for explicit data transmit is not set, each data transmission request will
instantly be acknowledged.
Data type: UFix_1_0
§ 0: Data values are not acknowledged for transmission.
§ 1: Current Data values are acknowledged and will be transmitted via IOCNET.
A data transmission request that is not acknowledged by Send Ack leads to task
overrun in the processor application. A task overrun will be logged as an I/O error
in the Messages page of the MicroLabBox II. The FPGA buffer that caused the task
overrun will also be logged.
Output
Sim_Data Simulates an IOCNET data exchange including fixed-point to floating-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768. The vector width depends on the specified buffer size.
Overflow Outputs a flag that indicates that a buffer overflow occurred. An overflow occurs if
the old buffer is not read completely before a new buffer is ready to be read.
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.
Data type: UFix_1_0
Sim_Status Outputs information about the simulated data exchange on the Sim_Data outport.
Available only if the access type is specified as Buffer and Enable simulation port
is set on the Parameters page.
Data type: UInt32
Data width: 3
§ Sim_Status[0]: Contains the number of valid elements in the Sim_Data vector.
§ Sim_Status[1]: Indicates whether the current buffer contains new or old values. It
is 1 if the buffer contains new values.
§ Sim_Status[2]: Indicates whether a buffer overflow occurred. At least one buffer
was not read and its data was lost before the currently read buffer was filled.
Read_Req Outputs a flag that indicates that a data transmission is requested via IOCNET. With
Read_Req and Send_Ack you can trigger a processor synchronous data exchange.
A data transmission is always requested at the beginning of a task, before the
processor model is computed. Each time a new data transmission is requested by
Read_Req, Send_Ack must explicitly acknowledge the Data values for transmission
within one task period. To send current data, you can delay the transmission. After a
new data transmission is requested, you write the current data values to the buffer.
Then you must acknowledge the new data for transmission.

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Port Description
Available only if Enable Read_Req and Send_Ack ports for explicit data
transmit is set on the Parameters page. If Enable Read_Req and Send_Ack
ports for explicit data transmit is not set, each data transmission request will
instantly be acknowledged.
Data type: UFix_1_0
§ 0: No data transmission is requested.
§ 1: A data transmission is requested. This value is set for one clock cycle.
A data transmission request that is not acknowledged by Send Ack leads to task
overrun in the processor application. A task overrun will be logged as an I/O error
in the Messages page of the MicroLabBox II. The FPGA buffer that caused the task
overrun will also be logged.

Note

The range can be exceeded for the Data inport. The inport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Buffer Out settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 136.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 32-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation status port Lets you enable an outport to get status
information about the simulation data that is available when you have enabled
the simulation data port. The Sim_Status outport is added to the block.

Enable Read_Req and Send_Ack ports for explicit data transmit Lets you
add the Read_Req and Send_Ack ports to the block to trigger a processor
synchronous data exchange.

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Buffer64 Out description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a 64-bit data value to be written to an IOCNET buffer. The data format
depends on the related dialog settings.
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double, except the data type
without a binary point (binary point position = 0). Therefore, the fixed-point
resolution of fixed-point data types with a binary point (binary point position > 0)
is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Enable Specifies the current valid Data port value.
Data type: UFix_1_0
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.
Ready Explicitly specifies the buffer state as ready to send immediately, even if the buffer
is not completely filled. The data values are written to a new buffer in the following
clock cycle. While the port value is 1, the buffer switches every clock cycle. You are
therefore recommended to set the value for only one clock cycle. If the buffer is
completely filled, it is automatically switched, and the data values are stored in a
new buffer.
Data type: UFix_1_0
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready to send, even if it is not completely filled. The
buffer is switched and the data values are accessible via IOCNET in the following
clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.
Send_Ack Triggers a data transmission to IOCNET. With Send_Ack and Read_Req you can
trigger a processor synchronous data exchange.
A data transmission is always requested at the beginning of a task, before the
processor model is computed. Each time a new data transmission is requested by
Read_Req, Send_Ack must explicitly acknowledge the Data values for transmission
within one task period. To send current data, you can delay the transmission. After a

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Port Description
new data transmission is requested, you write the current data values to the buffer.
Then you must acknowledge the new data for transmission.
Available only if Enable Read_Req and Send_Ack ports for explicit data
transmit is set on the Parameters page. If Enable Read_Req and Send_Ack
ports for explicit data transmit is not set, each data transmission request will
instantly be acknowledged.
Data type: UFix_1_0
§ 0: Data values are not acknowledged for transmission.
§ 1: Current Data values are acknowledged and will be transmitted via IOCNET.
A data transmission request that is not acknowledged by Send Ack leads to task
overrun in the processor application. A task overrun will be logged as an I/O error
in the Messages page of the MicroLabBox II. The FPGA buffer that caused the task
overrun will also be logged.
Output
Sim_Data Simulates an IOCNET data exchange including fixed-point to floating-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768. The vector width depends on the specified buffer size or
the number of bus signals.
Overflow Outputs a flag that indicates that a buffer overflow occurred. An overflow occurs if
the old buffer is not read completely before a new buffer is ready to be read.
Available only if the bus transfer mode is disabled on the Parameters page.
Data type: UFix_1_0
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.
Sim_Status Outputs information about the simulated data exchange on the Sim_Data outport.
Available only if the access type is specified as Buffer and Enable simulation port
is set on the Parameters page.
Data type: UInt32
Data width: 3
§ Sim_Status[0]: Contains the number of valid elements in the Sim_Data vector.
§ Sim_Status[1]: Indicates whether the current buffer contains new or old values. It
is 1 if the buffer contains new values.
§ Sim_Status[2]: Indicates whether a buffer overflow occurred. At least one buffer
was not read and its data was lost before the currently read buffer was filled.
Read_Req Outputs a flag that indicates that a data transmission is requested via IOCNET. With
Read_Req and Send_Ack you can trigger a processor synchronous data exchange.
A data transmission is always requested at the beginning of a task, before the
processor model is computed. Each time a new data transmission is requested by
Read_Req, Send_Ack must explicitly acknowledge the Data values for transmission
within one task period. To send current data, you can delay the transmission. After a
new data transmission is requested, you write the current data values to the buffer.
Then you must acknowledge the new data for transmission.
Available only if Enable Read_Req and Send_Ack ports for explicit data
transmit is set on the Parameters page. If Enable Read_Req and Send_Ack

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Port Description
ports for explicit data transmit is not set, each data transmission request will
instantly be acknowledged.
Data type: UFix_1_0
§ 0: No data transmission is requested.
§ 1: A data transmission is requested. This value is set for one clock cycle.
A data transmission request that is not acknowledged by Send Ack leads to task
overrun in the processor application. A task overrun will be logged as an I/O error
in the Messages page of the MicroLabBox II. The FPGA buffer that caused the task
overrun will also be logged.

Buffer64 Out settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 136.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation status port Lets you enable an outport to get status
information about the simulation data that is available when you have enabled
the simulation data port. The Sim_Status outport is added to the block.

Enable Read_Req and Send_Ack ports for explicit data transmit Lets you
add the Read_Req and Send_Ack ports to the block to trigger a processor
synchronous data exchange.

Bus Out description Block display If you specify the buffer access type, the block display changes.
The Read_Req and Sim_Data ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a Simulink bus to be transmitted to the processor application.
The data types of the signals depend on the bus topology that is set via Copy bus
topology from corresponding processor block or Copy bus topology from gcb
on the Parameters page. The maximum bit width is 64 bits.
The resolution of the data type is restricted to 53 bits, because the block converts all
data values to double for transmission.
Output
Read_Req Outputs a flag that indicates that a data transmission is requested from the
processor application. A data transmission is always requested at the beginning of a
task, before the processor application is computed.
Data type: UFix_1_0
§ 0: No data transmission is requested.
§ 1: A data transmission is requested. This value is set for one clock cycle.
A data transmission request automatically triggers a data transmission.
Sim_Data Simulates a data transmission including fixed-point to floating-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Simulink bus

Bus Out settings The following dialog settings are specific for the Bus access type. For common
dialog settings, refer to Common settings on page 136.

Buffer size Displays the size of the buffer in the range 1 … 32,768. The
buffer size depends on the number of bus signals.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1,024
words. For example, a buffer with a buffer size of 1 allocates a memory
block of 1,024 words with a data width of 64 bits in the FPGA memory.
This applies to any buffer and the related swinging buffer.

Edit bus topology Opens a dialog to display and configure the

bus signals. For more information, refer to Bus Editor Dialog -
FPGA_XDATA_READ_BL/FPGA_XDATA_WRITE_BL on page 66.

Copy bus topology from corresponding processor block Lets you copy an
existing bus topology from the corresponding processor block in the processor
model. For more information, refer to How to Use Simulink Buses of the
Processor Model to Model the Processor Communication (FPGA Programming
Blockset Guide ).

Analyze bus topology of input Lets you set the Data inport to the bus
topology of the connected Simulink bus.

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If clicked, the FPGA Programming Blockset analyzes the connected Simulink

bus and sets the Data port to a matching bus topology. For instructions,
refer to How to Use Simulink Buses of the FPGA Model to Model Processor
Communication (FPGA Programming Blockset Guide ).

Reset bus topology Lets you clear the bus topology of the Data port.

Bus data transmission method Lets you select the method for transmitting
data to the processor application:
§ Synchronous to Read_Req method
Select this method to transmit data that is captured synchronously to the read
request.
The FPGA application writes data to the swinging buffer when the processor
application makes a read request. After the data is written to the buffer, the
buffer swings and sends the data to the processor application.
§ Free running method
Select this method if the transmission time is crucial.
The FPGA application continuously writes data to the swinging buffer. A read
request of the processor application immediately transmits the last complete
data set of the swinging buffer to the processor application.
For instructions, refer to How to Configure the Bus Data Transmission Method
(FPGA Programming Blockset Guide ).

Register Out description Block display If you specify the register access type, the block display
changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Data Specifies a 32-bit data value to be written to an IOCNET register. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Output

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Port Description
Sim_Data Simulates an IOCNET data exchange including fixed-point to floating-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1

Note

The range can be exceeded for the Data inport. The inport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register Out settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 136.

Register group ID Lets you specify a number in the range 1 … 63 to

create register groups. Registers which you specified with the same group ID are
sampled simultaneously in the FPGA application. The values form a consistent
data group that is written to the IOCNET.

Register64 Out description Block display If you specify the register access type, the block display
changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Data Specifies a 64-bit data value to be written to an IOCNET register. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double, except the data type
without a binary point (binary point position = 0). Therefore, the fixed-point
resolution of fixed-point data types with a binary point (binary point position > 0)
is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53

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Port Description
Output
Sim_Data Simulates an IOCNET data exchange including fixed-point to floating-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1

Note

The range can be exceeded for the Data inport. The inport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register64 Out settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 136.

Register group ID Lets you specify a number in the range 1 … 63 to create

register groups. All registers – 32‑bit and 64‑bit registers – which you specified
with the same group ID are sampled simultaneously in the FPGA application. The
values form a consistent data group that is written to the IOCNET.

Related topics References

Block Settings for the MicroLabBox II Framework.................................................................... 125

FPGA_XDATA_WRITE_BL.......................................................................................................... 49

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FPGA_IO_READ_BL (MicroLabBox II)

Purpose To configure read access to I/O signals when using the DS1303 (KU15P) Multi-I/O
Board framework.

Where to go from here Information in this section

Parameters Page (FPGA_IO_READ_BL)................................................... 147

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_READ_BL).......................................................... 165

To specify the inverting, scaling, and saturation settings for the selected
I/O function.

Information in other sections

Common settings
Block Description (FPGA_IO_READ_BL).................................................... 54
To implement read access to a physical input channel in the FPGA model.

Unit Page (FPGA_IO_READ_BL)................................................................ 55

To specify the I/O type and channel to be used for read access.

Parameters Page (FPGA_IO_READ_BL)

Purpose To specify relevant settings for the selected I/O function.

Description The frameworks provide different I/O types, which you can select on the Unit
page of the block:
§ Analog In 23
§ Analog In 24
§ Analog In 25
§ APU Slave
§ Aurora 64b66b In
§ Aurora 64b66b 128 Bit In
§ CN App Status
§ Digital In/Out 14 (In)
§ IOCNET Global time
§ MGT In
§ MGT In Opto Ready

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§ Status In
§ Watchdog

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_IO_READ_BLx block, except
for the Status In function.

Enable simulation port Lets you enable an inport for offline simulation data.
The Sim_Data inport is added to the block to connect it to simulation data
coming from a Simulink-based I/O environment model.

Analog In 23 description Block display If you select an Analog In 23 channel from the channel list, the
block display changes. The simulation port is displayed optionally.

I/O characteristics The following table shows the scaling between the analog
input voltage and the output of the Data port:

Input Voltage Range Data Port

‑10 V … +10 V ‑32,768 … +32,767

The following table describes the ports of the block for analog input channels:

Port Description
Input
Convert Triggers the sampling of the A/D converter. The port allows a precise definition of
the starting point of ADC sampling. The Data New port signals the end of the
conversion process.
Data type: UFix_1_0
Data width: 1
Values
§ 0: No conversion.
§ Set to 1 for at least one clock cycle: The ADC starts the conversion.
§ Permanently set to 1: The ADC samples continuously.
Sim Data In Simulates an input signal in the same range as that specified for the real input
signal.
Available only if Enable simulation port parameter is set on the Parameters page.
Data type: Double
Data width: 1
Input voltage range: ‑10 V … +10 V
Output

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Port Description
Data Outputs the current results of the A/D conversions on the current channel.
Data type: Fix_16_0 1)
Range: ‑32,768 … +32,767
Update rate: 2 MS/s
Data New Outputs an end of conversion signal if the conversion result is available.
Data type: UFix_1_0
Range: 0 or 1
If the flag changes from 0 to 1, the ADC data contains a new value. The flag is set
to 1 for only one clock cycle.
1) You can change the data type of the Data port with the Scaling format parameter
on the Scaling page. Refer to How to Change the Data Type of Analog Signals (FPGA
Programming Blockset Guide ).
If the hardware input signal or the value of the Sim_Data inport exceeds
the specified input voltage range, Data outport is saturated to minimum or
maximum range value.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping For the I/O mapping, refer to Analog In 23 Characteristics

(MicroLabBox II Hardware Installation and Configuration ).

Analog In 23 settings The following settings on the Parameters page are specific to the Analog
In 23 I/O function. For common dialog settings, refer to Common settings on
page 148.

Input range Displays the input voltage range that can be converted from
analog to digital.
Input voltages outside the displayed voltage range will be saturated to the
minimum or maximum values.

Scaling Displays the scaling of the measuring results:

§ Bit [Fix_16_0]
The Data port outputs the raw measuring results as signed bit values.
Value range: ‑32,768 … +32,767

Analog In 24 description Block display If you select an Analog In 24 channel from the channel list, the
block display changes. The simulation port is displayed optionally.

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I/O characteristics The following table shows the scaling between the analog
input voltage and the output of the Data port:

Input Voltage Range Data Port

‑10 V … +10 V ‑32,768 … +32,767
‑1 V … +1 V

The following table describes the ports of the block for analog input channels:

Port Description
Input
Convert Triggers the sampling of the A/D converter. The port allows a precise definition of
the starting point of ADC sampling. The Data New port signals the end of the
conversion process.
Data type: UFix_1_0
Data width: 1
Values
§ 0: No conversion.
§ Set to 1 for at least one clock cycle: The ADC starts the conversion.
§ Permanently set to 1: The ADC samples continuously.
Sim Data In Simulates an input signal in the same range as that specified for the real input
signal.
Available only if Enable simulation port parameter is set on the Parameters page.
Data type: Double
Data width: 1
Input voltage range: Set by the Input range parameter on the Parameters page.
Output
Data Outputs the current results of the A/D conversions on the current channel.
Data type: Fix_16_0 1)
Range: ‑32,768 … +32,767
Update rate: 5 MS/s
Data New Outputs an end of conversion signal if the conversion result is available.
Data type: UFix_1_0
Range: 0 or 1
If the flag changes from 0 to 1, the ADC data contains a new value. The flag is set
to 1 for only one clock cycle.
1) You can change the data type of the Data port with the Scaling format parameter
on the Scaling page. Refer to How to Change the Data Type of Analog Signals (FPGA
Programming Blockset Guide ).
If the hardware input signal or the value of the Sim_Data inport exceeds
the specified input voltage range, Data outport is saturated to minimum or
maximum range value.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping For the I/O mapping, refer to Analog In 24 Characteristics

(MicroLabBox II Hardware Installation and Configuration ).

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Analog In 24 settings The following settings on the Parameters page are specific to the Analog
In 24 I/O function. For common dialog settings, refer to Common settings on
page 148.

Input range Lets you specify the input voltage range that can be converted
from analog to digital for the chosen ADC channel. Input voltages outside the
specified range are saturated.
This electrical interface setting can be changed in ConfigurationDesk.

Scaling Displays the scaling of the measuring results:

§ Bit [Fix_16_0]
The Data port outputs the raw measuring results as signed bit values.
Value range: ‑32,768 … +32,767

Analog In 25 description Block display If you select an Analog In 25 channel from the channel list, the
block display changes. The simulation port is displayed optionally.

I/O characteristics The following table shows the scaling between the analog
input voltage and the output of the Data port:

Input Voltage Range Data Port

‑10 V … +10 V ‑32,768 … +32,767
‑1 V … +1 V

The following table describes the ports of the block for analog input channels:

Port Description
Input
Convert Triggers the sampling of the A/D converter. The port allows a precise definition of
the starting point of ADC sampling. The Data New port signals the end of the
conversion process.
Data type: UFix_1_0
Data width: 1
Values
§ 0: No conversion.
§ Set to 1 for at least one clock cycle: The ADC starts the conversion.
§ Permanently set to 1: The ADC samples continuously.

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Port Description
Sim Data In Simulates an input signal in the same range as that specified for the real input
signal.
Available only if Enable simulation port parameter is set on the Parameters page.
Data type: Double
Data width: 1
Input voltage range: Set by the Input range parameter on the Parameters page.
Output
Data Outputs the current results of the A/D conversions on the current channel.
Data type: Fix_16_0 1)
Range: ‑32,768 … +32,767
Update rate: 5 MS/s
Data New Outputs an end of conversion signal if the conversion result is available.
Data type: UFix_1_0
Range: 0 or 1
If the flag changes from 0 to 1, the ADC data contains a new value. The flag is set
to 1 for only one clock cycle.
1) You can change the data type of the Data port with the Scaling format parameter
on the Scaling page. Refer to How to Change the Data Type of Analog Signals (FPGA
Programming Blockset Guide ).
If the hardware input signal or the value of the Sim_Data inport exceeds
the specified input voltage range, Data outport is saturated to minimum or
maximum range value.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping For the I/O mapping, refer to Analog In 25 Characteristics

(MicroLabBox II Hardware Installation and Configuration ).

Analog In 25 settings The following settings on the Parameters page are specific to the Analog
In 25 I/O function. For common dialog settings, refer to Common settings on
page 148.

Input range Lets you specify the input voltage range that can be converted
from analog to digital for the chosen ADC channel. Input voltages outside the
specified range are saturated.
This electrical interface setting can be changed in ConfigurationDesk.

Scaling Displays the scaling of the measuring results:

§ Bit [Fix_16_0]
The Data port outputs the raw measuring results as signed bit values.
Value range: ‑32,768 … +32,767

Load Lets you enable a 255 Ω resistor between the analog signal and the
signal reference.
This electrical interface setting can be changed in ConfigurationDesk.

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APU Slave description Block display If you select the APU Slave channel from the channel list, the
block display changes. For example:

I/O characteristics The following table describes the port of the block for
digital input channels:

Port Description
Input
Sim Phi Read Simulates the APU bus value for Phi Read.
Available only if Enable simulation Phi Read port is set on the
Parameters page.
Data type: Double
Data width: 1
The value range depends on the angle range of the simulated APU bus:
§ 360 ° angle range: 0 ... 32767 (215-1)
§ 720 ° angle range: 0 ... 65535 (216-1)
APU bus clock cycle: 8 ns
The range can be exceeded, and saturation is performed to a minimum or
maximum value.
Sim Rev Read Simulates the hardware input value for Rev Read.
Available only if Enable simulation Rev Read port is set on the
Parameters page.
Data type: Double
Data width: 1
The 37-bit range is -236 ... +236 - 1.
APU bus clock cycle: 8 ns
It is not possible to exceed the range.
Sim Phi Read HD Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Sim Delta Phi Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Sim Delta Phi Enable Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Sim Angle Range Simulates the angle range of the APU bus.
Available only if Enable simulation Angle Range port is set on the
Parameters page.
Data type: Double
Data width: 1
Values:
§ 0 (low): 720 ° angle range
§ 1 (high): 360 ° angle range
Output

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Port Description
Phi Read Outputs the angle value that APU Slave reads from the APU bus. The angle
value is independent from the angle range of the APU bus.
Formula for angle calculation: alpha[°] = Phi Read * 720°/216
Data type: UFix_16_0
Data width: 1
The value range depends on the angle range of the APU bus:
§ 360 ° angle range: 0 ... 32767 (215-1)
§ 720 ° angle range: 0 ... 65535 (216-1)
APU bus clock cycle: 8 ns
It is not possible to exceed the range.
Rev Read Outputs the 37 bit total revolution (rev) value for the APU bus.
Data type: Double
Data width: 1
The APU bus clock cycle is 8 ns. The 37-bit range is -236 ... 236 - 1.
It is not possible to exceed the range.
Phi Read HD Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Delta Phi Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Delta Phi Enable Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Angle Range Outputs the angle range of the APU bus.
Data type: UFix_1_0
Data width: 1
Values:
§ 0 (low): 720 ° angle range
§ 1 (high): 360 ° angle range

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping No external connection.

APU Slave settings The Parameters page provides the following dialog setting:

Enable Phi Read HD port The Phi Read HD port is available in the block
only if you enable it.

Enable Delta Phi port The Delta Phi port is available in the block only if you
enable it.

Enable Delta Phi Enable port The Delta Phi Enable port is available in the
block only if you enable it.

Enable simulation Phi Read port The Sim Phi Read port is available in the
block only if you enable it.

Enable simulation Rev Read port The Sim Rev Read port is available in the
block only if you enable it.

Enable simulation Phi Read HD port The Sim Phi Read HD port is
available in the block only if you enable it.

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Enable simulation Delta Phi port The Sim Delta Phi port is available in the
block only if you enable it.

Enable simulation Delta Phi Enable port The Sim Delta Phi Enable port is
available in the block only if you enable it.

Enable simulation Angle Range port The Sim Angle Range port is
available in the block only if you enable it.

Angle range For the slave APU, you can inherit the angle range of the APU
bus or you specify a local angle range independent from the APU bus. The
following table shows you the possible combinations of angle range settings.

APU Bus Slave APU Resulting Angle Range of the Slave

Setting Setting APU
360° Inherit 360°
720° 720°
360° 360° 360°
720° 720° 1)
720° 360° 360° 2)
720° 720°
1) Two engine cycles are required to run through the 720 ° angle range. If you simulate a
four-stroke piston engine, for example, the angle values of the function block are not
clearly related to the camshaft position.
2) One engine cycle runs twice through the 360 ° angle range.

Aurora 64b66b In description Purpose To read 64-bit data values from an MGT communication channel
using the Aurora 64b66b link-layer protocol.

Used communication protocol setting The I/O function uses the Aurora
64B/66B protocol with the following settings:
§ Transceiver: GTH
§ Line Rate: 10.3125 Gbps
§ Dataflow Mode: Duplex
§ Interface: Framing
§ Flow Control: NFC
§ USER K: off
§ Little Endian Support: off
§ CRC: off
For more information on the protocol, refer to https://docs.xilinx.com/r/en-
US/pg074-aurora-64b66b.

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Block display If you select an Aurora 64b66b In channel from the channel
list, the block display changes. The inport Sim Data is displayed optionally.

I/O characteristics The following table describes the ports of the block for
the MGT module.

Port Description
Input
Ready Specifies that the communication channel is ready to read new data. Use this port
to prevent a data overflow.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The communication channel is not ready.
§ 1: New data can be read.
Sim Data Simulates a data exchange via the MGT communication bus including floating-
point to fixed-point data conversion.
Available only if the Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Output
Data Reads a 64-bit data value from the MGT communication bus.
User data transfer rate: Max. 8 Gbit/s (125 MHz FPGA clock, 64 bits)
MGT latency1):
§ With maximum data rate: 456 ns
§ Single words: Max. 472 ns, typ. 384 ns
If you implement inter-FPGA communication via MGT modules, clock drifts can
result in additional latencies. Refer to Implementing Inter-FPGA Communication
via MGT Modules (FPGA Programming Blockset Guide ).
Data type: UFix_64_0
Data width: 1
Data New Indicates whether a new data value was received by the MGT module.
Data type: UFix_1_0
Data width: 1
If the MGT module contains a new value, the flag changes from 0 to 1 for one
clock cycle:
§ 0: No new data available.
§ 1: New data available.
1) Latency between sender and receiver via an optical loopback.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

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I/O mapping The MGT communication bus uses the MGT connector of the
rear panel.
The recommended and tested standard network interface module for
the MicroLabBox II is the QSFP28-SR4-100G module manufactured by FS
(https://www.fs.com).

Aurora 64b66b In settings Only common dialog settings. Refer to Common settings on page 148.

Aurora 64b66b 128 Bit In Purpose To read 128-bit data values from an MGT communication channel
description using the Aurora 64b66b link-layer protocol.

Used communication protocol setting The I/O function uses the Aurora
64B/66B protocol with the following settings:
§ Transceiver: GTH
§ Line Rate: 10.3125 Gbps
§ Dataflow Mode: Duplex
§ Interface: Framing
§ Flow Control: NFC
§ USER K: off
§ Little Endian Support: off
§ CRC: off
For more information on the protocol, refer to https://docs.xilinx.com/r/en-
US/pg074-aurora-64b66b.

Block display If you select an Aurora 64b66b 128 Bit In channel from
the channel list, the block display changes. The inport Sim Data is displayed
optionally.

I/O characteristics The following table describes the ports of the block for
the MGT module.

Port Description
Input
Ready Specifies that the communication channel is ready to read new data. Use this port
to prevent a data overflow.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The communication channel is not ready.
§ 1: New data can be read.

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Port Description
Sim Data Simulates a data exchange via the MGT communication bus including floating-
point to fixed-point data conversion. The converting can lead to inaccuracies.
Available only if the Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Output
Data Reads a 128-bit data value from the MGT communication bus.
User data transfer rate: Max. 10.3125 Gbit/s, limited by the MGT module.
MGT latency1):
§ With maximum data rate: Max. 6.272 µs, typ. 6.192 µs
The latency increases, because the TX-FIFO buffer becomes full when the data
stream fills the buffer with 16 Gbit/s (128 bits at 125 MHz).
§ Single words: Max. 472 ns, typ. 384 ns
If you implement inter-FPGA communication via MGT modules, clock drifts can
result in additional latencies. Refer to Implementing Inter-FPGA Communication
via MGT Modules (FPGA Programming Blockset Guide ).
Data type: UFix_128_0
Data width: 1
Data New Indicates whether a new data value was received by the MGT module.
Data type: UFix_1_0
Data width: 1
If the MGT module contains a new value, the flag changes from 0 to 1 for one
clock cycle:
§ 0: No new data available.
§ 1: New data available.
1) Latency between sender and receiver via an optical loopback.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping The MGT communication bus uses the MGT connector of the
rear panel.
The recommended and tested standard network interface module for
the MicroLabBox II is the QSFP28-SR4-100G module manufactured by FS
(https://www.fs.com).

Aurora 64b66b 128 Bit In Only common dialog settings. Refer to Common settings on page 148.
settings

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CN App Status description Block display If you select the CN App Status channel from the channel list,
the block display changes.

I/O characteristics The following table describes the port of the block:

Port Description
Output
Status Outputs the state of the processor application.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The processor application is stopped.
§ 1: The processor application is running.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping No external connection.

CN App Status settings None

Digital In/Out 14 (In) Block display If you select a Digital In/Out 14 (In) channel from the channel
description list, the block display changes. Except the Enable and Data ports, all ports are
displayed optionally.

I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Input
Enable Lets you enable the measurement of of the input channel.
Data type: UFix_1_0
Data width: 1
Values:
§ 1: The measurement is enabled.
§ 0: The measurement is disabled.

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Port Description
Sim Data In Simulates an input signal in the same range specified for the real input signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Threshold level: Set by the Threshold init voltage parameter on the Parameters
page.
Output
Data Outputs the current results of digital input channel.
Data type: UFix_1_0
Data width: 1
Non-inverted values:
§ 0: High-low transition
§ 1: Low-high transition
Threshold level: Set by the Threshold init voltage parameter on the Parameters
page.
Update rate: FPGA clock frequency1)
1) The frequency that can be detected by the digital channel is much smaller than
the update rate. Refer to Digital In/Out 14 Characteristics (MicroLabBox II Hardware
Installation and Configuration ).

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping For the I/O mapping, refer to Digital In/Out 14 Characteristics
(MicroLabBox II Hardware Installation and Configuration ).

Digital In/Out 14 (In) settings The following settings on the Parameters page are specific to the Digital
In/Out 14 (In) I/O function. For common dialog settings, refer to Common
settings on page 148.

Invert values Lets you select whether to invert the input and output values of
the digital channel.
§ Off: The Data port does not invert the values: A logical 1 represents a low-
high transition of the physical signal.
§ On: The Data port inverts the values: A logical 1 represents a high-low
transition of the physical signal.
This electrical interface setting can be changed in ConfigurationDesk.

Threshold init voltage Lets you specify the threshold level for the current
digital channel. If the input signal is below this level, a logical 0 is detected,
otherwise a logical 1.
The selected threshold voltage is also valid for the optional simulation data
inport.

Disable filter Lets you disable the input filter:

§ On: The input filter is disabled.
§ Off: The input filter is enabled.
This electrical interface setting can be changed in ConfigurationDesk.

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Input filter Lets you specify the minimum pulse length for detecting a valid
input in the range 0 … 1,250,000 ns in steps of 8 ns.
This electrical interface setting can be changed in ConfigurationDesk.

Rising edge delay Lets you specify whether to use a delay for the rising edge
detection. The delay can be specified in the range 0 … 50,000 ns in steps of
8 ns.
This electrical interface setting can be changed in ConfigurationDesk.

Enable configuration ports Lets you enable configuration ports to change

the initial configuration of the channel at runtime.

IOCNET Global Time Block display If you select the IOCNET Global Time channel from the channel
description list, the block display changes.

I/O characteristics The following table describes the port of the block:

Port Description
Output
Time Outputs the number of hardware ticks that occurred since the MicroLabBox II was
powered on.
Data type: 56 bit
Tick step-width: 8.5 ns

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping No external connection.

IOCNET Global Time settings None

MGT In description Purpose To provide the information about the connection between the GTH
transceivers and the MGT module and to specify the reference clock frequency.
The information is required for customer-specific protocol blocks that configure
the GTH transceivers. A GTH transceiver is a configurable transceiver of the AMD
UltraScale FPGA architecture.

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Block display If you select an MGT In channel from the channel list, the block
display changes.

I/O characteristics The following table describes the ports of the block for
the MGT module.

Port Description
Output
CLK_P Provides the MGT reference clock frequency.
CLK_N The ports represent the differential signal of an internal clock. The ports must be
connected to a block that provides the configuration for the GTH transceivers.
The reference frequency is specified on the Parameters page.
Data type: UFix_1_0
Data width: 1
RX_P Reads the raw data from the MGT module.
RX_N The ports represent the differential output signals of the MGT module. The ports
must be connected to a block that provides the configurations for the GTH
transceiver.
Data type: UFix_4_0
Each bit represents the output of one MGT channel.
Data width: 1
Update rate: Clock frequency of the GTH transceivers.

Multiple clock domain support This block can be used in a user clock
domain to be synchronous to the MGT transceivers, for example. Refer to
Using Multiple Clock Domains for FPGA Modeling (FPGA Programming Blockset
Guide ).

I/O mapping The MGT communication bus uses the MGT connector of the
rear panel.

Demo model For implementing an MGT communication with a customized

protocol, refer to Modeling MGT Communication Using a Customized Protocol
(FPGA Programming Blockset Guide ).

MGT In settings The Parameters page provides the following dialog setting:

MGT reference clock frequency Lets you specify the reference clock
frequency that is used to generate the MGT clock frequency.
The reference clock frequency depends on the protocol type, transfer rate, and
internal scaling factors. In many cases, the reference clock frequency for the
MGT module of the FPGA base board is 156.25 MHz.
For more information, refer to Modeling MGT Communication Using a
Customized Protocol (FPGA Programming Blockset Guide ).

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MGT In Opto Ready Purpose To provide status information on the connection.

description
Block display If you select an MGT In Opto Ready channel from the channel
list, the block display changes.

I/O characteristics The following table describes the ports of the block for
the MGT module.

Port Description
Output
Opto_Ready Indicates whether the MGT module is ready for data exchange. The port changes
to 1 during the initialization phase, i.e. before the CN APP Status block changes
from stop to running.
Data type: UFix_1_0
Data width: 1
If the MGT module is ready, the flag changes from 0 to 1:
§ 0: The MGT module is not ready.
§ 1: The MGT module is ready.
Update rate: 125 MHz

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping The MGT communication bus uses the MGT connector of the
rear panel.
The recommended and tested standard network interface module for
the MicroLabBox II is the QSFP28-SR4-100G module manufactured by FS
(https://www.fs.com).

Demo model For implementing an MGT communication with a customized

protocol, refer to Modeling MGT Communication Using a Customized Protocol
(FPGA Programming Blockset Guide ).

MGT In Opto Ready settings None

Status In description Block display If you select the Status In channel from the channel list, the
block display changes.

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I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Output
Init Done Outputs the state of the initialization sequence that is started after programming
the FPGA.
Data type: UFix_1_0
§ 0: Initialization sequence is in progress.
§ 1: Initialization sequence has finished.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping No external connection.

Status In settings None

Watchdog description Block display If you select the Watchdog channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block for
the watchdog input channel:

Port Description
Output
Status Outputs a flag that indicates that the processor application transmits a keep-alive
signal within the specified timeout.
§ 0: The watchdog timer expires without a keep-alive signal being transmitted to
the FPGA application.
§ 1: The processor application is alive.
Data type: UFix_1_0

Tip

In ConfigurationDesk, you deactivate the watchdog functionality by not

mapping the Trigger port of the watchdog function to a model port.
If deactivated, the Status port of the Watchdog block always outputs 1 in
the FPGA application.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

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Watchdog settings None

Related topics HowTos

How to Implement the Watchdog (FPGA Programming Blockset Guide )

References

Block Settings for the MicroLabBox II Framework.................................................................... 125

FPGA_IO_READ_BL................................................................................................................... 54

Scaling Page (FPGA_IO_READ_BL)

Purpose To specify the inverting, scaling, and saturation settings for the selected I/O
function.

Description You can modify the I/O signal of the selected I/O function if you select the
Enable FPGA test access and scaling parameter on the FPGA Access page
of the FPGA_SETUP_BL block dialog. The possible modifications depend on the
selected I/O function.

Common settings The following settings on the Scaling page are common to the I/O functions that
you can select on the Unit page.

Enable FPGA test access and scaling for this block Lets you disable FPGA
test access and scaling for the selected I/O function.

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Analog In settings The following settings on the Scaling page are specific to the Analog In 23,
Analog In 24, and Analog In 25 I/O functions.

Note

Scaling of analog I/O signals also effects the signal path:

§ If you use the parameters of the Scaling page to scale analog signals, the
data type of the Data port is set to the specified data format for scaling.
For more information, refer to How to Change the Data Type of Analog
Signals (FPGA Programming Blockset Guide ).
§ FPGA scaling of analog I/O signals might cause additional latency. If
the latency can be calculated during the modeling, analog I/O functions
display the total latency.

Scaling format Lets you select the data format for scaling and saturation.
§ Signed/Unsigned:
The values of the parameters for scaling and saturation are in fixed‑point
format. The signed fixed-point format reserves one bit for the sign.
You can specify the number of bits and the binary point position with the
Number of bits and Binary point (fraction width) parameters.
§ Single:
The values of the parameters for scaling and saturation are 32-bit values in
the single-precision floating‑point format with a fraction width of 24, which
complies with the IEEE 754 standard (single).
§ Double:
The values of the parameters for scaling and saturation are 64-bit values in
the double-precision floating‑point format with a fraction width of 53, which
complies with the IEEE 754 standard (double).

Number of bits This setting depends on the Scaling format setting.

§ Fixed-point format:
Lets you specify the bit width of the scaling parameters and the Data port in
the range 1 ... 64.
§ Floating-point format:
Displays the bit width of the scaling parameters and the Data port.

Binary point (fraction width) This setting depends on the Scaling format
setting.
§ Fixed-point format:
Lets you specify the binary point position of the scaling parameters and the
Data port. The position 0 represents the lowest bit position
§ Floating-point format:
Displays the fraction width of the scaling parameters and the Data port.

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Scaling factor Lets you specify the scaling factor. The scaling factor gains the
signal of the Data port before it is saturated or replaced via FPGA test access.
You must check whether the specified and displayed value is supported by
the specified scaling format. The value of the Scaling factor parameter will
be executed with the maximum accuracy of the specified scaling format
and saturated to the minimum and maximum values that the scaling format
supports.

Scaling offset Lets you add a signal offset after the signal of the Data port is
scaled with the scaling factor.
You must check whether the specified and displayed value is supported by
the specified scaling format. The value of the Scaling offset parameter will
be executed with the maximum accuracy of the specified scaling format
and saturated to the minimum and maximum values that the scaling format
supports.

Saturation minimum value Lets you specify the minimum value to which
the measured and scaled signal is saturated before it is output via the Data port.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation minimum
value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

Saturation maximum value Lets you specify the maximum value to which
the measured and scaled signal is saturated before it is output via the Data port.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation maximum
value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

Multiplier latency Lets you specify the latency that is caused by the
multiplier for scaling. The multiplier is used to multiply the signal with the value
of the Scaling factor parameter.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The multiplication will be implemented without latency.
§ 1 ... 20: The multiplication will be implemented with the specified latency.
Use this value range in the exceptional case that the optimized latency cause
timing problems during the build process.

Adder latency Lets you specify the latency that is caused by the offset adder.
The offset adder is used to add the value of the Scaling offset parameter to the
signal.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The adding will be implemented without latency.
§ 1 ... 20: The adding will be implemented with the specified latency.

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Use this value range in the exceptional case that the optimized latency causes
timing problems during the build process.

Digital In settings The following settings on the Scaling page are specific to the Digital In/Out 14
(In) I/O function.

Invert input polarity Lets you adapt the measured values to the electrical
input signal:
§ Disabled:
The Data port outputs the signals as measured: A low-high transition results in
a 1 and vice versa.
§ Enabled:
The output of the Data port is inverted: A low-high transition results in a 0
and vice versa.

Other I/O function settings The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

Related topics Basics

Basics on FPGA Test Access and Scaling (FPGA Programming Blockset Guide )

References

Block Settings for the MicroLabBox II Framework.................................................................... 125

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FPGA_IO_WRITE_BL (MicroLabBox II)

Purpose To configure write access to I/O signals when using the DS1303 (KU15P) Multi-
I/O Board framework.

Where to go from here Information in this section

Parameters Page (FPGA_IO_WRITE_BL).................................................. 169

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_WRITE_BL)........................................................ 188

To specify the inverting settings for the selected I/O function.

Information in other sections

Common settings
Block Description (FPGA_IO_WRITE_BL)................................................... 59
To implement write access to a physical output channel in the FPGA
model.

Unit Page (FPGA_IO_WRITE_BL)............................................................... 60

To specify the I/O type and channel to be used for write access.

Parameters Page (FPGA_IO_WRITE_BL)

Purpose To specify relevant settings for the selected I/O function.

Description The frameworks provide different I/O types, which you can select on the Unit
page of the block:
§ Analog Out 19
§ Analog Out 20
§ APU Master
§ Aurora 64b66b Out
§ Aurora 64b66b 128 Bit Out
§ Digital In/Out 14 (In/Out‑Z)
§ Digital In/Out 15
§ LED Out
§ MGT Out

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Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_IO_WRITE_BL block, except
for the LED Out function.

Enable simulation port Lets you enable an outport for offline simulation
data. The Sim Data outport is added to the block to connect it to a Simulink-
based I/O environment model.
For the digital In/Out I/O functions, there are separate settings for enabling the
input and output simulation ports.

Analog Out 19 description Block display If you select an Analog Out 19 channel from the channel list,
the block display changes. The simulation port is displayed optionally.

I/O characteristics The following table shows the scaling between the Data
port value and the output of the analog channel:

Data Port Value Generated Voltage

‑32,768 … +32,767 ‑10 V … +10 V

The following table describes the ports of the block for analog output channels:

Port Description
Input
Data Generates a voltage signal in the specified range.
Data type: Fix_16_0 1)
Data width: 1
Value range: ‑32,768 … +32,767
Update rate: 2.5 MS/s
Enable Lets you enable on-demand conversion of the Data port value. When a new value
can be converted, the Ready port outputs 1.
Note: If you connect the Ready port directly to the Enable port, the analog output
channel works in the same way as in a free-running mode.
Data Type: UFix_1_0
Data width: 1
Output
Ready Indicates that the channel is ready to be updated.
Data type: UFix_1_0
Data width: 1
Update rate: 2.5 MS/s

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Port Description
Sim Data Simulates the analog output signal.
Available only if Enable simulation port parameter is set on the Parameters
page.
Data type: Double
Data width: 1
Value range: Displayed by the Output range parameter on the Parameters page.
1) You can change the data type of the Data port with the Scaling format parameter
on the Scaling page. Refer to How to Change the Data Type of Analog Signals (FPGA
Programming Blockset Guide ).

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping For the I/O mapping, refer to Analog Out 19 Characteristics
(MicroLabBox II Hardware Installation and Configuration ).

Analog Out 19 parameters The following settings on the Parameters page are specific to the Analog
Out 19 I/O function. For common dialog settings, refer to Common settings on
page 170.

Noise amplitude Lets you enable a pseudo-random noise that is added to

the generated output signal.
Value range: 0 … 65,535 (216-1)
Resulting noise amplitude: 0 V … 10 V
Set the noise amplitude to 0 to disable the noise generation.
This electrical interface setting can be changed in ConfigurationDesk.

Scaling Displays the scaling of the Data port:

§ Bit [Fix_16_0]
Lets you specify the output voltage with a signed bit value.
Value range: ‑32,768 … +32,767 (16-bit converter)

Output range Displays the output range of the analog output channel.

Analog Out 20 description Block display If you select an Analog Out 20 channel from the channel list,
the block display changes. The simulation port is displayed optionally.

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I/O characteristics The following table shows the scaling between the Data
port value and the output of the analog channel:

Data Port Value Generated Voltage

‑32,768 … +32,767 § ‑10 V DC… +10 V DC (direct output)
§ ‑20 V AC … +20 V AC (transformer-coupled
output)

The following table describes the ports of the block for analog output channels:

Port Description
Input
Data Generates a voltage signal in the specified range.
Data type: Fix_16_0 1)
Data width: 1
Value range: ‑32,768 … +32,767
Update rate: 5 MS/s
Enable Lets you enable on-demand conversion of the Data port value. When a new value
can be converted, the Ready port outputs 1.
Note: If you connect the Ready port directly to the Enable port, the analog output
channel works in the same way as in a free-running mode.
Data Type: UFix_1_0
Data width: 1
Output
Ready Indicates that the channel is ready to be updated.
Data type: UFix_1_0
Data width: 1
Update rate: 5 MS/s
Sim Data Simulates the analog output signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Value range: Set by the Output range parameter on the Parameters page.
1) You can change the data type of the Data port with the Scaling format parameter
on the Scaling page. Refer to How to Change the Data Type of Analog Signals (FPGA
Programming Blockset Guide ).

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping For the I/O mapping, refer to Analog Out 20 Characteristics
(MicroLabBox II Hardware Installation and Configuration ).

Analog Out 20 parameters The following settings on the Parameters page are specific to the Analog
Out 20 I/O function. For common dialog settings, refer to Common settings on
page 170.

Noise amplitude Lets you enable a pseudo-random noise that is added to

the generated output signal.
Value range: 0 … 65,535 (216-1)

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Resulting noise amplitude: 0 V … 10 V (direct output) or 0 V … 20 V

(transformer-coupled output)
Set the noise amplitude to 0 to disable the noise generation.
This electrical interface setting can be changed in ConfigurationDesk.

Scaling Displays the scaling of the Data port:

§ Bit [Fix_16_0]
Lets you specify the output voltage with a signed bit value.
Value range: ‑32,768 … +32,767 (16-bit converter)

Output range Lets you select the voltage range and converter mode of the
analog output channel:
§ ‑10 V … +10 V DC:
The DA converter directly outputs the voltage signal without using a
transformer. The output voltage range is ‑10 V DC … +10 V DC.
§ ‑20 V … +20 V AC:
The DA converter outputs the voltage signal via a transformer. The output
voltage range is ‑20 V AC … +20 V AC.
For the AC characteristics, refer to Analog Out 20 Characteristics
(MicroLabBox II Hardware Installation and Configuration ).
This electrical interface setting can be changed in ConfigurationDesk.

APU Master description Block display If you select the APU Master channel from the channel list, the
block display changes. For example:

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Velocity Specifies a velocity value in degrees/second to be applied as APU Master
speed.
The value will be applied if Set Velocity is 1 (high) and Busy is 0 (low).
Data type: Fix_32_10
Data width: 1
Range: -1,200,000 °/s ... +1,200,000 °/s
It is not possible to exceed the range. The port is saturated at the higher or
lower limit.

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Port Description
Set Velocity Specifies the current value of Velocity as new velocity value.
The new value is set only if Set Velocity is 1 (high) and Busy is 0 (low).
Data type: UFix_1_0
Data width: 1
To distribute and execute a new velocity value takes at least 10 μs,
depending on the IOCNET structure.
Output
Phi Read Outputs the angle counter value of the APU that the APU Master writes to
the APU bus. The step size of the angle counter is approximately 0.011°. The
step size is independent from the angle range.
Formula for angle calculation: alpha[°] = Phi Read * 720°/216
Data type: UFix_16_0
Data width: 1
The value range depends on the Angle range on the Parameters page:
§ 360 ° angle range: 0 ... 32767 (215-1)
§ 720 ° angle range: 0 ... 65535 (216-1)
APU bus clock cycle: 8 ns
It is not possible to exceed the range.
Rev Read Outputs the 37-bit total revolution (rev) value that APU Master reads from
the APU bus.
Data type: Fix_37_0
Data width: 1
The 37-bit range is -236 ... 236 - 1.
APU bus clock cycle: 8 ns
It is not possible to exceed the range.
Phi Read HD Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Delta Phi Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Delta Phi Enable Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Angle Range Outputs the angle range of the APU bus. You set the angle range on the
Parameters page.
Data type: UFix_1_0
Data width: 1
Values:
§ 0 (low): 720 ° angle range
§ 1 (high): 360 ° angle range
Busy Outputs whether APU Master is busy to set the last velocity value.
Data type: UFix_1_0
Data width: 1
If the Busy port is 1 (high), new velocity values cannot be set.
The Busy port stays active for at least 10 µs depending on the IOCNET
structure.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping No external connection.

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APU Master settings The Parameters page provides the following dialog setting:

Angle range Lets you select the angle range of the APU in degree.
§ 360: The angle range is 360 ° and cannot be changed in ConfigurationDesk.
§ 720: The angle range is 720 ° and cannot be changed in ConfigurationDesk.
§ Individual: The Angle range property of the FPGA custom function block in
ConfigurationDesk lets you set the angle range of the APU. The default value
is 720°.

Initial position Lets you set the initial APU master position in degree.
§ Value range: -1,440 ° ... +1,440 °

Enable advanced ports The internal ports for the dSPACE Electric Motor HIL
Solution are available in the block only if you enable them.

Aurora 64b66b Out Purpose To write 64-bit data values to an MGT communication channel using
description the Aurora 64b66b link-layer protocol.

Used communication protocol setting The I/O function uses the Aurora
64B/66B protocol with the following settings:
§ Transceiver: GTH
§ Line Rate: 10.3125 Gbps
§ Dataflow Mode: Duplex
§ Interface: Framing
§ Flow Control: NFC
§ USER K: off
§ Little Endian Support: off
§ CRC: off
For more information on the protocol, refer to https://docs.xilinx.com/r/en-
US/pg074-aurora-64b66b.

Block display If you select an Aurora 64b66b Out channel from the channel
list, the block display changes. The outport Sim Data is displayed optionally.

I/O characteristics The following table describes the ports of the block for
the MGT module:

Port Description
Input
Data Writes a 64-bit data value to the MGT communication bus.
User data transfer rate: Max. 8 Gbit/s (125 MHz FPGA clock, 64 bits)

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Port Description
MGT latency1):
§ With maximum data rate: 456 ns
§ Single words: Max. 472 ns, typ. 384 ns
If you implement inter-FPGA communication via MGT modules, clock drifts can
result in additional latencies. Refer to Implementing Inter-FPGA Communication
via MGT Modules (FPGA Programming Blockset Guide ).
Data type: UFix_64_0
Data width: 1
Enable Enables the write access to the MGT communication bus.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: No write access.
§ 1: The Data port value of the current clock cycle is written on the MGT
communication bus.
Output
Ready Outputs a flag that indicates that the MGT module is ready to write new data on
the MGT communication bus.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The MGT channel is busy.
§ 1: New data values can be written to the MGT communication bus.
Sim Data Simulates a data exchange via the MGT communication bus including fixed-point
to floating-point data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
1) Latency between sender and receiver via an optical loopback.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping The MGT communication bus uses the MGT connector of the
rear panel.
The recommended and tested standard network interface module for
the MicroLabBox II is the QSFP28-SR4-100G module manufactured by FS
(https://www.fs.com).

Aurora 64b66b Out settings Only common dialog settings. Refer to Common settings on page 170.

Aurora 64b66b 128 Bit Out Purpose To write 128-bit data values to an MGT communication channel
description using the Aurora 64b66b link-layer protocol.

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Used communication protocol setting The I/O function uses the Aurora
64B/66B protocol with the following settings:
§ Transceiver: GTH
§ Line Rate: 10.3125 Gbps
§ Dataflow Mode: Duplex
§ Interface: Framing
§ Flow Control: NFC
§ USER K: off
§ Little Endian Support: off
§ CRC: off
For more information on the protocol, refer to https://docs.xilinx.com/r/en-
US/pg074-aurora-64b66b.

Block display If you select an MGT Out channel from the channel list, the
block display changes. The outport Sim Data is displayed optionally.

I/O characteristics The following table describes the ports of the block for
the MGT module:

Port Description
Input
Data Writes a 128-bit data value to the MGT communication bus.
User data transfer rate: Max. 10.3125 Gbit/s, limited by the MGT module.
MGT latency1):
§ With maximum data rate: Max. 6.272 µs, typ. 6.192 µs
The latency increases, because the TX-FIFO buffer becomes full when the data
stream fills the buffer with 16 Gbit/s (128 bits at 125 MHz).
§ Single words: Max. 472 ns, typ. 384 ns
If you implement inter-FPGA communication via MGT modules, clock drifts can
result in additional latencies. Refer to Implementing Inter-FPGA Communication
via MGT Modules (FPGA Programming Blockset Guide ).
Data type: UFix_128_0
Data width: 1
Enable Enables the write access to the MGT communication bus.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: No write access.
§ 1: The Data port value of the current clock cycle is written on the MGT
communication bus.
Output

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Port Description
Ready Outputs a flag that indicates that the MGT module is ready to write new data on
the MGT communication bus.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The MGT channel is busy.
§ 1: New data values can be written to the MGT communication bus.
Sim Data Simulates a data exchange via the MGT communication bus including fixed-point
to floating-point data conversion. The converting can lead to inaccuracies.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
1) Latency between sender and receiver via an optical loopback.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping The MGT communication bus uses the MGT connector of the
rear panel.
The recommended and tested standard network interface module for
the MicroLabBox II is the QSFP28-SR4-100G module manufactured by FS
(https://www.fs.com).

Aurora 64b66b 128 Bit Out Only common dialog settings. Refer to Common settings on page 170.
settings

Digital In/Out 14 (In/Out‑Z) Block display If you select a Digital In/Out channel from the channel list, the
description block display changes. Except for the Data In, Data Out, and Enable ports, all
the ports are displayed optionally.

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I/O characteristics

Note

If you use the same digital channel for the input and the output, the
maximum input voltage for the digital input channel is equal to the
specified high supply, and the applicable threshold voltage is lower than
the specified high supply.
To use the maximum input voltage range, you have to use Digital In/Out
14 (In) (refer to Parameters Page (FPGA_IO_READ_BL) on page 147).

The following table describes the ports of the block:

Port Description
Input
Data Out Outputs a signal in the specified range if the Enable port is set to 1.
To set the voltage level, use the High Supply parameter on the Parameters page.
Data Type: UFix_1_0
Data width: 1
If driven with 0, the hardware outputs a low-level signal. If driven with 1, the
hardware outputs a high-level signal.
Update rate: FPGA clock frequency1)
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Enable Write Enables the output of data values and disables the high-impedance state.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The output is set to the high-impedance state.
§ 1: The output is enabled and outputs the data values of the Data inport.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Invert Lets you invert the data port values. The setting will not take effect until the Invert
Set port rises from 0 to 1.
Available only if the Enable configuration ports parameter is set.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: A data port does not invert the values. A logical 1 represents a low-high
transition of the physical signal.
§ 1: A data port inverts the values. A logical 1 represents a high-low transition of
the physical signal.
Invert Set Lets you set the inverting as specified by the Invert port. A new setting overwrites
the settings of the Invert values parameter on the Parameters page.
Available only if the Enable configuration ports parameter is set.
Data type: UFix_1_0
Data width: 1

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Port Description
Values:
§ No transition, or a 1 to 0 transition: A new setting does not take effect.
§ 0 to 1 transition: The new setting is sent to the input channel. The Invert Ack
port outputs a flag if the channel is up-to-date.
Update rate: FPGA clock frequency
Mode Specifies the digital output mode. A new output mode will not take effect until the
Mode Set port rises from 0 to 1.
Available only if the Enable configuration ports parameter is set on the
Parameters page.
Data Type: UFix_6_0
Data width: 1
Values:
§ 49: Enables the low-side switch that drives a load connected to the high supply
voltage.
§ 50: Enables the high-side switch that drives a load connected to GND.
§ 51: Enables a push-pull switch that drives a load with the high supply voltage and
GND.
Mode Set Sets the output mode as specified by the Mode port. A new setting overwrites the
settings of the Output Mode on the Parameters page.
Available only if the Enable configuration ports parameter is set.
Data type: UFix_1_0
Data width: 1
Values:
§ No transition, or a 1 to 0 transition: A new mode does not take effect.
§ 0 to 1 transition: New settings are sent to the output channel. The Mode Ack
port outputs a flag if the channel is up-to-date.
Update rate: FPGA clock frequency
Sim Data In Simulates an input signal that you can connect to a Simulink-based I/O environment
model. The threshold voltage determines a logical 0 or 1 as output of the Data
port.
Available only if Enable digital in simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Range: -35 V ... +35 V
Range exceeding is possible and will be saturated to the minimum or maximum
values.
Output
Data In Outputs the current results of the digital input channel.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Input voltage of the channel is below the threshold voltage of a high-low
transition.
§ 1: Input voltage of the channel is higher than or equal to the threshold voltage of
a low-high transition.

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Port Description
Threshold level: Set by the Threshold init voltage parameter on the Parameters
page.
Update rate: FPGA clock frequency1)
Invert Ack Outputs a flag that acknowledges a change of the inverting setting.
Available only if the Enable configuration ports parameter is set.
Data type: UFix_1_0
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one clock
cycle.
Mode Ack Outputs a flag that acknowledges a change of the output mode.
Available only if the Enable configuration ports is set on the Parameters page.
Data type: Double
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one clock
cycle.
Sim Data Out Simulates an output signal that you can connect to a Simulink-based I/O
environment model. The signal is in the same range as specified for the hardware
output signal.
Available only if the Enable digital out simulation port parameter is set on the
Parameters page.
Data type: Double
Output voltage: 0 V … 5 V or 0 V … 3.3 V, set by the High Supply parameter
Update rate: FPGA clock frequency
1) The frequency that can be generated or detected by the digital channel is much
smaller than the update rate. Refer to Digital In/Out 14 Characteristics (MicroLabBox II
Hardware Installation and Configuration ).

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping For the I/O mapping, refer to Digital In/Out 14 Characteristics
(MicroLabBox II Hardware Installation and Configuration ).

Digital In/Out 14 (In/Out‑Z) The following settings on the Parameters page are specific to the Digital
settings In/Out‑Z I/O function.

Invert values Lets you select whether to invert the input and output values of
the digital channel.
§ Off: The Data port does not invert the values: A logical 1 represents a low-
high transition of the physical signal.
§ On: The Data port inverts the values: A logical 1 represents a high-low
transition of the physical signal.
This electrical interface setting can be changed in ConfigurationDesk.

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Output Mode Lets you select the output mode.

§ Low-side switch
Lets you actively drive the output to GND to output a low-level signal.
An external load to the high supply voltage is required to output a high-level
signal.
§ High-side switch
Lets you actively drive the output to the high supply voltage to output a
high-level signal.
An external load to GND is necessary to output a low-level signal.
§ Push-pull
Lets you drive the output between the high supply voltage and GND.
An external load is not required.
This electrical interface setting can be changed in ConfigurationDesk.

Threshold init voltage Lets you specify the threshold level for the current
digital channel. If the input signal is below this level, a logical 0 is detected,
otherwise a logical 1.
The selected threshold voltage is also valid for the optional simulation data
inport.

Input filter Lets you specify the minimum pulse length for detecting a valid
input in the range 0 … 1,250,000 ns in steps of 8 ns.
This electrical interface setting can be changed in ConfigurationDesk.

Rising edge delay Lets you specify whether to use a delay for the rising edge
detection. The delay can be specified in the range 0 … 50,000 ns in steps of
8 ns.
This electrical interface setting can be changed in ConfigurationDesk.

High Supply Lets you select the the high supply voltage voltage that
determines the high-level voltage for the high‑side switch.
This electrical interface setting can be changed in ConfigurationDesk.

Drive Config Lets you enable/disable the termination of the signal line by an
internal resistor.
§ Direct Drive
Lets you directly drive the I/O signal. The internal termination resistor is
disabled.
§ 68 Ohm Terminated
Lets you terminate the I/O signal with an internal 68 Ω resistor.
This electrical interface setting can be changed in ConfigurationDesk.

Enable configuration ports Lets you enable configuration ports to change

the initial configuration of the channel at runtime.

Enable digital in simulation port Lets you enable an inport for offline
simulation data. The Sim Data In inport is added to the block to connect it to
simulation data coming from a Simulink-based I/O environment model. This port
is relevant only if the signal direction is in.

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Enable digital out simulation port Lets you enable an outport for offline
simulation data. The Sim Data Out port is added to the block to connect it to a
Simulink-based I/O environment model.

Digital In/Out 15 description Block display If you select a Digital In/Out 15 channel from the channel list,
the block display changes. Except for the Data In, Data Out, and Enable ports,
all the ports are displayed optionally.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Out Outputs a signal in the specified range if the Enable port is set to 1.
Data Type: UFix_1_0
Data width: 1
If driven with 0, the hardware outputs a low-level signal. If driven with 1, the
hardware outputs a high-level signal.
Update rate: FPGA clock frequency1)
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Enable Write Enables the output of data values and disables the high-impedance state.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The output is set to the high-impedance state.
§ 1: The output is enabled and outputs the data values of the Data inport.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Invert Lets you invert the data port values. The setting will not take effect until the Invert
Set port rises from 0 to 1.
Available only if the Enable configuration ports parameter is set.
Data type: UFix_1_0
Data width: 1

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Port Description
Values:
§ 0: A data port does not invert the values. A logical 1 represents a low-high
transition of the physical signal.
§ 1: A data port inverts the values. A logical 1 represents a high-low transition of
the physical signal.
Invert Set Lets you set the inverting as specified by the Invert port. A new setting overwrites
the settings of the Invert values parameter on the Parameters page.
Available only if the Enable configuration ports parameter is set.
Data type: UFix_1_0
Data width: 1
Values:
§ No transition, or a 1 to 0 transition: A new setting does not take effect.
§ 0 to 1 transition: The new setting is sent to the input channel. The Invert Ack
port outputs a flag if the channel is up-to-date.
Update rate: FPGA clock frequency
Termination Specifies whether the signal line is terminated. A new configuration will not take
effect until the Termination Set port rises from 0 to 1.
Available only if the Enable configuration ports parameter is set.
Data Type: UFix_1_0
Data width: 1
Values:
§ 0: The signal line is driven directly without a termination.
§ 1: The signal line is terminated via an internal RC termination with 120 Ω/5 nF.
Termination Lets you set the termination signal lines as specified by the Termination port. A
Set new setting overwrites the settings of the Termination on the Parameters page.
Available only if the Enable configuration ports parameter is set.
Data type: UFix_1_0
Data width: 1
Values:
§ No transition, or a 1 to 0 transition: A new termination setting does not take
effect.
§ 0 to 1 transition: The new settings are sent to the channel. The Termination Ack
port outputs a flag if the channel is up-to-date.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Sim Data In Simulates an input signal that you can connect to a Simulink-based I/O environment
model. The threshold voltage of 0 V determines a logical 0 or 1 as output of the
Data port.
Available only if Enable digital in simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Value range: -5 V … +5 V
Range exceeding is possible and will be saturated to the minimum or maximum
values.
Output

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Port Description
Data In Outputs the current results of the digital input channel.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Input voltage made a high-low transition.
§ 1: Input voltage made a low-high transition.
Update rate: FPGA clock frequency1)
Invert Ack Outputs a flag that acknowledges a change of the inverting setting.
Available only if the Enable configuration ports parameter is set.
Data type: UFix_1_0
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one clock
cycle.
Termination Outputs a flag that acknowledges a change of the termination setting.
Ack Available only if Enable configuration ports parameter is set.
Data type: UFix_1_0
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one clock
cycle.
Sim Data Out Simulates an output signal that you can connect to a Simulink-based I/O
environment model. The signal is in the same range as specified for the hardware
output signal.
Available only if Enable digital in simulation port is set on the Parameters page.
Data type: Double
Output voltage: ±3.3 V
Update rate: FPGA clock frequency
1) The frequency that can be generated or detected by the digital channel is much
smaller than the update rate. Refer to Digital In/Out 15 Characteristics (MicroLabBox II
Hardware Installation and Configuration ).
If the value of the Data In inport exceeds the specified data width, only the
lowest bit is used. If the hardware signal or the value of the Sim Data In
inport exceeds the minimum or maximum input voltage, it is saturated to the
corresponding minimum or maximum value.

Note

Asynchronous input data might lead to metastable register states because

input data is synchronized only by a single register stage. Further
synchronization techniques might be necessary.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping For the I/O mapping, refer to Digital In/Out 15 Characteristics
(MicroLabBox II Hardware Installation and Configuration ).

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Digital In/Out 15 settings The following settings on the Parameters page are specific to the Digital
In/Out 15 I/O function.

Invert values Lets you select whether to invert the input and output values of
the digital channel.
§ Off: The Data port does not invert the values: A logical 1 represents a low-
high transition of the physical signal.
§ On: The Data port inverts the values: A logical 1 represents a high-low
transition of the physical signal.
This electrical interface setting can be changed in ConfigurationDesk.

Termination Lets you enable an internal termination between the signal

lines. The setting can be overwritten by the termination ports.
§ Open
The signal lines are not terminated.
§ Terminated
An internal 120 Ω/5 nF RC termination terminates the signal lines.
This electrical interface setting can be changed in ConfigurationDesk.

Input filter Lets you specify the minimum pulse length for detecting a valid
input in the range 0 … 1,250,000 ns in steps of 8 ns.
This electrical interface setting can be changed in ConfigurationDesk.

Enable configuration ports Lets you enable configuration ports to change

the initial configuration of the channel at runtime.

Enable digital in simulation port Lets you enable an inport for offline
simulation data. The Sim Data In inport is added to the block to connect it to
simulation data coming from a Simulink-based I/O environment model. This port
is relevant only if the signal direction is in.

Enable digital out simulation port Lets you enable an outport for offline
simulation data. The Sim Data Out port is added to the block to connect it to a
Simulink-based I/O environment model.

LED Out description Block display If you select the LED Out channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Controls the USR LED 1 on the MicroLabBox II.
Data type: UFix_1_0
Data width: 1

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Port Description
Values:
§ 0: The LED outputs status information for custom FPGA applications. Refer
to LED States of the MicroLabBox II (MicroLabBox II Hardware Installation and
Configuration ).
§ 1: LED lights orange.
If the value of the Data port exceeds the specified data width, only the lowest bit is
used (=1).

I/O mapping No external connection.

LED Out settings None

MGT Out description Purpose To provide the information about the connection between the GTH
transceivers and the MGT module. The information is required for customer-
specific protocol blocks that configure the GTH transceivers. A GTH transceiver is
a configurable transceiver of the AMD UltraScale FPGA architecture.

Block display If you select an MGT Out channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block for
the MGT module:

Port Description
Input
TX_P Writes data to the MGT module.
TX_N The ports represent the differential signals of the GTH transceivers that are
connected to the MGT module. The ports must be connected to a block that
provides the configuration for the GTH transceivers.
Data type: UFix_4_0
Data width: 1
Each bit represents the input for one MGT channel.
Update rate: MGT reference clock frequency
The MGT reference clock frequency parameter of the MGT In block lets you
specify the reference frequency that is used to generate the MGT clock frequency.
Refer to MGT In description on page 161.

Multiple clock domain support This block can be used in a user clock
domain to be synchronous to the MGT transceivers, for example. Refer to
Using Multiple Clock Domains for FPGA Modeling (FPGA Programming Blockset
Guide ).

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I/O mapping The MGT communication bus uses the MGT connector of the
rear panel.
The recommended and tested standard network interface module for
the MicroLabBox II is the QSFP28-SR4-100G module manufactured by FS
(https://www.fs.com).

Demo model For implementing an MGT communication with a customized

protocol, refer to Modeling MGT Communication Using a Customized Protocol
(FPGA Programming Blockset Guide ).

MGT Out settings None

Related topics Basics

Modeling MGT Communication Using a Customized Protocol (FPGA Programming

Blockset Guide )

References

Block Settings for the MicroLabBox II Framework.................................................................... 125

FPGA_IO_WRITE_BL.................................................................................................................. 58

Scaling Page (FPGA_IO_WRITE_BL)

Purpose To specify the inverting settings for the selected I/O function.

Description You can invert digital I/O signals and UART signals of the selected I/O function
if you select the Enable FPGA test access and scaling parameter on the FPGA
Access page of the FPGA_SETUP_BL block dialog. The possible modifications
depend on the selected I/O function.

Common settings The following settings on the Scaling page are common to the I/O functions that
you can select on the Unit page.

Enable FPGA test access and scaling for this block Lets you disable FPGA
test access and scaling for the selected I/O function.

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Analog Out settings The following settings on the Scaling page are specific to the Analog Out 19
and Analog Out 20 I/O functions.

Note

Scaling of analog I/O signals also effects the signal path:

§ If you use the parameters of the Scaling page to scale analog signals, the
data type of the Data port is set to the specified data format for scaling.
For more information, refer to How to Change the Data Type of Analog
Signals (FPGA Programming Blockset Guide ).
§ FPGA scaling of analog I/O signals might cause additional latency. If
the latency can be calculated during the modeling, analog I/O functions
display the total latency.

Scaling format Lets you select the data format for scaling and saturation.
§ Signed/Unsigned:
The values of the parameters for scaling and saturation are in fixed‑point
format. The signed fixed-point format reserves one bit for the sign.
You can specify the number of bits and the binary point position with the
Number of bits and Binary point (fraction width) parameters.
§ Single:
The values of the parameters for scaling and saturation are 32-bit values in
the single-precision floating‑point format with a fraction width of 24, which
complies with the IEEE 754 standard (single).
§ Double:
The values of the parameters for scaling and saturation are 64-bit values in
the double-precision floating‑point format with a fraction width of 53, which
complies with the IEEE 754 standard (double).

Number of bits This setting depends on the Scaling format setting.

§ Fixed-point format:
Lets you specify the bit width of the scaling parameters and the Data port in
the range 1 ... 64.
§ Floating-point format:
Displays the bit width of the scaling parameters and the Data port.

Binary point (fraction width) This setting depends on the Scaling format
setting.
§ Fixed-point format:
Lets you specify the binary point position of the scaling parameters and the
Data port. The position 0 represents the lowest bit position
§ Floating-point format:
Displays the fraction width of the scaling parameters and the Data port.

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Scaling factor Lets you specify the scaling factor. The scaling factor gains
the signal of the Data port or the replace value (FPGA test access) before it is
saturated.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Scaling factor parameter
will be saturated to the minimum and maximum values that the scaling format
and the hardware supports.

Scaling offset Lets you add a signal offset after the signal of the Data port is
scaled with the scaling factor.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Scaling offset parameter
will be saturated to the minimum and maximum values that the scaling format
and the hardware supports.

Saturation minimum value Lets you specify the minimum value to which
the scaled Data inport signal is saturated before it is output via an analog output
channel.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation minimum
value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

Saturation maximum value Lets you specify the maximum value to which
the scaled Data inport signal is saturated before it is output via an analog output
channel.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation maximum
value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

Multiplier latency Lets you specify the latency that is caused by the
multiplier for scaling. The multiplier is used to multiply the signal with the value
of the Scaling factor parameter.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The multiplication will be implemented without latency.
§ 1 ... 20: The multiplication will be implemented with the specified latency.
Use this value range in the exceptional case that the optimized latency cause
timing problems during the build process.

Adder latency Lets you specify the latency that is caused by the offset adder.
The offset adder is used to add the value of the Scaling offset parameter to the
signal.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The adding will be implemented without latency.
§ 1 ... 20: The adding will be implemented with the specified latency.

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Use this value range in the exceptional case that the optimized latency causes
timing problems during the build process.

Digital In/Out settings The following settings on the Scaling page are specific to the Digital In/Out 14
(In/Out-Z) and Digital In/Out 15 I/O functions.

Invert input polarity Lets you invert the measured values of the electrical
input signal:
§ Disabled:
The Data port outputs the signals as measured: A low-high transition results in
a 1 and vice versa.
§ Enabled:
The output of the Data port is inverted: A low-high transition results in a 0
and vice versa.

Invert output polarity Lets you adapt the electrical output signal:
§ Disabled:
If driven with 1, the hardware outputs a high-level signal.
If driven with 0, the hardware outputs a low-level signal.
§ Enabled:
If driven with 1, the hardware outputs a low-level signal.
If driven with 0, the hardware outputs a high-level signal.

Other I/O function settings The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

Related topics Basics

Basics on FPGA Test Access and Scaling (FPGA Programming Blockset Guide )

References

Block Settings for the MicroLabBox II Framework.................................................................... 125

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FPGA_INT_BL (MicroLabBox II)

Purpose To configure the FPGA interrupt channel when using the DS1303 (KU15P) Multi-
I/O Board framework.

Where to go from here Information in this section

Parameters Page (FPGA_INT_BL)............................................................ 192

To enable the simulation port for an interrupt.

Information in other sections

Unit Page (FPGA_INT_BL)......................................................................... 64

To specify the interrupt channel used to trigger a task in the processor
model.

Parameters Page (FPGA_INT_BL)

Purpose To enable the simulation port for an interrupt.

Description The MicroLabBox II provides 8 interrupt lines.

An interrupt is requested if the Int port is set to 1 for at least one clock cycle. If
you set the Int port to 0, the last interrupt is not released but saved. An interrupt
is edge-triggered.

Int description Block display The figure below shows the block display with the optional
simulation port.

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I/O characteristics The following table describes the ports of the block:

Port Description
Input
Int Provides the interrupt request line.
Data type: UFix_1_0
0 to 1: Interrupt is requested (edge-triggered).
0: No interrupt is requested. Last requested interrupt is saved.
Output
Sim_Int Simulates an interrupt by performing a function call to enable a function-call
subsystem.
Available only if Enable simulation port is set on the Parameters page.
Data type: Function call

Int settings Enable simulation port Lets you enable an outport for a simulated interrupt.
The Sim_Int outport is added to the block to connect it to a function-call
subsystem in the processor model.

Related topics HowTos

How to Trigger Interrupt-Driven Processor Tasks (FPGA Programming Blockset

Guide )

References

Block Settings for the MicroLabBox II Framework.................................................................... 125

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Block Settings for the SCALEXIO Frameworks

Where to go from here Information in this section

Block Settings for the DS2655 FPGA Base Board Framework.................. 196
The block dialogs provide hardware-specific settings after you load one
of the DS2655 FPGA Base Board frameworks.

Block Settings for the DS6601 FPGA Base Board Framework.................. 241
The block dialogs provide hardware-specific settings after you load the
DS6601 (KU035) FPGA Base Board framework.

Block Settings for the DS6602 FPGA Base Board Framework.................. 288
The block dialogs provide hardware-specific settings after you load the
DS6602 (KU15P) FPGA Base Board framework.

Block Settings for the DS2655M1 I/O Module Framework...................... 344

The block dialogs provide hardware-specific settings after you load the
DS2655M1 I/O Module framework.

Block Settings for the DS2655M2 I/O Module Framework...................... 368

The block dialogs provide hardware-specific settings after you load the
DS2655M2 I/O Module framework.

Block Settings for the DS6651 Multi-I/O Module Framework.................. 400

The block dialogs provide hardware-specific settings after you load the
DS6651 Multi-I/O Module framework.

Block Settings for the DS660X_MGT Framework................................... 450

The block dialogs provide hardware-specific settings after you load the
DS660X_MGT framework for SCALEXIO.

Block Settings for the Inter-FPGA Interface Framework.......................... 464

The block dialogs provide hardware-specific settings after you load the
Inter-FPGA Interface framework for SCALEXIO.

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Block Settings for the DS2655 FPGA Base Board Framework

Introduction The block dialogs provide hardware-specific settings after you load one of the
following frameworks:
§ DS2655 (7K160) FPGA Base Board
§ DS2655 (7K410) FPGA Base Board

Where to go from here Information in this section

FPGA_XDATA_READ_BL (DS2655 FPGA Base Board Settings)................. 196

To configure read access to IOCNET data in the FPGA model when using
one of the DS2655 FPGA Base Board frameworks.

FPGA_XDATA_WRITE_BL (DS2655 FPGA Base Board Settings)................ 206

To configure write access to IOCNET data in the FPGA model when using
one of the DS2655 FPGA Base Board frameworks

FPGA_IO_READ_BL (DS2655 FPGA Base Board Settings)........................ 217

To configure read access to analog and digital input signals in the FPGA
model when using one of the DS2655 FPGA Base Board frameworks.

FPGA_IO_WRITE_BL (DS2655 FPGA Base Board Settings)....................... 229

To configure write access to analog and digital output signals in
the FPGA model when using one of the DS2655 FPGA Base Board
frameworks.

FPGA_INT_BL (DS2655 FPGA Base Board Settings)................................. 239

To configure the FPGA interrupt channel when using one of the DS2655
FPGA Base Board frameworks.

FPGA_XDATA_READ_BL (DS2655 FPGA Base Board Settings)

Purpose To configure read access to IOCNET data in the FPGA model when using one of
the following frameworks:
§ DS2655 (7K160) FPGA Base Board
§ DS2655 (7K410) FPGA Base Board

Where to go from here Information in this section

Parameters Page (FPGA_XDATA_READ_BL)............................................ 197

To specify the data format and specific settings for the selected access
type.

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Information in other sections

Unit Page (FPGA_XDATA_READ_BL)......................................................... 46

To specify the general configuration for the FPGA board's processor bus
read access.

Parameters Page (FPGA_XDATA_READ_BL)

Purpose To specify the data format and specific settings for the selected access type.

Description The frameworks of the DS2655 FPGA Boards provide the following access types
that you can select on the Unit page of the block's dialog:
§ Register/Register64
If you select Register or Register64 as the access type, the data is read from
an IOCNET register. 256 registers are available with a data width of 32 bits
each and 256 registers with a data width of 64 bits each. The values are
transmitted element by element.
If you want to access data from several registers simultaneously, you can group
these registers by specifying the same group identifier for them.
Ungrouped registers are automatically combined into one register group with
group ID Ungrouped to optimize data transfer. Since register groups can be
only accessed by one task, you have to explicitly group registers which are
used by different tasks.
§ Buffer/Buffer64
If you select Buffer or Buffer64 as the access type, the data is read from
an IOCNET buffer. 32 buffers are available that provides elements with a data
width of 32 bits each and 32 buffers that provides elements with a data
width of 64 bits each. Each buffer has a variable buffer size of 1 up to 32768
elements.
§ Bus
If you select Bus as the access type, the data is read from an IOCNET buffer.
The bus access type lets you use Simulink buses to model the data exchange
between the processor and the FPGA.

There are settings that are common and settings that are specific to each access
type.

For more information, refer to Details on the access types on page 46.

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_XDATA_READ_BL block.

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Binary point position (or fraction width) This setting depends on the
format selected in the Format setting.
§ signed/unsigned
The values of the Data outport are in fixed‑point format.
You can specify the binary point position of the 32‑bit value in the range
0 … 32 and the binary point position of the 64‑bit value in the range 0 … 64.
0 represents the lowest bit position, 32 or 64 the highest bit position.
§ floating‑point
The values of the Data outport are in floating‑point format. The fraction width
is displayed.

Format Lets you select the data format of the Data outport.
§ signed/unsigned
The values of the Data outport are in fixed‑point format with or without one
bit reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
64-bit fixed-point data types are converted to double, except the data
type without a binary point (binary point position = 0). Therefore, the fixed-
point resolution of fixed-point data types with a binary point (binary point
position > 0) is restricted to 53 bits.
§ floating‑point
The values of the Data outport are in floating‑point format.
The 32‑bit data value supports the single-precision floating‑point format with a
fraction width of 24, which complies with the IEEE 754 standard (single).
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is displayed in the Binary point position (or fraction
width) setting.

Enable simulation port Lets you enable an inport for offline simulation data.
The Sim_Data inport is added to the block to connect it to any Simulink signal
used for simulation.

Simulation ports sample time Lets you specify the sample time of the
ports used for simulation, for example, Sim_Data. By default, the sample time
is inherited. You must only specify the sample time explicitly, if the modeling
situation inhibits to inherit the sample time, for example, if the corresponding
PROC block is part of an asynchronous task or is used for multiple access to the
same channel.

Register In description Block display If you specify the register access type, the block display
changes. The simulation ports are optionally displayed.

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I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Sim_Data Simulates an IOCNET data exchange including floating-point to fixed-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Output
Data Outputs a 32-bit data value to be read from a IOCNET register. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Data New Outputs a flag that indicates the changes of the register status. If the flag changes
from 0 to 1 and then to 0 again, the requested register contains a new value. The
flag is set to 1 only within one clock cycle.
Data type: UFix_1_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register In settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 197.

Register group ID Lets you specify a number in the range 1 … 63 to

create register groups. Registers which you specified with the same group ID are
read from the IOCNET sequentially and then provided to the FPGA application
simultaneously.
Specify 0 for ungrouped read access.

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Buffer In description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Sim_Data Simulates an IOCNET data exchange including floating-point to fixed-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768
Address Specifies an element in the buffer you want to read. The block requires 3 clock
cycles to update the value of the Data outport according to the specified address.
The maximum port range depends on the specified buffer size in the Parameters
page. The valid port range depends on the number of elements currently in the
buffer (see Data Count outport). If you request data from an address that is greater
than the Data Count value, the output of the Data outport is undefined. The first
element of a buffer is addressed by 0.
Data type: UFix_16_0
Output
Data Outputs a 32-bit data value to be read from an IOCNET buffer. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Data New Outputs a flag that indicates the changes of the buffer status. If the flag changes
from 0 to 1 and then to 0 again, the requested buffer contains new values and is
ready to be read. The flag is set to 1 only within one clock cycle.
Data type: UFix_1_0
Data Count Outputs the number of elements in the current buffer.
The maximum range depends on the specified buffer size. You can use the value to
define the valid range for the Address inport of 0 … (Data Count -1).
Data type: UFix_16_0

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Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Buffer In settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 197.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.
The maximum range of the Address inport depends on the buffer size.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 32-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Register64 In description Block display If you specify the register access type, the block display
changes. The simulation ports are optionally displayed.

I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Sim_Data Simulates an IOCNET data exchange including floating-point to fixed-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Output
Data Outputs a 64-bit data value to be read from an IOCNET register. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>

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Port Description
64-bit fixed-point data types are converted to double, except the data type
without a binary point (binary point position = 0). Therefore, the fixed-point
resolution of fixed-point data types with a binary point (binary point position > 0)
is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Data New Outputs a flag that indicates the changes of the register status. If the flag changes
from 0 to 1 and then to 0 again, the requested register contains a new value. The
flag is set to 1 only within one clock cycle.
Data type: UFix_1_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register64 In settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 197.

Register group ID Lets you specify a number in the range 1 … 63 to

create register groups. All registers – 32‑bit and 64‑bit registers – which you
specified with the same group ID are read from the IOCNET sequentially and
then provided to the FPGA application simultaneously.
Specify 0 for ungrouped read access.

Buffer64 In description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Sim_Data Simulates an IOCNET data exchange including floating-point to fixed-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768
Address Specifies an element in the buffer you want to read. The block requires 3 clock
cycles to update the value of the Data outport according to the specified address.
The maximum port range depends on the specified buffer size in the Parameters
page. The valid port range depends on the number of elements currently in the
buffer (see Data Count outport). If you request data from an address that is greater
than the Data Count value, the output of the Data outport is undefined. The first
element of a buffer is addressed by 0.
Data type: UFix_16_0
Output
Data Outputs a 64-bit data value to be read from an IOCNET buffer. The data format
depends on the related dialog settings.
Data type if the bus transfer mode is disabled on the Parameters page:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double, except the data type
without a binary point (binary point position = 0). Therefore, the fixed-point
resolution of fixed-point data types with a binary point (binary point position > 0)
is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Data New Outputs a flag that indicates the changes of the buffer status. If the flag changes
from 0 to 1 and then to 0 again, the requested buffer contains new values and is
ready to be read. The flag is set to 1 only within one clock cycle.
Data type: UFix_1_0
Data Count Outputs the number of elements in the current buffer.
The maximum range depends on the specified buffer size. You can use the value to
define the valid range for the Address inport of 0 … (Data Count -1).
Data type: UFix_16_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

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Buffer64 In settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 197.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.
The maximum range of the Address inport depends on the buffer size.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Bus In description Block display If you specify the access type, the block display changes. The
simulation port is optionally displayed.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Sim_Data Simulates a bus data exchange including floating-point to fixed-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768
Output
Data Outputs the signals of the Simulink bus. The data types of the signals depend
on the bus topology that is copied via Copy bus topology from corresponding
processor block or Copy bus topology from gcb on the Parameters page. The
maximum bit wide is 64 bits.
The resolution of the data types is restricted to 53 bits, because the data type of the
received bus signals from the processor application is double and the block converts
the signals to the signal data types.
Data New Outputs a flag that indicates the changes of the buffer status. If the flag changes
from 0 to 1 and then to 0 again, the requested buffer contains new values and is
ready to be read. The flag is set to 1 only within one clock cycle.
Data type: UFix_1_0

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Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Bus In settings The following dialog settings are specific for the Bus access type. For common
dialog settings, refer to Common settings on page 197.

Buffer size Displays the size of the buffer in the range 1 … 32,768. The
buffer size depends on the number of bus signals.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1,024
words. For example, a buffer with a buffer size of 1 allocates a memory
block of 1,024 words with a data width of 64-bit in the FPGA memory. This
applies to any buffer and the related swinging buffer.

Edit bus topology Opens a dialog to display and configure the

bus signals. For more information, refer to Bus Editor Dialog -
FPGA_XDATA_READ_BL/FPGA_XDATA_WRITE_BL on page 66.

Copy bus topology from corresponding processor block Lets you copy an
existing bus topology from the corresponding processor block in the processor
model. For more information, refer to How to Use Simulink Buses of the
Processor Model to Model the Processor Communication (FPGA Programming
Blockset Guide ).

Copy bus topology from gcb Lets you copy an existing FPGA bus topology
from the selected Simulink Bus Creator block, subsystem inport block, or
subsystem outport block to the Data port of the Bus In block.
You cannot copy a bus topology from the processor model, because these
topologies do not include the FPGA data types. For instructions, refer to How
to Use Simulink Buses of the FPGA Model to Model Processor Communication
(FPGA Programming Blockset Guide ).

Reset bus topology Lets you clear the bus topology of the Data port.

Related topics Basics

Modeling Processor Model Access (FPGA Programming Blockset Guide )

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FPGA_XDATA_WRITE_BL (DS2655 FPGA Base Board

Settings)
Purpose To configure write access to IOCNET data in the FPGA model when using one of
the following frameworks:
§ DS2655 (7K160) FPGA Base Board
§ DS2655 (7K410) FPGA Base Board

Where to go from here Information in this section

Parameters Page (FPGA_XDATA_WRITE_BL)........................................... 206

To specify the data format and specific settings for the selected access
type.

Information in other sections

Unit Page (FPGA_XDATA_WRITE_BL)............................................. .......... 51

To specify the general configuration for the FPGA board's processor bus
write access.

Parameters Page (FPGA_XDATA_WRITE_BL)

Purpose To specify the data format and specific settings for the selected access type.

Description The frameworks of the DS2655 FPGA Boards provide the following access types
that you can select in the Unit page of the block's dialog:
§ Register/Register64
If you select Register or Register64 as the access type, the data is written
to an IOCNET register. 256 registers are available with a data width of 32
bits each and 256 registers with a data width of 64 bits each. The values
are transmitted element by element. If you want to access data from several
registers simultaneously, you can group these registers by specifying the same
group identifier for them.
§ Buffer/Buffer64
If you select Buffer or Buffer64 as the access type, the data is written to
an IOCNET buffer. 32 buffers are available that provides elements with a data
width of 32 bits each and 32 buffers that provides elements with a data
width of 64 bits each. Each buffer has a variable buffer size of 1 up to 32768
elements.

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§ Bus
If you select Bus as the access type, the data is written to an IOCNET buffer.
The bus access type lets you use Simulink buses to model the data exchange
between the processor and the FPGA.

There are settings that are common and settings that are specific to each access
type.

For more information, refer to Details on the access types on page 51.

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_XDATA_WRITE_BL block.

Binary point position (or fraction width) This setting depends on the
format selected in the Format setting.
§ signed/unsigned
The values of the Data outport are in fixed‑point format.
You can specify the binary point position of the 32‑bit value in the range
0 … 32 and the binary point position of the 64‑bit value in the range 0 … 64.
0 represents the lowest bit position, 32 or 64 the highest bit position.
§ floating‑point
The values of the Data outport are in floating‑point format. The fraction width
is displayed.

Format Lets you select the data format of the Data inport.
§ signed/unsigned
The values of the Data inport are in fixed‑point format with or without one bit
reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
64-bit fixed-point data types are converted to double, except the data
type without a binary point (binary point position = 0). Therefore, the fixed-
point resolution of fixed-point data types with a binary point (binary point
position > 0) is restricted to 53 bits.
§ floating‑point
The values of the Data inport are in floating‑point format.
The 32‑bit data value supports the single-precision floating‑point format with a
fraction width of 24, which complies with the IEEE 754 standard (single).
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is displayed in the Binary point position (or fraction
width) setting.

Enable simulation port/Enable simulation data port Lets you enable an

outport for offline simulation data. The Sim_Data outport is added to the block
to connect it to any Simulink signal used for simulation.

Simulation ports sample time Lets you specify the sample time of the ports
used for simulation, for example, Sim_Data and Sim_Status. By default, the
sample time is inherited. You must only specify the sample time explicitly, if
the modeling situation inhibits to inherit the sample time, for example, if the

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corresponding PROC block is part of an asynchronous task or is used for multiple

access to the same channel.

Register Out description Block display If you specify the register access type, the block display
changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Data Specifies a 32-bit data value to be written to an IOCNET register. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Output
Sim_Data Simulates an IOCNET data exchange including fixed-point to floating-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1

Note

The range can be exceeded for the Data inport. The inport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register Out settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 207.

Register group ID Lets you specify a number in the range 1 … 63 to

create register groups. Registers which you specified with the same group ID are
sampled simultaneously in the FPGA application. The values form a consistent
data group that is written to the IOCNET.

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Buffer Out description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a 32-bit data value to be written to an IOCNET buffer. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Enable Specifies the current valid Data port value.
Data type: UFix_1_0
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.
Ready Explicitly specifies the buffer state as ready to send immediately, even if the buffer
is not completely filled. The data values are written to a new buffer in the following
clock cycle. While the port value is 1, the buffer switches every clock cycle. You are
therefore recommended to set the value for only one clock cycle. If the buffer is
completely filled, it is automatically switched, and the data values are stored in a
new buffer.
Data type: UFix_1_0
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready to send, even if it is not completely filled. The
buffer is switched and the data values are accessible via IOCNET in the following
clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.
Send_Ack Triggers a data transmission to IOCNET. With Send_Ack and Read_Req you can
trigger a processor synchronous data exchange.
A data transmission is always requested at the beginning of a task, before the
processor model is computed. Each time a new data transmission is requested by
Read_Req, Send_Ack must explicitly acknowledge the Data values for transmission
within one task period. To send current data, you can delay the transmission. After a
new data transmission is requested, you write the current data values to the buffer.
Then you must acknowledge the new data for transmission.

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Port Description
Available only if Enable Read_Req and Send_Ack ports for explicit data
transmit is set on the Parameters page. If Enable Read_Req and Send_Ack
ports for explicit data transmit is not set, each data transmission request will
instantly be acknowledged.
Data type: UFix_1_0
§ 0: Data values are not acknowledged for transmission.
§ 1: Current Data values are acknowledged and will be transmitted via IOCNET.
A data transmission request that is not acknowledged by Send Ack leads to task
overrun in the processor application. A task overrun will be logged as an I/O error in
the Messages page of the SCALEXIO system. The FPGA buffer that caused the task
overrun will also be logged.
Output
Sim_Data Simulates an IOCNET data exchange including fixed-point to floating-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768. The vector width depends on the specified buffer size.
Overflow Outputs a flag that indicates that a buffer overflow occurred. An overflow occurs if
the old buffer is not read completely before a new buffer is ready to be read.
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.
Data type: UFix_1_0
Sim_Status Outputs information about the simulated data exchange on the Sim_Data outport.
Available only if the access type is specified as Buffer and Enable simulation port
is set on the Parameters page.
Data type: UInt32
Data width: 3
§ Sim_Status[0]: Contains the number of valid elements in the Sim_Data vector.
§ Sim_Status[1]: Indicates whether the current buffer contains new or old values. It
is 1 if the buffer contains new values.
§ Sim_Status[2]: Indicates whether a buffer overflow occurred. At least one buffer
was not read and its data was lost before the currently read buffer was filled.
Read_Req Outputs a flag that indicates that a data transmission is requested via IOCNET. With
Read_Req and Send_Ack you can trigger a processor synchronous data exchange.
A data transmission is always requested at the beginning of a task, before the
processor model is computed. Each time a new data transmission is requested by
Read_Req, Send_Ack must explicitly acknowledge the Data values for transmission
within one task period. To send current data, you can delay the transmission. After a
new data transmission is requested, you write the current data values to the buffer.
Then you must acknowledge the new data for transmission.
Available only if Enable Read_Req and Send_Ack ports for explicit data
transmit is set on the Parameters page. If Enable Read_Req and Send_Ack
ports for explicit data transmit is not set, each data transmission request will
instantly be acknowledged.
Data type: UFix_1_0
§ 0: No data transmission is requested.
§ 1: A data transmission is requested. This value is set for one clock cycle.

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Port Description
A data transmission request that is not acknowledged by Send Ack leads to task
overrun in the processor application. A task overrun will be logged as an I/O error in
the Messages page of the SCALEXIO system. The FPGA buffer that caused the task
overrun will also be logged.

Note

The range can be exceeded for the Data inport. The inport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Buffer Out settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 207.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 32-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation status port Lets you enable an outport to get status
information about the simulation data that is available when you have enabled
the simulation data port. The Sim_Status outport is added to the block.

Enable Read_Req and Send_Ack ports for explicit data transmit Lets you
add the Read_Req and Send_Ack ports to the block to trigger a processor
synchronous data exchange.

Register64 Out description Block display If you specify the register access type, the block display
changes. The simulation ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Data Specifies a 64-bit data value to be written to an IOCNET register. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double, except the data type
without a binary point (binary point position = 0). Therefore, the fixed-point
resolution of fixed-point data types with a binary point (binary point position > 0)
is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Output
Sim_Data Simulates an IOCNET data exchange including fixed-point to floating-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1

Note

The range can be exceeded for the Data inport. The inport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register64 Out settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 207.

Register group ID Lets you specify a number in the range 1 … 63 to create

register groups. All registers – 32‑bit and 64‑bit registers – which you specified
with the same group ID are sampled simultaneously in the FPGA application. The
values form a consistent data group that is written to the IOCNET.

Buffer64 Out description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a 64-bit data value to be written to an IOCNET buffer. The data format
depends on the related dialog settings.
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double, except the data type
without a binary point (binary point position = 0). Therefore, the fixed-point
resolution of fixed-point data types with a binary point (binary point position > 0)
is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Enable Specifies the current valid Data port value.
Data type: UFix_1_0
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.
Ready Explicitly specifies the buffer state as ready to send immediately, even if the buffer
is not completely filled. The data values are written to a new buffer in the following
clock cycle. While the port value is 1, the buffer switches every clock cycle. You are
therefore recommended to set the value for only one clock cycle. If the buffer is
completely filled, it is automatically switched, and the data values are stored in a
new buffer.
Data type: UFix_1_0
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready to send, even if it is not completely filled. The
buffer is switched and the data values are accessible via IOCNET in the following
clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.
Send_Ack Triggers a data transmission to IOCNET. With Send_Ack and Read_Req you can
trigger a processor synchronous data exchange.
A data transmission is always requested at the beginning of a task, before the
processor model is computed. Each time a new data transmission is requested by
Read_Req, Send_Ack must explicitly acknowledge the Data values for transmission
within one task period. To send current data, you can delay the transmission. After a
new data transmission is requested, you write the current data values to the buffer.
Then you must acknowledge the new data for transmission.
Available only if Enable Read_Req and Send_Ack ports for explicit data
transmit is set on the Parameters page. If Enable Read_Req and Send_Ack
ports for explicit data transmit is not set, each data transmission request will
instantly be acknowledged.
Data type: UFix_1_0
§ 0: Data values are not acknowledged for transmission.
§ 1: Current Data values are acknowledged and will be transmitted via IOCNET.

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Port Description
A data transmission request that is not acknowledged by Send Ack leads to task
overrun in the processor application. A task overrun will be logged as an I/O error in
the Messages page of the SCALEXIO system. The FPGA buffer that caused the task
overrun will also be logged.
Output
Sim_Data Simulates an IOCNET data exchange including fixed-point to floating-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768. The vector width depends on the specified buffer size or
the number of bus signals.
Overflow Outputs a flag that indicates that a buffer overflow occurred. An overflow occurs if
the old buffer is not read completely before a new buffer is ready to be read.
Available only if the bus transfer mode is disabled on the Parameters page.
Data type: UFix_1_0
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.
Sim_Status Outputs information about the simulated data exchange on the Sim_Data outport.
Available only if the Enable simulation status port is set on the Parameters page.
Data type: UInt32
Data width: 3
§ Sim_Status[0]: Contains the number of valid elements in the Sim_Data vector.
§ Sim_Status[1]: Indicates whether the current buffer contains new or old values. It
is 1 if the buffer contains new values.
§ Sim_Status[2]: Indicates whether a buffer overflow occurred. At least one buffer
was not read and its data was lost before the currently read buffer was filled.
Read_Req Outputs a flag that indicates that a data transmission is requested via IOCNET. With
Read_Req and Send_Ack you can trigger a processor synchronous data exchange.
A data transmission is always requested at the beginning of a task, before the
processor model is computed. Each time a new data transmission is requested by
Read_Req, Send_Ack must explicitly acknowledge the Data values for transmission
within one task period. To send current data, you can delay the transmission. After a
new data transmission is requested, you write the current data values to the buffer.
Then you must acknowledge the new data for transmission.
Available only if Enable Read_Req and Send_Ack ports for explicit data
transmit is set on the Parameters page. If Enable Read_Req and Send_Ack
ports for explicit data transmit is not set, each data transmission request will
instantly be acknowledged.
Data type: UFix_1_0
§ 0: No data transmission is requested.
§ 1: A data transmission is requested. This value is set for one clock cycle.
A data transmission request that is not acknowledged by Send Ack leads to task
overrun in the processor application. A task overrun will be logged as an I/O error in
the Messages page of the SCALEXIO system. The FPGA buffer that caused the task
overrun will also be logged.

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Buffer64 Out settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 207.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation status port Lets you enable an outport to get status
information about the simulation data that is available when you have enabled
the simulation data port. The Sim_Status outport is added to the block.

Enable Read_Req and Send_Ack ports for explicit data transmit Lets you
add the Read_Req and Send_Ack ports to the block to trigger a processor
synchronous data exchange.

Bus Out description Block display If you specify the buffer access type, the block display changes.
The Send_Ack, Read_Req, and Sim_Data ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a Simulink bus to be transmitted to the processor application.
The data types of the signals depend on the bus topology that is set via Copy bus
topology from corresponding processor block or Copy bus topology from gcb
on the Parameters page. The maximum bit width is 64 bits.
The resolution of the data type is restricted to 53 bits, because the block converts all
data values to double for transmission.
Send_Ack Triggers a data transmission to IOCNET. With Send_Ack and Read_Req, you can
trigger a processor synchronous data exchange.
A data transmission is always requested at the beginning of a task, before the
processor model is computed. Each time a new data transmission is requested by
Read_Req, Send_Ack must explicitly acknowledge the Data values for transmission
within one task period. To send the data in the desired state, you can wait to finish
last data processing before acknowledging the data transfer.
Available only if the User acknowledged bus data transmission method is set on
the Parameters page. If you use subchannels, only the first subchannel displays the
Read_Req and Send_Ack ports.

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Port Description
Data type: UFix_1_0
§ 0: Data values are not acknowledged for transmission.
§ 1: Current Data values are acknowledged and will be transmitted via IOCNET.
A data transmission request that is not acknowledged by Send Ack leads to task
overrun in the processor application. A task overrun will be logged as an I/O error in
the Messages page of the SCALEXIO system. The FPGA buffer that caused the task
overrun will also be logged.
Output
Sim_Data Simulates a data transmission including fixed-point to floating-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Simulink bus
Read_Req Outputs a flag that indicates that a data transmission is requested from the
processor application. A data transmission is always requested at the beginning of a
task, before the processor application is computed.
Available only if the User acknowledged bus data transmission method is set on
the Parameters page. If you use subchannels, only the first subchannel displays the
Read_Req and Send_Ack ports.
Data type: UFix_1_0
§ 0: No data transmission is requested.
§ 1: A data transmission is requested. This value is set for one clock cycle.
A data transmission request automatically triggers a data transmission.

Bus Out settings The following dialog settings are specific for the Bus access type. For common
dialog settings, refer to Common settings on page 207.

Buffer size Displays the size of the buffer in the range 1 … 32,768. The
buffer size depends on the number of bus signals.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1,024
words. For example, a buffer with a buffer size of 1 allocates a memory
block of 1,024 words with a data width of 64 bits in the FPGA memory.
This applies to any buffer and the related swinging buffer.

Edit bus topology Opens a dialog to display and configure the

bus signals. For more information, refer to Bus Editor Dialog -
FPGA_XDATA_READ_BL/FPGA_XDATA_WRITE_BL on page 66.

Copy bus topology from corresponding processor block Lets you copy an
existing bus topology from the corresponding processor block in the processor
model. For more information, refer to How to Use Simulink Buses of the
Processor Model to Model the Processor Communication (FPGA Programming
Blockset Guide ).

Analyze bus topology of input Lets you set the Data inport to the bus
topology of the connected Simulink bus.

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If clicked, the FPGA Programming Blockset analyzes the connected Simulink

bus and sets the Data port to a matching bus topology. For instructions,
refer to How to Use Simulink Buses of the FPGA Model to Model Processor
Communication (FPGA Programming Blockset Guide ).

Reset bus topology Lets you clear the bus topology of the Data port.

Bus data transmission method Lets you select the method for transmitting
data to the processor application:
§ Synchronous to task method
Select this method to transmit data that is captured synchronously to the
processor task.
The FPGA application writes data to the swinging buffer when the processor
application makes a read request. After the data is written to the buffer, the
buffer swings and sends the data to the processor application.
§ Free running method
Select this method if the transmission time is crucial.
The FPGA application continuously writes data to the swinging buffer. A read
request of the processor application immediately transmits the last complete
data set of the swinging buffer to the processor application.
§ User acknowledged method
Select this method to acknowledge the data to be transmitted to the processor
application, for example, to trigger the processing of some data before it is
transmitted to the processor application.
The FPGA application writes data to the swinging buffer when you
acknowledge the data with the Send_Ack port. After the data is written to
the buffer, the buffer swings and sends the data to the processor application.
You must acknowledge each data transmission request so that data transfer is
synchronous to the processor task, as with the Synchronous to task method.
For instructions, refer to How to Configure the Bus Data Transmission Method
(FPGA Programming Blockset Guide ).

Related topics Basics

Modeling Processor Model Access (FPGA Programming Blockset Guide )

FPGA_IO_READ_BL (DS2655 FPGA Base Board Settings)

Purpose To configure read access to information signals in the FPGA model when using
one of the following frameworks:
§ DS2655 (7K160) FPGA Base Board
§ DS2655 (7K410) FPGA Base Board

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Where to go from here Information in this section

Parameters Page (FPGA_IO_READ_BL)................................................... 218

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_READ_BL).......................................................... 229

The Scaling page is empty because the I/O functions of this framework
do not support FPGA scaling.

Information in other sections

Unit Page (FPGA_IO_READ_BL)................................................................ 55

To specify the I/O type and channel to be used for read access.

Parameters Page (FPGA_IO_READ_BL)

Purpose To specify relevant settings for the selected I/O function.

Description The framework provides the I/O types APU, IFPGA32, IFPGA64, and Other, which
you can select on the Unit page of the block. The number of the available
physical connections determines the I/O functions that you can select:
§ APU Slave 1 … 6
§ CN APP Status
§ I‑FPGA In 1 … 32 (IOCNET)
§ I‑FPGA64 In 1 … 32 (IOCNET)
§ IOCNET Global Time
§ Status In
§ Subsystem Clock
§ System Clock
§ System Signal Block

Common settings No common settings.

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APU Slave description Block display If you select the APU Slave channel from the channel list, the
block display changes. For example:

I/O characteristics The following table describes the port of the block for
digital input channels:

Port Description
Input
Sim Phi Read Simulates the APU bus value for Phi Read.
Available only if Enable simulation Phi Read port is set on the
Parameters page.
Data type: Double
Data width: 1
The value range depends on the angle range of the simulated APU bus:
§ 360 ° angle range: 0 ... 32767 (215-1)
§ 720 ° angle range: 0 ... 65535 (216-1)
APU bus clock cycle: 8 ns
The range can be exceeded, and saturation is performed to a minimum or
maximum value.
Sim Rev Read Simulates the hardware input value for Rev Read.
Available only if Enable simulation Rev Read port is set on the
Parameters page.
Data type: Double
Data width: 1
The 37-bit range is -236 ... +236 - 1.
APU bus clock cycle: 8 ns
It is not possible to exceed the range.
Sim Phi Read HD Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Sim Delta Phi Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Sim Delta Phi Enable Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Sim Angle Range Simulates the angle range of the APU bus.
Available only if Enable simulation Angle Range port is set on the
Parameters page.
Data type: Double
Data width: 1
Values:
§ 0 (low): 720 ° angle range
§ 1 (high): 360 ° angle range
Output

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Port Description
Phi Read Outputs the angle value that APU Slave reads from the APU bus. The angle
value is independent from the angle range of the APU bus.
Formula for angle calculation: alpha[°] = Phi Read * 720°/216
Data type: UFix_16_0
Data width: 1
The value range depends on the angle range of the APU bus:
§ 360 ° angle range: 0 ... 32767 (215-1)
§ 720 ° angle range: 0 ... 65535 (216-1)
APU bus clock cycle: 8 ns
It is not possible to exceed the range.
Rev Read Outputs the 37 bit total revolution (rev) value for the APU bus.
Data type: Double
Data width: 1
The 37-bit range is -236 ... 236 - 1.
The APU bus clock cycle is 8 ns.
It is not possible to exceed the range.
Phi Read HD Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Delta Phi Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Delta Phi Enable Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Angle Range Outputs the angle range of the APU bus.
Data type: UFix_1_0
Data width: 1
Values:
§ 0 (low): 720 ° angle rangeThe angle range is 0° ... 720°
§ 1 (high): 360 ° angle range

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping No external connection.

APU Slave settings The Parameters page provide the following dialog setting:

Enable Phi Read HD port The Phi Read HD port is available in the block
only if you enable it.

Enable Delta Phi port The Delta Phi port is available in the block only if you
enable it.

Enable Delta Phi Enable port The Delta Phi Enable port is available in the
block only if you enable it.

Enable simulation Phi Read port The Sim Phi Read port is available in the
block only if you enable it.

Enable simulation Rev Read port The Sim Rev Read port is available in the
block only if you enable it.

Enable simulation Phi Read HD port The Sim Phi Read HD port is
available in the block only if you enable it.

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Enable simulation Delta Phi port The Sim Delta Phi port is available in the
block only if you enable it.

Enable simulation Delta Phi Enable port The Sim Delta Phi Enable port is
available in the block only if you enable it.

Enable simulation Angle Range port The Sim Angle Range port is
available in the block only if you enable it.

Angle range For the slave APU, you can inherit the angle range of the APU
bus or you specify a local angle range independent from the APU bus. The
following table shows you the possible combinations of angle range settings.

APU Bus Slave APU Resulting Angle Range of the Slave

Setting Setting APU
360° Inherit 360°
720° 720°
360° 360° 360°
720° 720° 1)
720° 360° 360° 2)
720° 720°
1) Two engine cycles are required to run through the 720 ° angle range. If you simulate a
four-stroke piston engine, for example, the angle values of the function block are not
clearly related to the camshaft position.
2) One engine cycle runs twice through the 360 ° angle range.

CN App Status description Block display If you select the CN App Status channel from the channel list,
the block display changes.

I/O characteristics The following table describes the port of the block:

Port Description
Output
Status Outputs the state of the processor application.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The processor application is stopped.
§ 1: The processor application is running.

I/O mapping No external connection.

CN App Status settings None

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I-FPGA In 1 … 32 (IOCNET) Block display If you select the I-FPGA In (IOCNET) channel from the channel
description list, the block display changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Address Specifies a data value in the IOCNET buffer to be read. The block requires
one clock cycle to update the value of the Data outport with the data value
of the specified address.
Data type: UFix_16_0
Data width: 1
The maximum address range depends on the Buffer size on the Parameters
page. The address range with valid data values can be derived from the value
of the Data Count port.
Sim Data Simulates a data exchange between two FPGA boards via IOCNET. The
provided data values are converted to the data format of the Data port
and written to a simulated IOCNET buffer.
Available only if the Enable simulation data port is set on the Parameters
page.
Data type: Double
Data width: 1 … 1024
Range: Single precision value range
Sim Data New Simulates the reception of new data values.
Available only if the Enable simulation data new port is set on the
Parameters page.
Data type: Double
Data width: 1
Values:
§ 0: The reception of new data values is not simulated.
§ 1: The Data New port changes from 0 to 1 for one clock cycle to indicate
new data values.
Output
Data Outputs a 32-bit raw data value from the specified address of the IOCNET
buffer.
Data type: UFix_32_0
Data width: 1

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Port Description
Data New Outputs a flag that indicates the update of the Data port.
Data type: UFix_1_0
Data width: 1
If the flag changes from 0 to 1 and then to 0 again, the requested buffer
contains new values and is ready to be read. The flag is set to 1 within only
one clock cycle.
Data Count Outputs the number of elements in the current IOCNET buffer. You can use
the value to define the valid range for the Address port from 0 to (Data
Count -1).
Data type: UFix_16_0
Data width: 1
The maximum value range depends on the Buffer size on the Parameters
page.

Note

You can transfer any data type with a bit width of up to 32 Bit via inter-
FPGA over IOCNET. Use the Reinterpret block from the HDL library of the
AMD Vitis Model Composer to change your data type to UFix_32_0 and
vice versa. Reinterpreting data types does not cost any hardware or latency.
The range can be exceeded for the Data outport. The outport's value is
then cast to UFix_32_0.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I-FPGA In 1 … 32 (IOCNET) The following dialog settings are specific for the I-FPGA In (IOCNET) I/O
settings function. For common dialog settings, refer to Common settings on page 218.

Buffer size Lets you specify the size of the IOCNET buffer in the range
1 … 1024. The maximum range of the Address inport depends on the buffer
size.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 32-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation data port Lets you enable an inport for offline simulation
data.
The Sim Data inport is added to the block.

Enable simulation data new port Lets you enable an inport for the offline
simulating of new data values at the Data outport.
The Sim Data New inport is added to the block.

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I-FPGA64 1 … 32 In (IOCNET) Block display If you select the I-FPGA64 Out (IOCNET) channel from the
description channel list, the block display changes. The simulation ports are displayed
optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Address Specifies a data value in the IOCNET buffer to be read. The block requires
one clock cycle to update the value of the Data outport with the data value
of the specified address.
Data type: UFix_16_0
Data width: 1
The maximum address range depends on the Buffer size on the Parameters
page. The address range with valid data values can be derived from the value
of the Data Count port.
Sim Data Simulates a data exchange between two FPGA boards via IOCNET. The
provided data values are converted to the data format of the Data port
and written to a simulated IOCNET buffer.
Available only if the Enable simulation data port is set on the Parameters
page.
Data type: Double
Data width: 1 … 512
Range: Double precision value range
Sim Data New Simulates the reception of new data values.
Available only if the Enable simulation data new port is set on the
Parameters page.
Data type: Double
Data width: 1
Values:
§ 0: The reception of new data values is not simulated.
§ 1: The Data New port changes from 0 to 1 for one clock cycle to indicate
new data values.
Output
Data Outputs a 64-bit raw data value from the specified address of the IOCNET
buffer.
Data type: UFix_64_0
Data width: 1

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Port Description
Data New Outputs a flag that indicates the update of the Data port.
Data type: UFix_1_0
Data width: 1
If the flag changes from 0 to 1 and then to 0 again, the requested buffer
contains new values and is ready to be read. The flag is set to 1 within only
one clock cycle.
Data Count Outputs the number of elements in the current IOCNET buffer. You can use
the value to define the valid range for the Address port from 0 to (Data
Count -1).
Data type: UFix_16_0
Data width: 1
The maximum value range depends on the Buffer size on the Parameters
page.

Note

You can transfer any data type with a bit width of up to 64 Bit via inter-
FPGA over IOCNET. Use the Reinterpret block from the HDL library of the
AMD Vitis Model Composer to change your data type to UFix_64_0 and
vice versa. Reinterpreting data types does not cost any hardware or latency.
The range can be exceeded for the Data outport. The outport's value is
then cast to UFix_64_0.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I-FPGA64 In 1 … 32 (IOCNET) The following dialog settings are specific for the I-FPGA64 In (IOCNET) I/O
settings function. For common dialog settings, refer to Common settings on page 218.

Buffer size Lets you specify the size of the IOCNET buffer in the range
1 … 512. The maximum range of the Address inport depends on the buffer
size.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64 bits in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation data port Lets you enable an inport for offline simulation
data.
The Sim Data inport is added to the block.

Enable simulation data new port Lets you enable an inport for the offline
simulating of new data values at the Data outport.
The Sim Data New inport is added to the block.

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IOCNET Global Time Block display If you select the IOCNET Global Time channel from the channel
description list, the block display changes.

I/O characteristics The following table describes the port of the block:

Port Description
Output
Time Outputs the number of hardware ticks that occurred since the SCALEXIO system
power was switched to on. If you use a multiprocessor system, the value is set to
zero each time an application is reloaded and restarted.
Data type: 56 bit
Tick step-width: 8.5 ns

I/O mapping No external connection.

IOCNET Global Time settings None

Status In description Block display If you select the Status In channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Output
Init Done Outputs the state of the initialization sequence that is started after programming
the FPGA.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Initialization sequence is in progress.
§ 1: Initialization sequence has finished.

I/O mapping No external connection.

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Status In settings None

Subsystem Clock description Block display If you select the Subsystem Clock channel from the channel
list, the block display changes.

I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Output
Subsystem Outputs the clock signal of the selected subsystem clock domain. You specify the
Clock subsystem clock domain in the FPGA Setup block. Refer to How to Use Multiple
Clock Domains for FPGA Modeling (FPGA Programming Blockset Guide ).
Data type: UFix_1_0
Data width: 1

Multiple clock domain support This block is intended to be used in a user

clock domain with an individual clock period.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping No external connection.

Subsystem Clock settings None

System Clock description Block display If you select the System Clock channel from the channel list,
the block display changes.

I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Output
System Clock Outputs the clock signal of the FPGA (base clock rate).
Data type: UFix_1_0
Data width: 1

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Multiple clock domain support This block is intended to be used in a user

clock domain with an individual clock period.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping No external connection.

System Clock settings None

System Signal Block Block display If you select the System Signal Block channel from the channel
description list, the block display changes.

I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Output
System Clock Outputs the clock signal of the FPGA (base clock rate).
Data type: UFix_1_0
Data width: 1
Init Done Outputs the state of the initialization sequence that is started after programming
the FPGA.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Initialization sequence is in progress.
§ 1: Initialization sequence has finished.
CN App Outputs the state of the processor application.
Status Data type: UFix_1_0
Data width: 1
Values:
§ 0: The processor application is stopped.
§ 1: The processor application is running.
Opto_Ready Indicates whether an MGT module is ready for data exchange.
The port value remains 0, because the used dSPACE hardware does not support
MGT modules.

Multiple clock domain support This block is intended to be used in a user

clock domain with an individual clock period.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

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I/O mapping No external connection.

System Signal Block settings None

Related topics Basics

Modeling Inter-FPGA Communication via IOCNET (FPGA Programming Blockset

Guide )

Scaling Page (FPGA_IO_READ_BL)

Description The Scaling page is empty because the I/O functions of this framework do not
support FPGA scaling.

Frameworks with scaling The frameworks of the I/O modules support FPGA scaling:
support § DS2655M1 I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 350
§ Scaling Page (FPGA_IO_WRITE_BL) on page 363
§ DS2655M2 Digital I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 377
§ Scaling Page (FPGA_IO_WRITE_BL) on page 397
§ DS6651 Multi-I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 413
§ Scaling Page (FPGA_IO_WRITE_BL) on page 445

Related topics Basics

Basics on FPGA Test Access and Scaling (FPGA Programming Blockset Guide )

FPGA_IO_WRITE_BL (DS2655 FPGA Base Board Settings)

Purpose To configure write access to information signals in the FPGA model when using
one of the following frameworks:
§ DS2655 (7K160) FPGA Base Board
§ DS2655 (7K410) FPGA Base Board

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Where to go from here Information in this section

Parameters Page (FPGA_IO_WRITE_BL).................................................. 230

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_WRITE_BL)........................................................ 238

The Scaling page is empty because the I/O functions of this framework
do not support FPGA scaling.

Information in other sections

Unit Page (FPGA_IO_WRITE_BL)............................................................... 60

To specify the I/O type and channel to be used for write access.

Parameters Page (FPGA_IO_WRITE_BL)

Purpose To specify relevant settings for the selected I/O function.

Description The framework provides the I/O types APU, IFPGA32, IFPGA64, and Other, which
you can select on the Unit page of the block. The number of the available
physical connections determines the I/O functions that you can select:
§ APU Master 1 … APU Master 6
§ I-FPGA Out (IOCNET)
§ I-FPGA64 Out (IOCNET)
§ LED Out
§ User Clock Out 1 … 32

Common settings None

APU Master 1 … 6 description Block display If you select the APU Master channel from the channel list, the
block display changes. For example:

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I/O characteristics The following table describes the ports of the block:

Port Description
Input
Velocity Specifies a velocity value in degree/second to be applied as APU Master
speed.
The value will be applied if Set Velocity is 1 (high) and Busy is 0 (low).
Data type: Fix_32_10
Data width: 1
Range: -1,200,000 °/s ... +1,200,000 °/s
It is not possible to exceed the range. The port is saturated at the higher or
lower limit.
Set Velocity Specifies the current value of Velocity as new velocity value.
The new value is set only if Set Velocity is 1 (high) and Busy is 0 (low).
Data type: UFix_1_0
Data width: 1
To distribute and execute a new velocity value takes at least 10 μs,
depending on the IOCNET structure.
Output
Phi Read Outputs the angle counter value of the APU that the APU Master writes to
the APU bus. The step size of the angle counter is approximately 0.011°. The
step size is independent from the angle range.
Formula for angle calculation: alpha[°] = Phi Read * 720°/216
Data type: UFix_16_0
Data width: 1
The value range depends on the Angle range on the Parameters page:
§ 360 ° angle range: 0 ... 32767 (215-1)
§ 720 ° angle range: 0 ... 65535 (216-1)
APU bus clock cycle: 8 ns
It is not possible to exceed the range.
Rev Read Outputs the 37 bit total revolution (rev) value that the APU Master reads
from the APU bus.
Data type: Fix_37_0
Data width: 1
The 37-bit range is -236 ... 236 - 1.
APU bus clock cycle: 8 ns
It is not possible to exceed the range.
Phi Read HD Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Delta Phi Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Delta Phi Enable Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Angle Range Outputs the angle range of the APU bus. You set the Angle range on the
Parameters page.
Data type: UFix_1_0
Data width: 1
Values:
§ 0 (low): 720 ° angle range
§ 1 (high): 360 ° angle range

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Port Description
Busy Outputs whether APU Master is busy to set the last velocity value.
Data type: UFix_1_0
Data width: 1
If Busy is 1 (high), new velocity values cannot be set.
Busy stays active for at least 10 µs depending on the IOCNET structure.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping No external connection.

APU Master 1 … 6 settings The Parameters page provide the following dialog setting:

Angle range Lets you select the angle range of the APU in degree.
§ 360: The angle range is 360° and cannot be changed in ConfigurationDesk.
§ 720: The angle range is 720° and cannot be changed in ConfigurationDesk.
§ Individual: The Angle range property of the FPGA custom function block in
ConfigurationDesk lets you set the angle range of the APU. The default value
is 720°.

Initial position Lets you set the initial APU master position in degree.
§ Value range: -1440° ... +1440°

Enable advanced ports The internal ports for the dSPACE Electric Motor HIL
Solution are available in the block only if you enable it.

I-FPGA Out (IOCNET) Block display If you select the I-FPGA Out (IOCNET) channel from the
description channel list, the block display changes. The simulation ports are displayed
optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a 32-bit raw data value to be written to an IOCNET buffer.
Data type: UFix_32_0
Data width: 1

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Port Description
Enable Specifies the current valid Data port value.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The Data value to be written is not stored in the IOCNET buffer.
§ 1: The Data value to be written is stored in the IOCNET buffer. The value of the
current clock cycle is used.
Ready Explicitly specifies the buffer state as ready to send immediately, even if the buffer
is not completely filled. The data values are written to a new buffer in the following
clock cycle. While the port value is 1, the buffer switches every clock cycle. You are
therefore recommended to set the value for only one clock cycle. If the buffer is
completely filled, it is automatically switched, and the data values are stored in a
new buffer.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready to send, even if it is not completely filled.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.
Send Triggers a data transmission via IOCNET.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Data values are not acknowledged for transmission.
§ 1: Current Data values are acknowledged and will be transmitted via IOCNET.
Output
Overflow Outputs a flag that indicates that a buffer overflow occurred. An overflow occurs
when the new buffer is triggered for transmission and the old buffer was not sent
completely.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.
Sim Data Simulates a data exchange between two FPGA boards via IOCNET. The port
provides the data values that are written to a simulated IOCNET buffer, including
fixed-point to floating-point data conversion.
Available only if the Enable simulation data port is set on the Parameters page.
Data type: Double
Data width: 1 … 1024, depends on the Buffer size parameter.
Range: Single precision value range

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Port Description
Sim Data New Simulates the update of data values provided by the Sim Data outport.
Available only if the Enable simulation data new port is set on the Parameters
page.
Data type: Double
Data width: 1
A transition from 0 to 1 indicates that the Sim Data outport provides new data.
Sim Status Outputs information about the simulated data exchange on the Sim Data outport.
Available only if the Enable simulation status port is set on the Parameters
page.
Data type: UInt32
Data width: 3
§ Sim Status[0]: Contains the number of valid elements in the Sim Data vector.
§ Sim Status[1]: Indicates whether the current buffer contains new or old values.
The status is 1 if the buffer contains new values.
§ Sim Status[2]: Indicates whether a buffer overflow occurred. At least one buffer
was not read and its data was lost before the currently read buffer was filled.

Note

You can transfer any data type with a bit width of up to 32 Bit via inter-
FPGA over IOCNET. Use the Reinterpret block from the HDL library of the
AMD Vitis Model Composer to change your data type to UFix_32_0 and
vice versa. Reinterpreting data types does not cost any hardware or latency.
The range of the Data inport can be exceeded. The value of the inport is
then cast to the raw data format UFix_32_0.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I-FPGA Out 1 … 32 (IOCNET) The Parameters page provide the following dialog setting:
settings
Buffer size Lets you specify the size of the IOCNET buffer in the range
1 … 1024.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 32-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation data port Lets you enable an outport for offline
simulation data.
The Sim Data inport is added to the block.

Enable simulation data new port Lets you enable an outport for the offline
simulating of new data values at the Sim Data inport.
The Sim Data New outport is added to the block.

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Enable simulation status port Lets you enable an outport to get status
information about the simulation data that is available when you enabled a
simulation port. The Sim Status outport is added to the block.

I-FPGA64 Out (IOCNET) Block display If you select the I-FPGA64 Out (IOCNET) channel from the
description channel list, the block display changes. The simulation ports are displayed
optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a 64-bit raw data value to be written to an IOCNET buffer.
Data type: UFix_64_0
Data width: 1
Enable Specifies the current valid Data port value.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The Data value to be written is not stored in the IOCNET buffer.
§ 1: The Data value to be written is stored in the IOCNET buffer. The value of the
current clock cycle is used.
Ready Explicitly specifies the buffer state as ready to send immediately, even if the buffer
is not completely filled. The data values are written to a new buffer in the following
clock cycle. While the port value is 1, the buffer switches every clock cycle. You are
therefore recommended to set the value for only one clock cycle. If the buffer is
completely filled, it is automatically switched, and the data values are stored in a
new buffer.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready to send, even if it is not completely filled.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.

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Port Description
Send Triggers a data transmission via IOCNET.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Data values are not acknowledged for transmission.
§ 1: Current Data values are acknowledged and will be transmitted via IOCNET.
Output
Overflow Outputs a flag that indicates that a buffer overflow occurred. An overflow occurs
when the new buffer is triggered for transmission and the old buffer was not sent
completely.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.
Sim_Data Simulates a data exchange between two FPGA boards via IOCNET. The port
provides the data values that are written to a simulated IOCNET buffer.
Available only if the Enable simulation data port is set on the Parameters page.
Data type: Double
Data width: 1 … 512, depends on the Buffer size parameter.
Range: Double precision value range
Sim_Data Simulates the update of data values provided by the Sim Data outport.
New Available only if the Enable simulation data new port is set on the Parameters
page.
Data type: Double
Data width: 1
A transition from 0 to 1 indicates that the Sim Data outport provides new data.
Sim Status Outputs information about the simulated data exchange on the Sim Data outport.
Available only if the Enable simulation status port is set on the Parameters
page.
Data type: UInt32
Data width: 3
§ Sim Status[0]: Contains the number of valid elements in the Sim Data vector.
§ Sim Status[1]: Indicates whether the current buffer contains new or old values.
The status is 1 if the buffer contains new values.
§ Sim Status[2]: Indicates whether a buffer overflow occurred. At least one buffer
was not read and its data was lost before the currently read buffer was filled.

Note

You can transfer any data type with a bit width of up to 64 Bit via inter-
FPGA over IOCNET. Use the Reinterpret block from the HDL library of the
AMD Vitis Model Composer to change your data type to UFix_64_0 and
vice versa. Reinterpreting data types does not cost any hardware or latency.
The range of the Data inport can be exceeded. The value of the inport is
then cast to the raw data format UFix_64_0.

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Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I-FPGA64 Out 1 … 32 The Parameters page provides the following dialog setting:
(IOCNET) settings
Buffer size Lets you specify the size of the IOCNET buffer in the range
1 … 512.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64 bits in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation data port Lets you enable an outport for offline
simulation data.
The Sim Data inport is added to the block.

Enable simulation data new port Lets you enable an outport for the offline
simulating of new data values at the Sim Data inport.
The Sim Data New outport is added to the block.

Enable simulation status port Lets you enable an outport to get status
information about the simulation data that is available when you enabled a
simulation port. The Sim Status outport is added to the block.

LED Out description Block display If you select the LED Out channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Controls the LED on the DS2655 FPGA Base Board.
Data type: UFix_1_0
Values:
§ 0: LED lights green.
§ 1: LED lights orange.

If the value of the Data inport exceeds the specified data width, only the lowest
bit is used (=1).

I/O mapping No external connection.

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LED Out settings None

User Clock Out 1 … 32 Block display If you select the User Clock Out channel from the channel list,
description the block display changes.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
User Clock Clock signal for the clock domain used within the subsystem to which the block
belongs. For more information, refer to Using Multiple Clock Domains for FPGA
Modeling (FPGA Programming Blockset Guide ).
Data type: UFix_1_0
Data width: 1

I/O mapping No external connection.

User Clock Out 1 … 32 The Parameters page provides the following dialog setting:
settings
User clock period Lets you specify the expected clock period used within the
subsystem to which the block belongs. A common value for the clock period is in
the range 20 ns ... 4 ns (50 MHz ... 250 MHz).
The value is used during the build process when no user clock is available, for
example, to specify timing constraints.

User clock offline simulation period Lets you specify the clock period to be
used in offline simulation mode. The value must be greater than or equal to the
value of the User clock period parameter.

Related topics Basics

Modeling Inter-FPGA Communication via IOCNET (FPGA Programming Blockset

Guide )

Scaling Page (FPGA_IO_WRITE_BL)

Description The Scaling page is empty because the I/O functions of this framework do not
support FPGA scaling.

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Frameworks with scaling The frameworks of the I/O modules support FPGA scaling:
support § DS2655M1 I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 350
§ Scaling Page (FPGA_IO_WRITE_BL) on page 363
§ DS2655M2 Digital I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 377
§ Scaling Page (FPGA_IO_WRITE_BL) on page 397
§ DS6651 Multi-I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 413
§ Scaling Page (FPGA_IO_WRITE_BL) on page 445

Related topics Basics

Basics on FPGA Test Access and Scaling (FPGA Programming Blockset Guide )

FPGA_INT_BL (DS2655 FPGA Base Board Settings)

Purpose To configure the FPGA interrupt channel when using one of the following
frameworks:
§ DS2655 (7K160) FPGA Base Board
§ DS2655 (7K410) FPGA Base Board

Where to go from here Information in this section

Parameters Page (FPGA_INT_BL)............................................................ 239

To enable the simulation port for an interrupt.

Information in other sections

Unit Page (FPGA_INT_BL)......................................................................... 64

To specify the interrupt channel used to trigger a task in the processor
model.

Parameters Page (FPGA_INT_BL)

Purpose To enable the simulation port for an interrupt.

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Description The DS2655 FPGA Base Board provides 8 interrupt lines.

An interrupt is requested if the Int port is set to 1 for at least one clock cycle. If
you set the Int port to 0, the last interrupt is not released but saved. An interrupt
is edge-triggered.

Int description Block display The figure below shows the block display with the optional
simulation port.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Int Provides the interrupt request line.
Data type: UFix_1_0
0 to 1: Interrupt is requested (edge-triggered).
0: No interrupt is requested. Last requested interrupt is saved.
Output
Sim_Int Simulates an interrupt by performing a function call to enable a function-call
subsystem.
Available only if Enable simulation port is set on the Parameters page.
Data type: Function call

Int settings Enable simulation port Lets you enable an outport for a simulated interrupt.
The Sim_Int outport is added to the block to connect it to a function-call
subsystem in the processor model.

Related topics HowTos

How to Trigger Interrupt-Driven Processor Tasks (FPGA Programming Blockset

Guide )

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Block Settings for the DS6601 FPGA Base Board Framework

Introduction The block dialogs provide hardware-specific settings after you load the DS6601
(KU035) FPGA Base Board framework.

Where to go from here Information in this section

FPGA_XDATA_READ_BL (DS6601 FPGA Base Board Settings)................. 241

To configure read access to IOCNET data in the FPGA model when using
the DS6601 (KU035) FPGA Base Board framework.

FPGA_XDATA_WRITE_BL (DS6601 FPGA Base Board Settings)................ 251

To configure write access to IOCNET data in the FPGA model when using
the DS6601 (KU035) FPGA Base Board framework.

FPGA_IO_READ_BL (DS6601 FPGA Base Board Settings)........................ 262

To configure read access to analog and digital input signals in the FPGA
model when using the DS6601 (KU035) FPGA Base Board framework.

FPGA_IO_WRITE_BL (DS6601 FPGA Base Board Settings)....................... 276

To configure write access to analog and digital output signals in
the FPGA model when using the DS6601 (KU035) FPGA Base Board
framework.

FPGA_INT_BL (DS6601 FPGA Base Board Settings)................................. 286

To configure the FPGA interrupt channel when using the DS6601
(KU035) FPGA Base Board framework.

FPGA_XDATA_READ_BL (DS6601 FPGA Base Board Settings)

Purpose To configure read access to IOCNET data in the FPGA model when using the
DS6601 (KU035) FPGA Base Board framework.

Where to go from here Information in this section

Parameters Page (FPGA_XDATA_READ_BL)............................................ 242

To specify the data format and specific settings for the selected access
type.

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Information in other sections

Unit Page (FPGA_XDATA_READ_BL)......................................................... 46

To specify the general configuration for the FPGA board's processor bus
read access.

Parameters Page (FPGA_XDATA_READ_BL)

Purpose To specify the data format and specific settings for the selected access type.

Description The DS6601 (KU035) FPGA Base Board framework provides the following access
types that you can select on the Unit page of the block's dialog:
§ Register/Register64
If you select Register or Register64 as the access type, the data is read from
an IOCNET register. 256 registers are available with a data width of 32 bits
each and 256 registers with a data width of 64 bits each. The values are
transmitted element by element.
If you want to access data from several registers simultaneously, you can group
these registers by specifying the same group identifier for them.
Ungrouped registers are automatically combined into one register group with
group ID Ungrouped to optimize data transfer. Since register groups can be
only accessed by one task, you have to explicitly group registers which are
used by different tasks.
§ Buffer/Buffer64
If you select Buffer or Buffer64 as the access type, the data is read from
an IOCNET buffer. 32 buffers are available that provides elements with a data
width of 32 bits each and 32 buffers that provides elements with a data
width of 64 bits each. Each buffer has a variable buffer size of 1 up to 32768
elements.
§ Bus
If you select Bus as the access type, the data is read from an IOCNET buffer.
The bus access type lets you use Simulink buses to model the data exchange
between the processor and the FPGA.

There are settings that are common and settings that are specific to each access
type.

For more information, refer to Details on the access types on page 46.

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_XDATA_READ_BL block.

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Binary point position (or fraction width) This setting depends on the
format selected in the Format setting.
§ signed/unsigned
The values of the Data outport are in fixed‑point format.
You can specify the binary point position of the 32‑bit value in the range
0 … 32 and the binary point position of the 64‑bit value in the range 0 … 64.
0 represents the lowest bit position, 32 or 64 the highest bit position.
§ floating‑point
The values of the Data outport are in floating‑point format. The fraction width
is displayed.

Format Lets you select the data format of the Data outport.
§ signed/unsigned
The values of the Data outport are in fixed‑point format with or without one
bit reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
64-bit fixed-point data types are converted to double, except the data
type without a binary point (binary point position = 0). Therefore, the fixed-
point resolution of fixed-point data types with a binary point (binary point
position > 0) is restricted to 53 bits.
§ floating‑point
The values of the Data outport are in floating‑point format.
The 32‑bit data value supports the single-precision floating‑point format with a
fraction width of 24, which complies with the IEEE 754 standard (single).
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is displayed in the Binary point position (or fraction
width) setting.

Enable simulation port Lets you enable an inport for offline simulation data.
The Sim_Data inport is added to the block to connect it to any Simulink signal
used for simulation.

Simulation ports sample time Lets you specify the sample time of the
ports used for simulation, for example, Sim_Data. By default, the sample time
is inherited. You must only specify the sample time explicitly, if the modeling
situation inhibits to inherit the sample time, for example, if the corresponding
PROC block is part of an asynchronous task or is used for multiple access to the
same channel.

Register In description Block display If you specify the register access type, the block display
changes. The simulation ports are optionally displayed.

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I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Sim_Data Simulates an IOCNET data exchange including floating-point to fixed-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Output
Data Outputs a 32-bit data value to be read from a IOCNET register. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Data New Outputs a flag that indicates the changes of the register status. If the flag changes
from 0 to 1 and then to 0 again, the requested register contains a new value. The
flag is set to 1 only within one clock cycle.
Data type: UFix_1_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register In settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 242.

Register group ID Lets you specify a number in the range 1 … 63 to

create register groups. Registers which you specified with the same group ID are
read from the IOCNET sequentially and then provided to the FPGA application
simultaneously.
Specify 0 for ungrouped read access.

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Buffer In description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Sim_Data Simulates an IOCNET data exchange including floating-point to fixed-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768
Address Specifies an element in the buffer you want to read. The block requires 3 clock
cycles to update the value of the Data outport according to the specified address.
The maximum port range depends on the specified buffer size in the Parameters
page. The valid port range depends on the number of elements currently in the
buffer (see Data Count outport). If you request data from an address that is greater
than the Data Count value, the output of the Data outport is undefined. The first
element of a buffer is addressed by 0.
Data type: UFix_16_0
Output
Data Outputs a 32-bit data value to be read from an IOCNET buffer. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Data New Outputs a flag that indicates the changes of the buffer status. If the flag changes
from 0 to 1 and then to 0 again, the requested buffer contains new values and is
ready to be read. The flag is set to 1 only within one clock cycle.
Data type: UFix_1_0
Data Count Outputs the number of elements in the current buffer.
The maximum range depends on the specified buffer size. You can use the value to
define the valid range for the Address inport of 0 … (Data Count -1).
Data type: UFix_16_0

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Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Buffer In settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 242.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.
The maximum range of the Address inport depends on the buffer size.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 32-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Register64 In description Block display If you specify the register access type, the block display
changes. The simulation ports are optionally displayed.

I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Sim_Data Simulates an IOCNET data exchange including floating-point to fixed-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Output
Data Outputs a 64-bit data value to be read from an IOCNET register. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>

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Port Description
64-bit fixed-point data types are converted to double, except the data type
without a binary point (binary point position = 0). Therefore, the fixed-point
resolution of fixed-point data types with a binary point (binary point position > 0)
is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Data New Outputs a flag that indicates the changes of the register status. If the flag changes
from 0 to 1 and then to 0 again, the requested register contains a new value. The
flag is set to 1 only within one clock cycle.
Data type: UFix_1_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register64 In settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 242.

Register group ID Lets you specify a number in the range 1 … 63 to

create register groups. All registers – 32‑bit and 64‑bit registers – which you
specified with the same group ID are read from the IOCNET sequentially and
then provided to the FPGA application simultaneously.
Specify 0 for ungrouped read access.

Buffer64 In description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Sim_Data Simulates an IOCNET data exchange including floating-point to fixed-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768
Address Specifies an element in the buffer you want to read. The block requires 3 clock
cycles to update the value of the Data outport according to the specified address.
The maximum port range depends on the specified buffer size in the Parameters
page. The valid port range depends on the number of elements currently in the
buffer (see Data Count outport). If you request data from an address that is greater
than the Data Count value, the output of the Data outport is undefined. The first
element of a buffer is addressed by 0.
Data type: UFix_16_0
Output
Data Outputs a 64-bit data value to be read from an IOCNET buffer. The data format
depends on the related dialog settings.
Data type if the bus transfer mode is disabled on the Parameters page:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double, except the data type
without a binary point (binary point position = 0). Therefore, the fixed-point
resolution of fixed-point data types with a binary point (binary point position > 0)
is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Data New Outputs a flag that indicates the changes of the buffer status. If the flag changes
from 0 to 1 and then to 0 again, the requested buffer contains new values and is
ready to be read. The flag is set to 1 only within one clock cycle.
Data type: UFix_1_0
Data Count Outputs the number of elements in the current buffer.
The maximum range depends on the specified buffer size. You can use the value to
define the valid range for the Address inport of 0 … (Data Count -1).
Data type: UFix_16_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

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Buffer64 In settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 242.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.
The maximum range of the Address inport depends on the buffer size.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Bus In description Block display If you specify the access type, the block display changes. The
simulation port is optionally displayed.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Sim_Data Simulates a bus data exchange including floating-point to fixed-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768
Output
Data Outputs the signals of the Simulink bus. The data types of the signals depend
on the bus topology that is copied via Copy bus topology from corresponding
processor block or Copy bus topology from gcb on the Parameters page. The
maximum bit wide is 64 bits.
The resolution of the data types is restricted to 53 bits, because the data type of the
received bus signals from the processor application is double and the block converts
the signals to the signal data types.
Data New Outputs a flag that indicates the changes of the buffer status. If the flag changes
from 0 to 1 and then to 0 again, the requested buffer contains new values and is
ready to be read. The flag is set to 1 only within one clock cycle.
Data type: UFix_1_0

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Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Bus In settings The following dialog settings are specific for the Bus access type. For common
dialog settings, refer to Common settings on page 242.

Buffer size Displays the size of the buffer in the range 1 … 32,768. The
buffer size depends on the number of bus signals.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1,024
words. For example, a buffer with a buffer size of 1 allocates a memory
block of 1,024 words with a data width of 64-bit in the FPGA memory. This
applies to any buffer and the related swinging buffer.

Edit bus topology Opens a dialog to display and configure the

bus signals. For more information, refer to Bus Editor Dialog -
FPGA_XDATA_READ_BL/FPGA_XDATA_WRITE_BL on page 66.

Copy bus topology from corresponding processor block Lets you copy an
existing bus topology from the corresponding processor block in the processor
model. For more information, refer to How to Use Simulink Buses of the
Processor Model to Model the Processor Communication (FPGA Programming
Blockset Guide ).

Copy bus topology from gcb Lets you copy an existing FPGA bus topology
from the selected Simulink Bus Creator block, subsystem inport block, or
subsystem outport block to the Data port of the Bus In block.
You cannot copy a bus topology from the processor model, because these
topologies do not include the FPGA data types. For instructions, refer to How
to Use Simulink Buses of the FPGA Model to Model Processor Communication
(FPGA Programming Blockset Guide ).

Reset bus topology Lets you clear the bus topology of the Data port.

Related topics Basics

Modeling Processor Model Access (FPGA Programming Blockset Guide )

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FPGA_XDATA_WRITE_BL (DS6601 FPGA Base Board

Settings)
Purpose To configure write access to IOCNET data in the FPGA model when using the
DS6601 (KU035) FPGA Base Board framework.

Where to go from here Information in this section

Parameters Page (FPGA_XDATA_WRITE_BL)........................................... 251

To specify the data format and specific settings for the selected access
type.

Information in other sections

Unit Page (FPGA_XDATA_WRITE_BL)............................................. .......... 51

To specify the general configuration for the FPGA board's processor bus
write access.

Parameters Page (FPGA_XDATA_WRITE_BL)

Purpose To specify the data format and specific settings for the selected access type.

Description The DS6601 (KU035) FPGA Base Board framework provides the following access
types that you can select in the Unit page of the block's dialog:
§ Register/Register64
If you select Register or Register64 as the access type, the data is written
to an IOCNET register. 256 registers are available with a data width of 32
bits each and 256 registers with a data width of 64 bits each. The values
are transmitted element by element. If you want to access data from several
registers simultaneously, you can group these registers by specifying the same
group identifier for them.
§ Buffer/Buffer64
If you select Buffer or Buffer64 as the access type, the data is written to
an IOCNET buffer. 32 buffers are available that provides elements with a data
width of 32 bits each and 32 buffers that provides elements with a data
width of 64 bits each. Each buffer has a variable buffer size of 1 up to 32768
elements.

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§ Bus
If you select Bus as the access type, the data is written to an IOCNET buffer.
The bus access type lets you use Simulink buses to model the data exchange
between the processor and the FPGA.

There are settings that are common and settings that are specific to each access
type.

For more information, refer to Details on the access types on page 51.

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_XDATA_WRITE_BL block.

Binary point position (or fraction width) This setting depends on the
format selected in the Format setting.
§ signed/unsigned
The values of the Data inport are in fixed‑point format.
You can specify the binary point position of the 32‑bit value in the range
0 … 32 and the binary point position of the 64‑bit value in the range 0 … 64.
0 represents the lowest bit position, 32 or 64 the highest bit position.
§ floating‑point
The values of the Data inport are in floating‑point format. The fraction width
is displayed.

Format Lets you select the data format of the Data inport.
§ signed/unsigned
The values of the Data inport are in fixed‑point format with or without one bit
reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
64-bit fixed-point data types are converted to double, except the data
type without a binary point (binary point position = 0). Therefore, the fixed-
point resolution of fixed-point data types with a binary point (binary point
position > 0) is restricted to 53 bits.
§ floating‑point
The values of the Data inport are in floating‑point format.
The 32‑bit data value supports the single-precision floating‑point format with a
fraction width of 24, which complies with the IEEE 754 standard (single).
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is displayed in the Binary point position (or fraction
width) setting.

Enable simulation data port Lets you enable an outport for offline
simulation data. The Sim_Data outport is added to the block to connect it to
any Simulink signal used for simulation.

Simulation ports sample time Lets you specify the sample time of the ports
used for simulation, for example, Sim_Data and Sim_Status. By default, the
sample time is inherited. You must only specify the sample time explicitly, if
the modeling situation inhibits to inherit the sample time, for example, if the

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corresponding PROC block is part of an asynchronous task or is used for multiple

access to the same channel.

Register Out description Block display If you specify the register access type, the block display
changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Data Specifies a 32-bit data value to be written to an IOCNET register. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Output
Sim_Data Simulates an IOCNET data exchange including fixed-point to floating-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1

Note

The range can be exceeded for the Data inport. The inport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register Out settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 252.

Register group ID Lets you specify a number in the range 1 … 63 to

create register groups. Registers which you specified with the same group ID are
sampled simultaneously in the FPGA application. The values form a consistent
data group that is written to the IOCNET.

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Buffer Out description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a 32-bit data value to be written to an IOCNET buffer. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Enable Specifies the current valid Data port value.
Data type: UFix_1_0
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.
Ready Explicitly specifies the buffer state as ready to send immediately, even if the buffer
is not completely filled. The data values are written to a new buffer in the following
clock cycle. While the port value is 1, the buffer switches every clock cycle. You are
therefore recommended to set the value for only one clock cycle. If the buffer is
completely filled, it is automatically switched, and the data values are stored in a
new buffer.
Data type: UFix_1_0
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready to send, even if it is not completely filled. The
buffer is switched and the data values are accessible via IOCNET in the following
clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.
Send_Ack Triggers a data transmission to IOCNET. With Send_Ack and Read_Req you can
trigger a processor synchronous data exchange.
A data transmission is always requested at the beginning of a task, before the
processor model is computed. Each time a new data transmission is requested by
Read_Req, Send_Ack must explicitly acknowledge the Data values for transmission
within one task period. To send current data, you can delay the transmission. After a
new data transmission is requested, you write the current data values to the buffer.
Then you must acknowledge the new data for transmission.

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Port Description
Available only if Enable Read_Req and Send_Ack ports for explicit data
transmit is set on the Parameters page. If Enable Read_Req and Send_Ack
ports for explicit data transmit is not set, each data transmission request will
instantly be acknowledged.
Data type: UFix_1_0
§ 0: Data values are not acknowledged for transmission.
§ 1: Current Data values are acknowledged and will be transmitted via IOCNET.
A data transmission request that is not acknowledged by Send Ack leads to task
overrun in the processor application. A task overrun will be logged as an I/O error in
the Messages page of the SCALEXIO system. The FPGA buffer that caused the task
overrun will also be logged.
Output
Sim_Data Simulates an IOCNET data exchange including fixed-point to floating-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768. The vector width depends on the specified buffer size.
Overflow Outputs a flag that indicates that a buffer overflow occurred. An overflow occurs if
the old buffer is not read completely before a new buffer is ready to be read.
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.
Data type: UFix_1_0
Sim_Status Outputs information about the simulated data exchange on the Sim_Data outport.
Available only if the access type is specified as Buffer and Enable simulation port
is set on the Parameters page.
Data type: UInt32
Data width: 3
§ Sim_Status[0]: Contains the number of valid elements in the Sim_Data vector.
§ Sim_Status[1]: Indicates whether the current buffer contains new or old values. It
is 1 if the buffer contains new values.
§ Sim_Status[2]: Indicates whether a buffer overflow occurred. At least one buffer
was not read and its data was lost before the currently read buffer was filled.
Read_Req Outputs a flag that indicates that a data transmission is requested via IOCNET. With
Read_Req and Send_Ack you can trigger a processor synchronous data exchange.
A data transmission is always requested at the beginning of a task, before the
processor model is computed. Each time a new data transmission is requested by
Read_Req, Send_Ack must explicitly acknowledge the Data values for transmission
within one task period. To send current data, you can delay the transmission. After a
new data transmission is requested, you write the current data values to the buffer.
Then you must acknowledge the new data for transmission.
Available only if Enable Read_Req and Send_Ack ports for explicit data
transmit is set on the Parameters page. If Enable Read_Req and Send_Ack
ports for explicit data transmit is not set, each data transmission request will
instantly be acknowledged.
Data type: UFix_1_0
§ 0: No data transmission is requested.
§ 1: A data transmission is requested. This value is set for one clock cycle.

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Port Description
A data transmission request that is not acknowledged by Send Ack leads to task
overrun in the processor application. A task overrun will be logged as an I/O error in
the Messages page of the SCALEXIO system. The FPGA buffer that caused the task
overrun will also be logged.

Note

The range can be exceeded for the Data inport. The inport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Buffer Out settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 252.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 32-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation status port Lets you enable an outport to get status
information about the simulation data that is available when you have enabled
the simulation data port. The Sim_Status outport is added to the block.

Enable Read_Req and Send_Ack ports for explicit data transmit Lets you
add the Read_Req and Send_Ack ports to the block to trigger a processor
synchronous data exchange.

Register64 Out description Block display If you specify the register access type, the block display
changes. The simulation ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Data Specifies a 64-bit data value to be written to an IOCNET register. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double, except the data type
without a binary point (binary point position = 0). Therefore, the fixed-point
resolution of fixed-point data types with a binary point (binary point position > 0)
is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Output
Sim_Data Simulates an IOCNET data exchange including fixed-point to floating-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1

Note

The range can be exceeded for the Data inport. The inport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register64 Out settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 252.

Register group ID Lets you specify a number in the range 1 … 63 to create

register groups. All registers – 32‑bit and 64‑bit registers – which you specified
with the same group ID are sampled simultaneously in the FPGA application. The
values form a consistent data group that is written to the IOCNET.

Buffer64 Out description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a 64-bit data value to be written to an IOCNET buffer. The data format
depends on the related dialog settings.
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double, except the data type
without a binary point (binary point position = 0). Therefore, the fixed-point
resolution of fixed-point data types with a binary point (binary point position > 0)
is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Enable Specifies the current valid Data port value.
Data type: UFix_1_0
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.
Ready Explicitly specifies the buffer state as ready to send immediately, even if the buffer
is not completely filled. The data values are written to a new buffer in the following
clock cycle. While the port value is 1, the buffer switches every clock cycle. You are
therefore recommended to set the value for only one clock cycle. If the buffer is
completely filled, it is automatically switched, and the data values are stored in a
new buffer.
Data type: UFix_1_0
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready to send, even if it is not completely filled. The
buffer is switched and the data values are accessible via IOCNET in the following
clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.
Send_Ack Triggers a data transmission to IOCNET. With Send_Ack and Read_Req you can
trigger a processor synchronous data exchange.
A data transmission is always requested at the beginning of a task, before the
processor model is computed. Each time a new data transmission is requested by
Read_Req, Send_Ack must explicitly acknowledge the Data values for transmission
within one task period. To send current data, you can delay the transmission. After a
new data transmission is requested, you write the current data values to the buffer.
Then you must acknowledge the new data for transmission.
Available only if Enable Read_Req and Send_Ack ports for explicit data
transmit is set on the Parameters page. If Enable Read_Req and Send_Ack
ports for explicit data transmit is not set, each data transmission request will
instantly be acknowledged.
Data type: UFix_1_0
§ 0: Data values are not acknowledged for transmission.
§ 1: Current Data values are acknowledged and will be transmitted via IOCNET.

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Port Description
A data transmission request that is not acknowledged by Send Ack leads to task
overrun in the processor application. A task overrun will be logged as an I/O error in
the Messages page of the SCALEXIO system. The FPGA buffer that caused the task
overrun will also be logged.
Output
Sim_Data Simulates an IOCNET data exchange including fixed-point to floating-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768. The vector width depends on the specified buffer size or
the number of bus signals.
Overflow Outputs a flag that indicates that a buffer overflow occurred. An overflow occurs if
the old buffer is not read completely before a new buffer is ready to be read.
Available only if the bus transfer mode is disabled on the Parameters page.
Data type: UFix_1_0
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.
Sim_Status Outputs information about the simulated data exchange on the Sim_Data outport.
Available only if the access type is specified as Buffer and Enable simulation port
is set on the Parameters page.
Data type: UInt32
Data width: 3
§ Sim_Status[0]: Contains the number of valid elements in the Sim_Data vector.
§ Sim_Status[1]: Indicates whether the current buffer contains new or old values. It
is 1 if the buffer contains new values.
§ Sim_Status[2]: Indicates whether a buffer overflow occurred. At least one buffer
was not read and its data was lost before the currently read buffer was filled.
Read_Req Outputs a flag that indicates that a data transmission is requested via IOCNET. With
Read_Req and Send_Ack you can trigger a processor synchronous data exchange.
A data transmission is always requested at the beginning of a task, before the
processor model is computed. Each time a new data transmission is requested by
Read_Req, Send_Ack must explicitly acknowledge the Data values for transmission
within one task period. To send current data, you can delay the transmission. After a
new data transmission is requested, you write the current data values to the buffer.
Then you must acknowledge the new data for transmission.
Available only if Enable Read_Req and Send_Ack ports for explicit data
transmit is set on the Parameters page. If Enable Read_Req and Send_Ack
ports for explicit data transmit is not set, each data transmission request will
instantly be acknowledged.
Data type: UFix_1_0
§ 0: No data transmission is requested.
§ 1: A data transmission is requested. This value is set for one clock cycle.
A data transmission request that is not acknowledged by Send Ack leads to task
overrun in the processor application. A task overrun will be logged as an I/O error in
the Messages page of the SCALEXIO system. The FPGA buffer that caused the task
overrun will also be logged.

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Buffer64 Out settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 252.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation status port Lets you enable an outport to get status
information about the simulation data that is available when you have enabled
the simulation data port. The Sim_Status outport is added to the block.

Enable Read_Req and Send_Ack ports for explicit data transmit Lets you
add the Read_Req and Send_Ack ports to the block to trigger a processor
synchronous data exchange.

Bus Out description Block display If you specify the buffer access type, the block display changes.
The Send_Ack, Read_Req, and Sim_Data ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a Simulink bus to be transmitted to the processor application.
The data types of the signals depend on the bus topology that is set via Copy bus
topology from corresponding processor block or Copy bus topology from gcb
on the Parameters page. The maximum bit width is 64 bits.
The resolution of the data type is restricted to 53 bits, because the block converts all
data values to double for transmission.
Send_Ack Triggers a data transmission to IOCNET. With Send_Ack and Read_Req, you can
trigger a processor synchronous data exchange.
A data transmission is always requested at the beginning of a task, before the
processor model is computed. Each time a new data transmission is requested by
Read_Req, Send_Ack must explicitly acknowledge the Data values for transmission
within one task period. To send the data in the desired state, you can wait to finish
last data processing before acknowledging the data transfer.
Available only if the User acknowledged bus data transmission method is set on
the Parameters page. If you use subchannels, only the first subchannel displays the
Read_Req and Send_Ack ports.

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Port Description
Data type: UFix_1_0
§ 0: Data values are not acknowledged for transmission.
§ 1: Current Data values are acknowledged and will be transmitted via IOCNET.
A data transmission request that is not acknowledged by Send Ack leads to task
overrun in the processor application. A task overrun will be logged as an I/O error in
the Messages page of the SCALEXIO system. The FPGA buffer that caused the task
overrun will also be logged.
Output
Sim_Data Simulates a data transmission including fixed-point to floating-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Simulink bus
Read_Req Outputs a flag that indicates that a data transmission is requested from the
processor application. A data transmission is always requested at the beginning of a
task, before the processor application is computed.
Available only if the User acknowledged bus data transmission method is set on
the Parameters page. If you use subchannels, only the first subchannel displays the
Read_Req and Send_Ack ports.
Data type: UFix_1_0
§ 0: No data transmission is requested.
§ 1: A data transmission is requested. This value is set for one clock cycle.
A data transmission request automatically triggers a data transmission.

Bus Out settings The following dialog settings are specific for the Bus access type. For common
dialog settings, refer to Common settings on page 252.

Buffer size Displays the size of the buffer in the range 1 … 32,768. The
buffer size depends on the number of bus signals.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1,024
words. For example, a buffer with a buffer size of 1 allocates a memory
block of 1,024 words with a data width of 64 bits in the FPGA memory.
This applies to any buffer and the related swinging buffer.

Edit bus topology Opens a dialog to display and configure the

bus signals. For more information, refer to Bus Editor Dialog -
FPGA_XDATA_READ_BL/FPGA_XDATA_WRITE_BL on page 66.

Copy bus topology from corresponding processor block Lets you copy an
existing bus topology from the corresponding processor block in the processor
model. For more information, refer to How to Use Simulink Buses of the
Processor Model to Model the Processor Communication (FPGA Programming
Blockset Guide ).

Analyze bus topology of input Lets you set the Data inport to the bus
topology of the connected Simulink bus.

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If clicked, the FPGA Programming Blockset analyzes the connected Simulink

bus and sets the Data port to a matching bus topology. For instructions,
refer to How to Use Simulink Buses of the FPGA Model to Model Processor
Communication (FPGA Programming Blockset Guide ).

Reset bus topology Lets you clear the bus topology of the Data port.

Bus data transmission method Lets you select the method for transmitting
data to the processor application:
§ Synchronous to task method
Select this method to transmit data that is captured synchronously to the
processor task.
The FPGA application writes data to the swinging buffer when the processor
application makes a read request. After the data is written to the buffer, the
buffer swings and sends the data to the processor application.
§ Free running method
Select this method if the transmission time is crucial.
The FPGA application continuously writes data to the swinging buffer. A read
request of the processor application immediately transmits the last complete
data set of the swinging buffer to the processor application.
§ User acknowledged method
Select this method to acknowledge the data to be transmitted to the processor
application, for example, to trigger the processing of some data before it is
transmitted to the processor application.
The FPGA application writes data to the swinging buffer when you
acknowledge the data with the Send_Ack port. After the data is written to
the buffer, the buffer swings and sends the data to the processor application.
You must acknowledge each data transmission request so that data transfer is
synchronous to the processor task, as with the Synchronous to task method.
For instructions, refer to How to Configure the Bus Data Transmission Method
(FPGA Programming Blockset Guide ).

Related topics Basics

Modeling Processor Model Access (FPGA Programming Blockset Guide )

FPGA_IO_READ_BL (DS6601 FPGA Base Board Settings)

Purpose To configure read access to analog and digital input signals in the FPGA model
when using the DS6601 (KU035) FPGA Base Board framework.

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Where to go from here Information in this section

Parameters Page (FPGA_IO_READ_BL)................................................... 263

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_READ_BL).......................................................... 275

The Scaling page is empty because the I/O functions of this framework
do not support FPGA scaling.

Information in other sections

Unit Page (FPGA_IO_READ_BL)................................................................ 55

To specify the I/O type and channel to be used for read access.

Parameters Page (FPGA_IO_READ_BL)

Purpose To specify relevant settings for the selected I/O function.

Description The framework provides the I/O types APU, IFPGA32, IFPGA64, and Other, which
you can select on the Unit page of the block. The number of the available
physical connections determines the I/O functions that you can select:
§ APU Slave 1 … APU Slave 6
§ CN APP Status
§ I‑FPGA In 1 … 32 (IOCNET)
§ I‑FPGA64 In 1 … 32 (IOCNET)
§ IOCNET Global Time
§ Status In
§ Subsystem Clock
§ System Clock
§ System Signal Block
§ Temperature
§ Watchdog

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_IO_READ_BL block.

Enable simulation port Lets you enable an inport for offline simulation data.
The Sim_Data inport is added to the block so you can connect it to simulation
data coming from a Simulink-based I/O environment model.

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APU Slave 1 ... 6 description Block display If you select the APU Slave channel from the channel list, the
block display changes. For example:

I/O characteristics The following table describes the port of the block for
digital input channels:

Port Description
Input
Sim Phi Read Simulates the APU bus value for Phi Read.
Available only if Enable simulation Phi Read port is set on the
Parameters page.
Data type: Double
Data width: 1
The value range depends on the angle range of the simulated APU bus:
§ 360 ° angle range: 0 ... 32767 (215-1)
§ 720 ° angle range: 0 ... 65535 (216-1)
APU bus clock cycle: 8 ns
The range can be exceeded, and saturation is performed to a minimum or
maximum value.
Sim Rev Read Simulates the hardware input value for Rev Read.
Available only if Enable simulation Rev Read port is set on the
Parameters page.
Data type: Double
Data width: 1
The 37-bit range is -236 ... +236 - 1.
APU bus clock cycle: 8 ns
It is not possible to exceed the range.
Sim Phi Read HD Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Sim Delta Phi Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Sim Delta Phi Enable Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Sim Angle Range Simulates the angle range of the APU bus.
Available only if Enable simulation Angle Range port is set on the
Parameters page.
Data type: Double
Data width: 1
Values:
§ 0 (low): 720 ° angle range
§ 1 (high): 360 ° angle range
Output

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Port Description
Phi Read Outputs the angle value that APU Slave reads from the APU bus. The angle
value is independent from the angle range of the APU bus.
Formula for angle calculation: alpha[°] = Phi Read * 720°/216
Data type: UFix_16_0
Data width: 1
The value range depends on the angle range of the APU bus:
§ 360 ° angle range: 0 ... 32767 (215-1)
§ 720 ° angle range: 0 ... 65535 (216-1)
APU bus clock cycle: 8 ns
It is not possible to exceed the range.
Rev Read Outputs the 37 bit total revolution (rev) value for the APU bus.
Data type: Double
Data width: 1
The APU bus clock cycle is 8 ns. The 37-bit range is -236 ... 236 - 1.
It is not possible to exceed the range.
Phi Read HD Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Delta Phi Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Delta Phi Enable Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Angle Range Outputs the angle range of the APU bus.
Data type: UFix_1_0
Data width: 1
Values:
§ 0 (low): 720 ° angle rangeThe angle range is 0° ... 720°
§ 1 (high): 360 ° angle range

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping No external connection.

APU Slave 1 ... 6 settings The Parameters page provides the following dialog setting:

Enable Phi Read HD port The Phi Read HD port is available in the block
only if you enable it.

Enable Delta Phi port The Delta Phi port is available in the block only if you
enable it.

Enable Delta Phi Enable port The Delta Phi Enable port is available in the
block only if you enable it.

Enable simulation Phi Read port The Sim Phi Read port is available in the
block only if you enable it.

Enable simulation Rev Read port The Sim Rev Read port is available in the
block only if you enable it.

Enable simulation Phi Read HD port The Sim Phi Read HD port is
available in the block only if you enable it.

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Enable simulation Delta Phi port The Sim Delta Phi port is available in the
block only if you enable it.

Enable simulation Delta Phi Enable port The Sim Delta Phi Enable port is
available in the block only if you enable it.

Enable simulation Angle Range port The Sim Angle Range port is
available in the block only if you enable it.

Angle range For the slave APU, you can inherit the angle range of the APU
bus or you specify a local angle range independent from the APU bus. The
following table shows you the possible combinations of angle range settings.

APU Bus Slave APU Resulting Angle Range of the Slave

Setting Setting APU
360° Inherit 360°
720° 720°
360° 360° 360°
720° 720° 1)
720° 360° 360° 2)
720° 720°
1) Two engine cycles are required to run through the 720 ° angle range. If you simulate a
four-stroke piston engine, for example, the angle values of the function block are not
clearly related to the camshaft position.
2) One engine cycle runs twice through the 360 ° angle range.

CN App Status description Block display If you select the CN App Status channel from the channel list,
the block display changes.

I/O characteristics The following table describes the port of the block:

Port Description
Output
Status Outputs the state of the application that is running on the computation node.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The application on the computation node is stopped.
§ 1: The application on the computation node is running.

I/O mapping No external connection.

CN App Status settings None

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I-FPGA In 1 … 32 (IOCNET) Block display If you select the I-FPGA In (IOCNET) channel from the channel
description list, the block display changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Address Specifies a data value in the IOCNET buffer to be read. The block requires
one clock cycle to update the value of the Data outport with the data value
of the specified address.
Data type: UFix_16_0
Data width: 1
The maximum address range depends on the Buffer size on the Parameters
page. The address range with valid data values can be derived from the value
of the Data Count port.
Sim Data Simulates a data exchange between two FPGA boards via IOCNET. The
provided data values are converted to the data format of the Data port
and written to a simulated IOCNET buffer.
Available only if the Enable simulation data port is set on the Parameters
page.
Data type: Double
Data width: 1 … 1024
Range: Single precision value range
Sim Data New Simulates the reception of new data values.
Available only if the Enable simulation data new port is set on the
Parameters page.
Data type: Double
Data width: 1
Values:
§ 0: The reception of new data values is not simulated.
§ 1: The Data New port changes from 0 to 1 for one clock cycle to indicate
new data values.
Output
Data Outputs a 32-bit raw data value from the specified address of the IOCNET
buffer.
Data type: UFix_32_0
Data width: 1

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Port Description
Data New Outputs a flag that indicates the update of the Data port.
Data type: UFix_1_0
Data width: 1
If the flag changes from 0 to 1 and then to 0 again, the requested buffer
contains new values and is ready to be read. The flag is set to 1 within only
one clock cycle.
Data Count Outputs the number of elements in the current IOCNET buffer. You can use
the value to define the valid range for the Address port from 0 to (Data
Count -1).
Data type: UFix_16_0
Data width: 1
The maximum value range depends on the Buffer size on the Parameters
page.

Note

You can transfer any data type with a bit width of up to 32 Bit via inter-
FPGA over IOCNET. Use the Reinterpret block from the HDL library of the
AMD Vitis Model Composer to change your data type to UFix_32_0 and
vice versa. Reinterpreting data types does not cost any hardware or latency.
The range can be exceeded for the Data outport. The outport's value is
then cast to UFix_32_0.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I-FPGA In 1 … 32 (IOCNET) The following dialog settings are specific for the I-FPGA In (IOCNET) I/O
settings function. For common dialog settings, refer to Common settings on page 263.

Buffer size Lets you specify the size of the IOCNET buffer in the range
1 … 1024. The maximum range of the Address inport depends on the buffer
size.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 32-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation data port Lets you enable an inport for offline simulation
data.
The Sim Data inport is added to the block.

Enable simulation data new port Lets you enable an inport for the offline
simulating of new data values at the Data outport.
The Sim Data New inport is added to the block.

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I-FPGA64 In 1 … 32 (IOCNET) Block display If you select the I-FPGA64 Out (IOCNET) channel from the
description channel list, the block display changes. The simulation ports are displayed
optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Address Specifies a data value in the IOCNET buffer to be read. The block requires
one clock cycle to update the value of the Data outport with the data value
of the specified address.
Data type: UFix_16_0
Data width: 1
The maximum address range depends on the Buffer size on the Parameters
page. The address range with valid data values can be derived from the value
of the Data Count port.
Sim Data Simulates a data exchange between two FPGA boards via IOCNET. The
provided data values are converted to the data format of the Data port
and written to a simulated IOCNET buffer.
Available only if the Enable simulation data port is set on the Parameters
page.
Data type: Double
Data width: 1 … 512
Range: Double precision value range
Sim Data New Simulates the reception of new data values.
Available only if the Enable simulation data new port is set on the
Parameters page.
Data type: Double
Data width: 1
Values:
§ 0: The reception of new data values is not simulated.
§ 1: The Data New port changes from 0 to 1 for one clock cycle to indicate
new data values.
Output
Data Outputs a 64-bit raw data value from the specified address of the IOCNET
buffer.
Data type: UFix_64_0
Data width: 1

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Port Description
Data New Outputs a flag that indicates the update of the Data port.
Data type: UFix_1_0
Data width: 1
If the flag changes from 0 to 1 and then to 0 again, the requested buffer
contains new values and is ready to be read. The flag is set to 1 within only
one clock cycle.
Data Count Outputs the number of elements in the current IOCNET buffer. You can use
the value to define the valid range for the Address port from 0 to (Data
Count -1).
Data type: UFix_16_0
Data width: 1
The maximum value range depends on the Buffer size on the Parameters
page.

Note

You can transfer any data type with a bit width of up to 64 Bit via inter-
FPGA over IOCNET. Use the Reinterpret block from the HDL library of the
AMD Vitis Model Composer to change your data type to UFix_64_0 and
vice versa. Reinterpreting data types does not cost any hardware or latency.
The range can be exceeded for the Data outport. The outport's value is
then cast to UFix_64_0.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I-FPGA64 In 1 … 32 (IOCNET) The following dialog settings are specific for the I-FPGA64 In (IOCNET) I/O
settings function. For common dialog settings, refer to Common settings on page 263.

Buffer size Lets you specify the size of the IOCNET buffer in the range
1 … 512. The maximum range of the Address inport depends on the buffer
size.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64 bits in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation data port Lets you enable an inport for offline simulation
data.
The Sim Data inport is added to the block.

Enable simulation data new port Lets you enable an inport for the offline
simulating of new data values at the Data outport.
The Sim Data New inport is added to the block.

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IOCNET Global Time Block display If you select the IOCNET Global Time channel from the channel
description list, the block display changes.

I/O characteristics The following table describes the port of the block:

Port Description
Output
Time Outputs the number of hardware ticks that occurred since the SCALEXIO system
power was switched to on. If you use a multiprocessor system, the value is set to
zero each time an application is reloaded and restarted.
Data type: 56 bit
Tick step-width: 8.5 ns

I/O mapping No external connection.

IOCNET Global Time settings None

Status In description Block display If you select the Status In channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Output
Init Done Outputs the state of the initialization sequence that is started after programming
the FPGA.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Initialization sequence is in progress.
§ 1: Initialization sequence has finished.

I/O mapping No external connection.

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Status In settings None

Subsystem Clock description Block display If you select the Subsystem Clock channel from the channel
list, the block display changes.

I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Output
Subsystem Outputs the clock signal of the selected subsystem clock domain. You specify the
Clock subsystem clock domain in the FPGA Setup block. Refer to How to Use Multiple
Clock Domains for FPGA Modeling (FPGA Programming Blockset Guide ).
Data type: UFix_1_0
Data width: 1

Multiple clock domain support This block is intended to be used in a user

clock domain with an individual clock period.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping No external connection.

Subsystem Clock settings None

System Clock description Block display If you select the System Clock channel from the channel list,
the block display changes.

I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Output
System Clock Outputs the clock signal of the FPGA (base clock rate).
Data type: UFix_1_0
Data width: 1

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Multiple clock domain support This block is intended to be used in a user

clock domain with an individual clock period.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping No external connection.

System Clock settings None

System Signal Block Block display If you select the System Signal Block channel from the channel
description list, the block display changes.

I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Output
System Clock Outputs the clock signal of the FPGA (base clock rate).
Data type: UFix_1_0
Data width: 1
Init Done Outputs the state of the initialization sequence that is started after programming
the FPGA.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Initialization sequence is in progress.
§ 1: Initialization sequence has finished.
CN App Outputs the state of the processor application.
Status Data type: UFix_1_0
Data width: 1
Values:
§ 0: The processor application is stopped.
§ 1: The processor application is running.
Opto_Ready Indicates whether the MGT module is ready for data exchange. The port changes
to 1 during the initialization phase, i.e., before the CN APP Status port changes
from stop to running. If no MGT module is connected to the dSPACE hardware, the
port value remains 0.
Data type: UFix_1_0
Data width: 1

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Port Description
If the MGT module is ready, the flag changes from 0 to 1:
§ 0: The MGT module is not ready.
§ 1: The MGT module is ready.

Multiple clock domain support This block is intended to be used in a user

clock domain with an individual clock period.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping No external connection.

System Signal Block settings None

Temperature description Block display If you select the Temperature channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block for
the die temperature input channel:

Port Description
Input
Sim_Temp Simulates the FPGA's die temperature (internal chip temperature).
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Input temperature range: -274.00 °C … 230.00 °C
The range can be exceeded. The values are then saturated to the minimum or
maximum values.
Output
RAW_temp Outputs the FPGA's die temperature measurement.
Data type: Fix_20_10
Data width: 1
Value range: -274.00 °C … 230.00 °C

I/O mapping No external connection.

Temperature settings Only common dialog settings. Refer to Common settings on page 263.

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Watchdog description Block display If you select the Watchdog channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block for
the watchdog input channel:

Port Description
Output
Status Outputs a flag that indicates that the processor application transmits a keep-alive
signal within the specified timeout.
§ 0: The watchdog timer expires without a keep-alive signal being transmitted to
the FPGA application.
§ 1: The processor application is alive.
Data type: UFix_1_0

Tip

In ConfigurationDesk, you deactivate the watchdog functionality by not

mapping the Trigger port of the watchdog function to a model port.
If deactivated, the Status port of the Watchdog block always outputs 1 in
the FPGA application.

Watchdog settings None

Related topics Basics

Modeling Inter-FPGA Communication via IOCNET (FPGA Programming Blockset

Guide )
Using a Watchdog (FPGA Programming Blockset Guide )

Scaling Page (FPGA_IO_READ_BL)

Description The Scaling page is empty because the I/O functions of this framework do not
support FPGA scaling.

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Frameworks with scaling The frameworks of the I/O modules support FPGA scaling:
support § DS2655M1 I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 350
§ Scaling Page (FPGA_IO_WRITE_BL) on page 363
§ DS2655M2 Digital I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 377
§ Scaling Page (FPGA_IO_WRITE_BL) on page 397
§ DS6651 Multi-I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 413
§ Scaling Page (FPGA_IO_WRITE_BL) on page 445

Related topics Basics

Basics on FPGA Test Access and Scaling (FPGA Programming Blockset Guide )

FPGA_IO_WRITE_BL (DS6601 FPGA Base Board Settings)

Purpose To configure write access to analog and digital output signals in the FPGA model
when using the DS6601 (KU035) FPGA Base Board framework.

Where to go from here Information in this section

Parameters Page (FPGA_IO_WRITE_BL).................................................. 276

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_WRITE_BL)........................................................ 285

The Scaling page is empty because the I/O functions of this framework
do not support FPGA scaling.

Information in other sections

Unit Page (FPGA_IO_WRITE_BL)............................................................... 60

To specify the I/O type and channel to be used for write access.

Parameters Page (FPGA_IO_WRITE_BL)

Purpose To specify relevant settings for the selected I/O function.

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Description The framework provides the I/O types APU, IFPGA32, IFPGA64, and Other, which
you can select on the Unit page of the block. The number of the available
physical connections determines the I/O functions that you can select:
§ APU Master 1 … APU Master 6
§ I-FPGA Out 1 … 32 (IOCNET)
§ I-FPGA64 Out 1 … 32 (IOCNET)
§ LED Out
§ User Clock Out 1 … 32

Common settings None

APU Master 1 … 6 description Block display If you select the APU Master channel from the channel list, the
block display changes. For example:

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Velocity Specifies a velocity value in degree/second to be applied as APU Master
speed.
The value will be applied if Set Velocity is 1 (high) and Busy is 0 (low).
Data type: Fix_32_10
Data width: 1
Range: -1,200,000 °/s ... +1,200,000 °/s
It is not possible to exceed the range. The port is saturated at the higher or
lower limit.
Set Velocity Specifies the current value of Velocity as new velocity value.
The new value is set only if Set Velocity is 1 (high) and Busy is 0 (low).
Data type: UFix_1_0
Data width: 1
To distribute and execute a new velocity value takes at least 10 μs,
depending on the IOCNET structure.
Output
Phi Read Outputs the angle counter value of the APU that the APU Master writes to
the APU bus. The step size of the angle counter is approximately 0.011°. The
step size is independent from the angle range.
Formula for angle calculation: alpha[°] = Phi Read * 720°/216
Data type: UFix_16_0

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Port Description
Data width: 1
The value range depends on the Angle range on the Parameters page.:
§ 360 ° angle range: 0 ... 32767 (215-1)
§ 720 ° angle range: 0 ... 65535 (216-1)
APU bus clock cycle: 8 ns
It is not possible to exceed the range.
Rev Read Outputs the 37 bit total revolution (rev) value that APU Master reads from
the APU bus.
Data type: Fix_37_0
Data width: 1
The 37-bit range is -236 ... 236 - 1.
APU bus clock cycle: 8 ns
It is not possible to exceed the range.
Phi Read HD Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Delta Phi Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Delta Phi Enable Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Angle Range Outputs the angle range of the APU bus. You set the angle range on the
Parameters page.
Data type: UFix_1_0
Data width: 1
Values:
§ 0 (low): 720 ° angle range
§ 1 (high): 360 ° angle range
Busy Outputs whether APU Master is busy to set the last velocity value.
Data type: UFix_1_0
Data width: 1
If the Busy port is 1 (high), new velocity values cannot be set.
The Busy port stays active for at least 10 µs depending on the IOCNET
structure.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping No external connection.

APU Master 1 … 6 settings The Parameters page provide the following dialog setting:

Angle range Lets you select the angle range of the APU in degree.
§ 360: The angle range is 360° and cannot be changed in ConfigurationDesk.
§ 720: The angle range is 720° and cannot be changed in ConfigurationDesk.
§ Individual: The Angle range property of the FPGA custom function block in
ConfigurationDesk lets you set the angle range of the APU. The default value
is 720°.

Initial position Lets you set the initial APU master position in degree.
§ Value range: -1440° ... +1440°

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Enable advanced ports The internal ports for the dSPACE Electric Motor HIL
Solution are available in the block only if you enable it.

I-FPGA Out 1 … 32 (IOCNET) Block display If you select the I-FPGA Out (IOCNET) channel from the
description channel list, the block display changes. The simulation ports are displayed
optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a 32-bit raw data value to be written to an IOCNET buffer.
Data type: UFix_32_0
Data width: 1
Enable Specifies the current valid Data port value.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The Data value to be written is not stored in the IOCNET buffer.
§ 1: The Data value to be written is stored in the IOCNET buffer. The value of the
current clock cycle is used.
Ready Explicitly specifies the buffer state as ready to send immediately, even if the buffer
is not completely filled. The data values are written to a new buffer in the following
clock cycle. While the port value is 1, the buffer switches every clock cycle. You are
therefore recommended to set the value for only one clock cycle. If the buffer is
completely filled, it is automatically switched, and the data values are stored in a
new buffer.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready to send, even if it is not completely filled.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.

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Port Description
Send Triggers a data transmission via IOCNET.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Data values are not acknowledged for transmission.
§ 1: Current Data values are acknowledged and will be transmitted via IOCNET.
Output
Overflow Outputs a flag that indicates that a buffer overflow occurred. An overflow occurs
when the new buffer is triggered for transmission and the old buffer was not sent
completely.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.
Sim Data Simulates a data exchange between two FPGA boards via IOCNET. The port
provides the data values that are written to a simulated IOCNET buffer, including
fixed-point to floating-point data conversion.
Available only if the Enable simulation data port is set on the Parameters page.
Data type: Double
Data width: 1 … 1024, depends on the Buffer size parameter.
Range: Single precision value range
Sim Data New Simulates the update of data values provided by the Sim Data outport.
Available only if the Enable simulation data new port is set on the Parameters
page.
Data type: Double
Data width: 1
A transition from 0 to 1 indicates that the Sim Data outport provides new data.
Sim Status Outputs information about the simulated data exchange on the Sim Data outport.
Available only if the Enable simulation status port is set on the Parameters
page.
Data type: UInt32
Data width: 3
§ Sim Status[0]: Contains the number of valid elements in the Sim Data vector.
§ Sim Status[1]: Indicates whether the current buffer contains new or old values.
The status is 1 if the buffer contains new values.
§ Sim Status[2]: Indicates whether a buffer overflow occurred. At least one buffer
was not read and its data was lost before the currently read buffer was filled.

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Note

You can transfer any data type with a bit width of up to 32 Bit via inter-
FPGA over IOCNET. Use the Reinterpret block from the HDL library of the
AMD Vitis Model Composer to change your data type to UFix_32_0 and
vice versa. Reinterpreting data types does not cost any hardware or latency.
The range of the Data inport can be exceeded. The value of the inport is
then cast to the raw data format UFix_32_0.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I-FPGA Out 1 … 32 (IOCNET) The Parameters page provide the following dialog setting:
settings
Buffer size Lets you specify the size of the IOCNET buffer in the range
1 … 1024.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 32-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation data port Lets you enable an outport for offline
simulation data.
The Sim Data inport is added to the block.

Enable simulation data new port Lets you enable an outport for the offline
simulating of new data values at the Sim Data inport.
The Sim Data New outport is added to the block.

Enable simulation status port Lets you enable an outport to get status
information about the simulation data that is available when you enabled a
simulation port. The Sim Status outport is added to the block.

I-FPGA64 Out 1 … 32 Block display If you select the I-FPGA64 Out (IOCNET) channel from the
(IOCNET) description channel list, the block display changes. The simulation ports are displayed
optionally.

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I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a 64-bit raw data value to be written to an IOCNET buffer.
Data type: UFix_64_0
Data width: 1
Enable Specifies the current valid Data port value.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The Data value to be written is not stored in the IOCNET buffer.
§ 1: The Data value to be written is stored in the IOCNET buffer. The value of the
current clock cycle is used.
Ready Explicitly specifies the buffer state as ready to send immediately, even if the buffer
is not completely filled. The data values are written to a new buffer in the following
clock cycle. While the port value is 1, the buffer switches every clock cycle. You are
therefore recommended to set the value for only one clock cycle. If the buffer is
completely filled, it is automatically switched, and the data values are stored in a
new buffer.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready to send, even if it is not completely filled.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.
Send Triggers a data transmission via IOCNET.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Data values are not acknowledged for transmission.
§ 1: Current Data values are acknowledged and will be transmitted via IOCNET.
Output
Overflow Outputs a flag that indicates that a buffer overflow occurred. An overflow occurs
when the new buffer is triggered for transmission and the old buffer was not sent
completely.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.
Sim_Data Simulates a data exchange between two FPGA boards via IOCNET. The port
provides the data values that are written to a simulated IOCNET buffer.
Available only if the Enable simulation data port is set on the Parameters page.
Data type: Double

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Port Description
Data width: 1 … 512, depends on the Buffer size parameter.
Range: Double precision value range
Sim_Data Simulates the update of data values provided by the Sim Data outport.
New Available only if the Enable simulation data new port is set on the Parameters
page.
Data type: Double
Data width: 1
A transition from 0 to 1 indicates that the Sim Data outport provides new data.
Sim Status Outputs information about the simulated data exchange on the Sim Data outport.
Available only if the Enable simulation status port is set on the Parameters
page.
Data type: UInt32
Data width: 3
§ Sim Status[0]: Contains the number of valid elements in the Sim Data vector.
§ Sim Status[1]: Indicates whether the current buffer contains new or old values.
The status is 1 if the buffer contains new values.
§ Sim Status[2]: Indicates whether a buffer overflow occurred. At least one buffer
was not read and its data was lost before the currently read buffer was filled.

Note

You can transfer any data type with a bit width of up to 64 Bit via inter-
FPGA over IOCNET. Use the Reinterpret block from the HDL library of the
AMD Vitis Model Composer to change your data type to UFix_64_0 and
vice versa. Reinterpreting data types does not cost any hardware or latency.
The range of the Data inport can be exceeded. The value of the inport is
then cast to the raw data format UFix_64_0.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I-FPGA64 Out 1 … 32 The Parameters page provides the following dialog setting:
(IOCNET) settings
Buffer size Lets you specify the size of the IOCNET buffer in the range
1 … 512.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64 bits in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation data port Lets you enable an outport for offline
simulation data.
The Sim Data inport is added to the block.

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Enable simulation data new port Lets you enable an outport for the offline
simulating of new data values at the Sim Data inport.
The Sim Data New outport is added to the block.

Enable simulation status port Lets you enable an outport to get status
information about the simulation data that is available when you enabled a
simulation port. The Sim Status outport is added to the block.

LED Out description Block display If you select the LED Out channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Controls the LED on the DS6601 FPGA Base Board.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: LED lights green.
§ 1: LED lights orange.
If the value of the Data port exceeds the specified data width, only the lowest bit is
used (=1).

I/O mapping No external connection.

LED Out settings None

User Clock Out 1 … 32 Block display If you select the User Clock Out channel from the channel list,
description the block display changes.

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I/O characteristics The following table describes the ports of the block:

Port Description
Input
User Clock Clock signal for the clock domain used within the subsystem to which the block
belongs. For more information, refer to Using Multiple Clock Domains for FPGA
Modeling (FPGA Programming Blockset Guide ).
Data type: UFix_1_0
Data width: 1

I/O mapping No external connection.

User Clock Out 1 … 32 The Parameters page provides the following dialog setting:
settings
User clock period Lets you specify the expected clock period used within the
subsystem to which the block belongs. A common value for the clock period is in
the range 20 ns ... 4 ns (50 MHz ... 250 MHz).
The value is used during the build process when no user clock is available, for
example, to specify timing constraints.

User clock offline simulation period Lets you specify the clock period to be
used in offline simulation mode. The value must be greater than or equal to the
value of the User clock period parameter.

Related topics Basics

Modeling Inter-FPGA Communication via IOCNET (FPGA Programming Blockset

Guide )

Scaling Page (FPGA_IO_WRITE_BL)

Description The Scaling page is empty because the I/O functions of this framework do not
support FPGA scaling.

Frameworks with scaling The frameworks of the I/O modules support FPGA scaling:
support § DS2655M1 I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 350
§ Scaling Page (FPGA_IO_WRITE_BL) on page 363
§ DS2655M2 Digital I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 377
§ Scaling Page (FPGA_IO_WRITE_BL) on page 397

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§ DS6651 Multi-I/O Module

§ Scaling Page (FPGA_IO_READ_BL) on page 413
§ Scaling Page (FPGA_IO_WRITE_BL) on page 445

Related topics Basics

Basics on FPGA Test Access and Scaling (FPGA Programming Blockset Guide )

FPGA_INT_BL (DS6601 FPGA Base Board Settings)

Purpose To configure the FPGA interrupt channel when using the DS6601 (KU035) FPGA
Base Board framework.

Where to go from here Information in this section

Parameters Page (FPGA_INT_BL)............................................................ 286

To enable the simulation port for an interrupt.

Information in other sections

Unit Page (FPGA_INT_BL)......................................................................... 64

To specify the interrupt channel used to trigger a task in the processor
model.

Parameters Page (FPGA_INT_BL)

Purpose To enable the simulation port for an interrupt.

Description The DS6601 FPGA Base Board provides 16 interrupt lines.

An interrupt is requested if the Int port is set to 1 for at least one clock cycle. If
you set the Int port to 0, the last interrupt is not released but saved. An interrupt
is edge-triggered.

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Int description Block display The figure below shows the block display with the optional
simulation port.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Int Provides the interrupt request line.
Data type: UFix_1_0
0 to 1: Interrupt is requested (edge-triggered).
0: No interrupt is requested. Last requested interrupt is saved.
Output
Sim_Int Simulates an interrupt by performing a function call to enable a function-call
subsystem.
Available only if Enable simulation port is set on the Parameters page.
Data type: Function call

Int settings Enable simulation port Lets you enable an outport for a simulated interrupt.
The Sim_Int outport is added to the block to connect it to a function-call
subsystem in the processor model.

Related topics HowTos

How to Trigger Interrupt-Driven Processor Tasks (FPGA Programming Blockset

Guide )

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Block Settings for the DS6602 FPGA Base Board Framework

Introduction The block dialogs provide hardware-specific settings after you load the DS6602
(KU15P) FPGA Base Board framework.

Where to go from here Information in this section

FPGA_XDATA_READ_BL (DS6602 FPGA Base Board Settings)................. 288

To configure read access to IOCNET data in the FPGA model when using
the DS6602 (KU15P) FPGA Base Board framework.

FPGA_XDATA_WRITE_BL (DS6602 FPGA Base Board Settings)................ 298

To configure write access to IOCNET data in the FPGA model when using
the DS6602 (KU15P) FPGA Base Board framework.

FPGA_IO_READ_BL (DS6602 FPGA Base Board Settings)........................ 309

To configure read access to analog and digital input signals in the FPGA
model when using the DS6602 (KU15P) FPGA Base Board framework.

FPGA_IO_WRITE_BL (DS6602 FPGA Base Board Settings)....................... 323

To configure write access to analog and digital output signals in
the FPGA model when using the DS6602 (KU15P) FPGA Base Board
framework.

FPGA_INT_BL (DS6602 FPGA Base Board Settings)................................. 342

To configure the FPGA interrupt channel when using the DS6602
(KU15P) FPGA Base Board framework.

FPGA_XDATA_READ_BL (DS6602 FPGA Base Board Settings)

Purpose To configure read access to IOCNET data in the FPGA model when using the
DS6602 (KU15P) FPGA Base Board framework.

Where to go from here Information in this section

Parameters Page (FPGA_XDATA_READ_BL)............................................ 289

To specify the data format and specific settings for the selected access
type.

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Information in other sections

Unit Page (FPGA_XDATA_READ_BL)......................................................... 46

To specify the general configuration for the FPGA board's processor bus
read access.

Parameters Page (FPGA_XDATA_READ_BL)

Purpose To specify the data format and specific settings for the selected access type.

Description The DS6602 (KU15P) FPGA Base Board framework provides the following access
types that you can select on the Unit page of the block dialog:
§ Register/Register64
If you select Register or Register64 as the access type, the data is read from
an IOCNET register. 256 registers are available with a data width of 32 bits
each and 256 registers with a data width of 64 bits each. The values are
transmitted element by element.
If you want to access data from several registers simultaneously, you can group
these registers by specifying the same group identifier for them.
Ungrouped registers are automatically combined into one register group with
group ID Ungrouped to optimize data transfer. Because register groups can
be accessed only by one task, you have to explicitly group registers which are
used by different tasks.
§ Buffer/Buffer64
If you select Buffer or Buffer64 as the access type, the data is read from
an IOCNET buffer. 32 buffers are available that provide elements with a data
width of 32 bits each and 32 buffers that provides elements with a data
width of 64 bits each. Each buffer has a variable buffer size of 1 up to 32768
elements.
§ Bus
If you select Bus as the access type, the data is read from an IOCNET buffer.
The bus access type lets you use Simulink buses to model the data exchange
between the processor and the FPGA.

There are settings that are common and settings that are specific to each access
type.

For more information, refer to Details on the access types on page 46.

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_XDATA_READ_BL block.

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Binary point position (or fraction width) This setting depends on the
format selected in the Format setting.
§ signed/unsigned
The values of the Data outport are in fixed‑point format.
You can specify the binary point position of the 32‑bit value in the range
0 … 32 and the binary point position of the 64‑bit value in the range 0 … 64.
0 represents the lowest bit position, 32 or 64 the highest bit position.
§ floating‑point
The values of the Data outport are in floating‑point format. The fraction width
is displayed.

Format Lets you select the data format of the Data outport.
§ signed/unsigned
The values of the Data outport are in fixed‑point format with or without one
bit reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
64-bit fixed-point data types are converted to double, except the data
type without a binary point (binary point position = 0). Therefore, the fixed-
point resolution of fixed-point data types with a binary point (binary point
position > 0) is restricted to 53 bits.
§ floating‑point
The values of the Data outport are in floating‑point format.
The 32‑bit data value supports the single-precision floating‑point format with a
fraction width of 24, which complies with the IEEE 754 standard (single).
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is displayed in the Binary point position (or fraction
width) setting.

Enable simulation port Lets you enable an inport for offline simulation data.
The Sim_Data inport is added to the block to connect it to any Simulink signal
used for simulation.

Simulation ports sample time Lets you specify the sample time of the
ports used for simulation, for example, Sim_Data. By default, the sample time
is inherited. You must only specify the sample time explicitly, if the modeling
situation inhibits inheriting the sample time, for example, if the corresponding
PROC block is part of an asynchronous task or is used for multiple access to the
same channel.

Register In description Block display If you specify the register access type, the block display
changes. The simulation ports are optionally displayed.

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I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Sim_Data Simulates an IOCNET data exchange including floating-point to fixed-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Output
Data Outputs a 32-bit data value to be read from a IOCNET register. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Data New Outputs a flag that indicates the changes of the register status. If the flag changes
from 0 to 1 and then to 0 again, the requested register contains a new value. The
flag is set to 1 within only one clock cycle.
Data type: UFix_1_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register In settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 289.

Register group ID Lets you specify a number in the range 1 … 63 to

create register groups. Registers that you specified with the same group ID are
read from the IOCNET sequentially and then provided to the FPGA application
simultaneously.
Specify 0 for ungrouped read access.

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Buffer In description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Sim_Data Simulates an IOCNET data exchange including floating-point to fixed-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768
Address Specifies an element you want to read in the buffer. The block requires 3 clock cycles
to update the value of the Data outport according to the specified address.
The maximum port range depends on the specified buffer size in the Parameters
page. The valid port range depends on the number of elements currently in the
buffer (see Data Count outport). If you request data from an address that is greater
than the Data Count value, the output of the Data outport is undefined. The first
element of a buffer is addressed by 0.
Data type: UFix_16_0
Output
Data Outputs a 32-bit data value to be read from an IOCNET buffer. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Data New Outputs a flag that indicates the changes of the buffer status. If the flag changes
from 0 to 1 and then to 0 again, the requested buffer contains new values and is
ready to be read. The flag is set to 1 within only one clock cycle.
Data type: UFix_1_0
Data Count Outputs the number of elements in the current buffer.
The maximum range depends on the specified buffer size. You can use the value to
define the valid range for the Address inport of 0 … (Data Count -1).
Data type: UFix_16_0

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Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Buffer In settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 289.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.
The maximum range of the Address inport depends on the buffer size.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 32-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Register64 In description Block display If you specify the register access type, the block display
changes. The simulation ports are optionally displayed.

I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Sim_Data Simulates an IOCNET data exchange including floating-point to fixed-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Output
Data Outputs a 64-bit data value to be read from an IOCNET register. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>

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Port Description
64-bit fixed-point data types are converted to double, except the data type
without a binary point (binary point position = 0). Therefore, the fixed-point
resolution of fixed-point data types with a binary point (binary point position > 0)
is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Data New Outputs a flag that indicates the changes of the register status. If the flag changes
from 0 to 1 and then to 0 again, the requested register contains a new value. The
flag is set to 1 within only one clock cycle.
Data type: UFix_1_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register64 In settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 289.

Register group ID Lets you specify a number in the range 1 … 63 to

create register groups. All registers – 32‑bit and 64‑bit registers – which you
specified with the same group ID are read from the IOCNET sequentially and
then provided to the FPGA application simultaneously.
Specify 0 for ungrouped read access.

Buffer64 In description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Sim_Data Simulates an IOCNET data exchange including floating-point to fixed-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768
Address Specifies an element in the buffer you want to read. The block requires 3 clock
cycles to update the value of the Data outport according to the specified address.
The maximum port range depends on the specified buffer size in the Parameters
page. The valid port range depends on the number of elements currently in the
buffer (see Data Count outport). If you request data from an address that is greater
than the Data Count value, the output of the Data outport is undefined. The first
element of a buffer is addressed by 0.
Data type: UFix_16_0
Output
Data Outputs a 64-bit data value to be read from an IOCNET buffer. The data format
depends on the related dialog settings.
Data type if the bus transfer mode is disabled on the Parameters page:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double, except the data type
without a binary point (binary point position = 0). Therefore, the fixed-point
resolution of fixed-point data types with a binary point (binary point position > 0)
is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Data New Outputs a flag that indicates the changes of the buffer status. If the flag changes
from 0 to 1 and then to 0 again, the requested buffer contains new values and is
ready to be read. The flag is set to 1 within only one clock cycle.
Data type: UFix_1_0
Data Count Outputs the number of elements in the current buffer.
The maximum range depends on the specified buffer size. You can use the value to
define the valid range for the Address inport of 0 … (Data Count -1).
Data type: UFix_16_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

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Buffer64 In settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 289.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.
The maximum range of the Address inport depends on the buffer size.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Bus In description Block display If you specify the access type, the block display changes. The
simulation port is optionally displayed.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Sim_Data Simulates a bus data exchange including floating-point to fixed-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768
Output
Data Outputs the signals of the Simulink bus. The data types of the signals depend
on the bus topology that is copied via Copy bus topology from corresponding
processor block or Copy bus topology from gcb on the Parameters page. The
maximum bit wide is 64 bits.
The resolution of the data types is restricted to 53 bits, because the data type of the
received bus signals from the processor application is double and the block converts
the signals to the signal data types.
Data New Outputs a flag that indicates the changes of the buffer status. If the flag changes
from 0 to 1 and then to 0 again, the requested buffer contains new values and is
ready to be read. The flag is set to 1 only within one clock cycle.
Data type: UFix_1_0

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Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Bus In settings The following dialog settings are specific for the Bus access type. For common
dialog settings, refer to Common settings on page 289.

Buffer size Displays the size of the buffer in the range 1 … 32,768. The
buffer size depends on the number of bus signals.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1,024
words. For example, a buffer with a buffer size of 1 allocates a memory
block of 1,024 words with a data width of 64-bit in the FPGA memory. This
applies to any buffer and the related swinging buffer.

Edit bus topology Opens a dialog to display and configure the

bus signals. For more information, refer to Bus Editor Dialog -
FPGA_XDATA_READ_BL/FPGA_XDATA_WRITE_BL on page 66.

Copy bus topology from corresponding processor block Lets you copy an
existing bus topology from the corresponding processor block in the processor
model. For more information, refer to How to Use Simulink Buses of the
Processor Model to Model the Processor Communication (FPGA Programming
Blockset Guide ).

Copy bus topology from gcb Lets you copy an existing FPGA bus topology
from the selected Simulink Bus Creator block, subsystem inport block, or
subsystem outport block to the Data port of the Bus In block.
You cannot copy a bus topology from the processor model, because these
topologies do not include the FPGA data types. For instructions, refer to How
to Use Simulink Buses of the FPGA Model to Model Processor Communication
(FPGA Programming Blockset Guide ).

Reset bus topology Lets you clear the bus topology of the Data port.

Related topics Basics

Modeling Processor Model Access (FPGA Programming Blockset Guide )

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FPGA_XDATA_WRITE_BL (DS6602 FPGA Base Board

Settings)
Purpose To configure write access to IOCNET data in the FPGA model when using the
DS6602 (KU15P) FPGA Base Board framework.

Where to go from here Information in this section

Parameters Page (FPGA_XDATA_WRITE_BL)........................................... 298

To specify the data format and specific settings for the selected access
type.

Information in other sections

Unit Page (FPGA_XDATA_WRITE_BL)............................................. .......... 51

To specify the general configuration for the FPGA board's processor bus
write access.

Parameters Page (FPGA_XDATA_WRITE_BL)

Purpose To specify the data format and specific settings for the selected access type.

Description The DS6602 (KU15P) FPGA Base Board framework provides the following access
types that you can select in the Unit page of the block's dialog:
§ Register/Register64
If you select Register or Register64 as the access type, the data is written
to an IOCNET register. 256 registers are available with a data width of 32
bits each and 256 registers with a data width of 64 bits each. The values
are transmitted element by element. If you want to access data from several
registers simultaneously, you can group these registers by specifying the same
group identifier for them.
§ Buffer/Buffer64
If you select Buffer or Buffer64 as the access type, the data is written to
an IOCNET buffer. 32 buffers are available that provides elements with a data
width of 32 bits each and 32 buffers that provides elements with a data
width of 64 bits each. Each buffer has a variable buffer size of 1 up to 32768
elements.

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§ Bus
If you select Bus as the access type, the data is written to an IOCNET buffer.
The bus access type lets you use Simulink buses to model the data exchange
between the processor and the FPGA.

There are settings that are common and settings that are specific to each access
type.

For more information, refer to Details on the access types on page 51.

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_XDATA_WRITE_BL block.

Binary point position (or fraction width) This setting depends on the
format selected in the Format setting.
§ signed/unsigned
The values of the Data outport are in fixed‑point format.
You can specify the binary point position of the 32‑bit value in the range
0 … 32 and the binary point position of the 64‑bit value in the range 0 … 64.
0 represents the lowest bit position, 32 or 64 the highest bit position.
§ floating‑point
The values of the Data outport are in floating‑point format. The fraction width
is displayed.

Format Lets you select the data format of the Data inport.
§ signed/unsigned
The values of the Data inport are in fixed‑point format with or without one bit
reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
64-bit fixed-point data types are converted to double, except the data
type without a binary point (binary point position = 0). Therefore, the fixed-
point resolution of fixed-point data types with a binary point (binary point
position > 0) is restricted to 53 bits.
§ floating‑point
The values of the Data inport are in floating‑point format.
The 32‑bit data value supports the single-precision floating‑point format with a
fraction width of 24, which complies with the IEEE 754 standard (single).
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is displayed in the Binary point position (or fraction
width) setting.

Enable simulation data port Lets you enable an outport for offline
simulation data. The Sim_Data outport is added to the block to connect it to
any Simulink signal used for simulation.

Simulation ports sample time Lets you specify the sample time of the ports
used for simulation, for example, Sim_Data and Sim_Status. By default, the
sample time is inherited. You must only specify the sample time explicitly, if
the modeling situation inhibits to inherit the sample time, for example, if the

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corresponding PROC block is part of an asynchronous task or is used for multiple

access to the same channel.

Register Out description Block display If you specify the register access type, the block display
changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Data Specifies a 32-bit data value to be written to an IOCNET register. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Output
Sim_Data Simulates an IOCNET data exchange including fixed-point to floating-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1

Note

The range can be exceeded for the Data inport. The inport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register Out settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 299.

Register group ID Lets you specify a number in the range 1 … 63 to create

register groups. Registers that you specified with the same group ID are sampled
simultaneously in the FPGA application. The values form a consistent data group
that is written to the IOCNET.

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Buffer Out description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a 32-bit data value to be written to an IOCNET buffer. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Enable Specifies the current valid Data port value.
Data type: UFix_1_0
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.
Ready Explicitly specifies the buffer state as ready to send immediately, even if the buffer
is not completely filled. The data values are written to a new buffer in the following
clock cycle. While the port value is 1, the buffer switches every clock cycle. You are
therefore recommended to set the value for only one clock cycle. If the buffer is
completely filled, it is automatically switched, and the data values are stored in a
new buffer.
Data type: UFix_1_0
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready to send, even if it is not completely filled. The
buffer is switched and the data values are accessible via IOCNET in the following
clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.
Send_Ack Triggers a data transmission to IOCNET. With Send_Ack and Read_Req you can
trigger a processor synchronous data exchange.
A data transmission is always requested at the beginning of a task, before the
processor model is computed. Each time a new data transmission is requested by
Read_Req, Send_Ack must explicitly acknowledge the Data values for transmission
within one task period. To send current data, you can delay the transmission. After a
new data transmission is requested, you write the current data values to the buffer.
Then you must acknowledge the new data for transmission.

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Port Description
Available only if Enable Read_Req and Send_Ack ports for explicit data
transmit is set on the Parameters page. If Enable Read_Req and Send_Ack
ports for explicit data transmit is not set, each data transmission request will
instantly be acknowledged.
Data type: UFix_1_0
§ 0: Data values are not acknowledged for transmission.
§ 1: Current Data values are acknowledged and will be transmitted via IOCNET.
A data transmission request that is not acknowledged by Send Ack leads to task
overrun in the processor application. A task overrun will be logged as an I/O error in
the Messages page of the SCALEXIO system. The FPGA buffer that caused the task
overrun will also be logged.
Output
Sim_Data Simulates an IOCNET data exchange including fixed-point to floating-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768. The vector width depends on the specified buffer size.
Overflow Outputs a flag that indicates that a buffer overflow occurred. An overflow occurs if
the old buffer is not read completely before a new buffer is ready to be read.
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.
Data type: UFix_1_0
Sim_Status Outputs information about the simulated data exchange on the Sim_Data outport.
Available only if the access type is specified as Buffer and Enable simulation port
is set on the Parameters page.
Data type: UInt32
Data width: 3
§ Sim_Status[0]: Contains the number of valid elements in the Sim_Data vector.
§ Sim_Status[1]: Indicates whether the current buffer contains new or old values. It
is 1 if the buffer contains new values.
§ Sim_Status[2]: Indicates whether a buffer overflow occurred. At least one buffer
was not read and its data was lost before the currently read buffer was filled.
Read_Req Outputs a flag that indicates that a data transmission is requested via IOCNET. With
Read_Req and Send_Ack you can trigger a processor synchronous data exchange.
A data transmission is always requested at the beginning of a task, before the
processor model is computed. Each time a new data transmission is requested by
Read_Req, Send_Ack must explicitly acknowledge the Data values for transmission
within one task period. To send current data, you can delay the transmission. After a
new data transmission is requested, you write the current data values to the buffer.
Then you must acknowledge the new data for transmission.
Available only if Enable Read_Req and Send_Ack ports for explicit data
transmit is set on the Parameters page. If Enable Read_Req and Send_Ack
ports for explicit data transmit is not set, each data transmission request will
instantly be acknowledged.
Data type: UFix_1_0
§ 0: No data transmission is requested.
§ 1: A data transmission is requested. This value is set for one clock cycle.

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Port Description
A data transmission request that is not acknowledged by Send Ack leads to task
overrun in the processor application. A task overrun will be logged as an I/O error in
the Messages page of the SCALEXIO system. The FPGA buffer that caused the task
overrun will also be logged.

Note

The range can be exceeded for the Data inport. The inport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Buffer Out settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 299.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 32-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation status port Lets you enable an outport to get status
information about the simulation data that is available when you have enabled
the simulation data port. The Sim_Status outport is added to the block.

Enable Read_Req and Send_Ack ports for explicit data transmit Lets you
add the Read_Req and Send_Ack ports to the block to trigger a processor
synchronous data exchange.

Register64 Out description Block display If you specify the register access type, the block display
changes. The simulation ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Data Specifies a 64-bit data value to be written to an IOCNET register. The data format
depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double, except the data type
without a binary point (binary point position = 0). Therefore, the fixed-point
resolution of fixed-point data types with a binary point (binary point position > 0)
is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Output
Sim_Data Simulates an IOCNET data exchange including fixed-point to floating-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1

Note

The range can be exceeded for the Data inport. The inport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register64 Out settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 299.

Register group ID Lets you specify a number in the range 1 … 63 to create

register groups. All registers – 32‑bit and 64‑bit registers – which you specified
with the same group ID are sampled simultaneously in the FPGA application. The
values form a consistent data group that is written to the IOCNET.

Buffer64 Out description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a 64-bit data value to be written to an IOCNET buffer. The data format
depends on the related dialog settings.
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double, except the data type
without a binary point (binary point position = 0). Therefore, the fixed-point
resolution of fixed-point data types with a binary point (binary point position > 0)
is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Enable Specifies the current valid Data port value.
Data type: UFix_1_0
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.
Ready Explicitly specifies the buffer state as ready to send immediately, even if the buffer
is not completely filled. The data values are written to a new buffer in the following
clock cycle. While the port value is 1, the buffer switches every clock cycle. You are
therefore recommended to set the value for only one clock cycle. If the buffer is
completely filled, it is automatically switched, and the data values are stored in a
new buffer.
Data type: UFix_1_0
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready to send, even if it is not completely filled. The
buffer is switched and the data values are accessible via IOCNET in the following
clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.
Send_Ack Triggers a data transmission to IOCNET. With Send_Ack and Read_Req you can
trigger a processor synchronous data exchange.
A data transmission is always requested at the beginning of a task, before the
processor model is computed. Each time a new data transmission is requested by
Read_Req, Send_Ack must explicitly acknowledge the Data values for transmission
within one task period. To send current data, you can delay the transmission. After a
new data transmission is requested, you write the current data values to the buffer.
Then you must acknowledge the new data for transmission.
Available only if Enable Read_Req and Send_Ack ports for explicit data
transmit is set on the Parameters page. If Enable Read_Req and Send_Ack
ports for explicit data transmit is not set, each data transmission request will
instantly be acknowledged.
Data type: UFix_1_0
§ 0: Data values are not acknowledged for transmission.
§ 1: Current Data values are acknowledged and will be transmitted via IOCNET.

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Port Description
A data transmission request that is not acknowledged by Send Ack leads to task
overrun in the processor application. A task overrun will be logged as an I/O error in
the Messages page of the SCALEXIO system. The FPGA buffer that caused the task
overrun will also be logged.
Output
Sim_Data Simulates an IOCNET data exchange including fixed-point to floating-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768. The vector width depends on the specified buffer size or
the number of bus signals.
Overflow Outputs a flag that indicates that a buffer overflow occurred. An overflow occurs if
the old buffer is not read completely before a new buffer is ready to be read.
Available only if the bus transfer mode is disabled on the Parameters page.
Data type: UFix_1_0
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.
Sim_Status Outputs information about the simulated data exchange on the Sim_Data outport.
Available only if the access type is specified as Buffer and Enable simulation port
is set on the Parameters page.
Data type: UInt32
Data width: 3
§ Sim_Status[0]: Contains the number of valid elements in the Sim_Data vector.
§ Sim_Status[1]: Indicates whether the current buffer contains new or old values.
The status is 1 if the buffer contains new values.
§ Sim_Status[2]: Indicates whether a buffer overflow occurred. At least one buffer
was not read and its data was lost before the currently read buffer was filled.
Read_Req Outputs a flag that indicates that a data transmission is requested via IOCNET. With
Read_Req and Send_Ack you can trigger a processor synchronous data exchange.
A data transmission is always requested at the beginning of a task, before the
processor model is computed. Each time a new data transmission is requested by
Read_Req, Send_Ack must explicitly acknowledge the Data values for transmission
within one task period. To send current data, you can delay the transmission. After a
new data transmission is requested, you write the current data values to the buffer.
Then you must acknowledge the new data for transmission.
Available only if Enable Read_Req and Send_Ack ports for explicit data
transmit is set on the Parameters page. If Enable Read_Req and Send_Ack
ports for explicit data transmit is not set, each data transmission request will
instantly be acknowledged.
Data type: UFix_1_0
§ 0: No data transmission is requested.
§ 1: A data transmission is requested. This value is set for one clock cycle.
A data transmission request that is not acknowledged by Send Ack leads to task
overrun in the processor application. A task overrun will be logged as an I/O error in
the Messages page of the SCALEXIO system. The FPGA buffer that caused the task
overrun will also be logged.

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Buffer64 Out settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 299.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation status port Lets you enable an outport to get status
information about the simulation data that is available when you have enabled
the simulation data port. The Sim_Status outport is added to the block.

Enable Read_Req and Send_Ack ports for explicit data transmit Lets you
add the Read_Req and Send_Ack ports to the block to trigger a processor
synchronous data exchange.

Bus Out description Block display If you specify the buffer access type, the block display changes.
The Send_Ack, Read_Req, and Sim_Data ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a Simulink bus to be transmitted to the processor application.
The data types of the signals depend on the bus topology that is set via Copy bus
topology from corresponding processor block or Copy bus topology from gcb
on the Parameters page. The maximum bit width is 64 bits.
The resolution of the data type is restricted to 53 bits, because the block converts all
data values to double for transmission.
Send_Ack Triggers a data transmission to IOCNET. With Send_Ack and Read_Req, you can
trigger a processor synchronous data exchange.
A data transmission is always requested at the beginning of a task, before the
processor model is computed. Each time a new data transmission is requested by
Read_Req, Send_Ack must explicitly acknowledge the Data values for transmission
within one task period. To send the data in the desired state, you can wait to finish
last data processing before acknowledging the data transfer.
Available only if the User acknowledged bus data transmission method is set on
the Parameters page. If you use subchannels, only the first subchannel displays the
Read_Req and Send_Ack ports.

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Port Description
Data type: UFix_1_0
§ 0: Data values are not acknowledged for transmission.
§ 1: Current Data values are acknowledged and will be transmitted via IOCNET.
A data transmission request that is not acknowledged by Send Ack leads to task
overrun in the processor application. A task overrun will be logged as an I/O error in
the Messages page of the SCALEXIO system. The FPGA buffer that caused the task
overrun will also be logged.
Output
Sim_Data Simulates a data transmission including fixed-point to floating-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Simulink bus
Read_Req Outputs a flag that indicates that a data transmission is requested from the
processor application. A data transmission is always requested at the beginning of a
task, before the processor application is computed.
Available only if the User acknowledged bus data transmission method is set on
the Parameters page. If you use subchannels, only the first subchannel displays the
Read_Req and Send_Ack ports.
Data type: UFix_1_0
§ 0: No data transmission is requested.
§ 1: A data transmission is requested. This value is set for one clock cycle.
A data transmission request automatically triggers a data transmission.

Bus Out settings The following dialog settings are specific for the Bus access type. For common
dialog settings, refer to Common settings on page 299.

Buffer size Displays the size of the buffer in the range 1 … 32,768. The
buffer size depends on the number of bus signals.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1,024
words. For example, a buffer with a buffer size of 1 allocates a memory
block of 1,024 words with a data width of 64 bits in the FPGA memory.
This applies to any buffer and the related swinging buffer.

Edit bus topology Opens a dialog to display and configure the

bus signals. For more information, refer to Bus Editor Dialog -
FPGA_XDATA_READ_BL/FPGA_XDATA_WRITE_BL on page 66.

Copy bus topology from corresponding processor block Lets you copy an
existing bus topology from the corresponding processor block in the processor
model. For more information, refer to How to Use Simulink Buses of the
Processor Model to Model the Processor Communication (FPGA Programming
Blockset Guide ).

Analyze bus topology of input Lets you set the Data inport to the bus
topology of the connected Simulink bus.

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If clicked, the FPGA Programming Blockset analyzes the connected Simulink

bus and sets the Data port to a matching bus topology. For instructions,
refer to How to Use Simulink Buses of the FPGA Model to Model Processor
Communication (FPGA Programming Blockset Guide ).

Reset bus topology Lets you clear the bus topology of the Data port.

Bus data transmission method Lets you select the method for transmitting
data to the processor application:
§ Synchronous to task method
Select this method to transmit data that is captured synchronously to the
processor task.
The FPGA application writes data to the swinging buffer when the processor
application makes a read request. After the data is written to the buffer, the
buffer swings and sends the data to the processor application.
§ Free running method
Select this method if the transmission time is crucial.
The FPGA application continuously writes data to the swinging buffer. A read
request of the processor application immediately transmits the last complete
data set of the swinging buffer to the processor application.
§ User acknowledged method
Select this method to acknowledge the data to be transmitted to the processor
application, for example, to trigger the processing of some data before it is
transmitted to the processor application.
The FPGA application writes data to the swinging buffer when you
acknowledge the data with the Send_Ack port. After the data is written to
the buffer, the buffer swings and sends the data to the processor application.
You must acknowledge each data transmission request so that data transfer is
synchronous to the processor task, as with the Synchronous to task method.
For instructions, refer to How to Configure the Bus Data Transmission Method
(FPGA Programming Blockset Guide ).

Related topics Basics

Modeling Processor Model Access (FPGA Programming Blockset Guide )

FPGA_IO_READ_BL (DS6602 FPGA Base Board Settings)

Purpose To configure read access to analog and digital input signals in the FPGA model
when using the DS6602 (KU15P) FPGA Base Board framework.

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Where to go from here Information in this section

Parameters Page (FPGA_IO_READ_BL)................................................... 310

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_READ_BL).......................................................... 322

The Scaling page is empty because the I/O functions of this framework
do not support FPGA scaling.

Information in other sections

Unit Page (FPGA_IO_READ_BL)................................................................ 55

To specify the I/O type and channel to be used for read access.

Parameters Page (FPGA_IO_READ_BL)

Purpose To specify relevant settings for the selected I/O function.

Description The framework provides the I/O types APU, IFPGA32, IFPGA64, and Others,
which you can select on the Unit page of the block. The number of the available
physical connections determines the I/O functions that you can select:
§ APU Slave 1 … 6
§ CN APP Status
§ I‑FPGA In 1 … 32 (IOCNET)
§ I‑FPGA64 In 1 … 32 (IOCNET)
§ IOCNET Global Time
§ Status In
§ Subsystem Clock
§ System Clock
§ System Signal Block
§ Temperature
§ Watchdog

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_IO_READ_BL block.

Enable simulation port Lets you enable an inport for offline simulation data.
The Sim_Data inport is added to the block so you can connect it to simulation
data coming from a Simulink-based I/O environment model.

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APU Slave 1 ... 6 description Block display If you select the APU Slave channel from the channel list, the
block display changes. For example:

I/O characteristics The following table describes the port of the block for
digital input channels:

Port Description
Input
Sim Phi Read Simulates the APU bus value for Phi Read.
Available only if Enable simulation Phi Read port is set on the
Parameters page.
Data type: Double
Data width: 1
The value range depends on the angle range of the simulated APU bus:
§ 360 ° angle range: 0 ... 32767 (215-1)
§ 720 ° angle range: 0 ... 65535 (216-1)
APU bus clock cycle: 8 ns
The range can be exceeded, and saturation is performed to a minimum or
maximum value.
Sim Rev Read Simulates the hardware input value for Rev Read.
Available only if Enable simulation Rev Read port is set on the
Parameters page.
Data type: Double
Data width: 1
The 37-bit range is -236 ... +236 - 1.
APU bus clock cycle: 8 ns
It is not possible to exceed the range.
Sim Phi Read HD Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Sim Delta Phi Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Sim Delta Phi Enable Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Sim Angle Range Simulates the angle range of the APU bus.
Available only if Enable simulation Angle Range port is set on the
Parameters page.
Data type: Double
Data width: 1
Values:
§ 0 (low): 720 ° angle range
§ 1 (high): 360 ° angle range
Output

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Port Description
Phi Read Outputs the angle value that APU Slave reads from the APU bus. The angle
value is independent from the angle range of the APU bus.
Formula for angle calculation: alpha[°] = Phi Read * 720°/216
Data type: UFix_16_0
Data width: 1
The value range depends on the angle range of the APU bus:
§ 360 ° angle range: 0 ... 32767 (215-1)
§ 720 ° angle range: 0 ... 65535 (216-1)
APU bus clock cycle: 8 ns
It is not possible to exceed the range.
Rev Read Outputs the 37 bit total revolution (rev) value for the APU bus.
Data type: Double
Data width: 1
The 37-bit range is -236 ... 236 - 1.
The APU bus clock cycle is 8 ns. It is not possible to exceed the range.
Phi Read HD Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Delta Phi Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Delta Phi Enable Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Angle Range Outputs the angle range of the APU bus.
Data type: UFix_1_0
Data width: 1
Values:
§ 0 (low): 720 ° angle rangeThe angle range is 0° ... 720°
§ 1 (high): 360 ° angle range

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping No external connection.

APU Slave 1 ... 6 settings The Parameters page provide the following dialog setting:

Enable Phi Read HD port The Phi Read HD port is available in the block
only if you enable it.

Enable Delta Phi port The Delta Phi port is available in the block only if you
enable it.

Enable Delta Phi Enable port The Delta Phi Enable port is available in the
block only if you enable it.

Enable simulation Phi Read port The Sim Phi Read port is available in the
block only if you enable it.

Enable simulation Rev Read port The Sim Rev Read port is available in the
block only if you enable it.

Enable simulation Phi Read HD port The Sim Phi Read HD port is
available in the block only if you enable it.

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Enable simulation Delta Phi port The Sim Delta Phi port is available in the
block only if you enable it.

Enable simulation Delta Phi Enable port The Sim Delta Phi Enable port is
available in the block only if you enable it.

Enable simulation Angle Range port The Sim Angle Range port is
available in the block only if you enable it.

Angle range For the slave APU, you can inherit the angle range of the APU
bus or you specify a local angle range independent from the APU bus. The
following table shows you the possible combinations of angle range settings.

APU Bus Slave APU Resulting Angle Range of the Slave

Setting Setting APU
360° Inherit 360°
720° 720°
360° 360° 360°
720° 720° 1)
720° 360° 360° 2)
720° 720°
1) Two engine cycles are required to run through the 720 ° angle range. If you simulate a
four-stroke piston engine, for example, the angle values of the function block are not
clearly related to the camshaft position.
2) One engine cycle runs twice through the 360 ° angle range.

CN App Status description Block display If you select the CN App Status channel from the channel list,
the block display changes.

I/O characteristics The following table describes the port of the block:

Port Description
Output
Status Outputs the state of the application that is running on the computation node.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The application on the computation node is stopped.
§ 1: The application on the computation node is running.

I/O mapping No external connection.

CN App Status settings None

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I-FPGA In 1 … 32 (IOCNET) Block display If you select the I-FPGA In (IOCNET) channel from the channel
description list, the block display changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Address Specifies a data value in the IOCNET buffer to be read. The block requires
one clock cycle to update the value of the Data outport with the data value
of the specified address.
Data type: UFix_16_0
Data width: 1
The maximum address range depends on the Buffer size on the Parameters
page. The address range with valid data values can be derived from the value
of the Data Count port.
Sim Data Simulates a data exchange between two FPGA boards via IOCNET. The
provided data values are converted to the data format of the Data port
and written to a simulated IOCNET buffer.
Available only if the Enable simulation data port is set on the Parameters
page.
Data type: Double
Data width: 1 … 1024
Range: Single precision value range
Sim Data New Simulates the reception of new data values.
Available only if the Enable simulation data new port is set on the
Parameters page.
Data type: Double
Data width: 1
Values:
§ 0: The reception of new data values is not simulated.
§ 1: The Data New port changes from 0 to 1 for one clock cycle to indicate
new data values.
Output
Data Outputs a 32-bit raw data value from the specified address of the IOCNET
buffer.
Data type: UFix_32_0
Data width: 1

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Port Description
Data New Outputs a flag that indicates the update of the Data port.
Data type: UFix_1_0
Data width: 1
If the flag changes from 0 to 1 and then to 0 again, the requested buffer
contains new values and is ready to be read. The flag is set to 1 within only
one clock cycle.
Data Count Outputs the number of elements in the current IOCNET buffer. You can use
the value to define the valid range for the Address port from 0 to (Data
Count -1).
Data type: UFix_16_0
Data width: 1
The maximum value range depends on the Buffer size on the Parameters
page.

Note

You can transfer any data type with a bit width of up to 32 Bit via inter-
FPGA over IOCNET. Use the Reinterpret block from the HDL library of the
AMD Vitis Model Composer to change your data type to UFix_32_0 and
vice versa. Reinterpreting data types does not cost any hardware or latency.
The range can be exceeded for the Data outport. The outport's value is
then cast to UFix_32_0.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I-FPGA In 1 … 32 (IOCNET) The following dialog settings are specific for the I-FPGA In (IOCNET) I/O
settings function. For common dialog settings, refer to Common settings on page 310.

Buffer size Lets you specify the size of the IOCNET buffer in the range
1 … 1024. The maximum range of the Address inport depends on the buffer
size.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 32-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation data port Lets you enable an inport for offline simulation
data.
The Sim Data inport is added to the block.

Enable simulation data new port Lets you enable an inport for the offline
simulating of new data values at the Data outport.
The Sim Data New inport is added to the block.

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I-FPGA64 In 1 … 32 (IOCNET) Block display If you select the I-FPGA64 Out (IOCNET) channel from the
description channel list, the block display changes. The simulation ports are displayed
optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Address Specifies a data value in the IOCNET buffer to be read. The block requires
one clock cycle to update the value of the Data outport with the data value
of the specified address.
Data type: UFix_16_0
Data width: 1
The maximum address range depends on the Buffer size on the Parameters
page. The address range with valid data values can be derived from the value
of the Data Count port.
Sim Data Simulates a data exchange between two FPGA boards via IOCNET. The
provided data values are converted to the data format of the Data port
and written to a simulated IOCNET buffer.
Available only if the Enable simulation data port is set on the Parameters
page.
Data type: Double
Data width: 1 … 512
Range: Double precision value range
Sim Data New Simulates the reception of new data values.
Available only if the Enable simulation data new port is set on the
Parameters page.
Data type: Double
Data width: 1
Values:
§ 0: The reception of new data values is not simulated.
§ 1: The Data New port changes from 0 to 1 for one clock cycle to indicate
new data values.
Output
Data Outputs a 64-bit raw data value from the specified address of the IOCNET
buffer.
Data type: UFix_64_0
Data width: 1

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Port Description
Data New Outputs a flag that indicates the update of the Data port.
Data type: UFix_1_0
Data width: 1
If the flag changes from 0 to 1 and then to 0 again, the requested buffer
contains new values and is ready to be read. The flag is set to 1 within only
one clock cycle.
Data Count Outputs the number of elements in the current IOCNET buffer. You can use
the value to define the valid range for the Address port from 0 to (Data
Count -1).
Data type: UFix_16_0
Data width: 1
The maximum value range depends on the Buffer size on the Parameters
page.

Note

You can transfer any data type with a bit width of up to 64 Bit via inter-
FPGA over IOCNET. Use the Reinterpret block from the HDL library of the
AMD Vitis Model Composer to change your data type to UFix_64_0 and
vice versa. Reinterpreting data types does not cost any hardware or latency.
The range can be exceeded for the Data outport. The outport's value is
then cast to UFix_64_0.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I-FPGA64 In 1 … 32 (IOCNET) The following dialog settings are specific for the I-FPGA64 In (IOCNET) I/O
settings function. For common dialog settings, refer to Common settings on page 310.

Buffer size Lets you specify the size of the IOCNET buffer in the range
1 … 512. The maximum range of the Address inport depends on the buffer
size.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64 bits in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation data port Lets you enable an inport for offline simulation
data.
The Sim Data inport is added to the block.

Enable simulation data new port Lets you enable an inport for the offline
simulating of new data values at the Data outport.
The Sim Data New inport is added to the block.

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IOCNET Global Time Block display If you select the IOCNET Global Time channel from the channel
description list, the block display changes.

I/O characteristics The following table describes the port of the block:

Port Description
Output
Time Outputs the number of hardware ticks that occurred since the SCALEXIO system
power was switched to on. If you use a multiprocessor system, the value is set to
zero each time an application is reloaded and restarted.
Data type: 56 bit
Tick step-width: 8.5 ns

I/O mapping No external connection.

IOCNET Global Time settings None

Status In description Block display If you select the Status In channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Output
Init Done Outputs the state of the initialization sequence that is started after programming
the FPGA.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Initialization sequence is in progress.
§ 1: Initialization sequence has finished.

I/O mapping No external connection.

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Status In settings None

Subsystem Clock description Block display If you select the Subsysten Clock channel from the channel list,
the block display changes.

I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Output
Subsystem Outputs the clock signal of the selected subsystem clock domain. You specify the
Clock subsystem clock domain in the FPGA Setup block. Refer to How to Use Multiple
Clock Domains for FPGA Modeling (FPGA Programming Blockset Guide ).
Data type: UFix_1_0
Data width: 1

Multiple clock domain support This block is intended to be used in a user

clock domain with an individual clock period.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping No external connection.

Subsystem Clock settings None

System Clock description Block display If you select the Systen Clock channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Output
System Clock Outputs the clock signal of the FPGA (base clock rate).
Data type: UFix_1_0
Data width: 1

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Multiple clock domain support This block is intended to be used in a user

clock domain with an individual clock period.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping No external connection.

System Clock settings None

System Signal Block Block display If you select the System Signal Block channel from the channel
description list, the block display changes.

I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Output
System Clock Outputs the clock signal of the FPGA (base clock rate).
Data type: UFix_1_0
Data width: 1
Init Done Outputs the state of the initialization sequence that is started after programming
the FPGA.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Initialization sequence is in progress.
§ 1: Initialization sequence has finished.
CN App Outputs the state of the processor application.
Status Data type: UFix_1_0
Data width: 1
Values:
§ 0: The processor application is stopped.
§ 1: The processor application is running.
Opto_Ready Indicates whether the MGT module is ready for data exchange. The port changes
to 1 during the initialization phase, i.e., before the CN APP Status port changes
from stop to running. If no MGT module is connected to the dSPACE hardware, the
port value remains 0.
Data type: UFix_1_0
Data width: 1

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Port Description
If the MGT module is ready, the flag changes from 0 to 1:
§ 0: The MGT module is not ready.
§ 1: The MGT module is ready.

Multiple clock domain support This block is intended to be used in a user

clock domain with an individual clock period.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping No external connection.

System Signal Block settings None

Temperature description Block display If you select the Temperature channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block for
the die temperature input channel:

Port Description
Input
Sim_Temp Simulates the FPGA's die temperature (internal chip temperature).
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Input temperature range: -274.00 °C … 230.00 °C
The range can be exceeded. The values are then saturated to the minimum or
maximum values.
Output
RAW_temp Outputs the FPGA's die temperature measurement.
Data type: Fix_20_10
Data width: 1
Value range: -274.00 °C … 230.00 °C

I/O mapping No external connection.

Temperature settings Only common dialog settings. Refer to Common settings on page 310.

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Watchdog description Block display If you select the Watchdog channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block for
the watchdog input channel:

Port Description
Output
Status Outputs a flag that indicates that the processor application transmits a keep-alive
signal within the specified timeout.
§ 0: The watchdog timer expires without a keep-alive signal being transmitted to
the FPGA application.
§ 1: The processor application is alive.
Data type: UFix_1_0

Tip

In ConfigurationDesk, you deactivate the watchdog functionality by not

mapping the Trigger port of the watchdog function to a model port.
If deactivated, the Status port of the Watchdog block always outputs 1 in
the FPGA application.

Watchdog settings None

Related topics Basics

Modeling Inter-FPGA Communication via IOCNET (FPGA Programming Blockset

Guide )
Using a Watchdog (FPGA Programming Blockset Guide )

Scaling Page (FPGA_IO_READ_BL)

Description The Scaling page is empty because the I/O functions of this framework do not
support FPGA scaling.

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Frameworks with scaling The frameworks of the I/O modules support FPGA scaling:
support § DS2655M1 I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 350
§ Scaling Page (FPGA_IO_WRITE_BL) on page 363
§ DS2655M2 Digital I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 377
§ Scaling Page (FPGA_IO_WRITE_BL) on page 397
§ DS6651 Multi-I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 413
§ Scaling Page (FPGA_IO_WRITE_BL) on page 445

Related topics Basics

Basics on FPGA Test Access and Scaling (FPGA Programming Blockset Guide )

FPGA_IO_WRITE_BL (DS6602 FPGA Base Board Settings)

Purpose To configure write access to analog and digital output signals in the FPGA model
when using the DS6602 (KU15P) FPGA Base Board framework.

Where to go from here Information in this section

Parameters Page (FPGA_IO_WRITE_BL).................................................. 323

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_WRITE_BL)........................................................ 342

The Scaling page is empty because the I/O functions of this framework
do not support FPGA scaling.

Information in other sections

Unit Page (FPGA_IO_WRITE_BL)............................................................... 60

To specify the I/O type and channel to be used for write access.

Parameters Page (FPGA_IO_WRITE_BL)

Purpose To specify relevant settings for the selected I/O function.

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Description The framework provides the I/O types APU, IFPGA32, IFPGA64, and Other, which
you can select on the Unit page of the block. The number of the available
physical connections determines the I/O functions that you can select:
§ APU Master 1 … APU Master 6
§ DDR4 32 Mode 1
§ DDR4 64 Mode 1
§ DDR4 32 Mode 2
§ DDR4 64 Mode 2
§ I-FPGA Out 1 … 32 (IOCNET)
§ I-FPGA64 Out 1 … 32 (IOCNET)
§ LED Out
§ User Clock Out 1 … 32

Common settings None

APU Master 1 … 6 description Block display If you select the APU Master channel from the channel list, the
block display changes. For example:

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Velocity Specifies a velocity value in degree/second to be applied as APU Master
speed.
The value will be applied if Set Velocity is 1 (high) and Busy is 0 (low).
Data type: Fix_32_10
Data width: 1
Range: -1,200,000 °/s ... +1,200,000 °/s
It is not possible to exceed the range. The port is saturated at the higher or
lower limit.
Set Velocity Specifies the current value of Velocity as new velocity value.
The new value is set only if Set Velocity is 1 (high) and Busy is 0 (low).
Data type: UFix_1_0
Data width: 1
To distribute and execute a new velocity value takes at least 10 μs,
depending on the IOCNET structure.
Output

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Port Description
Phi Read Outputs the angle counter value of the APU that the APU Master writes to
the APU bus. The step size of the angle counter is approximately 0.011°. The
step size is independent from the angle range.
Formula for angle calculation: alpha[°] = Phi Read * 720°/216
Data type: UFix_16_0
Data width: 1
The value range depends on the Angle range on the Parameters page:
§ 360 ° angle range: 0 ... 32767 (215-1)
§ 720 ° angle range: 0 ... 65535 (216-1)
APU bus clock cycle: 8 ns
It is not possible to exceed the range.
Rev Read Outputs the 37 bit total revolution (rev) value that APU Master reads from
the APU bus.
Data type: Fix_37_0
Data width: 1
The 37-bit range is -236 ... 236 - 1.
APU bus clock cycle: 8 ns
It is not possible to exceed the range.
Phi Read HD Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Delta Phi Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Delta Phi Enable Internal port - only for use in the dSPACE Electric Motor HIL Solution.
Angle Range Outputs the angle range of the APU bus. You set the angle range on the
Parameters page.
Data type: UFix_1_0
Data width: 1
Values:
§ 0 (low): 720 ° angle range
§ 1 (high): 360 ° angle range
Busy Outputs whether APU Master is busy to set the last velocity value.
Data type: UFix_1_0
Data width: 1
If the Busy port is 1 (high), new velocity values cannot be set.
The Busy port stays active for at least 10 µs depending on the IOCNET
structure.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping No external connection.

APU Master 1 … 6 settings The Parameters page provides the following dialog setting:

Angle range Lets you select the angle range of the APU in degree.
§ 360: The angle range is 360° and cannot be changed in ConfigurationDesk.
§ 720: The angle range is 720° and cannot be changed in ConfigurationDesk.

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§ Individual: The Angle range property of the FPGA custom function block in
ConfigurationDesk lets you set the angle range of the APU. The default value
is 720°.

Initial position Lets you set the initial APU master position in degree.
§ Value range: -1440° ... +1440°

Enable advanced ports The internal ports for the dSPACE Electric Motor HIL
Solution are available in the block only if you enable it.

DDR 4 32 Mode 1 description Block display If you select the DDR 4 32 Mode 1 channel from the channel
list, the block display changes.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Write Specifies a 32-bit data value to be written to the RAM. 16 ports specify 16 data
1 … 16 values. The Address port specifies the memory address to write the data values.
Data type: UFix_32_0
Data width: 1 per port
Address Specifies the first element in the RAM for the read/write access. The memory is
addressed 512 bit-wise to read/write 16 x 32-bit data values with the same address.
Data type: UFix_26_0
Data width: 1
Range: 0 … 67,108,863 (226-1)

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Port Description
Enable Enables the RAM access.
Data type: UFix_1_0
Data width: 1
Values:
§ 1: Data values are written to the RAM or read from the RAM.
§ 0: No read/write access.
Direction Controls the direction of data access.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Write access
§ 1: Read access
Output
Data Read Outputs a 32-bit data value to be read from the RAM. 16 ports output 16 data
1 … 16 values. The Address port specifies the memory address to read the data values.
Data type: UFix_32_0
Data width: 1 per port
Busy Outputs a flag that indicates the state of the DDR4 RAM.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The DDR4 module is ready for new read/write operations.
§ 1: The DDR4 module is busy.
Data valid Outputs a flag that indicates that the data values of the Data Read ports are valid.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The values are not valid.
§ 1: The values are valid. This value is set for one clock cycle. The data values must
be read by the FPAG application within the same clock cycle.
Init Done Outputs a flag that indicates that the RAM is initialized with specified data values.
For more information, refer to Modeling DDR4 RAM Access (FPGA Programming
Blockset Guide ).
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The RAM is not initialized.
§ 1: The RAM is initialized.
Init Failed Outputs a flag that the initializing of the RAM with initial values failed.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The RAM is not initialized or no failure occurs.
§ 1: A failure occurs during the initialization of the RAM.

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Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping No external connection.

DDR 4 32 Mode 1 settings The Parameters page provides the following dialog setting:

Simulation init variable Lets you enter a workspace variable that provides
values to initialize the RAM memory during offline simulation.
If the workspace variable does not provide a data value for each element of
the RAM memory, the remaining elements are initialized with 0. For more
information, refer to Initializing the DDR4 RAM of the DS6602 for Offline
Simulation (FPGA Programming Blockset Guide ).

DDR 4 64 Mode 1 description Block display If you select the DDR 4 64 Mode 1 channel from the channel
list, the block display changes.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Write Specifies a 64-bit data value to be written to the RAM. 8 ports specify 8 data values
1…8 at the same time. The Address port specifies the memory address to write the data
values.
Data type: UFix_64_0
Data width: 1 per port
Address Specifies the first element in the RAM for the read/write access. The memory is
addressed 512 bit-wise to read/write 8 x 64-bit data values with the same address.
Data type: UFix_26_0
Data width: 1
Range: 0 … 67,108,863 (226-1)

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Port Description
Enable Enables the RAM access.
Data type: UFix_1_0
Data width: 1
Values:
§ 1: Data values are written to the RAM or read from the RAM.
§ 0: No read/write access.
Direction Controls the direction of data access.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Write access
§ 1: Read access
Output
Data Read Outputs a 32-bit data value to be read from the RAM. 8 ports output 8 data values
1 … 16 at the same time. The Address port specifies the memory address to read the data
values.
Data type: UFix_64_0
Data width: 1 per port
Busy Outputs a flag that indicates the state of the DDR4 RAM
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The DDR4 module is ready for new read/write operations.
§ 1: The DDR4 module is busy.
Data valid Outputs a flag that indicates that the data values of the Data Read ports are valid.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The values are not valid.
§ 1: The values are valid. This value is set for one clock cycle. The data values must
be read by the FPAG application within the same clock cycle.
Init Done Outputs a flag that indicates that the RAM is initialized with specified data values.
For more information, refer to Modeling DDR4 RAM Access (FPGA Programming
Blockset Guide ).
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The RAM is not initialized.
§ 1: The RAM is initialized.
Init Failed Outputs a flag that the initializing of the RAM with initial values failed.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The RAM is not initialized or no failure occurs.
§ 1: A failure occurs during the initialization of the RAM.

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Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping No external connection.

DDR 4 64 Mode 1 settings The Parameters page provides the following dialog setting:

Simulation init variable Lets you enter a workspace variable that provides
values to initialize the RAM memory during offline simulation.
If the workspace variable does not provide a data value for each element of
the RAM memory, the remaining elements are initialized with 0. For more
information, refer to Initializing the DDR4 RAM of the DS6602 for Offline
Simulation (FPGA Programming Blockset Guide ).

DDR 4 32 Mode 2 description Block display If you select the DDR 4 32 Mode 2 channel from the channel
list, the block display changes.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Write Specifies a 32-bit data value to be written to the RAM. 8 ports specify 8 data values
A1 … A8 at the same time.
The Address A port specifies the memory address to write the data values.
Data type: UFix_32_0
Data width: 1 per port

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Port Description
Data Write Specifies a 32-bit data value to be written to the RAM. 8 ports specify 8 data values
B1 … B8 at the same time.
The Address B port specifies the memory address to write the data values.
Data type: UFix_32_0
Data width: 1 per port
Address A Specifies the first element in the RAM for the read/write access of the Data
Write A/Data Read A ports. The memory is addressed 256 bit-wise to read/write
8 x 32-bit data values with the same address.
Data type: UFix_27_0
Data width: 1
Range: 0 … 134,217,727 (227-1)
Address B Specifies the first element in the RAM for the read/write access of the Data
Write B/Data Read B ports. The memory is addressed 256 bit-wise to read/write
8 x 32-bit data values with the same address.
Data type: UFix_27_0
Data width: 1
Range: 0 … 134,217,727 (227-1)
Enable Enables the RAM access.
Data type: UFix_1_0
Data width: 1
Values:
§ 1: Data values are written to the RAM or read from the RAM.
§ 0: No read/write access.
Direction Controls the direction of data access.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Write access
§ 1: Read access
Output
Data Read Outputs a 32-bit data value to be read from the RAM. 8 ports output 8 data values
A1 … A8 at the same time. The Address A port specifies the memory address to read the
data values.
Data type: UFix_32_0
Data width: 1 per port
Data Read Outputs a 32-bit data value to be read from the RAM. 8 ports output 8 data values
B1 … B8 at the same time. The Address B port specifies the memory address to read the
data values.
Data type: UFix_32_0
Data width: 1 per port

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Port Description
Busy Outputs a flag that indicates the state of the DDR4 RAM.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The DDR4 module is ready for new read/write operations.
§ 1: The DDR4 module is busy.
Data valid A Outputs a flag that indicates that the data values of the Data Read A ports are
valid
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The values are not valid.
§ 1: The values are valid. This value is set for one clock cycle. The data values must
be written within the same clock cycle.
Data valid B Outputs a flag that indicates that the data values of the Data Read B ports are valid
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The values are not valid.
§ 1: The values are valid. This value is set for one clock cycle. The data values must
be read by the FPAG application within the same clock cycle.
Init Done Outputs a flag that indicates that the RAM is initialized with specified data values.
For more information, refer to Modeling DDR4 RAM Access (FPGA Programming
Blockset Guide ).
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The RAM is not initialized.
§ 1: The RAM is initialized.
Init Failed Outputs a flag that the initializing of the RAM with initial values failed.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The RAM is not initialized or no failure occurs.
§ 1: A failure occurs during the initialization of the RAM.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping No external connection.

DDR 4 32 Mode 2 settings The Parameters page provides the following dialog setting:

Simulation init variable Lets you enter a workspace variable that provides
values to initialize the RAM memory during offline simulation.

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If the workspace variable does not provide a data value for each element of
the RAM memory, the remaining elements are initialized with 0. For more
information, refer to Initializing the DDR4 RAM of the DS6602 for Offline
Simulation (FPGA Programming Blockset Guide ).

DDR 4 64 Mode 2 description Block display If you select the DDR 4 32 Mode 2 channel from the channel
list, the block display changes.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Write Specifies a 64-bit data value to be written to the RAM. 4 ports specify 4 data values
A1 … A4 at the same time.
The Address A port specifies the memory address to write the data values.
Data type: UFix_64_0
Data width: 1 per port
Data Write Specifies a 64-bit data value to be written to the RAM. 4 ports specify 4 data values
B1 … B4 at the same time.
The Address B port specifies the memory address to write the data values.
Data type: UFix_64_0
Data width: 1 per port
Address A Specifies the first element in the RAM for the read/write access of the Data
Write A/Data Read A ports. The memory is addressed 256 bit-wise to read/write
4 x 64-bit data values with the same address.
Data type: UFix_27_0
Data width: 1
Range: 0 … 134,217,727 (227-1)
Address B Specifies the first element in the RAM for the read/write access of the Data
Write B/Data Read B ports. The memory is addressed 256 bit-wise to read/write
4 x 64-bit data values with the same address.
Data type: UFix_27_0
Data width: 1
Range: 0 … 134,217,727 (227-1)

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Port Description
Enable Enables the RAM access.
Data type: UFix_1_0
Data width: 1
Values:
§ 1: Data values are written to the RAM or read from the RAM.
§ 0: No read/write access.
Direction Controls the direction of data access.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Write access
§ 1: Read access
Output
Data Read Outputs a 64-bit data value to be read from the RAM. 4 ports output 4 data values
A1 … A4 at the same time. The Address A port specifies the memory address to read the
data values.
Data type: UFix_64_0
Data width: 1 per port
Data Read Outputs a 64-bit data value to be read from the RAM. 4 ports output 4 data values
B1 … B4 at the same time. The Address B port specifies the memory address to read the
data values.
Data type: UFix_64_0
Data width: 1 per port
Busy Outputs a flag that indicates the state of the DDR4 RAM.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The DDR4 module is ready for new read/write operations.
§ 1: The DDR4 module is busy.
Data valid A Outputs a flag that indicates that the data values of the Data Read A ports are
valid.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The values are not valid.
§ 1: The values are valid. This value is set for one clock cycle. The data values must
be read by the FPAG application within the same clock cycle.
Data valid B Outputs a flag that indicates that the data values of the Data Read B ports are
valid.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The values are not valid.
§ 1: The values are valid. This value is set for one clock cycle. The data values must
be read by the FPAG application within the same clock cycle.

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Port Description
Init Done Outputs a flag that indicates that the RAM is initialized with specified data values.
For more information, refer to Modeling DDR4 RAM Access (FPGA Programming
Blockset Guide ).
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The RAM is not initialized.
§ 1: The RAM is initialized.
Init Failed Outputs a flag that the initializing of the RAM with initial values failed.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The RAM is not initialized or no failure occurs.
§ 1: A failure occurs during the initialization of the RAM.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping No external connection.

DDR 4 64 Mode 2 settings The Parameters page provides the following dialog setting:

Simulation init variable Lets you enter a workspace variable that provides
values to initialize the RAM memory during offline simulation.
If the workspace variable does not provide a data value for each element of
the RAM memory, the remaining elements are initialized with 0. For more
information, refer to Initializing the DDR4 RAM of the DS6602 for Offline
Simulation (FPGA Programming Blockset Guide ).

I-FPGA Out 1 … 32 (IOCNET) Block display If you select the I-FPGA Out (IOCNET) channel from the
description channel list, the block display changes. The simulation ports are displayed
optionally.

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I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a 32-bit raw data value to be written to an IOCNET buffer.
Data type: UFix_32_0
Data width: 1
Enable Specifies the current valid Data port value.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The Data value to be written is not stored in the IOCNET buffer.
§ 1: The Data value to be written is stored in the IOCNET buffer. The value of the
current clock cycle is used.
Ready Explicitly specifies the buffer state as ready to send immediately, even if the buffer
is not completely filled. The data values are written to a new buffer in the following
clock cycle. While the port value is 1, the buffer switches every clock cycle. You are
therefore recommended to set the value for only one clock cycle. If the buffer is
completely filled, it is automatically switched, and the data values are stored in a
new buffer.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready to send, even if it is not completely filled.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.
Send Triggers a data transmission via IOCNET.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Data values are not acknowledged for transmission.
§ 1: Current Data values are acknowledged and will be transmitted via IOCNET.
Output
Overflow Outputs a flag that indicates that a buffer overflow occurred. An overflow occurs
when the new buffer is triggered for transmission and the old buffer was not sent
completely.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.
Sim Data Simulates a data exchange between two FPGA boards via IOCNET. The port
provides the data values that are written to a simulated IOCNET buffer, including
fixed-point to floating-point data conversion.
Available only if the Enable simulation data port is set on the Parameters page.

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Port Description
Data type: Double
Data width: 1 … 1024, depends on the Buffer size parameter.
Range: Single precision value range
Sim Data New Simulates the update of data values provided by the Sim Data outport.
Available only if the Enable simulation data new port is set on the Parameters
page.
Data type: Double
Data width: 1
A transition from 0 to 1 indicates that the Sim Data outport provides new data.
Sim Status Outputs information about the simulated data exchange on the Sim Data outport.
Available only if the Enable simulation status port is set on the Parameters
page.
Data type: UInt32
Data width: 3
§ Sim Status[0]: Contains the number of valid elements in the Sim Data vector.
§ Sim Status[1]: Indicates whether the current buffer contains new or old values.
The status is 1 if the buffer contains new values.
§ Sim Status[2]: Indicates whether a buffer overflow occurred. At least one buffer
was not read and its data was lost before the currently read buffer was filled.

Note

You can transfer any data type with a bit width of up to 32 Bit via inter-
FPGA over IOCNET. Use the Reinterpret block from the HDL library of the
AMD Vitis Model Composer to change your data type to UFix_32_0 and
vice versa. Reinterpreting data types does not cost any hardware or latency.
The range of the Data inport can be exceeded. The value of the inport is
then cast to the raw data format UFix_32_0.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I-FPGA Out 1 … 32 (IOCNET) The Parameters page provide the following dialog setting:
settings
Buffer size Lets you specify the size of the IOCNET buffer in the range
1 … 1024.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 32-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation data port Lets you enable an outport for offline
simulation data.
The Sim Data inport is added to the block.

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Enable simulation data new port Lets you enable an outport for the offline
simulating of new data values at the Sim Data inport.
The Sim Data New outport is added to the block.

Enable simulation status port Lets you enable an outport to get status
information about the simulation data that is available when you enabled a
simulation port. The Sim Status outport is added to the block.

I-FPGA64 Out 1 … 32 Block display If you select the I-FPGA64 Out (IOCNET) channel from the
(IOCNET) description channel list, the block display changes. The simulation ports are displayed
optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a 64-bit raw data value to be written to an IOCNET buffer.
Data type: UFix_64_0
Data width: 1
Enable Specifies the current valid Data port value.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The Data value to be written is not stored in the IOCNET buffer.
§ 1: The Data value to be written is stored in the IOCNET buffer. The value of the
current clock cycle is used.
Ready Explicitly specifies the buffer state as ready to send immediately, even if the buffer
is not completely filled. The data values are written to a new buffer in the following
clock cycle. While the port value is 1, the buffer switches every clock cycle. You are
therefore recommended to set the value for only one clock cycle. If the buffer is
completely filled, it is automatically switched, and the data values are stored in a
new buffer.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready to send, even if it is not completely filled.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.

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Port Description
Send Triggers a data transmission via IOCNET.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Data values are not acknowledged for transmission.
§ 1: Current Data values are acknowledged and will be transmitted via IOCNET.
Output
Overflow Outputs a flag that indicates that a buffer overflow occurred. An overflow occurs
when the new buffer is triggered for transmission and the old buffer was not sent
completely.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.
Sim_Data Simulates a data exchange between two FPGA boards via IOCNET. The port
provides the data values that are written to a simulated IOCNET buffer.
Available only if the Enable simulation data port is set on the Parameters page.
Data type: Double
Data width: 1 … 512, depends on the Buffer size parameter.
Range: Double precision value range
Sim_Data Simulates the update of data values provided by the Sim Data outport.
New Available only if the Enable simulation data new port is set on the Parameters
page.
Data type: Double
Data width: 1
A transition from 0 to 1 indicates that the Sim Data outport provides new data.
Sim Status Outputs information about the simulated data exchange on the Sim Data outport.
Available only if the Enable simulation status port is set on the Parameters
page.
Data type: UInt32
Data width: 3
§ Sim Status[0]: Contains the number of valid elements in the Sim Data vector.
§ Sim Status[1]: Indicates whether the current buffer contains new or old values.
The status is 1 if the buffer contains new values.
§ Sim Status[2]: Indicates whether a buffer overflow occurred. At least one buffer
was not read and its data was lost before the currently read buffer was filled.

Note

You can transfer any data type with a bit width of up to 64 Bit via inter-
FPGA over IOCNET. Use the Reinterpret block from the HDL library of the
AMD Vitis Model Composer to change your data type to UFix_64_0 and
vice versa. Reinterpreting data types does not cost any hardware or latency.
The range of the Data inport can be exceeded. The value of the inport is
then cast to the raw data format UFix_64_0.

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Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I-FPGA64 Out 1 … 32 The Parameters page provides the following dialog setting:
(IOCNET) settings
Buffer size Lets you specify the size of the IOCNET buffer in the range
1 … 512.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64 bits in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation data port Lets you enable an outport for offline
simulation data.
The Sim Data inport is added to the block.

Enable simulation data new port Lets you enable an outport for the offline
simulating of new data values at the Sim Data inport.
The Sim Data New outport is added to the block.

Enable simulation status port Lets you enable an outport to get status
information about the simulation data that is available when you enabled a
simulation port. The Sim Status outport is added to the block.

LED Out description Block display If you select the LED Out channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Controls the LED on the DS6602 FPGA Base Board.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: LED is lit in green.
§ 1: LED is lit in orange.
If the value of the Data inport exceeds the specified data width, only the lowest bit
is used (=1).

I/O mapping No external connection.

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LED Out settings None

User Clock Out 1 … 32 Block display If you select the User Clock Out channel from the channel list,
description the block display changes.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
User Clock Clock signal for the clock domain used within the subsystem to which the block
belongs. For more information, refer to Using Multiple Clock Domains for FPGA
Modeling (FPGA Programming Blockset Guide ).
Data type: UFix_1_0
Data width: 1

I/O mapping No external connection.

User Clock Out 1 … 32 The Parameters page provides the following dialog setting:
settings
User clock period Lets you specify the expected clock period used within the
subsystem to which the block belongs. A common value for the clock period is in
the range 20 ns ... 4 ns (50 MHz ... 250 MHz).
The value is used during the build process when no user clock is available, for
example, to specify timing constraints.

User clock offline simulation period Lets you specify the clock period to be
used in offline simulation mode. The value must be greater than or equal to the
value of the User clock period parameter.

Related topics Basics

Modeling DDR4 RAM Access (FPGA Programming Blockset Guide )

Modeling Inter-FPGA Communication via IOCNET (FPGA Programming Blockset
Guide )

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Scaling Page (FPGA_IO_WRITE_BL)

Description The Scaling page is empty because the I/O functions of this framework do not
support FPGA scaling.

Frameworks with scaling The frameworks of the I/O modules support FPGA scaling:
support § DS2655M1 I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 350
§ Scaling Page (FPGA_IO_WRITE_BL) on page 363
§ DS2655M2 Digital I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 377
§ Scaling Page (FPGA_IO_WRITE_BL) on page 397
§ DS6651 Multi-I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 413
§ Scaling Page (FPGA_IO_WRITE_BL) on page 445

Related topics Basics

Basics on FPGA Test Access and Scaling (FPGA Programming Blockset Guide )

FPGA_INT_BL (DS6602 FPGA Base Board Settings)

Purpose To configure the FPGA interrupt channel when using the DS6602 (KU15P) FPGA
Base Board framework.

Where to go from here Information in this section

Parameters Page (FPGA_INT_BL)............................................................ 343

To enable the simulation port for an interrupt.

Information in other sections

Unit Page (FPGA_INT_BL)......................................................................... 64

To specify the interrupt channel used to trigger a task in the processor
model.

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Parameters Page (FPGA_INT_BL)

Purpose To enable the simulation port for an interrupt.

Description The DS6602 FPGA Base Board provides 16 interrupt lines.

An interrupt is requested if the Int port is set to 1 for at least one clock cycle. If
you set the Int port to 0, the last interrupt is not released but saved. An interrupt
is edge-triggered.

Int description Block display The figure below shows the block display with the optional
simulation port.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Int Provides the interrupt request line.
Data type: UFix_1_0
0 to 1: Interrupt is requested (edge-triggered).
0: No interrupt is requested. Last requested interrupt is saved.
Output
Sim_Int Simulates an interrupt by performing a function call to enable a function-call
subsystem.
Available only if Enable simulation port is set on the Parameters page.
Data type: Function call

Int settings Enable simulation port Lets you enable an outport for a simulated interrupt.
The Sim_Int outport is added to the block to connect it to a function-call
subsystem in the processor model.

Related topics HowTos

How to Trigger Interrupt-Driven Processor Tasks (FPGA Programming Blockset

Guide )

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Block Settings for the DS2655M1 I/O Module Framework

Introduction The block dialogs provide hardware-specific settings after you load one of
the following frameworks together with at least one DS2655M1 I/O Module
framework:
§ DS2655 (7K160) FPGA Base Board framework
§ DS2655 (7K410) FPGA Base Board framework
§ DS6601 (KU035) FPGA Base Board framework
§ DS6602 (KU15P) FPGA Base Board framework

Where to go from here Information in this section

FPGA_IO_READ_BL (DS2655M1 I/O Module Settings)............................ 344

To configure read access to analog and digital input signals in the FPGA
model when using the DS2655M1 I/O Module framework.

FPGA_IO_WRITE_BL (DS2655M1 I/O Module Settings)........................... 353

To configure write access to analog and digital input signals in the FPGA
model when using the DS2655M1 I/O Module framework.

FPGA_IO_READ_BL (DS2655M1 I/O Module Settings)

Purpose To configure read access to analog and digital input signals in the FPGA model
when using the DS2655M1 I/O Module framework.

Where to go from here Information in this section

Parameters Page (FPGA_IO_READ_BL)................................................... 345

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_READ_BL).......................................................... 350

To specify the inverting, scaling, and saturation settings for the selected
I/O function.

Information in other sections

Unit Page (FPGA_IO_READ_BL)................................................................ 55

To specify the I/O type and channel to be used for read access.

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Parameters Page (FPGA_IO_READ_BL)

Purpose To specify relevant settings for the selected I/O function.

Description The framework provides the I/O types Digital_Mod_x and Analog_Mod_x, which
you can select on the Unit page of the block. The module number <x> depends
on the slot that the I/O module is connected to.

The number of the available physical connections on the DS2655M1 I/O Module
determines the I/O functions that you can select:
§ Analog In - Ch: 11 … Analog In - Ch: 15
§ Digital In - Ch: 1 … Digital In - Ch: 10

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_IO_READ_BL block.

Enable simulation port Lets you enable an inport for offline simulation data.
The Sim Data inport is added to the block to connect it to simulation data
coming from a Simulink-based I/O environment model.

Analog In description Block display If you select an Analog In channel from the channel list, the
block display changes. The simulation port is displayed optionally.

I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Input
Sim Data Simulates an input signal that you can connect to a Simulink-based I/O
environment model.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
The value range corresponds to the settings of the Input range parameter in V.
Range exceeding is possible and will be saturated to the minimum or maximum
values.
Output

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Port Description
Data Outputs the current result of the analog input channel.
Data type: Fix_16_0 1)
Data width: 1
Update rate: 2 Msps
Data New Outputs a flag that indicates the current status of the Data port.
The port is set to 1 for one clock cycle if the Data port provides new values.
New measured values from analog input channels of the same I/O module
are always provided synchronously. If analog inputs are read from different I/O
modules, the measured values are provided either synchronously or offset by two
clock cycles (16 ns). However, the sample time of the analog measurements is
synchronous on different I/O modules except for 8 ns.
If synchronous measured values from analog inputs of different I/O modules are
required, you can implement a logic to wait with the further processing of analog
values until the Data New ports flag new data within two clock cycles. The
following example shows a logic for the Data New ports to use synchronous
analog input signals of different I/O modules.

Data type: UFix_1_0

Data width: 1
Values:
§ 0: No new values are available at the Data port.
§ 1: New values are available at the Data port.
1) You can change the data type of the Data port with the Scaling format parameter
on the Scaling page. Refer to How to Change the Data Type of Analog Signals (FPGA
Programming Blockset Guide ).
Mapping for the Data output:

Input Voltage Simulink Data Output

-5 V ... +5 V The output port range depends on the setting
of the Scaling parameter:
§ -5000 ... +5000 mV
§ -8192 ... +8191
-30 V ... +30 V The output port range depends on the setting
of the Scaling parameter:
§ -30000 ... +30000 mV
§ -8192 ... +8191

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If the hardware signal or the value of the Sim Data inport exceeds the minimum
or maximum threshold voltage, it is saturated to the corresponding minimum or
maximum value.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping The following I/O mapping is relevant if you use the DS2655M1
I/O Module framework for analog input channels. The signals are available at the
female 50-pin Sub-D I/O connector of the respective DS2655M1 I/O Module.

Outport Channel Type Channel Connector Pin Signal

Data Analog In 3 11 10 Analog In - Ch: 11 [Mod: x]
26 Reference
12 27 Analog In - Ch: 12 [Mod: x]
43 Reference
13 44 Analog In - Ch: 13 [Mod: x]
11 Reference
14 12 Analog In - Ch: 14 [Mod: x]
28 Reference
15 29 Analog In - Ch: 15 [Mod: x]
45 Reference

Analog In settings The following settings on the Parameters page are specific to the Analog In I/O
function. For common dialog settings, refer to Common settings on page 345.

The Parameters page provide the following dialog setting:

Input range Lets you specify the input voltage range that can be converted
from analog to digital for the chosen ADC channel. Input voltages outside the
specified range are saturated.
This electrical interface setting can be changed in ConfigurationDesk.

Scaling Lets you select whether the I/O function scales the measuring results
of the A/D converter to mV.
§ mV
To output the measuring results in mV. The valid value range corresponds to
the settings of the Input range parameter in mV.
§ Bit
To output the raw measuring results as a signed Bit value.
The value range is -8192 … +8191.

Digital In description Block display If you select a Digital In channel from the channel list, the block
display changes. The Sim Data port and the threshold voltage configuration
ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Input
Threshold Voltage Specifies a trigger level in mV. A new threshold voltage level takes effect only
after the Threshold Set port rises from 0 to 1.
Available only if Enable Threshold Voltage configuration ports is set on
the Parameters page.
Data type: UFix_14_0
Data width: 1
Range: 0 ... 10500 mV
Update rate: FPGA clock frequency
The range can be exceeded, and saturation is performed to a minimum or
maximum value.
Threshold Set Lets you set the trigger level as specified by the Threshold Voltage port.
A new setting overwrites the settings of Threshold init voltage on the
Parameters page.
Available only if Enable Threshold Voltage configuration ports is set on
the Parameters page.
Data type: UFix_1_0
Range:
§ No transition, or a 1 to 0 transition: A new voltage setting does not take
effect.
§ 0 to 1 transition: The new settings are sent to the output channel. The
Threshold Ack port outputs a flag if the channel is up-to-date.
Update rate: FPGA clock frequency
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.
Sim Data Simulates an input signal in the same range specified for the real input signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Threshold level: 0 mV ... 10500 mV
Output
Data Outputs the current results of digital input channel.
Data type: UFix_1_0
Data width: 1

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Port Description
Values:
§ 0: Input voltage of the channel is below the threshold voltage of a high-low
transition.
§ 1: Input voltage of the channel is higher than or equal to the threshold
voltage of a low-high transition.
Update rate: FPGA clock frequency
If the hardware signal or the value of the Sim Data inport exceeds the
minimum or maximum threshold voltage, it is saturated to the corresponding
minimum or maximum value.
For information on the electrical characteristics of the DS2655M1 I/O Module,
refer to Data Sheet of the DS2655M1 Multi-I/O Module (SCALEXIO Hardware
Installation and Configuration ).
Threshold Ack Outputs a flag that indicates whether the threshold voltage level is up-to-date.
Available only if Enable Threshold Voltage configuration ports is set on
the Parameters page.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The channel currently updates its threshold voltage.
§ 1: The channel is up-to-date and a new configuration can be set.

Note

Asynchronous input data might lead to metastable register states because

input data is synchronized only by a single register stage. Further
synchronization techniques might be necessary.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use the DS2655M1
I/O Module framework for digital input channels. The signals are available at the
female 50-pin Sub-D I/O connector of the respective DS2655M1 I/O Module.

Outport Channel Type Channel Connector Pin Signal

Data Digital In/Out 2 1 2 Digital In - Ch: 1 [Mod: x]
18 Reference
2 19 Digital In - Ch: 2 [Mod: x]
35 Reference
3 36 Digital In - Ch: 3 [Mod: x]
3 Reference
4 4 Digital In - Ch: 4 [Mod: x]

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Outport Channel Type Channel Connector Pin Signal

20 Reference
5 21 Digital In - Ch: 5 [Mod: x]
37 Reference
6 6 Digital In - Ch: 6 [Mod: x]
22 Reference
7 23 Digital In - Ch: 7 [Mod: x]
39 Reference
8 40 Digital In - Ch: 8 [Mod: x]
7 Reference
9 8 Digital In - Ch: 9 [Mod: x]
24 Reference
10 25 Digital In - Ch: 10 [Mod: x]
41 Reference

Digital In settings The following settings on the Parameters page are specific to the Digital In I/O
function. For common dialog settings, refer to Common settings on page 345.

Threshold init voltage Lets you specify the voltage value that is used for
the threshold in mV. Range: 0 mV ... 10500 mV in 100 mV steps. This electrical
interface setting can be changed in ConfigurationDesk.

Enable Threshold Voltage configuration ports Lets you enable ports to

set the threshold voltage. The ports can overwrite the value of Threshold init
voltage.
The following ports are added to the block:
§ Threshold Voltage
§ Threshold Set
§ Threshold Ack

Related topics Basics

Modeling External I/O Access (FPGA Programming Blockset Guide )

Scaling Page (FPGA_IO_READ_BL)

Purpose To specify the inverting, scaling, and saturation settings for the selected I/O
function.

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Description You can modify the I/O signal of the selected I/O function if you select the
Enable FPGA test access and scaling parameter on the FPGA Access page
of the FPGA_SETUP_BL block dialog. The possible modifications depend on the
selected I/O function.

Common settings The following settings on the Scaling page are common to the I/O functions that
you can select on the Unit page.

Enable FPGA test access and scaling for this block Lets you disable FPGA
test access and scaling for the selected I/O function.

Digital In settings The following settings on the Scaling page are specific to the Digital In I/O
function.

Invert input polarity Lets you adapt the measured values to the electrical
input signal:
§ Disabled:
The Data port outputs the signals as measured: A low-high transition results in
a 1 and vice versa.
§ Enabled:
The output of the Data port is inverted: A low-high transition results in a 0
and vice versa.

Analog In settings The following settings on the Scaling page are specific to the Analog In I/O
function.

Note

Scaling of analog I/O signals also effects the signal path:

§ If you use the parameters of the Scaling page to scale analog signals, the
data type of the Data port is set to the specified data format for scaling.
For more information, refer to How to Change the Data Type of Analog
Signals (FPGA Programming Blockset Guide ).
§ FPGA scaling of analog I/O signals might cause additional latency. If
the latency can be calculated during the modeling, analog I/O functions
display the total latency.

Scaling format Lets you select the data format for scaling and saturation.
§ Signed/Unsigned:
The values of the parameters for scaling and saturation are in fixed‑point
format. The signed fixed-point format reserves one bit for the sign.
You can specify the number of bits and the binary point position with the
Number of bits and Binary point (fraction width) parameters.

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§ Single:
The values of the parameters for scaling and saturation are 32-bit values in
the single-precision floating‑point format with a fraction width of 24, which
complies with the IEEE 754 standard (single).
§ Double:
The values of the parameters for scaling and saturation are 64-bit values in
the double-precision floating‑point format with a fraction width of 53, which
complies with the IEEE 754 standard (double).

Number of bits This setting depends on the Scaling format setting.

§ Fixed-point format:
Lets you specify the bit width of the scaling parameters and the Data port in
the range 1 ... 64.
§ Floating-point format:
Displays the bit width of the scaling parameters and the Data port.

Binary point (fraction width) This setting depends on the Scaling format
setting.
§ Fixed-point format:
Lets you specify the binary point position of the scaling parameters and the
Data port. The position 0 represents the lowest bit position
§ Floating-point format:
Displays the fraction width of the scaling parameters and the Data port.

Scaling factor Lets you specify the scaling factor. The scaling factor gains the
signal of the Data port before it is saturated or replaced via FPGA test access.
You must check whether the specified and displayed value is supported by
the specified scaling format. The value of the Scaling factor parameter will
be executed with the maximum accuracy of the specified scaling format
and saturated to the minimum and maximum values that the scaling format
supports.

Scaling offset Lets you add a signal offset after the signal of the Data port is
scaled with the scaling factor.
You must check whether the specified and displayed value is supported by
the specified scaling format. The value of the Scaling offset parameter will
be executed with the maximum accuracy of the specified scaling format
and saturated to the minimum and maximum values that the scaling format
supports.

Saturation minimum value Lets you specify the minimum value to which
the measured and scaled signal is saturated before it is output via the Data port.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation minimum
value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

Saturation maximum value Lets you specify the maximum value to which
the measured and scaled signal is saturated before it is output via the Data port.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation maximum

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value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

Multiplier latency Lets you specify the latency that is caused by the
multiplier for scaling. The multiplier is used to multiply the signal with the value
of the Scaling factor parameter.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The multiplication will be implemented without latency.
§ 1 ... 20: The multiplication will be implemented with the specified latency.
Use this value range in the exceptional case that the optimized latency cause
timing problems during the build process.

Adder latency Lets you specify the latency that is caused by the offset adder.
The offset adder is used to add the value of the Scaling offset parameter to the
signal.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The adding will be implemented without latency.
§ 1 ... 20: The adding will be implemented with the specified latency.
Use this value range in the exceptional case that the optimized latency causes
timing problems during the build process.

Related topics Basics

Basics on FPGA Test Access and Scaling (FPGA Programming Blockset Guide )

FPGA_IO_WRITE_BL (DS2655M1 I/O Module Settings)

Purpose To configure write access to analog and digital input signals in the FPGA model
when using the DS2655M1 I/O Module framework.

Where to go from here Information in this section

Parameters Page (FPGA_IO_WRITE_BL).................................................. 354

To specify relevant settings for the selected I/O function.

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Scaling Page (FPGA_IO_WRITE_BL)........................................................ 363

To specify the inverting, scaling, and saturation settings for the selected
I/O function.

Information in other sections

Unit Page (FPGA_IO_WRITE_BL)............................................................... 60

To specify the I/O type and channel to be used for write access.

Parameters Page (FPGA_IO_WRITE_BL)

Purpose To specify relevant settings for the selected I/O function.

Description The framework provides the I/O types Digital_Mod_x and Analog_Mod_x, which
you can select on the Unit page of the block. The module number <x> depends
on the slot that the I/O module is connected to.

The number of the available physical connections on the DS2655M1 Multi-I/O

Module determines the I/O functions that you can select:
§ Analog Out - Ch: 16 … Analog Out - Ch: 20
§ Digital InOut - Ch: 1 … Digital InOut - Ch: 10
§ Digital Out - Ch: 1 … Digital Out - Ch: 10

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_IO_WRITE_BL.

Enable simulation port Lets you enable an outport for offline simulation
data. The Sim Data outport is added to the block to connect it to a Simulink-
based I/O environment model.

Analog Out description Block display If you select an Analog Out channel from the channel list, the
block display changes. The simulation port and the Tx Ready port are displayed
optionally.

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I/O characteristics The following table describes the ports of the block for
analog output channels:

Port Description
Input
Data Outputs a voltage signal in the specified range.
Data type: Fix_15_0 1)
Data width: 1
Mapping: see table below
Update rate: 7.8125 MSPS
Output
Sim Data Analog output data signal. The output is fixed to -10 V … +10 V.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Range:
§ -10000 … +10000 mV
§ -8192 … +8191
TX Ready Outputs a flag that indicates that the I/O channel of the DS2655M1 Multi-I/O
Module is ready to be updated. The minimum update period is 96 ns. When you
update data values only within the time slot for updating the output signal, the
output signal has no jitter. The time slot begins two FPGA clock cycles before the
flag is set to high and ends after three clock cycles.
Time slot for signal
updating without jitter

FPGA clock

TX Ready

Note

Parallel output without jitter

The Analog Out channels are synchronously updated if you do not use
Digital InOut channels 5 ... 10. This lets you output parallel signals without
jitter.
Analog Out channels 16 ... 20 and Digital InOut channels 5 ... 10 share
resources. If you use Analog Out channels, the Analog Out channels
and the related Digital InOut channels use their own update process. This
update process also lets you output parallel signals without jitter, but not
synchronously to the other Digital InOut channels.
For example, if you use Digital InOut channels 8 ... 10, Analog Out channels
16 ... 17 are synchronously updated. Analog Out channels 18 ... 20 are
updated at another point in time, but these channels are also synchronously
updated.

Available only if Enable Tx Ready port is set on the Parameters page.

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Port Description
Data type: UFix_1_0
Data width: 1
1) You can change the data type of the Data port with the Scaling format parameter
on the Scaling page. Refer to How to Change the Data Type of Analog Signals (FPGA
Programming Blockset Guide ).

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping The following I/O mapping is relevant if you use the DS2655M1
I/O Module framework for analog output channels. The signals are available at
the female 50-pin Sub-D I/O connector of the respective DS2655M1 Multi-I/O
Module.

Outport Channel Type Channel Connector Pin Signal

Data Analog Out 5 16 14 Analog Out - Ch: 16 [Mod: x]
30 Reference
17 31 Analog Out - Ch: 17 [Mod: x]
47 Reference
18 48 Analog Out - Ch: 18 [Mod: x]
15 Reference
19 16 Analog Out - Ch: 19 [Mod: x]
32 Reference
20 33 Analog Out - Ch: 20 [Mod: x]
49 Reference

Analog Out settings The following settings on the Parameters page are specific to the Analog
Out I/O function. For common dialog settings, refer to Common settings on
page 354.

Scaling Lets you select the scaling of the Data inport.

§ mV
To specify the output voltage in mV.
The value range is ‑10,000 mV … +10,000 mV.
§ Bit
To specify the output voltage with a signed bit value.
The value range is ‑8,192 ... +8,191 (14-bit converter).

Enable Tx Ready port Lets you enable an outport to indicate that the analog
output channel is ready to be updated. The Tx Ready port is added to the block.

Output range Displays the output range of the analog output channel.

Digital InOut description Block display If you select a Digital InOut channel from the channel list, the
block display changes. The simulation ports, the threshold voltage configuration
ports, and the Tx Ready port are displayed optionally.

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I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Out Outputs a signal in the specified range.
Data Type: UFix_1_0
Data width: 1
If driven with 0, the hardware outputs a low-level signal at the I/O
connector. If driven with 1, the hardware outputs a high-level signal.
Update rate: 15.625 MHz
For information on the electrical characteristics of the DS2655M1 Multi-
I/O Module, refer to Data Sheet of the DS2655M1 Multi-I/O Module
(SCALEXIO Hardware Installation and Configuration ).
Direction Specifies the direction of the digital signal.
Data Type: UFix_1_0
Data width: 1
Values:
§ 0: digital in
§ 1: digital out
Update rate: 125 MHz
In Threshold Voltage Specifies a trigger level in mV. A new threshold voltage level takes effect
only after the In Threshold Set port rises from 0 to 1.
Available only if Enable In Threshold Voltage configuration ports is set
on the Parameters page.
Data Type: UFix_14_0
Data width: 1
Range: 0 mV … +10500 mV in 100 mV steps
Update rate: 125 MHz
The range can be exceeded, and saturation is performed to a minimum or
maximum value.
In Threshold Set Lets you set the trigger level as specified by the In Threshold Voltage
port. A new setting overwrites the settings of Threshold init voltage on
the Parameters page.
Available only if Enable In Threshold Voltage ports is set on the
Parameters page.
Data Type: UFix_1_0
Data width: 1

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Port Description
Values:
§ No transition, or a 1 to 0 transition: A new voltage setting does not take
effect.
§ 0 to 1 transition: The new settings are sent to the output channel. The
Threshold Ack port outputs a flag if the channel is up-to-date.
Update rate: 125 MHz
Range exceeding is possible (using input bit widths > 1) and will be cast to
1 bit by using only the lowest bit.
Sim Data In Simulates an input signal in the same range specified for the real input
signal.
Available only if Enable digital in simulation port is set on the
Parameters page.
Data type: Double
Data width: 1
Threshold level: 0 mV … 10500 mV
Output
Data In Outputs a signal that is 0 if the hardware input is driven with a voltage
lower than the threshold voltage.
Data Type: UFix_1_0
Data width: 1
For information on the electrical characteristics of the DS2655M1 Multi-
I/O Module, refer to Data Sheet of the DS2655M1 Multi-I/O Module
(SCALEXIO Hardware Installation and Configuration ).
Sim Data Out Simulates an output signal in the same range as that specified for the real
output signal.
Available only if Enable digital out simulation port is set on the
Parameters page.
Data type: Double
Data width: 1
Output voltage: 0 V … 5 V or 0 V … 3.3 V
Update rate: 125 MHz
Threshold Ack Outputs a flag that indicates changes of the threshold voltage level
configuration.
Available only if Enable In Threshold Voltage configuration ports is set
on the Parameters page.
Data type: UFix_1_0
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one
clock cycle.
Tx Ready Outputs a flag that indicates that the I/O channel of the DS2655M1 Multi-
I/O Module is ready to be updated. The minimum update period is 96 ns.
When you update data values only within the time slot for updating the
output signal, the output signal has no jitter. The time slot begins two
FPGA clock cycles before the flag is set to high and ends after three clock
cycles.

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Port Description
Time slot for signal
updating without jitter

FPGA clock

TX Ready

Note

Parallel output without jitter

The Digital InOut channels are synchronously updated if you do not
use Analog Out channels. This lets you output parallel signals without
jitter.
Digital InOut channels 5 ... 10 and Analog Out channels 16 ...
20 share resources. If you use Analog Out channels, the Analog
Out channels and the related Digital InOut channels use their own
update process. This update process also lets you output parallel
signals without jitter, but not synchronously to the other Digital InOut
channels.
For example, if you use Analog Out channels 18 ... 20, Digital InOut
channels 1 ... 7 are synchronously updated. Digital InOut channels
8 ... 10 are updated at another point in time, but these channels are
also synchronously updated.

Available only if Enable Tx Ready port is set on the Parameters page.

Data type: UFix_1_0
Data width: 1

Note

If you use a Digital InOut channel, the applicable threshold voltage for the
digital input channel is less than or equal to the specified high supply.
To apply the maximum input voltage range, you have to use a Digital In
channel.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping The following I/O mapping is relevant if you use the DS2655M1
I/O Module framework for digital input/output channels. The signals are available
at the female 50-pin Sub-D I/O connector of the respective DS2655M1 Multi-I/O
Module.

Port Channel Type Channel Connector Pin Signal

Data In and Data Out Digital In/Out 2 1 2 Digital InOut - Ch: 1 [Mod: x]
18 Reference
2 19 Digital InOut - Ch: 2 [Mod: x]

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Port Channel Type Channel Connector Pin Signal

35 Reference
3 36 Digital InOut - Ch: 3 [Mod: x]
3 Reference
4 4 Digital InOut - Ch: 4 [Mod: x]
20 Reference
5 21 Digital InOut - Ch: 5 [Mod: x]
37 Reference
6 6 Digital InOut - Ch: 6 [Mod: x]
22 Reference
7 23 Digital InOut - Ch: 7 [Mod: x]
39 Reference
8 40 Digital InOut - Ch: 8 [Mod: x]
7 Reference
9 8 Digital InOut - Ch: 9 [Mod: x]
24 Reference
10 25 Digital InOut - Ch: 10 [Mod: x]
41 Reference

Digital InOut settings The following settings on the Parameters page are specific to the Digital InOut
I/O function.

Output Mode Lets you select the output mode.

§ Low-side switch
Lets you actively drive the output to GND to output a low-level signal.
An external load to VCC is required to output a high-level signal.
§ High-side switch
Lets you actively drive the output to VCC to output a high-level signal.
An external load to GND is necessary to output a low-level signal.
§ Push-pull
Lets you drive the output between VCC and GND.
An external load is not required.
This electrical interface setting can be changed in ConfigurationDesk.

Drive Config Lets you enable/disable the termination of the signal line by an
internal resistor.
§ Direct Drive
Lets you directly drive the I/O signal. The internal termination resistor is
disabled.
§ 68 Ohm Terminated
Lets you terminate the I/O signal with an internal 68 Ω resistor.
This electrical interface setting can be changed in ConfigurationDesk.

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High supply Lets you select the VCC voltage that determines the high-level
voltage for the high‑side switch.
This electrical interface setting can be changed in ConfigurationDesk.

Digital In threshold init voltage (0 mV ... +10500 mV) Lets you set the
initial threshold voltage for a digital input signal in 100 mV steps. This electrical
interface setting can be changed in ConfigurationDesk.

Enable In Threshold Voltage configuration ports Lets you enable ports to

set the threshold voltage. The ports can overwrite the value of the Digital In
threshold init voltage.
The following ports are added to the block:
§ In Threshold Voltage
§ In Threshold Set
§ In Threshold Ack

Enable digital out simulation port Lets you enable an outport for offline
simulation data. The Sim Data Out outport is added to the block to connect it
to a Simulink-based I/O environment model.

Enable digital in simulation port Lets you enable an inport for offline
simulation data. The Sim Data In inport is added to the block to connect it to
simulation data coming from a Simulink-based I/O environment model. This port
is relevant only if the signal direction is in.

Enable Tx Ready port Lets you enable an outport to indicate that the analog
output channel is ready to be updated. The Tx Ready port is added to the block.

Digital Out description Block display If you select a Digital Out channel from the channel list, the
block display changes. The Sim Data port is displayed optionally.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Outputs a signal in the specified range.
Data Type: UFix_1_0
Data width: 1
If driven with 0, the hardware outputs a low-level signal at the I/O connector. If
driven with 1, the hardware outputs a high-level signal.
Update rate: FPGA clock frequency
If the value of the Data inport exceeds the specified data width, only the lowest bit
is used.
Note: The frequency that can be generated is smaller than the update rate. For
information on the electrical characteristics of the DS2655M1 Multi-I/O Module,

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Port Description
refer to Data Sheet of the DS2655M1 Multi-I/O Module (SCALEXIO Hardware
Installation and Configuration ).
Output
Sim Data Simulates an output signal in the same range as that specified for the real output
signal.
Available only if Enable simulation port is set on the Parameters page.
Data Type: Double
Data width: 1
Output voltage: 0 V … 5 V or 0 V … 3.3 V
Update rate: FPGA clock frequency

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use the DS2655M1
I/O Module framework for digital output channels. The signals are available at
the female 50-pin Sub-D I/O connector of the respective DS2655M1 Multi-I/O
Module.

Outport Channel Type Channel Connector Pin Signal

Data Digital In/Out 2 1 2 Digital Out - Ch: 1 [Mod: x]
18 Reference
2 19 Digital Out - Ch: 2 [Mod: x]
35 Reference
3 36 Digital Out - Ch: 3 [Mod: x]
3 Reference
4 4 Digital Out - Ch: 4 [Mod: x]
20 Reference
5 21 Digital Out - Ch: 5 [Mod: x]
37 Reference
6 6 Digital Out - Ch: 6 [Mod: x]
22 Reference
7 23 Digital Out - Ch: 7 [Mod: x]
39 Reference
8 40 Digital Out - Ch: 8 [Mod: x]
7 Reference
9 8 Digital Out - Ch: 9 [Mod: x]
24 Reference

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Outport Channel Type Channel Connector Pin Signal

10 25 Digital Out - Ch: 10 [Mod: x]
41 Reference

Digital Out settings The following settings on the Parameters page are specific to the Digital
Out I/O function. For common dialog settings, refer to Common settings on
page 354.

Output Mode Lets you select the output mode.

§ Low-side switch
Lets you actively drive the output to GND to output a low-level signal.
An external load to VCC is required to output a high-level signal.
§ High-side switch
Lets you actively drive the output to VCC to output a high-level signal.
An external load to GND is necessary to output a low-level signal.
§ Push-pull
Lets you drive the output between VCC and GND.
An external load is not required.
This electrical interface setting can be changed in ConfigurationDesk.

Drive Config Lets you enable/disable the termination of the signal line by an
internal resistor.
§ Direct Drive
Lets you directly drive the I/O signal. The internal termination resistor is
disabled.
§ 68 Ohm Terminated
Lets you terminate the I/O signal with an internal 68 Ω resistor.
This electrical interface setting can be changed in ConfigurationDesk.

High supply Lets you select the VCC voltage that determines the high-level
voltage for the high‑side switch.
This electrical interface setting can be changed in ConfigurationDesk.

Related topics Basics

Modeling External I/O Access (FPGA Programming Blockset Guide )

Scaling Page (FPGA_IO_WRITE_BL)

Purpose To specify the inverting, scaling, and saturation settings for the selected I/O
function.

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Description You can modify the I/O signal of the selected I/O function if you select the
Enable FPGA test access and scaling parameter on the FPGA Access page
of the FPGA_SETUP_BL block dialog. The possible modifications depend on the
selected I/O function.

Common settings The following settings on the Scaling page are common to the I/O functions that
you can select on the Unit page.

Enable FPGA test access and scaling for this block Lets you disable FPGA
test access and scaling for the selected I/O function.

Digital Out settings The following settings on the Scaling page are specific to the Digital Out I/O
function.

Invert polarity Lets you adapt the electrical output signal:

§ Disabled:
If driven with 1, the hardware outputs a high-level signal.
If driven with 0, the hardware outputs a low-level signal.
§ Enabled:
If driven with 1, the hardware outputs a low-level signal.
If driven with 0, the hardware outputs a high-level signal.

Digital InOut settings The following settings on the Scaling page are specific to the Digital InOut I/O
function.

Invert input polarity Lets you invert the measured values of the electrical
input signal:
§ Disabled:
The Data port outputs the signals as measured: A low-high transition results in
a 1 and vice versa.
§ Enabled:
The output of the Data port is inverted: A low-high transition results in a 0
and vice versa.

Invert output polarity Lets you adapt the electrical output signal:
§ Disabled:
If driven with 1, the hardware outputs a high-level signal.
If driven with 0, the hardware outputs a low-level signal.
§ Enabled:
If driven with 1, the hardware outputs a low-level signal.
If driven with 0, the hardware outputs a high-level signal.

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Analog Out settings The following settings on the Scaling page are specific to the Analog Out I/O
function.

Note

Scaling of analog I/O signals also effects the signal path:

§ If you use the parameters of the Scaling page to scale analog signals, the
data type of the Data port is set to the specified data format for scaling.
For more information, refer to How to Change the Data Type of Analog
Signals (FPGA Programming Blockset Guide ).
§ FPGA scaling of analog I/O signals might cause additional latency. If
the latency can be calculated during the modeling, analog I/O functions
display the total latency.

Scaling format Lets you select the data format for scaling and saturation.
§ Signed/Unsigned:
The values of the parameters for scaling and saturation are in fixed‑point
format. The signed fixed-point format reserves one bit for the sign.
You can specify the number of bits and the binary point position with the
Number of bits and Binary point (fraction width) parameters.
§ Single:
The values of the parameters for scaling and saturation are 32-bit values in
the single-precision floating‑point format with a fraction width of 24, which
complies with the IEEE 754 standard (single).
§ Double:
The values of the parameters for scaling and saturation are 64-bit values in
the double-precision floating‑point format with a fraction width of 53, which
complies with the IEEE 754 standard (double).

Number of bits This setting depends on the Scaling format setting.

§ Fixed-point format:
Lets you specify the bit width of the scaling parameters and the Data port in
the range 1 ... 64.
§ Floating-point format:
Displays the bit width of the scaling parameters and the Data port.

Binary point (fraction width) This setting depends on the Scaling format
setting.
§ Fixed-point format:
Lets you specify the binary point position of the scaling parameters and the
Data port. The position 0 represents the lowest bit position
§ Floating-point format:
Displays the fraction width of the scaling parameters and the Data port.

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Scaling factor Lets you specify the scaling factor. The scaling factor gains
the signal of the Data port or the replace value (FPGA test access) before it is
saturated.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Scaling factor parameter
will be saturated to the minimum and maximum values that the scaling format
and the hardware supports.

Scaling offset Lets you add a signal offset after the signal of the Data port is
scaled with the scaling factor.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Scaling offset parameter
will be saturated to the minimum and maximum values that the scaling format
and the hardware supports.

Saturation minimum value Lets you specify the minimum value to which
the scaled Data inport signal is saturated before it is output via an analog output
channel.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation minimum
value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

Saturation maximum value Lets you specify the maximum value to which
the scaled Data inport signal is saturated before it is output via an analog output
channel.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation maximum
value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

Multiplier latency Lets you specify the latency that is caused by the
multiplier for scaling. The multiplier is used to multiply the signal with the value
of the Scaling factor parameter.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The multiplication will be implemented without latency.
§ 1 ... 20: The multiplication will be implemented with the specified latency.
Use this value range in the exceptional case that the optimized latency cause
timing problems during the build process.

Adder latency Lets you specify the latency that is caused by the offset adder.
The offset adder is used to add the value of the Scaling offset parameter to the
signal.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The adding will be implemented without latency.
§ 1 ... 20: The adding will be implemented with the specified latency.

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Use this value range in the exceptional case that the optimized latency causes
timing problems during the build process.

Related topics Basics

Basics on FPGA Test Access and Scaling (FPGA Programming Blockset Guide )

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Block Settings for the DS2655M2 I/O Module Framework

Introduction The block dialogs provide hardware-specific settings after you load one of
the following frameworks together with at least one DS2655M2 I/O Module
framework:
§ DS2655 (7K160) FPGA Base Board framework
§ DS2655 (7K410) FPGA Base Board framework
§ DS6601 (KU035) FPGA Base Board framework
§ DS6602 (KU15P) FPGA Base Board framework

Where to go from here Information in this section

FPGA_IO_READ_BL (DS2655M2 I/O Module Settings)............................ 368

To configure read access to the selected I/O function when using the
DS2655M2 I/O Module framework.

FPGA_IO_WRITE_BL (DS2655M2 I/O Module Settings)........................... 378

To configure write access to analog and digital input signals in the FPGA
model when using the DS2655M2 I/O Module framework.

FPGA_IO_READ_BL (DS2655M2 I/O Module Settings)

Purpose To configure read access to the selected I/O function when using the DS2655M2
I/O Module framework.

Where to go from here Information in this section

Parameters Page (FPGA_IO_READ_BL)................................................... 369

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_READ_BL).......................................................... 377

To specify the inverting settings for the selected I/O function.

Information in other sections

Unit Page (FPGA_IO_READ_BL)................................................................ 55

To specify the I/O type and channel to be used for read access.

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Parameters Page (FPGA_IO_READ_BL)

Purpose To specify relevant settings for the selected I/O function.

Description The framework provides the I/O type Digital_Mod_<x>, which you can select on
the Unit page of the block. The module number <x> depends on the slot that
the I/O module is connected to.

The number of the available channels on the selected DS2655M2 Digital I/O
Module determines the I/O functions that you can select:
§ Digital In - Ch: 1, … , Digital In - Ch: 32
§ RS232 Rx - Ch: 2, ... , RS232 Rx - Ch: 30
§ RS485 Rx - Ch: 1-2, ... , RS485 Rx - Ch: 29-30

Channel dependencies The I/O functions of the DS2655M2 I/O Module framework share the I/O
channels that provide the I/O functionality. The DS2655M2 Digital I/O Module
provides 32 I/O channels. Some channels provide only specific I/O functionalities
and some I/O functions use more than one I/O channel. These channel
dependencies limit the number of available I/O functions.

For an overview of the DS2655M2 Digital I/O Module, refer to DS2655M2 Digital
I/O Module (SCALEXIO Hardware Installation and Configuration ).

For details on the signal mapping, refer to Signal Mapping of the DS2655M2
Digital I/O Module (SCALEXIO Hardware Installation and Configuration ).

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_IO_READ_BL block.

Enable simulation port Lets you enable an inport for offline simulation data.
The Sim Data inport is added to the block to connect it to simulation data
coming from a Simulink-based I/O environment model.

Digital In description Block display If you select a Digital In channel from the channel list, the
block display changes. Except for the outport Data, all the ports are displayed
optionally.

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I/O characteristics The following table describes the ports of the block:

Port Description
Input
Threshold Voltage Specifies a trigger level in mV. A new threshold voltage level takes effect only
after the Threshold Set port rises from 0 to 1.
Available only if Enable Threshold Voltage ports is set on the Parameters
page.
Data type: UFix_14_0
Data width: 1
Range: 0 mV ... 10500 mV
Update rate: FPGA clock frequency, max 250 MHz.
The range can be exceeded, and saturation is performed to a minimum or
maximum value.
Threshold Set Lets you set the trigger level as specified by the Threshold Voltage port.
A new setting overwrites the settings of Threshold init voltage on the
Parameters page.
Available only if Enable Threshold Voltage ports is set on the Parameters
page.
Data type: UFix_1_0
Data width: 1
Values:
§ No transition, or a 1 to 0 transition: A new voltage setting does not take
effect.
§ 0 to 1 transition: If the Threshold Set port rises from 0 to 1, the new
settings are sent to the output channel. The Threshold Ack port outputs a
flag if the channel is up-to-date.
Update rate: FPGA clock frequency
Range exceeding is possible (using input bit widths > 1) and will be cast to
1 bit by using only the lowest bit.
Sim Data Simulates an input signal that you can connect to a Simulink-based I/O
environment model. The threshold voltage determines a logical 0 or 1 as
output of the Data port.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Range: 0 V ... 10.5 V
Range exceeding is possible and will be saturated to the minimum or
maximum values.
Output
Data Outputs the current results of digital input channel.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Input voltage of the channel is below the threshold voltage of a high-low
transition.
§ 1: Input voltage of the channel is higher than or equal to the threshold
voltage of a low-high transition.

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Port Description
Update rate: FPGA clock frequency, max 250 MHz
For information on the electrical characteristics of the DS2655M2 Digital I/O
Module, refer to Data Sheet of the DS2655M2 Digital I/O Module (SCALEXIO
Hardware Installation and Configuration ).
Threshold Ack Outputs a flag that acknowledges a change of the threshold voltage level
configuration.
Available only if Enable Threshold Voltage ports is set on the Parameters
page.
Data type: UFix_1_0
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one
clock cycle.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use the DS2655M2
I/O Module framework for Digital In channels. The signals are available at the
female 50-pin Sub-D I/O connector of the respective DS2655M2 Digital I/O
Module.

Outport Channel Type Channel Connector Pin Signal

Data Digital In/Out 4 1 18 Dig In (Ch. 1)
2 2 Dig In (Ch. 2)
Digital In/Out 2 3 35 Dig In (Ch. 3)
4 19 Dig In (Ch. 4)
Digital In/Out 4 5 20 Dig In (Ch. 5)
6 4 Dig In (Ch. 6)
Digital In/Out 2 7 37 Dig In (Ch. 7)
8 21 Dig In (Ch. 8)
Digital In/Out 4 9 22 Dig In (Ch. 9)
10 6 Dig In (Ch. 10)
Digital In/Out 2 11 39 Dig In (Ch. 11)
12 23 Dig In (Ch. 12)
Digital In/Out 4 13 24 Dig In (Ch. 13)
14 8 Dig In (Ch. 14)
Digital In/Out 2 15 41 Dig In (Ch. 15)
16 25 Dig In (Ch. 16)
Digital In/Out 4 17 26 Dig In (Ch. 17)
18 10 Dig In (Ch. 18)

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Outport Channel Type Channel Connector Pin Signal

Digital In/Out 2 19 43 Dig In (Ch. 19)
20 27 Dig In (Ch. 20)
Digital In/Out 4 21 28 Dig In (Ch. 21)
22 12 Dig In (Ch. 22)
Digital In/Out 2 23 45 Dig In (Ch. 23)
24 29 Dig In (Ch. 24)
Digital In/Out 4 25 30 Dig In (Ch. 25)
26 14 Dig In (Ch. 26)
Digital In/Out 2 27 47 Dig In (Ch. 27)
28 31 Dig In (Ch. 28)
Digital In/Out 4 29 32 Dig In (Ch. 29)
30 16 Dig In (Ch. 30)
Digital In/Out 2 31 49 Dig In (Ch. 31)
32 33 Dig In (Ch. 32)

Digital In settings The following settings on the Parameters page are specific to the Digital In I/O
function. For common dialog settings, refer to Common settings on page 369.

Threshold init voltage Lets you specify the voltage value that is used for
the threshold in mV. Range: 0 mV ... 10500 mV in 100 mV steps. This electrical
interface setting can be changed in ConfigurationDesk.

Enable Threshold Voltage configuration ports Lets you enable ports to

set the threshold voltage. The ports can overwrite the value of Threshold init
voltage.
The following ports are added to the block:
§ Threshold Voltage
§ Threshold Set
§ Threshold Ack

RS232 Rx description Block display If you select an RS232 Rx channel from the channel list, the
block display changes. The simulation port is displayed optionally.

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I/O characteristics The following table describes the ports of the block:

Port Description
Input
Sim Data Simulates an input signal that you can connect to a Simulink-based I/O
environment model.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Range: –5.5 V ... +5.5 V
Range exceeding is possible and will be saturated to the minimum or maximum
values.
Output
Data Outputs the data received from the RS232 network.
Data type: UFix_1_0
Data width: 1
Range:
§ 0: The input voltage level is positive (≥ 0 V).
§ 1: The input voltage level is negative (< 0 V).
For information on the electrical characteristics of the DS2655M2 Digital I/O
Module, refer to Data Sheet of the DS2655M2 Digital I/O Module (SCALEXIO
Hardware Installation and Configuration ).

Note

To set the baud rate for a serial transmission, refer to Using the UART Demo
Model for SCALEXIO Systems (FPGA Programming Blockset Guide ).

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use the DS2655M2
I/O Module framework for RS232 Rx channels. The signals are available at the
female 50-pin Sub-D I/O connector of the respective DS2655M2 Digital I/O
Module.

Outport Channel Type Channel Connector Pin Signal

Data Digital In/Out 4 2 2 RX (Ch. 2)
6 4 RX (Ch. 6)
10 6 RX (Ch. 10)
14 8 RX (Ch. 14)
18 10 RX (Ch. 18)
22 12 RX (Ch. 22)

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Outport Channel Type Channel Connector Pin Signal

26 14 RX (Ch. 26)
30 16 RX (Ch. 30)

The I/O functions of the DS2655M2 I/O Module framework share the 32 I/O
channels of the DS2655M2 Digital I/O Module. For details on the signal mapping
to optimize channel usage, refer to Signal Mapping of the DS2655M2 Digital I/O
Module (SCALEXIO Hardware Installation and Configuration ).

RS232 Rx settings Only common dialog settings. Refer to Common settings on page 369.

RS485 Rx description Block display If you select an RS485 Rx channel from the channel list, the
block display changes. Except for the Data outport, all the ports are displayed
optionally.

Network mode With the RS485 Rx channel you can receive RS485 data
in simplex mode. To connect to RS485 networks in full-duplex mode, use the
corresponding RS485 Tx I/O function. For details on the RS485 Tx I/O function,
refer to RS485 Tx description on page 394.
To connect to a RS485 network in half-duplex mode, use the RS485 Rx/Tx I/O
function. For details, refer to RS485 Rx/Tx description on page 390.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Termination Specifies whether the termination of the signal lines is enabled or disabled. A new
termination configuration takes effect only after the Termination Set port rises
from 0 to 1.
Available only if Enable RS485 Termination configuration ports is set on the
Parameters page.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: No internal termination.
§ 1: A 120 Ω resistor between the signal lines terminates the RS485 signal.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Termination Lets you set the termination of the RS485 signal lines as specified by
Set the Termination port. A new setting overwrites the settings of the RS485
Termination on the Parameters page.

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Port Description
Available only if the Enable RS485 Termination configuration ports parameter is
set.
Data type: UFix_1_0
Data width: 1
Values:
§ No transition, or a 1 to 0 transition: A new termination setting does not take
effect.
§ 0 to 1 transition: The new settings are sent to the channel. The
Termination Ack port outputs a flag if the channel is up-to-date.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Sim Data Simulates an input signal that you can connect to a Simulink-based I/O
environment model.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Range: -5.5 V ... +5.5 V
Range exceeding is possible and will be saturated to the minimum or maximum
values.
Output
Data Outputs the data received from the RS485 network.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The input voltage level is negative (< 0 V).
§ 1: The input voltage level is positive (≥ 0 V).
Termination Outputs a flag that acknowledges a change of the termination setting.
Ack Available only if Enable RS485 Termination configuration ports parameter is set
on the Parameters page.
Data type: UFix_1_0
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one clock
cycle.

Note

To set the baud rate for a serial transmission, refer to Using the UART Demo
Model for SCALEXIO Systems (FPGA Programming Blockset Guide ).

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

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I/O mapping The following I/O mapping is relevant if you use the DS2655M2
I/O Module framework for RS485 Rx channels. The signals are available at the
female 50-pin Sub-D I/O connector of the respective DS2655M2 Digital I/O
Module.

Outport Channel Type Channel Connector Pin Signal

Data Digital In/Out 4 1 18 Rx– (Ch. 1-2)
2 2 Rx+ (Ch. 1-2)
5 20 Rx– (Ch. 5-6)
6 4 Rx+ (Ch. 5-6)
9 22 Rx– (Ch. 9-10)
10 6 Rx+ (Ch. 9-10)
13 24 Rx– (Ch. 13-14)
14 8 Rx+ (Ch. 13-14)
17 26 Rx– (Ch. 17-18)
18 10 Rx+ (Ch. 17-18)
21 28 Rx– (Ch. 21-22)
22 12 Rx+ (Ch. 21-22)
25 30 Rx– (Ch. 25-26)
26 14 Rx+ (Ch. 25-26)
29 32 Rx– (Ch. 29-30)
30 16 Rx+ (Ch. 29-30)

The I/O functions of the DS2655M2 I/O Module framework share the 32 I/O
channels of the DS2655M2 Digital I/O Module. For details on the signal mapping
to optimize channel usage, refer to Signal Mapping of the DS2655M2 Digital I/O
Module (SCALEXIO Hardware Installation and Configuration ).

RS485 Rx settings The following settings on the Parameters page are specific to the RS485 Rx I/O
function. For common dialog settings, refer to Common settings on page 369.

RS485 Termination Lets you enable an internal termination between the

signal lines. The setting can be overwritten by the RS485 termination ports.
§ Open
The signal lines are not terminated.
§ Terminated
An internal 120 Ω resistor terminates the signal lines.
This electrical interface setting can be changed in ConfigurationDesk.

Enable RS485 Termination configuration ports Lets you enable ports to

set the termination of the RS485 input. The following ports are added to the
block:
§ Termination
§ Termination Set
§ Termination Ack

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Related topics Basics

Modeling External I/O Access (FPGA Programming Blockset Guide )

Modeling UART Communication (FPGA Programming Blockset Guide )

Scaling Page (FPGA_IO_READ_BL)

Purpose To specify the inverting settings for the selected I/O function.

Description You can invert digital I/O signals and UART signals of the selected I/O function
if you select the Enable FPGA test access and scaling parameter on the FPGA
Access page of the FPGA_SETUP_BL block dialog. The possible modifications
depend on the selected I/O function.

Common settings The following settings on the Scaling page are common to the I/O functions that
you can select on the Unit page.

Enable FPGA test access and scaling for this block Lets you disable FPGA
test access and scaling for the selected I/O function.

Digital In settings The following settings on the Scaling page are specific to the Digital In I/O
function.

Invert input polarity Lets you adapt the measured values to the electrical
input signal:
§ Disabled:
The Data port outputs the signals as measured: A low-high transition results in
a 1 and vice versa.
§ Enabled:
The output of the Data port is inverted: A low-high transition results in a 0
and vice versa.

RS232 Rx settings The following settings on the Scaling page are specific to the RS232 Rx I/O
function.

Invert polarity Lets you adapt the electrical output signal:

§ Disabled:
If the input voltage is negative (<0 V), the Data port outputs a 1.
If the input voltage is positive (≥0 V), the Data port outputs a 0.
§ Enabled:
If the input voltage is negative (<0 V), the Data port outputs a 0.
If the input voltage is positive (≥0 V), the Data port outputs a 1.

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RS485 Rx settings The following settings on the Scaling page are specific to the RS485 Rx I/O
function.

Invert polarity Lets you adapt the electrical output signal:

§ Disabled:
If the input voltage is negative (<0 V), the Data port outputs a 0.
If the input voltage is positive (≥0 V), the Data port outputs a 1.
§ Enabled:
If the input voltage is negative (<0 V), the Data port outputs a 1.
If the input voltage is positive (≥0 V), the Data port outputs a 0.

Related topics Basics

Basics on FPGA Test Access and Scaling (FPGA Programming Blockset Guide )

FPGA_IO_WRITE_BL (DS2655M2 I/O Module Settings)

Purpose To configure write access to analog and digital input signals in the FPGA model
when using the DS2655M2 I/O Module framework.

Where to go from here Information in this section

Parameters Page (FPGA_IO_WRITE_BL).................................................. 378

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_WRITE_BL)........................................................ 397

To specify the inverting settings for the selected I/O function.

Information in other sections

Unit Page (FPGA_IO_WRITE_BL)............................................................... 60

To specify the I/O type and channel to be used for write access.

Parameters Page (FPGA_IO_WRITE_BL)

Purpose To specify relevant settings for the selected I/O function.

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Description The framework provides the I/O type Digital_Mod_<x>, which you can select on
the Unit page of the block. The module number <x> depends on the slot that
the I/O module is connected to.

The number of the available channels on the selected DS2655M2 Digital I/O
Module determines the I/O functions that you can select:
§ Digital Out - Ch: 1 … Digital Out - Ch: 32
§ Digital Out-Z - Ch: 1-2 … Digital Out-Z - Ch: 31-32
§ RS232 Tx - Ch: 1 ... RS232 Tx - Ch: 29
§ RS485 Rx/Tx - Ch: 1-3 ... RS485 Rx/Tx - Ch: 29-31
§ RS485 Tx - Ch: 1-2 ... RS485 Tx - Ch: 29-30

Channel dependencies The I/O functions of the DS2655M2 I/O Module framework share the I/O
channels that provide the I/O functionality. The DS2655M2 Digital I/O Module
provides 32 I/O channels. Some channels provide only specific I/O functionalities
and some I/O functions use more than one I/O channel. These channel
dependencies limit the number of available I/O functions.

For an overview of the DS2655M2 Digital I/O Module, refer to DS2655M2 Digital
I/O Module (SCALEXIO Hardware Installation and Configuration ).

For details on the signal mapping, refer to Signal Mapping of the DS2655M2
Digital I/O Module (SCALEXIO Hardware Installation and Configuration ).

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_IO_WRITE_BL.

Enable simulation port Lets you enable an outport for offline simulation
data. The Sim Data outport is added to the block to connect it to a Simulink-
based I/O environment model.

Digital Out description Block display If you select an Digital Out channel from the channel list, the
block display changes. Except for the inport Data, all the ports are displayed
optionally.

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I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Outputs a signal in the specified range.
To set the voltage level, use the High supply on the Parameters page or the
HighSupply Set inport.
Data Type: UFix_1_0
Data width: 1
If driven with 0, the hardware outputs a low-level signal. If driven with 1, the
hardware outputs a high-level signal.
Update rate: FPGA clock frequency
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.

Note

The frequency that can be generated is smaller than the update rate. For
information on the electrical characteristics of the DS2655M2 Digital I/O
Module, refer to Data Sheet of the DS2655M2 Digital I/O Module (SCALEXIO
Hardware Installation and Configuration ).

Mode Specifies the digital output mode. A new output mode takes effect only after the
Mode Set port rises from 0 to 1.
Available only if the Enable Output Mode configuration ports is set on the
Parameters page.
Data Type: UFix_3_0
Data width: 1
Values:
§ 5: Enables the low-side switch that drives a load connected to VCC.
§ 6: Enables the high-side switch that drives a load connected to GND.
§ 7: Enables a push-pull switch that drives a load with VCC and GND.
Mode Set Sets the output mode as specified by the Mode port. A new setting overwrites the
settings of the Output Mode on the Parameters page.
Available only if the Enable Output Mode configuration ports parameter is set.
Data type: UFix_1_0
Data width: 1
Values:
§ No transition, or a 1 to 0 transition: A new mode does not take effect.
§ 0 to 1 transition: New settings are sent to the output channel. The Mode Ack
port outputs a flag if the channel is up-to-date.
Update rate: FPGA clock frequency
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
DriveCfg Specifies the driver configuration. A new configuration takes effect only after the
DriveCfg Set port rises from 0 to 1.
Available only if the Enable Drive Config configuration ports is set on the
Parameters page.
Data Type: UFix_1_0

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Port Description
Data width: 1
Values:
§ 0: A serial 68 Ω resistor terminates the output signal.
§ 1: The output signal is driven directly without a termination.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
DriveCfg Set Sets the configuration as specified by the DriveCfg port. A new setting overwrites
the settings of the Drive Config on the Parameters page.
Available only if the Enable Drive Config configuration ports parameter is set.
Data type: UFix_1_0
Data width: 1
Values:
§ No transition, or a 1 to 0 transition: A new configuration does not take effect.
§ 0 to 1 transition: The output channel begins to update its channel. The
DriveCfg Ack port outputs a flag if the channel is up-to-date.
Update rate: FPGA clock frequency
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
HighSupply Specifies the supply voltage to output high-level signals.
A new supply voltage takes effect only after the HighSupply Set port rises from 0
to 1.
Available only if Enable High Supply configuration ports parameter is set on the
Parameters page.
Data Type: UFix_1_0
Data width: 1
Values:
§ 0: The supply voltage for high signals is 5 V.
§ 1: The supply voltage for high signals is 3.3 V.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
HighSupply Sets the supply voltage to the output high-level signal as specified by the
Set HighSupply port. A new setting overwrites the setting of the High Supply
parameter on the Parameters page.
Available only if Enable High Supply configuration ports parameter is set.
Data type: UFix_1_0
Data width: 1
Values:
§ No transition, or a 1 to 0 transition: A new supply voltage does not take effect.
§ 0 to 1 transition: The new setting is sent to the output channel. The
HighSupply Ack port outputs a flag if the channel is up-to-date.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Output

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Port Description
Mode Ack Outputs a flag that acknowledges a change of the output mode.
Available only if the Enable Output Mode configuration ports is set on the
Parameters page.
Data type: Double
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one clock
cycle.
DriveCfg Ack Outputs a flag that acknowledges a change of the driver configuration.
Available only if the Enable Drive Config configuration ports is set on the
Parameters page.
Data type: Double
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one clock
cycle.
HighSupply Outputs a flag that acknowledges a change of the high supply configuration.
Ack Available only if Enable High Supply configuration ports parameter is set on the
Parameters page.
Data type: Double
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one clock
cycle.
Sim Data Simulates an output signal that you can connect to a Simulink-based I/O
environment model. The signal is in the same range as specified for the hardware
output signal.
Available only if Enable simulation port property is set on the Parameters page.
Data type: Double
Data width: 1
Range: 0 V … 5 V or 0 V … 3.3 V
Update rate: FPGA clock frequency

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use the DS2655M2
I/O Module framework for digital output channels. The signals are available at
the female 50-pin Sub-D I/O connector of the respective DS2655M2 Digital I/O
Module.

Dig Outport Channel Type Channel Connector Pin Signal

Data Digital In/Out 4 1 18 Dig Out (Ch. 1)
2 2 Dig Out (Ch. 2)
Digital In/Out 2 3 35 Dig Out (Ch. 3)
4 19 Dig Out (Ch. 4)

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Dig Outport Channel Type Channel Connector Pin Signal

Digital In/Out 4 5 20 Dig Out (Ch. 5)
6 4 Dig Out (Ch. 6)
Digital In/Out 2 7 37 Dig Out (Ch. 7)
8 21 Dig Out (Ch. 8)
Digital In/Out 4 9 22 Dig Out (Ch. 9)
10 6 Dig Out (Ch. 10)
Digital In/Out 2 11 39 Dig Out (Ch. 11)
12 23 Dig Out (Ch. 12)
Digital In/Out 4 13 24 Dig Out (Ch. 13)
14 8 Dig Out (Ch. 14)
Digital In/Out 2 15 41 Dig Out (Ch. 15)
16 25 Dig Out (Ch. 16)
Digital In/Out 4 17 26 Dig Out (Ch. 17)
18 10 Dig Out (Ch. 18)
Digital In/Out 2 19 43 Dig Out (Ch. 19)
20 27 Dig Out (Ch. 20)
Digital In/Out 4 21 28 Dig Out (Ch. 21)
22 12 Dig Out (Ch. 22)
Digital In/Out 2 23 45 Dig Out (Ch. 23)
24 29 Dig Out (Ch. 24)
Digital In/Out 4 25 30 Dig Out (Ch. 25)
26 14 Dig Out (Ch. 26)
Digital In/Out 2 27 47 Dig Out (Ch. 27)
28 31 Dig Out (Ch. 28)
Digital In/Out 4 29 32 Dig Out (Ch. 29)
30 16 Dig Out (Ch. 30)
Digital In/Out 2 31 49 Dig Out (Ch. 31)
32 33 Dig Out (Ch. 32)

Digital Out settings The following settings on the Parameters page are specific to the Digital
Out I/O function. For common dialog settings, refer to Common settings on
page 379.

Output Mode Lets you select the output mode.

§ Low-side switch
Lets you actively drive the output to GND to output a low-level signal.
An external load to VCC is required to output a high-level signal.

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§ High-side switch
Lets you actively drive the output to VCC to output a high-level signal.
An external load to GND is necessary to output a low-level signal.
§ Push-pull
Lets you drive the output between VCC and GND.
An external load is not required.
This electrical interface setting can be changed in ConfigurationDesk.

Drive Config Lets you enable/disable the termination of the signal line by an
internal resistor.
§ Direct Drive
Lets you directly drive the I/O signal. The internal termination resistor is
disabled.
§ 68 Ohm Terminated
Lets you terminate the I/O signal with an internal 68 Ω resistor.
This electrical interface setting can be changed in ConfigurationDesk.

High supply Lets you select the VCC voltage that determines the high-level
voltage for the high‑side switch.
This electrical interface setting can be changed in ConfigurationDesk.

Enable Output Mode configuration ports Lets you enable ports to set the
digital output mode. The ports can overwrite the settings of the Output Mode
parameter.
The following ports are added to the block:
§ Mode
§ Mode Set
§ Mode Ack

Enable Drive Config configuration ports Lets you enable ports to

terminate the digital output. The ports can overwrite the settings of the Drive
Config parameter.
The following ports are added to the block:
§ DriveCfg
§ DriveCfg Set
§ DriveCfg Ack

Enable High Supply configuration ports Lets you enable ports to set the
voltage level of the high output signal. The ports can overwrite the settings of
the High supply parameter.
The following ports are added to the block:
§ HighSupply Data
§ HighSupply Set
§ HighSupply Ack

Digital Out-Z description Block display If you select an Digital Out-Z channel from the channel list, the
block display changes. Except for the Data and Enable inports, all the other
ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Outputs a signal in the specified range if the Enable port is set to 1.
To set the voltage level, use the High Supply parameter on the Parameters page
or the High Supply inport .
Data Type: UFix_1_0
Data width: 1
If driven with 0, the hardware outputs a low-level signal. If driven with 1, the
hardware outputs a high-level signal.
Update rate: FPGA clock frequency
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.

Note

The frequency that can be generated is smaller than the update rate. For
information on the electrical characteristics of the DS2655M2 Digital I/O
Module, refer to Data Sheet of the DS2655M2 Digital I/O Module (SCALEXIO
Hardware Installation and Configuration ).

Enable Enables the output of data values and disables the high-impedance state.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The output is set to the high-impedance state.
§ 1: The output is enabled and outputs the data values of the Data inport.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
DriveCfg Specifies the driver configuration. A new configuration takes effect only after the
DriveCfg Set port rises from 0 to 1.
Available only if the Enable Drive Config configuration ports is set on the
Parameters page.
Data Type: UFix_1_0
Data width: 1
Values:
§ 0: A serial 68 Ω resistor terminates the output signal.
§ 1: The output signal is driven directly without a termination.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.

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Port Description
DriveCfg Set Sets the configuration as specified by the DriveCfg port. A new setting overwrites
the settings of the Drive Config on the Parameters page.
Available only if the Enable Drive Config configuration ports parameter is set.
Data type: UFix_1_0
Data width: 1
Values:
§ No transition, or a 1 to 0 transition: A new configuration does not take effect.
§ 0 to 1 transition: The output channel begins to update its channel. The
DriveCfg Ack port outputs a flag if the channel is up-to-date.
Update rate: FPGA clock frequency
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
HighSupply Specifies the supply voltage to output high-level signals.
A new supply voltage takes effect only after the HighSupply Set port rises from 0
to 1.
Available only if Enable High Supply configuration ports parameter is set on the
Parameters page.
Data Type: UFix_1_0
Data width: 1
Values:
§ 0: The supply voltage for high signals is 5 V.
§ 1: The supply voltage for high signals is 3.3 V.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
HighSupply Sets the supply voltage to the output high-level signal as specified by the
Set HighSupply port. A new setting overwrites the setting of the High Supply
parameter on the Parameters page.
Available only if Enable High Supply configuration ports parameter is set.
Data type: UFix_1_0
Data width: 1
Values:
§ No transition, or a 1 to 0 transition: A new supply voltage does not take effect.
§ 0 to 1 transition: The new setting is sent to the output channel. The
HighSupply Ack port outputs a flag if the channel is up-to-date.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Output
DriveCfg Ack Outputs a flag that acknowledges a change of the driver configuration.
Available only if the Enable Drive Config configuration ports is set on the
Parameters page.
Data type: Double
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one clock
cycle.

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Port Description
HighSupply Outputs a flag that acknowledges a change of the high supply configuration.
Ack Available only if Enable High Supply configuration ports parameter is set on the
Parameters page.
Data type: Double
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one clock
cycle.
Sim Data Simulates an output signal that you can connect to a Simulink-based I/O
environment model. The signal is in the same range as specified for the hardware
output signal.
Available only if Enable simulation port property is set on the Parameters page.
Data type: Double
Data width: 1
Range: 0 V … 5 V or 0 V … 3.3 V
Update rate: FPGA clock frequency

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use the DS2655M2
I/O Module framework for digital output channels. The signals are available at
the female 50-pin Sub-D I/O connector of the respective DS2655M2 Digital I/O
Module.

Inport Channel Type Channel Connector Pin Signal

Data Digital In/Out 4 1 18 Dig Out-Z (Ch. 1-2)
2 2 Do not use
Digital In/Out 2 3 35 Dig Out-Z (Ch. 3-4)
4 19 Do not use
Digital In/Out 4 5 20 Dig Out-Z (Ch. 5-6)
6 4 Do not use
Digital In/Out 2 7 37 Dig Out-Z (Ch. 7-8)
8 21 Do not use
Digital In/Out 4 9 22 Dig Out-Z (Ch. 9-10)
10 6 Do not use
Digital In/Out 2 11 39 Dig Out-Z (Ch. 11-12)
12 23 Do not use
Digital In/Out 4 13 24 Dig Out-Z (Ch. 13-14)
14 8 Do not use
Digital In/Out 2 15 41 Dig Out-Z (Ch. 15-16)

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Inport Channel Type Channel Connector Pin Signal

16 25 Do not use
Digital In/Out 4 17 26 Dig Out-Z (Ch. 17-18)
18 10 Do not use
Digital In/Out 2 19 43 Dig Out-Z (Ch. 19-20)
20 27 Do not use
Digital In/Out 4 21 28 Dig Out-Z (Ch. 21-22)
22 12 Do not use
Digital In/Out 2 23 45 Dig Out-Z (Ch. 23-24)
24 29 Do not use
Digital In/Out 4 25 30 Dig Out-Z (Ch. 25-26)
26 14 Do not use
Digital In/Out 2 27 47 Dig Out-Z (Ch. 27-28)
28 31 Do not use
Digital In/Out 4 29 32 Dig Out-Z (Ch. 29-30)
30 16 Do not use
Digital In/Out 2 31 49 Dig Out-Z (Ch. 31-32)
32 33 Do not use

The I/O functions of the DS2655M2 I/O Module framework share the 32 I/O
channels of the DS2655M2 Digital I/O Module. For details on the signal mapping
to optimize channel usage, refer to Signal Mapping of the DS2655M2 Digital I/O
Module (SCALEXIO Hardware Installation and Configuration ).

Digital Out-Z settings The following settings on the Parameters page are specific to the Digital
Out‑Z I/O function. For common dialog settings, refer to Common settings on
page 379.

Drive Config Lets you enable/disable the termination of the signal line by an
internal resistor.
§ Direct Drive
Lets you directly drive the I/O signal. The internal termination resistor is
disabled.
§ 68 Ohm Terminated
Lets you terminate the I/O signal with an internal 68 Ω resistor.
This electrical interface setting can be changed in ConfigurationDesk.

High supply Lets you select the VCC voltage that determines the high-level
voltage for the high‑side switch.
This electrical interface setting can be changed in ConfigurationDesk.

Enable Drive Config configuration ports Lets you enable ports to

terminate the digital output. The ports can overwrite the settings of the Drive
Config parameter.

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The following ports are added to the block:

§ DriveCfg
§ DriveCfg Set
§ DriveCfg Ack

Enable High Supply configuration ports Lets you enable ports to set the
voltage level of the high output signal. The ports can overwrite the settings of
the High supply parameter.
The following ports are added to the block:
§ HighSupply Data
§ HighSupply Set
§ HighSupply Ack

RS232 Tx description Block display If you select an RS232 Tx channel from the channel list, the
block display changes. The simulation port is displayed optionally.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Outputs the data to be send to the RS232 Tx channel.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The output voltage level is +5.5 V.
§ 1: The output voltage level is –5.5 V.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
For information on the electrical characteristics of the DS2655M2 Digital I/O
Module, refer to Data Sheet of the DS2655M2 Digital I/O Module (SCALEXIO
Hardware Installation and Configuration ).
Output
Sim Data Simulates an output signal that you can connect to a Simulink-based I/O
environment model.
Available only if the Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Range: –5.5 V ... +5.5 V

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Note

To set the baud rate for a serial transmission, refer to Using the UART Demo
Model for SCALEXIO Systems (FPGA Programming Blockset Guide ).

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use the DS2655M2
I/O Module framework for RS232 Rx channels. The signals are available at the
female 50-pin Sub-D I/O connector of the respective DS2655M2 Digital I/O
Module.

Outport Channel Type Channel Connector Pin Signal

Data Digital In/Out 4 1 18 TX (Ch. 1)
5 20 TX (Ch. 5)
9 22 TX (Ch. 9)
13 24 TX (Ch. 13)
17 26 TX (Ch. 17)
21 28 TX (Ch. 21)
25 30 TX (Ch. 25)
29 32 TX (Ch. 29)

The I/O functions of the DS2655M2 I/O Module framework share the 32 I/O
channels of the DS2655M2 Digital I/O Module. For details on the signal mapping
to optimize channel usage, refer to Signal Mapping of the DS2655M2 Digital I/O
Module (SCALEXIO Hardware Installation and Configuration ).

RS232 Tx settings Only common dialog settings. Refer to Common settings on page 379.

RS485 Rx/Tx description Block display If you select an RS485 Rx/Tx channel from the channel list,
the block display changes. The simulation and termination ports are displayed
optionally.

Network mode With the RS485 Rx/Tx channel you can receive data from a
RS485 network in half-duplex mode.

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To connect to a RS485 network in simplex or full-duplex mode, use the RS485 Tx

and RS485 Rx I/O functions. For details, refer to RS485 Tx description on
page 394 and RS485 Rx description on page 374.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Tx Data Outputs the data to be send to the RS485 network if the Tx Enable port is set
to 1.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The output voltage level is –5.5 V.
§ 1: The output voltage level is +5.5 V.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Tx Enable Enables the output of data values to the RS485 network and disables the high-
impedance state.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The output is set to the high-impedance state (tri-state). The Rx Data outport
can output received data from the RS485 network.
§ 1: The output is enabled and transmits the data values of the Tx Data inport.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Termination Specifies whether the signals lines are terminated. A new configuration takes effect
only after the Termination Set port rises from 0 to 1.
Available only if the Enable RS485 Termination configuration ports is set on the
Parameters page.
Data Type: UFix_1_0
Data width: 1
Values:
§ 0: The signal lines are driven directly without a termination.
§ 1: An internal 120 Ω resistor terminates the signal lines.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Termination Lets you set the termination of the RS485 signal lines as specified by
Set the Termination port. A new setting overwrites the settings of the RS485
Termination on the Parameters page.
Available only if the Enable RS485 Termination configuration ports parameter is
set.
Data type: UFix_1_0
Data width: 1

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Port Description
Values:
§ No transition, or a 1 to 0 transition: A new termination setting does not take
effect.
§ 0 to 1 transition: The new settings are sent to the channel. The
Termination Ack port outputs a flag if the channel is up-to-date.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Sim Rx Data Simulates an input signal that you can connect to a Simulink-based I/O
environment model.
Available only if the Enable Rx Data simulation port is set on the Parameters
page.
Data type: Double
Data width: 1
Range: –5.5 V ... +5.5 V
Range exceeding is possible (using input bit widths > 1) and will be saturated to the
minimum or maximum values.
Output
Rx Data Outputs the data that is received from the RS485 network if the Tx Enable inport
is set to 0.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The input voltage level is negative (< 0 V).
§ 1: The input voltage level is positive (≥ 0 V).
Termination Outputs a flag that acknowledges a change of the termination setting.
Ack Available only if Enable RS485 Termination configuration ports parameter is set
on the Parameters page.
Data type: UFix_1_0
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one clock
cycle.
Sim Tx Data Simulates an output signal that you can connect to a Simulink-based I/O
environment model.
Available only if Enable Tx Data simulation configuration port is set on the
Parameters page.
Data type: Double
Data width: 1
Range: –5.5 V ... +5.5 V

Note

To set the baud rate for a serial transmission, refer to Using the UART Demo
Model for SCALEXIO Systems (FPGA Programming Blockset Guide ).

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.

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A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use the DS2655M2
I/O Module framework for RS485 Rx/Tx channels. The signals are available at
the female 50-pin Sub-D I/O connector of the respective DS2655M2 Digital I/O
Module.

Port Channel Type Channel Connector Pin Signal

1)
Tx Data inport and Rx Data outport Digital In/Out 4 1 18 RxTx– (Ch. 1-3)
2 2 RxTx+ (Ch. 1-3)
Digital In/Out 2 3 35 Do not use
Digital In/Out 4 5 20 RxTx– (Ch. 5-7)
6 4 RxTx+ (Ch. 5-7)
Digital In/Out 2 7 37 Do not use
Digital In/Out 4 9 22 RxTx– (Ch. 9-11)
10 6 RxTx+ (Ch. 9-11)
Digital In/Out 2 11 39 Do not use
Digital In/Out 4 13 24 RxTx– (Ch. 13-15)
14 8 RxTx+ (Ch. 13-15)
Digital In/Out 2 15 41 Do not use
Digital In/Out 4 17 26 RxTx– (Ch. 17-19)
18 10 RxTx+ (Ch. 17-19)
Digital In/Out 2 19 43 Do not use
Digital In/Out 4 21 28 RxTx– (Ch. 21-23)
22 12 RxTx+ (Ch. 21-23)
Digital In/Out 2 23 45 Do not use
Digital In/Out 4 25 30 RxTx– (Ch. 25-27)
26 14 RxTx+ (Ch. 25-27)
Digital In/Out 2 27 47 Do not use
Digital In/Out 4 29 32 RxTx– (Ch. 29-31)
30 16 RxTx+ (Ch. 29-31)
Digital In/Out 2 31 49 Do not use
1)
The RS485 Rx/Tx network is a half-duplex network.
The I/O functions of the DS2655M2 I/O Module framework share the 32 I/O
channels of the DS2655M2 Digital I/O Module. For details on the signal mapping
to optimize channel usage, refer to Signal Mapping of the DS2655M2 Digital I/O
Module (SCALEXIO Hardware Installation and Configuration ).

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RS485 Rx/Tx settings The following settings on the Parameters page are specific to the RS485 Rx/Tx
I/O function.

RS485 Termination Lets you enable an internal termination between the

signal lines. The setting can be overwritten by the RS485 termination ports.
§ Open
The signal lines are not terminated.
§ Terminated
An internal 120 Ω resistor terminates the signal lines.
This electrical interface setting can be changed in ConfigurationDesk.

Enable RS485 Termination configuration ports Lets you enable ports to

set the termination of the RS485 input. The following ports are added to the
block:
§ Termination
§ Termination Set
§ Termination Ack

Enable Rx Data simulation port Lets you enable an inport for offline
simulation data. The Sim Rx Data inport is added to the block to connect it
to a Simulink-based I/O environment model.

Enable Tx Data simulation port Lets you enable an outport for offline
simulation data. The Sim Tx Data outport is added to the block to connect it to
a Simulink-based I/O environment model.

RS485 Tx description Block display If you select an RS485 Tx channel from the channel list,
the block display changes. The simulation and termination ports are displayed
optionally.

Network mode With the RS485 Tx channel you can transmit data to a RS485
network in simplex mode. To connect to a RS485 network in full-duplex mode,
also use the corresponding RS485 Rx I/O function. For details on the RS485 Rx
I/O function, refer to RS485 Rx description on page 374.
To connect to a RS485 network in half-duplex mode, use the RS485 Rx/Tx I/O
function. For details, refer to RS485 Rx/Tx description on page 390.

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I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Outputs the data to the RS485 network if the Enable port is set to 1.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The output voltage level is –5.5 V.
§ 1: The output voltage level is +5.5 V.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Enable Enables the output of data values to the RS485 network.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The output is disabled.
The output voltage level is 0 V. The output does not support an high-impedance
state (tri-state).
§ 1: The output is enabled and transmits the data values of the Data inport.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Termination Specifies whether the signals lines are terminated. A new configuration takes effect
only after the Termination Set port rises from 0 to 1.
Available only if the Enable RS485 Termination configuration ports is set on the
Parameters page.
Data Type: UFix_1_0
Data width: 1
Values:
§ 0: The signal lines are driven directly without a termination.
§ 1: An internal 120 Ω resistor terminates the signal lines.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Termination Lets you set the termination of the RS485 signal lines as specified by
Set the Termination port. A new setting overwrites the settings of the RS485
Termination on the Parameters page.
Available only if the Enable RS485 Termination configuration ports parameter is
set.
Data type: UFix_1_0
Data width: 1
Values:
§ No transition, or a 1 to 0 transition: A new termination setting does not take
effect.
§ 0 to 1 transition: The new settings are sent to the channel. The
Termination Ack port outputs a flag if the channel is up-to-date.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.

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Port Description
Output
Termination Outputs a flag that acknowledges a change of the termination setting.
Ack Available only if Enable RS485 Termination configuration ports parameter is set
on the Parameters page.
Data type: UFix_1_0
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one clock
cycle.
Sim Data Simulates an output signal that you can connect to a Simulink-based I/O
environment model.
Available only if the Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Range: –5.5 V ... +5.5 V

Note

To set the baud rate for a serial transmission, refer to Using the UART Demo
Model for SCALEXIO Systems (FPGA Programming Blockset Guide ).

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use the DS2655M2
I/O Module framework for RS485 Tx channels. The signals are available at the
female 50-pin Sub-D I/O connector of the respective DS2655M2 Digital I/O
Module.

Outport Channel Type Channel Connector Pin Signal

Data Digital In/Out 4 1 18 Tx– (1-2)
2 2 Tx+ (1-2)
5 20 Tx– (5-6)
6 4 Tx+ (5-6)
9 22 Tx– (9-10)
10 6 Tx+ (9-10)
13 24 Tx– (13-14)
14 8 Tx+ (13-14)
17 26 Tx– (17-18)
18 10 Tx+ (17-18)
21 28 Tx– (21-22)
22 12 Tx+ (21-22)

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Outport Channel Type Channel Connector Pin Signal

25 30 Tx– (25-26)
26 14 Tx+ (25-26)
29 32 Tx– (29-30)
30 16 Tx+ (29-30)

The I/O functions of the DS2655M2 I/O Module framework share the 32 I/O
channels of the DS2655M2 Digital I/O Module. For details on the signal mapping
to optimize channel usage, refer to Signal Mapping of the DS2655M2 Digital I/O
Module (SCALEXIO Hardware Installation and Configuration ).

RS485 Tx settings The following settings on the Parameters page are specific to the RS485 Tx I/O
function. For common dialog settings, refer to Common settings on page 379.

RS485 Termination Lets you enable an internal termination between the

signal lines. The setting can be overwritten by the RS485 termination ports.
§ Open
The signal lines are not terminated.
§ Terminated
An internal 120 Ω resistor terminates the signal lines.
This electrical interface setting can be changed in ConfigurationDesk.

Enable RS485 Termination configuration ports Lets you enable ports to

set the termination of the RS485 input. The following ports are added to the
block:
§ Termination
§ Termination Set
§ Termination Ack

Related topics Basics

Modeling External I/O Access (FPGA Programming Blockset Guide )

Modeling UART Communication (FPGA Programming Blockset Guide )

Scaling Page (FPGA_IO_WRITE_BL)

Purpose To specify the inverting settings for the selected I/O function.

Description You can invert digital I/O signals and UART signals of the selected I/O function
if you select the Enable FPGA test access and scaling parameter on the FPGA
Access page of the FPGA_SETUP_BL block dialog. The possible modifications
depend on the selected I/O function.

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Common settings The following settings on the Scaling page are common to the I/O functions that
you can select on the Unit page.

Enable FPGA test access and scaling for this block Lets you disable FPGA
test access and scaling for the selected I/O function.

Digital Out settings The following settings on the Scaling page are specific to the Digital Out I/O
function.

Invert polarity Lets you adapt the electrical output signal:

§ Disabled:
If driven with 1, the hardware outputs a high-level signal.
If driven with 0, the hardware outputs a low-level signal.
§ Enabled:
If driven with 1, the hardware outputs a low-level signal.
If driven with 0, the hardware outputs a high-level signal.

Digital Out‑Z settings The following settings on the Scaling page are specific to the Digital Out‑Z I/O
function.

Invert polarity Lets you adapt the electrical output signal:

§ Disabled:
If driven with 1, the hardware outputs a high-level signal.
If driven with 0, the hardware outputs a low-level signal.
§ Enabled:
If driven with 1, the hardware outputs a low-level signal.
If driven with 0, the hardware outputs a high-level signal.

RS232 TX settings The following settings on the Scaling page are specific to the RS232 TX I/O
function.

Invert polarity Lets you adapt the electrical output signal:

§ Disabled:
If driven with 1, the I/O function sets the output to –5.5 V.
If driven with 0, the I/O function sets the output to +5.5 V.
§ Enabled:
If driven with 1, the I/O function sets the output to +5.5 V.
If driven with 0, the I/O function sets the output to –5.5 V.

RS485 Rx/Tx settings The following settings on the Scaling page are specific to the RS485 Rx/Tx I/O
function.

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Invert input polarity Lets you adapt the electrical output signal:
§ Disabled:
If the input voltage is negative (<0 V), the Rx Data port outputs a 0.
If the input voltage is positive (≥0 V), the Rx Data port outputs a 1.
§ Enabled:
If the input voltage is negative (<0 V), the Rx Data port outputs a 1.
If the input voltage is positive (≥0 V), the Rx Data port outputs a 0.

Invert output polarity Lets you adapt the electrical output signal:
§ Disabled:
If the Tx Data port is driven with 1, the I/O function sets the output to the
high voltage level.
If the Tx Data port is driven with 0, the I/O function sets the output to the low
voltage level.
§ Enabled:
If the Tx Data port is driven with 1, the I/O function sets the output to the low
voltage level.
If the Tx Data port is driven with 0, the I/O function sets the output to the
high voltage level.

RS485 Tx settings The following settings on the Scaling page are specific to the RS485 Tx I/O
function.

Invert polarity Lets you adapt the electrical output signal:

§ Disabled:
If driven with 1, the I/O function sets the output to the high voltage level.
If driven with 0, the I/O function sets the output to the low voltage level.
§ Enabled:
If driven with 1, the I/O function sets the output to the low voltage level.
If driven with 0, the I/O function sets the output to the high voltage level.

Related topics Basics

Basics on FPGA Test Access and Scaling (FPGA Programming Blockset Guide )

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Block Settings for the DS6651 Multi-I/O Module Framework

Introduction The block dialogs provide hardware-specific settings after you load one of the
following frameworks together with at least one DS6651 Multi-I/O Module
framework:
§ DS2655 (7K160) FPGA Base Board framework
§ DS2655 (7K410) FPGA Base Board framework
§ DS6601 (KU035) FPGA Base Board framework
§ DS6602 (KU15P) FPGA Base Board framework

Where to go from here Information in this section

FPGA_IO_READ_BL (DS6651 Multi-I/O Module Settings)........................ 400

To configure read access to the selected I/O function when using the
DS6651 Multi-I/O Module framework.

FPGA_IO_WRITE_BL (DS6651 Multi-I/O Module Settings)....................... 416

To configure write access to analog and digital input signals in the FPGA
model when using the DS6651 Multi-I/O Module framework.

FPGA_IO_READ_BL (DS6651 Multi-I/O Module Settings)

Purpose To configure read access to the selected I/O function when using the DS6651
Multi-I/O Module framework.

Where to go from here Information in this section

Parameters Page (FPGA_IO_READ_BL)................................................... 401

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_READ_BL).......................................................... 413

To specify the inverting settings for the selected I/O function.

Information in other sections

Unit Page (FPGA_IO_READ_BL)................................................................ 55

To specify the I/O type and channel to be used for read access.

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Parameters Page (FPGA_IO_READ_BL)

Purpose To specify relevant settings for the selected I/O function.

Description The framework provides the I/O types Digital_Mod_<x> and Analog_Mod_<x>,
which you can select on the Unit page of the block. The module number <x>
depends on the slot that the I/O module is connected to.

The number of the available channels on the selected DS6651 Multi-I/O Module
determines the I/O functions that you can select:
§ Analog In - Ch: 23, … , Analog In - Ch: 26
§ Analog In‑L - Ch: 27 and Analog In‑L - Ch: 28
§ Digital In - Ch: 1, … , Digital In - Ch: 16
§ RS485 Rx - Ch: 1-2, ... , RS485 Rx - Ch: 15-16

Digital channel dependencies The I/O functions of the DS6651 Multi-I/O Module framework share the digital
I/O channels that provide the digital I/O functionality. The DS6651 Multi-I/O
Module provides 16 digital I/O channels. Some I/O channels provide only specific
I/O functionalities, and some I/O functions use more than one I/O channel. These
channel dependencies and I/O channel sharing limit the number of I/O functions
that can be implemented.

For the data sheet of the DS6651 Multi-I/O Module, refer to DS6651 Multi-I/O
Module (SCALEXIO Hardware Installation and Configuration ).

For details on the signal mapping to optimize channel usage, refer to Supported
Digital Functions and Related I/O Channels (SCALEXIO Hardware Installation and
Configuration ).

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_IO_READ_BL block.

Enable simulation port Lets you enable an inport for offline simulation data.
The Sim Data inport is added to the block to connect it to simulation data
coming from a Simulink-based I/O environment model.

Analog In description Block display If you select an Analog In channel from the channel list, the
block display changes. The simulation port is displayed optionally.

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I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Input
Sim Data Simulates an input signal that you can connect to a Simulink-based I/O
environment model.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
The value range corresponds to the settings of the Input range parameter in V.
Range exceeding is possible and will be saturated to the minimum or maximum
values.
Output
Data Outputs the measured values of the 16-bit AD converter.
Data type: Fix_22_5 1)
Data width: 1
The value range of the Data outport depends on the setting of the Scaling
parameter on the Parameters page. Refer to Scaling on page 403.
Data New Outputs a flag that indicates the current status of the Data port.
New measured values from analog input channels of the same I/O module
are always provided synchronously. If analog inputs are read from different I/O
modules, the measured values are provided either synchronously or offset by two
clock cycles (16 ns). However, the sample time of the analog measurements is
synchronous on different I/O modules except for 8 ns.
If synchronous measured values from analog inputs of different I/O modules are
required, you can implement a logic to wait with the further processing of analog
values until the Data New ports flag new data within two clock cycles. The
following example shows a logic for the Data New ports to use synchronous
analog input signals of different I/O modules.

Data type: UFix_1_0

Data width: 1
Values:
§ 0: No new value is available at the Data port.
§ 1: A new valid value is available at the Data port.
The port is set to 1 only for one clock cycle.
1) You can change the data type of the Data port with the Scaling format parameter
on the Scaling page. Refer to How to Change the Data Type of Analog Signals (FPGA
Programming Blockset Guide ).

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Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping The following I/O mapping is relevant if you use the DS6651
Multi-I/O Module framework for analog input channels. The signals are available
at the female 50-pin Sub-D I/O connector of the respective DS6651 Multi-I/O
Module.

Outport Channel Type Channel Connector Pin Signal

Data Analog In 18 23 29 Analog In - Ch: 23 [Mod: x]
45 Reference
24 14 Analog In - Ch: 24 [Mod: x]
30 Reference
25 31 Analog In - Ch: 25 [Mod: x]
47 Reference
26 48 Analog In - Ch: 26 [Mod: x]
15 Reference

Analog In settings The following settings on the Parameters page are specific to the Analog In I/O
function. For common dialog settings, refer to Common settings on page 401.

The Parameters page provide the following dialog setting:

Input range Lets you specify the input voltage range that can be converted
from analog to digital for the chosen ADC channel. Input voltages outside the
specified range are saturated.
This electrical interface setting can be changed in ConfigurationDesk.

Scaling Lets you select whether the I/O function scales the measuring results
of the A/D converter to mV.
§ mV
To output the measuring results in mV.
The valid value range corresponds to the settings of the Input range
parameter in mV.
The default data type is Fix_22_5 to provide the precision of the A/D converter
when using the ±1 V input voltage range.
§ Bit
To output the raw measuring results as a signed Bit value.
The value range is -32,768 … +32,767.

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Data type: Fix_22_5

Tip

If you select Bit, you can reduce the complexity of the logic by using only
16 bits of the raw measurement result due to the 16-bit resolution of the
A/D converter.
§ Eliminate the fraction bits and the most significant bit with the Slice
block from the HDL library of the AMD® VitisTM Model Composer.
§ Reinterpret the UFix_16_0 value of the Slice block to Fix_16_0 with the
AMD Reinterpret block.
In hardware this reduction costs nothing.

Trigger mode Lets you select the trigger mode and source for sampling the
analog input voltage.
§ Free running
The ADC samples the input voltage with a fixed sample period that is set by
the Sample period parameter.
§ Trigger 1 or Trigger 2
The ADC samples the input voltage with each trigger impulse provided by a
Trigger I/O function. Refer to Trigger description on page 445.
§ Digital In <x> (<edge type>, <filter type>)
The selected digital input channel triggers the sampling of the analog input
signal:
§ <x>: Indicates the channel number of the digital input channel.
§ <edge type>: Indicates which edge of a digital input signal triggers the
ADC. A rising edge is a low to high transition, a falling edge is a high to low
transition.
§ <filter type>: Indicates whether the digital signal is filtered. 8 ns is the time
constant of the digital low-pass filter.

Sample period Lets you specify the sample period of the ADC in the free
running mode.
Sample period = nselected · 8 ns
With the value range 25 ≤ nselected ≤ 3,750,000,000.
The resulting sample period is in the range 200 ns ... 30 s.

Analog In‑L description Block display If you select an Analog In-L channel from the channel list, the
block display changes. The simulation port is displayed optionally.

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I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Input
Sim Data Simulates an input signal that you can connect to a Simulink-based I/O
environment model.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
The value range corresponds to the settings of the Input range parameter in V.
Range exceeding is possible and will be saturated to the minimum or maximum
values.
Output
Data Outputs the measured values of the 16-bit AD converter.
Data type: Fix_22_5 1)
Data width: 1
The value range of the Data output depends on the setting of the Scaling
parameter on the Parameters page. Refer to Scaling on page 406.
Data New Outputs a flag that indicates the current status of the Data port.
New measured values from analog input channels of the same I/O module
are always provided synchronously. If analog inputs are read from different I/O
modules, the measured values are provided either synchronously or offset by two
clock cycles (16 ns). However, the sample time of the analog measurements is
synchronous on different I/O modules except for 8 ns.
If synchronous measured values from analog inputs of different I/O modules are
required, you can implement a logic to wait with the further processing of analog
values until the Data New ports flag new data within two clock cycles. The
following example shows a logic for the Data New ports to use synchronous
analog input signals of different I/O modules.

Data type: UFix_1_0

Data width: 1
Values:
§ 0: No new value is available at the Data port.
§ 1: A new valid value is available at the Data port.
The port is set to 1 only for one clock cycle.
1) You can change the data type of the Data port with the Scaling format parameter
on the Scaling page. Refer to How to Change the Data Type of Analog Signals (FPGA
Programming Blockset Guide ).

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Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping The following I/O mapping is relevant if you use the DS6651
Multi-I/O Module framework for analog input channels. The signals are available
at the female 50-pin Sub-D I/O connector of the respective DS6651 Multi-I/O
Module.

Outport Channel Type Channel Connector Pin Signal

Data Analog In 19 27 16 Analog In‑L - Ch: 27 [Mod: x]
32 Reference
28 33 Analog In‑L - Ch: 28 [Mod: x]
49 Reference

Analog In-L settings The following settings on the Parameters page are specific to the Analog
In-L I/O function. For common dialog settings, refer to Common settings on
page 401.

The Parameters page provide the following dialog settings:

Input range Lets you specify the input voltage range that can be converted
from analog to digital for the chosen ADC channel. Input voltages outside the
specified range are saturated.
This electrical interface setting can be changed in ConfigurationDesk.

Scaling Lets you select whether the I/O function scales the measuring results
of the A/D converter to mV.
§ mV
To output the measuring results in mV.
The valid value range corresponds to the settings of the Input range
parameter in mV.
The default data type is Fix_22_5 to provide the precision of the A/D converter
when using the ±1 V input voltage range.
§ Bit
To output the raw measuring results as a signed Bit value.
The value range is -32,768 … +32,767.
Data type: Fix_22_5

Tip

If you select Bit, you can reduce the complexity of the logic by using only
16 bits of the raw measurement result due to the 16-bit resolution of the
A/D converter.
§ Eliminate the fraction bits and the most significant bit with the Slice
block from the HDL library of the AMD® VitisTM Model Composer.
§ Reinterpret the UFix_16_0 value of the Slice block to Fix_16_0 with the
AMD Reinterpret block.
In hardware this reduction costs nothing.

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Load Config Lets you enable a 220 Ω resistor between the analog signal and
the signal reference.

Trigger mode Lets you select the trigger mode and source for sampling the
analog input voltage.
§ Free running
The ADC samples the input voltage with a fixed sample period that is set by
the Sample period parameter.
§ Trigger 1 or Trigger 2
The ADC samples the input voltage with each trigger impulse provided by a
Trigger I/O function. Refer to Trigger description on page 445.
§ Digital In <x> (<edge type>, <filter type>)
The selected digital input channel triggers the sampling of the analog input
signal:
§ <x>: Indicates the channel number of the digital input channel.
§ <edge type>: Indicates which edge of a digital input signal triggers the
ADC. A rising edge is a low to high transition, a falling edge is a high to low
transition.
§ <filter type>: Indicates whether the digital signal is filtered. 8 ns is the time
constant of the digital low-pass filter.

Sample period Lets you specify the sample period of the ADC in the free
running mode.
Sample period = nselected · 8 ns
With the value range 25 ≤ nselected ≤ 3,750,000,000.
The resulting sample period is in the range 200 ns ... 30 s.

Digital In description Block display If you select a Digital In channel from the channel list, the
block display changes. Except for the outport Data, all the ports are displayed
optionally.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Threshold Voltage Specifies the threshold voltage level in mV. A new threshold voltage level takes
effect only after the Threshold Set port rises from 0 to 1.
Available only if the Enable Threshold Voltage configuration ports is set
on the Parameters page.
Data type: UFix_14_0
Data width: 1
Range: 0 mV ... 12,000 mV
Update rate: FPGA clock frequency

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Port Description
The range can be exceeded, and saturation is performed to a minimum or
maximum value.
Threshold Set Lets you set the trigger level as specified by the Threshold Voltage port.
A new setting overwrites the settings of the Threshold init voltage on the
Parameters page.
Available only if Enable Threshold Voltage configuration ports parameter
is set.
Data type: UFix_1_0
Data width: 1
Values:
§ No transition, or a 1 to 0 transition: A new voltage setting does not take
effect.
§ 0 to 1 transition: If the Threshold Set port rises from 0 to 1, the new
settings are sent to the output channel. The Threshold Ack port outputs a
flag if the channel is up-to-date.
Update rate: FPGA clock frequency
Range exceeding is possible (using input bit widths > 1) and will be cast to
1 bit by using only the lowest bit.
Sim Data Simulates an input signal that you can connect to a Simulink-based I/O
environment model. The threshold voltage determines a logical 0 or 1 as
output of the Data port.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Range: 0 V ... 30 V
Range exceeding is possible and will be saturated to the minimum or
maximum values.
Output
Data Outputs the current results of the digital input channel.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Input voltage of the channel is below the threshold voltage of a high-low
transition.
§ 1: Input voltage of the channel is higher than or equal to the threshold
voltage of a low-high transition.
Update rate: FPGA clock frequency
For information on the electrical characteristics of the DS6651 Multi-I/O
Module, refer to DS6651 Multi-I/O Module (SCALEXIO Hardware Installation
and Configuration ).
Threshold Ack Outputs a flag that indicates whether the threshold voltage level is up-to-date.
Available only if the Enable Threshold Voltage configuration ports is set
on the Parameters page.
Data type: UFix_1_0
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one
clock cycle.

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Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use the DS6651
Multi-I/O Module framework for Digital In channels. The signals are available
at the female 50-pin Sub-D I/O connector of the respective DS6651 Multi-I/O
Module.

Outport Channel Type Channel Connector Pin Signal

Data Digital In/Out 11 1 18 Digital In (Ch. 1)
2 2 Digital In (Ch. 2)
3 35 Digital In (Ch. 3)
4 19 Digital In (Ch. 4)
5 3 Digital In (Ch. 5)
6 36 Digital In (Ch. 6)
7 20 Digital In (Ch. 7)
8 4 Digital In (Ch. 8)
9 37 Digital In (Ch. 9)
10 21 Digital In (Ch. 10)
11 22 Digital In (Ch. 11)
12 6 Digital In (Ch. 12)
13 39 Digital In (Ch. 13)
14 23 Digital In (Ch. 14)
15 7 Digital In (Ch. 15)
16 40 Digital In (Ch. 16)

The digital I/O functions of the DS6651 Multi-I/O Module framework share the
channels that provide the digital I/O functionality. For more information, refer to
Digital channel dependencies on page 401.

Digital In settings The following settings on the Parameters page are specific to the Digital In I/O
function. For common dialog settings, refer to Common settings on page 401.

Threshold init voltage Lets you specify the voltage value that is used for the
threshold in mV.
Range: 0 mV ... 12,000 mV in 100 mV steps.
This electrical interface setting can be changed in ConfigurationDesk.

Enable Threshold Voltage configuration ports Lets you enable ports to

set the threshold voltage. The ports can overwrite the value of Threshold init
voltage.

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The following ports are added to the block:

§ Threshold Voltage
§ Threshold Set
§ Threshold Ack

RS485 Rx description Block display If you select an RS485 Rx channel from the channel list, the
block display changes. Except for the Data outport, all the ports are displayed
optionally.

Network mode With the RS485 Rx channel you can receive RS485 data
in simplex mode. To connect to RS485 networks in full-duplex mode, use the
corresponding RS485 Tx I/O function. For details on the RS485 Tx I/O function,
refer to RS485 Tx description on page 442.
To connect to a RS485 network in half-duplex mode, use the RS485 Rx/Tx I/O
function. For details, refer to RS485 Rx/Tx description on page 438.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Termination Specifies whether the signals lines are terminated. A new configuration takes effect
only after the Termination Set port rises from 0 to 1.
Available only if the Enable RS485 Termination configuration ports is set on the
Parameters page.
Data Type: UFix_1_0
Data width: 1
Values:
§ 0: The signal lines are driven directly without a termination.
§ 1: The signal lines are terminated via an internal RC termination with 120 Ω/5 nF.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Termination Lets you set the termination of the RS485 signal lines as specified by
Set the Termination port. A new setting overwrites the settings of the RS485
Termination on the Parameters page.
Available only if the Enable RS485 Termination configuration ports parameter is
set.
Data type: UFix_1_0
Data width: 1

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Port Description
Values:
§ No transition, or a 1 to 0 transition: A new termination setting does not take
effect.
§ 0 to 1 transition: The new settings are sent to the channel. The
Termination Ack port outputs a flag if the channel is up-to-date.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Sim Data Simulates an input signal that you can connect to a Simulink-based I/O
environment model.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Range: -5.5 V ... +5.5 V
Range exceeding is possible and will be saturated to the minimum or maximum
values.
Output
Data Outputs the data received from the RS485 network.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The input voltage level is negative (< 0 V).
§ 1: The input voltage level is positive (≥ 0 V).
Termination Outputs a flag that acknowledges a change of the termination setting.
Ack Available only if Enable RS485 Termination configuration ports parameter is set
on the Parameters page.
Data type: UFix_1_0
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one clock
cycle.

Note

To set the baud rate for a serial transmission, refer to Using the UART Demo
Model for SCALEXIO Systems (FPGA Programming Blockset Guide ).

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use the DS6651
Multi-I/O Module framework for RS485 Rx channels. The signals are available at
the female 50-pin Sub-D I/O connector of the respective DS2655M2 Digital I/O
Module.

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Outport Channel Type Channel Connector Pin Signal

Data Digital In/Out 11 1 18 RS485 Rx– (Ch. 1-2)
2 2 RS485 Rx+ (Ch. 1-2)
3 35 RS485 Rx– (Ch. 3-4)
4 19 RS485 Rx+ (Ch. 3-4)
5 3 RS485 Rx– (Ch. 5-6)
6 36 RS485 Rx+ (Ch. 5-6)
7 20 RS485 Rx– (Ch. 7-8)
8 4 RS485 Rx+ (Ch. 7-8)
9 37 RS485 Rx– (Ch. 9-10)
10 21 RS485 Rx+ (Ch. 9-10)
11 22 RS485 Rx– (Ch. 11-12)
12 6 RS485 Rx+ (Ch. 11-12)
13 39 RS485 Rx– (Ch. 13-14)
14 23 RS485 Rx+ (Ch. 13-14)
15 7 RS485 Rx– (Ch. 15-16)
16 40 RS485 Rx+ (Ch. 15-16)

The digital I/O functions of the DS6651 Multi-I/O Module framework share the
channels that provide the digital I/O functionality. For more information, refer to
Digital channel dependencies on page 401.

RS485 Rx settings The following settings on the Parameters page are specific to the RS485 Rx I/O
function. For common dialog settings, refer to Common settings on page 401.

RS485 Termination Lets you enable an internal termination between the

signal lines. The setting can be overwritten by the RS485 termination ports.
§ Open
The signal lines are not terminated.
§ Terminated
An internal 120 Ω/5 nF RC termination terminates the signal lines.
This electrical interface setting can be changed in ConfigurationDesk.

Enable RS485 Termination configuration ports Lets you enable ports to

set the termination of the RS485 input. The following ports are added to the
block:
§ Termination
§ Termination Set
§ Termination Ack

Related topics Basics

Modeling External I/O Access (FPGA Programming Blockset Guide )

Modeling UART Communication (FPGA Programming Blockset Guide )

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Scaling Page (FPGA_IO_READ_BL)

Purpose To specify the inverting settings for the selected I/O function.

Description You can invert digital I/O signals and UART signals of the selected I/O function
if you select the Enable FPGA test access and scaling parameter on the FPGA
Access page of the FPGA_SETUP_BL block dialog. The possible modifications
depend on the selected I/O function.

Common settings The following settings on the Scaling page are common to the I/O functions that
you can select on the Unit page.

Enable FPGA test access and scaling for this block Lets you disable FPGA
test access and scaling for the selected I/O function.

Analog In/Analog In‑L settings The following settings on the Scaling page are specific to the Analog In and
Analog In‑L I/O functions.

Note

Scaling of analog I/O signals also effects the signal path:

§ If you use the parameters of the Scaling page to scale analog signals, the
data type of the Data port is set to the specified data format for scaling.
For more information, refer to How to Change the Data Type of Analog
Signals (FPGA Programming Blockset Guide ).
§ FPGA scaling of analog I/O signals might cause additional latency. If
the latency can be calculated during the modeling, analog I/O functions
display the total latency.

Scaling format Lets you select the data format for scaling and saturation.
§ Signed/Unsigned:
The values of the parameters for scaling and saturation are in fixed‑point
format. The signed fixed-point format reserves one bit for the sign.
You can specify the number of bits and the binary point position with the
Number of bits and Binary point (fraction width) parameters.
§ Single:
The values of the parameters for scaling and saturation are 32-bit values in
the single-precision floating‑point format with a fraction width of 24, which
complies with the IEEE 754 standard (single).

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§ Double:
The values of the parameters for scaling and saturation are 64-bit values in
the double-precision floating‑point format with a fraction width of 53, which
complies with the IEEE 754 standard (double).

Number of bits This setting depends on the Scaling format setting.

§ Fixed-point format:
Lets you specify the bit width of the scaling parameters and the Data port in
the range 1 ... 64.
§ Floating-point format:
Displays the bit width of the scaling parameters and the Data port.

Binary point (fraction width) This setting depends on the Scaling format
setting.
§ Fixed-point format:
Lets you specify the binary point position of the scaling parameters and the
Data port. The position 0 represents the lowest bit position
§ Floating-point format:
Displays the fraction width of the scaling parameters and the Data port.

Scaling factor Lets you specify the scaling factor. The scaling factor gains the
signal of the Data port before it is saturated or replaced via FPGA test access.
You must check whether the specified and displayed value is supported by
the specified scaling format. The value of the Scaling factor parameter will
be executed with the maximum accuracy of the specified scaling format
and saturated to the minimum and maximum values that the scaling format
supports.

Scaling offset Lets you add a signal offset after the signal of the Data port is
scaled with the scaling factor.
You must check whether the specified and displayed value is supported by
the specified scaling format. The value of the Scaling offset parameter will
be executed with the maximum accuracy of the specified scaling format
and saturated to the minimum and maximum values that the scaling format
supports.

Saturation minimum value Lets you specify the minimum value to which
the measured and scaled signal is saturated before it is output via the Data port.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation minimum
value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

Saturation maximum value Lets you specify the maximum value to which
the measured and scaled signal is saturated before it is output via the Data port.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation maximum
value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

Multiplier latency Lets you specify the latency that is caused by the
multiplier for scaling. The multiplier is used to multiply the signal with the value
of the Scaling factor parameter.

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The following values are possible:

§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The multiplication will be implemented without latency.
§ 1 ... 20: The multiplication will be implemented with the specified latency.
Use this value range in the exceptional case that the optimized latency cause
timing problems during the build process.

Adder latency Lets you specify the latency that is caused by the offset adder.
The offset adder is used to add the value of the Scaling offset parameter to the
signal.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The adding will be implemented without latency.
§ 1 ... 20: The adding will be implemented with the specified latency.
Use this value range in the exceptional case that the optimized latency causes
timing problems during the build process.

Digital In settings The following settings on the Scaling page are specific to the Digital In I/O
function.

Invert input polarity Lets you adapt the measured values to the electrical
input signal:
§ Disabled:
The Data port outputs the signals as measured: A low-high transition results in
a 1 and vice versa.
§ Enabled:
The output of the Data port is inverted: A low-high transition results in a 0
and vice versa.

RS485 Rx settings The following settings on the Scaling page are specific to the RS485 Rx I/O
function.

Invert polarity Lets you adapt the electrical output signal:

§ Disabled:
If the input voltage is negative (<0 V), the Data port outputs a 0.
If the input voltage is positive (≥0 V), the Data port outputs a 1.
§ Enabled:
If the input voltage is negative (<0 V), the Data port outputs a 1.
If the input voltage is positive (≥0 V), the Data port outputs a 0.

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Related topics Basics

Basics on FPGA Test Access and Scaling (FPGA Programming Blockset Guide )

FPGA_IO_WRITE_BL (DS6651 Multi-I/O Module Settings)

Purpose To configure write access to analog and digital input signals in the FPGA model
when using the DS6651 Multi-I/O Module framework.

Where to go from here Information in this section

Parameters Page (FPGA_IO_WRITE_BL).................................................. 416

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_WRITE_BL)........................................................ 445

To specify the inverting settings for the selected I/O function.

Information in other sections

Unit Page (FPGA_IO_WRITE_BL)............................................................... 60

To specify the I/O type and channel to be used for write access.

Parameters Page (FPGA_IO_WRITE_BL)

Purpose To specify relevant settings for the selected I/O function.

Description The framework provides the I/O types Digital_Mod_<x> and Analog_Mod_<x>,
which you can select on the Unit page of the block. The module number <x>
depends on the slot that the I/O module is connected to.

The number of the available channels on the selected DS6651 Multi-I/O Module
determines the I/O functions that you can select:
§ Analog Out - Ch: 17, … , Analog Out - Ch: 20
§ Analog Out‑T - Ch: 21 and Analog Out‑T - Ch: 22
§ Digital Out - Ch: 1 … Digital Out - Ch: 16
§ Digital Out-Z - Ch: 1-2 … Digital Out-Z - Ch: 15-16
§ Digital In/Out-Z - Ch: 1-3 ... Digital In/Out‑Z - Ch: 13-15
§ RS485 Rx/Tx - Ch: 1-3 ... RS485 Rx/Tx - Ch: 13-15

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§ RS485 Tx - Ch: 1-2 ... RS485 Tx - Ch: 15-16

§ Trigger 1 and Trigger 2

Digital channel dependencies The I/O functions of the DS6651 Multi-I/O Module framework share the digital
I/O channels that provide the digital I/O functionality. The DS6651 Multi-I/O
Module provides 16 digital I/O channels. Some I/O channels provide only specific
I/O functionalities, and some I/O functions use more than one I/O channel. These
channel dependencies and I/O channel sharing limit the number of I/O functions
that can be implemented.

For the data sheet of the DS6651 Multi-I/O Module, refer to DS6651 Multi-I/O
Module (SCALEXIO Hardware Installation and Configuration ).

For details on the signal mapping to optimize channel usage, refer to Supported
Digital Functions and Related I/O Channels (SCALEXIO Hardware Installation and
Configuration ).

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_IO_WRITE_BL.

Enable simulation port Lets you enable an outport for offline simulation
data. The Sim Data outport is added to the block to connect it to a Simulink-
based I/O environment model.

Analog Out description Block display If you select an Analog Out channel from the channel list, the
block display changes. The Enable port, the simulation port, and the Tx Ready
port are displayed optionally.

I/O characteristics The following table describes the ports of the block for
analog output channels:

Port Description
Input
Data Outputs a voltage signal in the specified range.
Data type: Fix_18_2 1)
Data width: 1
The Scaling parameter on the Parameters pags specifies the value range:
§ ‑10,000 mV … +10,000 mV
§ ‑32,768 … +32,776
Update rate: 10.417 MSPS
Enable Lets you enable on-demand conversion of the Data port value to save up to 64 ns
of latency compared to free-running mode. It takes 96 ns … 120 ns until a new

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Port Description
value can be converted. When a new value can be converted, the Tx Ready port
outputs 1 for one clock cycle.
The Tx Ready port has an internal time pattern of 32 ns. The port changes its value
to 1 only within this time pattern. Therefore, the output values can jitter up to
24 ns if you do not follow the 32 ns time pattern when setting the Enable port.
Tipp: You can ignore the Tx Ready signal if you are sure that you will never enable
the Data port in periods shorter than 96 ns.
If you enable the Data port in periods shorter than 96 ns, you can implement the
following best practise for a jitter free output signal: Set the Enable port on the
32ns time pattern by comparing a free running 2-bit counter output value to 3 and
resetting the counter by the signal from the Tx Ready port.
Note: If you connect the Tx Ready port directly to the Enable port, the analog
output channel works in the same way as in the free running mode.
Available only if the Enable Enable port is set on the Parameters page.
Data Type: UFix_1_0
Data width: 1
Output
Sim Data Simulates the analog output signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Value range: ‑10 V … +10 V
Tx Ready Outputs a flag that indicates that the analog output channel of the DS6651 Multi-
I/O Module is ready to be updated. The minimum update period is 96 ns. When
you update data values only within the time slot for updating the output signal, the
output signal has no jitter. The time slot begins two FPGA clock cycles before the
flag is set to high and ends after three clock cycles.
Time slot for signal
updating without jitter

FPGA clock

TX Ready

Available only if Enable Tx Ready port is set on the Parameters page.

Data type: UFix_1_0
Data width: 1
1) You can change the data type of the Data port with the Scaling format parameter
on the Scaling page. Refer to How to Change the Data Type of Analog Signals (FPGA
Programming Blockset Guide ).

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping The following I/O mapping is relevant if you use the DS6651
Multi-I/O Module framework for analog output channels. The signals are

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available at the female 50-pin Sub-D I/O connector of the respective DS6651
Multi-I/O Module Module.

Outport Channel Type Channel Connector Pin Signal

Data Analog Out 15 17 8 Analog Out - Ch: 17 [Mod: x]
24 Reference
18 25 Analog Out - Ch: 18 [Mod: x]
41 Reference
19 10 Analog Out - Ch: 19 [Mod: x]
26 Reference
20 27 Analog Out - Ch: 20 [Mod: x]
43 Reference

Analog Out settings The following settings on the Parameters page are specific to the Analog
Out I/O function. For common dialog settings, refer to Common settings on
page 417.

Scaling Lets you select the scaling of the Data inport.

§ mV
To specify the output voltage in mV.
The value range is ‑10,000 mV … +10,000 mV.
§ Bit
To specify the output voltage with a signed bit value.
The value range is -32,768 … +32,767 (16-bit converter).

Enable Tx Ready port Lets you enable an outport to indicate that the analog
output channel is ready to be updated. The Tx Ready port is added to the block.

Enable Enable port Lets you enable an inport to enable the conversion of
the Data port value. The Enable port is added to the block.
If you enable the Enable port, enable the Tx Ready port, too.

Output range Displays the output range of the analog output channel.

Analog Out-T description Block display If you select an Analog Out‑T channel from the channel list, the
block display changes. The simulation port and the Tx Ready port are displayed
optionally.

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I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Input
Data Outputs a voltage signal in the specified range.
Data type: Fix_18_2 1)
Data width: 1
The value range depends on the setting of the Scaling parameter. Refer to Scaling
on page 421.
Update rate: 10.417 MSPS
Output
Sim Data Simulates an output signal that you can connect to a Simulink-based I/O
environment model. The signal is in the same range as specified for the hardware
output signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
The value range depends on the setting of the Output range parameter. Refer to
Output range on page 421.
TX Ready Outputs a flag that indicates that the analog output channel of the DS6651 Multi-
I/O Module is ready to be updated. The minimum update period is 96 ns. When
you update data values only within the time slot for updating the output signal, the
output signal has no jitter. The time slot begins two FPGA clock cycles before the
flag is set to high and ends after three clock cycles.
Time slot for signal
updating without jitter

FPGA clock

TX Ready

Available only if Enable Tx Ready port is set on the Parameters page.

Data type: UFix_1_0
Data width: 1
1) You can change the data type of the Data port with the Scaling format parameter
on the Scaling page. Refer to How to Change the Data Type of Analog Signals (FPGA
Programming Blockset Guide ).

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping The following I/O mapping is relevant if you use the DS6651
Multi-I/O Module framework for analog output channels. The signals are
available at the female 50-pin Sub-D I/O connector of the respective DS6651
Multi-I/O Module.

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Outport Channel Type Channel Connector Pin Signal

Data Analog Out 16 21 44 Analog Out‑T - Ch: 21 [Mod: x]
11 Reference
22 12 Analog Out‑T - Ch: 22 [Mod: x]
28 Reference

Analog Out-T settings The following settings on the Parameters page are specific to the Analog
Out-T I/O function. For common dialog settings, refer to Common settings on
page 417.

Scaling Lets you select the scaling of the Data inport to specify the output
voltage.
§ mV
To specify the output voltage in mV.
The value range corresponds to the settings of the Mode parameter.
§ Bit
To specify the output voltage with a signed bit value.
The value range is -32,768 … +32,776 (16-bit converter).

Output range Lets you select the voltage range and converter mode of the
analog output channel:
§ ‑10 V … +10 V DC:
The DA converter directly outputs the voltage signal without using a
transformer. The output voltage range is ‑10 V DC … +10 V DC.
§ ‑20 V … +20 V AC:
The DA converter outputs the voltage signal via a transformer. The output
voltage range is ‑20 V AC … +20 V AC.
For the AC characteristics, refer to Data Sheet of the DS6651 Multi-I/O Module
(SCALEXIO Hardware Installation and Configuration ).
This electrical interface setting can be changed in ConfigurationDesk.

Enable Tx Ready port Lets you enable an outport to indicate that the analog
output channel is ready to be updated. The Tx Ready port is added to the block.

Digital Out description Block display If you select an Digital Out channel from the channel list, the
block display changes. Except for the Data inport, all the ports are displayed
optionally.

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I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Outputs a signal in the specified range.
To set the voltage level, use the High supply on the Parameters page or the
HighSupply Set inport.
Data Type: UFix_1_0
Data width: 1
If driven with 0, the hardware outputs a low-level signal. If driven with 1, the
hardware outputs a high-level signal.
Update rate: FPGA clock frequency
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.

Note

The frequency that can be generated is smaller than the update rate. For
information on the electrical characteristics of the DS6651 Multi-I/O Module,
refer to Data Sheet of the DS6651 Multi-I/O Module (SCALEXIO Hardware
Installation and Configuration ).

Mode Specifies the digital output mode. A new output mode takes effect only after the
Mode Set port rises from 0 to 1.
Available only if the Enable Output Mode configuration ports is set on the
Parameters page.
Data Type: UFix_5_0
Data width: 1
Values:
§ 17: Enables the low-side switch that drives a load connected to VCC.
§ 18: Enables the high-side switch that drives a load connected to GND.
§ 19: Enables a push-pull switch that drives a load with VCC and GND.
Mode Set Sets the output mode as specified by the Mode port. A new setting overwrites the
settings of the Output Mode on the Parameters page.
Available only if the Enable Output Mode configuration ports parameter is set.
Data type: UFix_1_0
Data width: 1
Values:
§ No transition, or a 1 to 0 transition: A new mode does not take effect.
§ 0 to 1 transition: New settings are sent to the output channel. The Mode Ack
port outputs a flag if the channel is up-to-date.
Update rate: FPGA clock frequency
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
DriveCfg Specifies the driver configuration. A new configuration takes effect only after the
DriveCfg Set port rises from 0 to 1.
Available only if the Enable Drive Config configuration ports is set on the
Parameters page.
Data Type: UFix_1_0

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Port Description
Data width: 1
Values:
§ 0: A serial 68 Ω resistor terminates the output signal.
§ 1: The output signal is driven directly without a termination.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
DriveCfg Set Sets the configuration as specified by the DriveCfg port. A new setting overwrites
the settings of the Drive Config on the Parameters page.
Available only if the Enable Drive Config configuration ports parameter is set.
Data type: UFix_1_0
Data width: 1
Values:
§ No transition, or a 1 to 0 transition: A new configuration does not take effect.
§ 0 to 1 transition: The output channel begins to update its channel. The
DriveCfg Ack port outputs a flag if the channel is up-to-date.
Update rate: FPGA clock frequency
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
HighSupply Specifies the supply voltage to output high-level signals.
A new supply voltage takes effect only after the HighSupply Set port rises from 0
to 1.
Available only if Enable High Supply configuration ports parameter is set on the
Parameters page.
Data Type: UFix_1_0
Data width: 1
Values:
§ 0: The supply voltage for high signals is 5 V.
§ 1: The supply voltage for high signals is 3.3 V.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
HighSupply Sets the supply voltage to the output high-level signal as specified by the
Set HighSupply port. A new setting overwrites the setting of the High Supply
parameter on the Parameters page.
Available only if Enable High Supply configuration ports parameter is set.
Data type: UFix_1_0
Data width: 1
Values:
§ No transition, or a 1 to 0 transition: A new supply voltage does not take effect.
§ 0 to 1 transition: The new setting is sent to the output channel. The
HighSupply Ack port outputs a flag if the channel is up-to-date.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Output

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Port Description
Mode Ack Outputs a flag that acknowledges a change of the output mode.
Available only if the Enable Output Mode configuration ports is set on the
Parameters page.
Data type: Double
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one clock
cycle.
DriveCfg Ack Outputs a flag that acknowledges a change of the driver configuration.
Available only if the Enable Drive Config configuration ports is set on the
Parameters page.
Data type: Double
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one clock
cycle.
HighSupply Outputs a flag that acknowledges a change of the high supply configuration.
Ack Available only if Enable High Supply configuration ports parameter is set on the
Parameters page.
Data type: Double
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one clock
cycle.
Sim Data Simulates an output signal that you can connect to a Simulink-based I/O
environment model. The signal is in the same range as specified for the hardware
output signal.
Available only if Enable simulation port property is set on the Parameters page.
Data type: Double
Data width: 1
Range: 0 V … 5 V or 0 V … 3.3 V
Update rate: FPGA clock frequency

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use the DS6651
Multi-I/O Module framework for digital output channels. The signals are available
at the female 50-pin Sub-D I/O connector of the respective DS6651 Multi-I/O
Module.
The digital I/O functions of the DS6651 Multi-I/O Module framework share the
channels that provide the digital I/O functionality. For more information, refer to
Digital channel dependencies on page 417.

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Digital Outport Channel Type Channel Connector Pin Signal

Data Digital In/Out 11 1 18 Digital Out (Ch. 1)
2 2 Digital Out (Ch. 2)
3 35 Digital Out (Ch. 3)
4 19 Digital Out (Ch. 4)
5 3 Digital Out (Ch. 5)
6 36 Digital Out (Ch. 6)
7 20 Digital Out (Ch. 7)
8 4 Digital Out (Ch. 8)
9 37 Digital Out (Ch. 9)
10 21 Digital Out (Ch. 10)
11 22 Digital Out (Ch. 11)
12 6 Digital Out (Ch. 12)
13 39 Digital Out (Ch. 13)
14 23 Digital Out (Ch. 14)
15 7 Digital Out (Ch. 15)
16 40 Digital Out (Ch. 16)

Digital Out settings The following settings on the Parameters page are specific to the Digital
Out I/O function. For common dialog settings, refer to Common settings on
page 417.

Output Mode Lets you select the output mode.

§ Low-side switch
Lets you actively drive the output to GND to output a low-level signal.
An external load to VCC is required to output a high-level signal.
§ High-side switch
Lets you actively drive the output to VCC to output a high-level signal.
An external load to GND is necessary to output a low-level signal.
§ Push-pull
Lets you drive the output between VCC and GND.
An external load is not required.
This electrical interface setting can be changed in ConfigurationDesk.

Drive Config Lets you enable/disable the termination of the signal line by an
internal resistor.
§ Direct Drive
Lets you directly drive the I/O signal. The internal termination resistor is
disabled.
§ 68 Ohm Terminated
Lets you terminate the I/O signal with an internal 68 Ω resistor.
This electrical interface setting can be changed in ConfigurationDesk.

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High supply Lets you select the VCC voltage that determines the high-level
voltage for the high‑side switch.
This electrical interface setting can be changed in ConfigurationDesk.

Enable Output Mode configuration ports Lets you enable ports to set the
digital output mode. The ports can overwrite the settings of the Output Mode
parameter.
The following ports are added to the block:
§ Mode
§ Mode Set
§ Mode Ack

Enable Drive Config configuration ports Lets you enable ports to

terminate the digital output. The ports can overwrite the settings of the Drive
Config parameter.
The following ports are added to the block:
§ DriveCfg
§ DriveCfg Set
§ DriveCfg Ack

Enable High Supply configuration ports Lets you enable ports to set the
voltage level of the high output signal. The ports can overwrite the settings of
the High supply parameter.
The following ports are added to the block:
§ HighSupply Data
§ HighSupply Set
§ HighSupply Ack

Digital Out-Z description Block display If you select an Digital Out-Z channel from the channel list, the
block display changes. Except for the Data and Enable inports, all the other
ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Outputs a signal in the specified range.
To set the voltage level, use the High supply on the Parameters page or the
HighSupply Set inport.
Data Type: UFix_1_0
Data width: 1
If driven with 0, the hardware outputs a low-level signal. If driven with 1, the
hardware outputs a high-level signal.
Update rate: FPGA clock frequency
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.

Note

The frequency that can be generated is smaller than the update rate. For
information on the electrical characteristics of the DS6651 Multi-I/O Module,
refer to Data Sheet of the DS6651 Multi-I/O Module (SCALEXIO Hardware
Installation and Configuration ).

Enable Enables the output of data values and disables the high-impedance state.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The output is set to the high-impedance state.
§ 1: The output is enabled and outputs the data values of the Data inport.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Mode Specifies the digital output mode. A new output mode takes effect only after the
Mode Set port rises from 0 to 1.
Available only if the Enable Output Mode configuration ports is set on the
Parameters page.
Data Type: UFix_6_0
Data width: 1
Values:
§ 33: Enables the low-side switch that drives a load connected to VCC.
§ 34: Enables the high-side switch that drives a load connected to GND.
§ 35: Enables a push-pull switch that drives a load with VCC and GND.
Mode Set Sets the output mode as specified by the Mode port. A new setting overwrites the
settings of the Output Mode on the Parameters page.
Available only if the Enable Output Mode configuration ports parameter is set.
Data type: UFix_1_0
Data width: 1
Values:
§ No transition, or a 1 to 0 transition: A new mode does not take effect.
§ 0 to 1 transition: New settings are sent to the output channel. The Mode Ack
port outputs a flag if the channel is up-to-date.

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Port Description
Update rate: FPGA clock frequency
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
DriveCfg Specifies the driver configuration. A new configuration takes effect only after the
DriveCfg Set port rises from 0 to 1.
Available only if the Enable Drive Config configuration ports is set on the
Parameters page.
Data Type: UFix_1_0
Data width: 1
Values:
§ 0: A serial 68 Ω resistor terminates the output signal.
§ 1: The output signal is driven directly without a termination.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
DriveCfg Set Sets the configuration as specified by the DriveCfg port. A new setting overwrites
the settings of the Drive Config on the Parameters page.
Available only if the Enable Drive Config configuration ports parameter is set.
Data type: UFix_1_0
Data width: 1
Values:
§ No transition, or a 1 to 0 transition: A new configuration does not take effect.
§ 0 to 1 transition: The output channel begins to update its channel. The
DriveCfg Ack port outputs a flag if the channel is up-to-date.
Update rate: FPGA clock frequency
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
HighSupply Specifies the supply voltage to output high-level signals.
A new supply voltage takes effect only after the HighSupply Set port rises from 0
to 1.
Available only if Enable High Supply configuration ports parameter is set on the
Parameters page.
Data Type: UFix_1_0
Data width: 1
Values:
§ 0: The supply voltage for high signals is 5 V.
§ 1: The supply voltage for high signals is 3.3 V.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
HighSupply Sets the supply voltage to the output high-level signal as specified by the
Set HighSupply port. A new setting overwrites the setting of the High Supply
parameter on the Parameters page.
Available only if Enable High Supply configuration ports parameter is set.
Data type: UFix_1_0
Data width: 1

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Port Description
Values:
§ No transition, or a 1 to 0 transition: A new supply voltage does not take effect.
§ 0 to 1 transition: The new setting is sent to the output channel. The
HighSupply Ack port outputs a flag if the channel is up-to-date.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Output
Mode Ack Outputs a flag that acknowledges a change of the output mode.
Available only if the Enable Output Mode configuration ports is set on the
Parameters page.
Data type: Double
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one clock
cycle.
DriveCfg Ack Outputs a flag that acknowledges a change of the driver configuration.
Available only if the Enable Drive Config configuration ports is set on the
Parameters page.
Data type: Double
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one clock
cycle.
HighSupply Outputs a flag that acknowledges a change of the high supply configuration.
Ack Available only if Enable High Supply configuration ports parameter is set on the
Parameters page.
Data type: Double
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one clock
cycle.
Sim Data Simulates an output signal that you can connect to a Simulink-based I/O
environment model. The signal is in the same range as specified for the hardware
output signal.
Available only if Enable simulation port property is set on the Parameters page.
Data type: Double
Data width: 1
Range: 0 V … 5 V or 0 V … 3.3 V
Update rate: FPGA clock frequency

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use the DS6651
Multi-I/O Module framework for digital output channels. The signals are available

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at the female 50-pin Sub-D I/O connector of the respective DS6651 Multi-I/O
Module.

Inport Channel Type Channel Connector Pin Signal

Data Digital In/Out 11 1 18 Digital Out-Z (Ch. 1-2)
2 2 Do no use
3 35 Digital Out-Z (Ch. 3-4)
4 19 Do no use
5 3 Digital Out-Z (Ch. 5-6)
6 36 Do no use
7 20 Digital Out-Z (Ch. 7-8)
8 4 Do no use
9 37 Digital Out-Z (Ch. 9-10)
10 21 Do no use
11 22 Digital Out-Z (Ch. 11-12)
12 6 Do no use
13 39 Digital Out-Z (Ch. 13-14)
14 23 Do no use
15 7 Digital Out-Z (Ch. 15-16)
16 40 Do no use

The digital I/O functions of the DS6651 Multi-I/O Module framework share the
channels that provide the digital I/O functionality. For more information, refer to
Digital channel dependencies on page 417.

Digital Out-Z settings The following settings on the Parameters page are specific to the Digital
Out‑Z I/O function. For common dialog settings, refer to Common settings on
page 417.

Output Mode Lets you select the output mode.

§ Low-side switch
Lets you actively drive the output to GND to output a low-level signal.
An external load to VCC is required to output a high-level signal.
§ High-side switch
Lets you actively drive the output to VCC to output a high-level signal.
An external load to GND is necessary to output a low-level signal.
§ Push-pull
Lets you drive the output between VCC and GND.
An external load is not required.
This electrical interface setting can be changed in ConfigurationDesk.

Drive Config Lets you enable/disable the termination of the signal line by an
internal resistor.
§ Direct Drive
Lets you directly drive the I/O signal. The internal termination resistor is
disabled.

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§ 68 Ohm Terminated
Lets you terminate the I/O signal with an internal 68 Ω resistor.
This electrical interface setting can be changed in ConfigurationDesk.

High supply Lets you select the VCC voltage that determines the high-level
voltage for the high‑side switch.
This electrical interface setting can be changed in ConfigurationDesk.

Enable Output Mode configuration ports Lets you enable ports to set the
digital output mode. The ports can overwrite the settings of the Output Mode
parameter.
The following ports are added to the block:
§ Mode
§ Mode Set
§ Mode Ack

Enable Drive Config configuration ports Lets you enable ports to

terminate the digital output. The ports can overwrite the settings of the Drive
Config parameter.
The following ports are added to the block:
§ DriveCfg
§ DriveCfg Set
§ DriveCfg Ack

Enable High Supply configuration ports Lets you enable ports to set the
voltage level of the high output signal. The ports can overwrite the settings of
the High supply parameter.
The following ports are added to the block:
§ HighSupply Data
§ HighSupply Set
§ HighSupply Ack

Digital In/Out‑Z description Block display If you select a Digital In/Out channel from the channel list, the
block display changes. Except for the Data In, Data Out, and Enable ports, all
the ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Out Outputs a signal in the specified range if the Enable port is set to 1.
To set the voltage level, use the High Supply parameter on the Parameters page
or the High Supply inport .
Data Type: UFix_1_0
Data width: 1
If driven with 0, the hardware outputs a low-level signal. If driven with 1, the
hardware outputs a high-level signal.
Update rate: FPGA clock frequency
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.

Note

The frequency that can be generated is smaller than the update rate. For
information on the electrical characteristics of the DS6651 Multi-I/O Module,
refer to Data Sheet of the DS6651 Multi-I/O Module (SCALEXIO Hardware
Installation and Configuration ).

Enable Enables the output of data values and disables the high-impedance state.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The output is set to the high-impedance state.
§ 1: The output is enabled and outputs the data values of the Data inport.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Threshold Specifies a trigger level in mV. A new threshold voltage level takes effect only after
Voltage the Threshold Set port rises from 0 to 1.

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Port Description
Available only if Enable digital in configuration ports is set on the Parameters
page.
Data type: UFix_14_0
Data width: 1
Range: 0 mV ... 12,000 mV
Update rate: FPGA clock frequency
The range can be exceeded, and saturation is performed to a minimum or maximum
value.
Threshold Set Lets you set the trigger level as specified by the Threshold Voltage port. A
new setting overwrites the settings of Threshold init voltage parameter on the
Parameters page.
Available only if the Enable digital in configuration ports is set.
Data type: UFix_1_0
Data width: 1
Values:
§ No transition, or a 1 to 0 transition: A new voltage setting does not take effect.
§ 0 to 1 transition: If the Threshold Set port rises from 0 to 1, the new settings are
sent to the output channel. The Threshold Ack port outputs a flag if the channel
is up-to-date.
Update rate: FPGA clock frequency
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Mode Specifies the digital output mode. A new output mode takes effect only after the
Mode Set port rises from 0 to 1.
Available only if the Enable digital out configuration ports parameter is set on
the Parameters page.
Data Type: UFix_6_0
Data width: 1
Values:
§ 49: Enables the low-side switch that drives a load connected to VCC.
§ 50: Enables the high-side switch that drives a load connected to GND.
§ 51: Enables a push-pull switch that drives a load with VCC and GND.
Mode Set Sets the output mode as specified by the Mode port. A new setting overwrites the
settings of the Output Mode on the Parameters page.
Available only if the Enable digital out configuration ports parameter is set.
Data type: UFix_1_0
Data width: 1
Values:
§ No transition, or a 1 to 0 transition: A new mode does not take effect.
§ 0 to 1 transition: New settings are sent to the output channel. The Mode Ack
port outputs a flag if the channel is up-to-date.
Update rate: FPGA clock frequency
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
DriveCfg Specifies the driver configuration. A new configuration takes effect only after the
DriveCfg Set port rises from 0 to 1.

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Port Description
Available only if the Enable digital out configuration ports is set on the
Parameters page.
Data Type: UFix_1_0
Data width: 1
Value range:
§ 0: An internal 68 Ω resistor to GND terminates the output signal.
§ 1: The output signal is driven directly without a termination.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
DriveCfg Set Sets the configuration as specified by the DriveCfg port. A new setting overwrites
the settings of the Drive Config on the Parameters page.
Available only if the Enable digital out configuration ports parameter is set.
Data type: UFix_1_0
Data width: 1
Value range:
§ No transition, or a 1 to 0 transition: A new configuration does not take effect.
§ 0 to 1 transition: The output channel begins to update its channel. The
DriveCfg Ack port outputs a flag if the channel is up-to-date.
Update rate: FPGA clock frequency
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
HighSupply Specifies the supply voltage to output high-level signals. A new supply voltage takes
effect only after the HighSupply Set port rises from 0 to 1.
Available only if the Enable digital out configuration ports is set on the
Parameters page.
Data Type: UFix_1_0
Data width: 1
Values:
§ 0: The supply voltage for high signals is 5 V.
§ 1: The supply voltage for high signals is 3.3 V.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
HighSupply Sets the supply voltage to the output high-level signal as specified by the
Set HighSupply port. A new setting overwrites the setting of the High Supply on
the Parameters page.
Available only if the Enable digital out configuration ports parameter is set.
Data type: UFix_1_0
Data width: 1
Range:
§ No transition, or a 1 to 0 transition: A new supply voltage does not take effect.
§ 0 to 1 transition: The new setting is sent to the output channel. The
HighSupply Ack port outputs a flag if the channel is up-to-date.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Sim Data In Simulates an input signal that you can connect to a Simulink-based I/O environment
model. The threshold voltage determines a logical 0 or 1 as output of the Data
port.

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Port Description
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Range: 0 V ... 12 V
Range exceeding is possible and will be saturated to the minimum or maximum
values.
Output
Data In Outputs the current results of the digital input channel.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Input voltage of the channel is below the threshold voltage of a high-low
transition.
§ 1: Input voltage of the channel is higher than or equal to the threshold voltage of
a low-high transition.
Update rate: FPGA clock frequency
For information on the electrical characteristics of the DS6651 Multi-I/O
Module, refer to DS6651 Multi-I/O Module (SCALEXIO Hardware Installation and
Configuration ).
In Threshold Outputs a flag that acknowledges a change of the threshold voltage level
Ack configuration.
Available only if the Enable digital in configuration ports is set on the
Parameters page.
Data type: UFix_1_0
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one clock
cycle.
Mode Ack Outputs a flag that acknowledges a change of the output mode.
Available only if Enable digital out configuration ports is set on the Parameters
page.
Data type: Double
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one clock
cycle.
DriveCfg Ack Outputs a flag that acknowledges a change of the driver configuration.
Available only if Enable digital out configuration ports is set on the Parameters
page.
Data type: Double
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one clock
cycle.

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Port Description
HighSupply Outputs a flag that acknowledges a change of the high supply configuration.
Ack Available only if Enable digital out configuration ports is set on the Parameters
page.
Data type: Double
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one clock
cycle.
Sim Data Out Simulates an output signal that you can connect to a Simulink-based I/O
environment model. The signal is in the same range as specified for the hardware
output signal.
Available only if Enable digital in simulation port is set on the Parameters page.
Data type: Double
Output voltage: 0 V … 5 V or 0 V … 3.3 V
Update rate: FPGA clock frequency

If the value of the Data In inport exceeds the specified data width, only the
lowest bit is used. If the hardware signal or the value of the Sim Data In
inport exceeds the minimum or maximum threshold voltage, it is saturated to the
corresponding minimum or maximum value.

Note

Asynchronous input data might lead to metastable register states because

input data is synchronized only by a single register stage. Further
synchronization techniques might be necessary.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use the DS6651
Multi-I/O Module framework for digital signals. The signals are available at the
female 50-pin Sub-D I/O connector of the respective DS2655M2 Digital I/O
Module.

Ports Channel Type Channel Connector Pin Signal

Data In and Data Out Digital In/Out 11 1 18 Digital In/Out-Z (Ch. 1-3)
2 2 Do no use
3 35 Do no use
4 19 Usable by other I/O functions
5 3 Digital In/Out-Z (Ch. 5-7)
6 36 Do no use
7 20 Do no use
8 4 Usable by other I/O functions

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Ports Channel Type Channel Connector Pin Signal

9 37 Digital In/Out-Z (Ch. 9-11)
10 21 Do no use
11 22 Do no use
12 6 Usable by other I/O functions
13 39 Digital In/Out-Z (Ch. 13-15)
14 23 Do no use
15 7 Do no use
16 40 Usable by other I/O functions

Digital In/Out‑Z settings The following settings on the Parameters page are specific to the Digital
In/Out‑Z I/O function.

Output Mode Lets you select the output mode.

§ Low-side switch
Lets you actively drive the output to GND to output a low-level signal.
An external load to VCC is required to output a high-level signal.
§ High-side switch
Lets you actively drive the output to VCC to output a high-level signal.
An external load to GND is necessary to output a low-level signal.
§ Push-pull
Lets you drive the output between VCC and GND.
An external load is not required.
This electrical interface setting can be changed in ConfigurationDesk.

Drive Config Lets you enable/disable the termination of the signal line by an
internal resistor.
§ Direct Drive
Lets you directly drive the I/O signal. The internal termination resistor is
disabled.
§ 68 Ohm Terminated
Lets you terminate the I/O signal with an internal 68 Ω resistor.
This electrical interface setting can be changed in ConfigurationDesk.

High supply Lets you select the VCC voltage that determines the high-level
voltage for the high‑side switch.
This electrical interface setting can be changed in ConfigurationDesk.

Threshold init voltage Lets you specify the voltage value that is used for the
threshold in mV.
Range: 0 mV ... 12,000 mV in 100 mV steps.
This electrical interface setting can be changed in ConfigurationDesk.

Enable digital in configuration ports Lets you enable ports to set the
threshold voltage. The ports can overwrite the settings of In Threshold init
voltage.

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The following ports are added to the block:

§ Threshold Voltage
§ Threshold Set
§ In Threshold Ack

Enable digital out simulation port Lets you enable ports to configure the
digital output. The ports can overwrite the settings of the Output Mode, Drive
Config, and High supply parameters.
The following ports are added to the block:
§ Mode
§ Mode set
§ DriveCfg
§ DriveCfg Set
§ HighSupply
§ HighSupply Set

Enable digital in simulation port Lets you enable an inport for offline
simulation data. The Sim Data In inport is added to the block to connect it to
simulation data coming from a Simulink-based I/O environment model. This port
is relevant only if the signal direction is in.

Enable digital out simulation port Lets you enable an outport for offline
simulation data. The Sim Data Out port is added to the block to connect it to a
Simulink-based I/O environment model.

RS485 Rx/Tx description Block display If you select an RS485 Rx/Tx channel from the channel list,
the block display changes. The simulation and termination ports are displayed
optionally.

Network mode With the RS485 Rx/Tx channel you can receive data from a
RS485 network in half-duplex mode.
To connect to a RS485 network in simplex or full-duplex mode, use the RS485 Tx
and RS485 Rx I/O functions. For details, refer to RS485 Tx description on
page 442 and RS485 Rx description on page 410.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Tx Data Outputs the data to be send to the RS485 network if the Tx Enable port is set
to 1.
The differential output voltage level depends on the High Supply setting on the
Parameters page.
Data type: UFix_1_0

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Port Description
Data width: 1
Values:
§ 0: The output voltage level is low.
§ 1: The output voltage level is high.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Tx Enable Enables the output of data values to the RS485 network and disables the high-
impedance state.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The output is set to the high-impedance state (tri-state). The Rx Data outport
can output received data from the RS485 network.
§ 1: The output is enabled and transmits the data values of the Tx Data inport.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Termination Specifies whether the signals lines are terminated. A new configuration takes effect
only after the Termination Set port rises from 0 to 1.
Available only if the Enable RS485 Termination configuration ports is set on the
Parameters page.
Data Type: UFix_1_0
Data width: 1
Values:
§ 0: The signal lines are driven directly without a termination.
§ 1: The signal lines are terminated via an internal RC termination with 120 Ω/5 nF.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Termination Lets you set the termination of the RS485 signal lines as specified by
Set the Termination port. A new setting overwrites the settings of the RS485
Termination on the Parameters page.
Available only if the Enable RS485 Termination configuration ports parameter is
set.
Data type: UFix_1_0
Data width: 1
Values:
§ No transition, or a 1 to 0 transition: A new termination setting does not take
effect.
§ 0 to 1 transition: The new settings are sent to the channel. The
Termination Ack port outputs a flag if the channel is up-to-date.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Sim Rx Data Simulates an input signal that you can connect to a Simulink-based I/O
environment model.
Available only if Enable Rx Data simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Range: ±3.3 V or ±5 V, depends on the High Supply parameter setting.

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Port Description
Range exceeding is possible and will be saturated to the minimum or maximum
values.
Output
Rx Data Outputs the data that is received from the RS485 network if the Tx Enable inport
is set to 0.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The input voltage level is negative (< 0 V).
§ 1: The input voltage level is positive (≥ 0 V).
Termination Outputs a flag that acknowledges a change of the termination setting.
Ack Available only if Enable RS485 Termination configuration ports parameter is set
on the Parameters page.
Data type: UFix_1_0
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one clock
cycle.
Sim Tx Data Simulates an output signal that you can connect to a Simulink-based I/O
environment model.
Available only if the Enable Tx Data simulation port is set on the Parameters
page.
Data type: Double
Data width: 1
Range: ±3.3 V or ±5 V, depends on the High Supply parameter setting.

Note

To set the baud rate for a serial transmission, refer to Using the UART Demo
Model for SCALEXIO Systems (FPGA Programming Blockset Guide ).

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use the DS6651
Multi-I/O Module framework for RS485 Rx/Tx channels. The signals are available
at the female 50-pin Sub-D I/O connector of the respective DS6651 Multi-I/O
Module.

Port Channel Type Channel Connector Pin Signal

1)
Tx Data inport and Rx Data outport Digital In/Out 11 1 18 RS485 RxTx– (Ch. 1-3)
2 2 RS485 RxTx+ (Ch. 1-3)
3 35 Do no use

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Port Channel Type Channel Connector Pin Signal

4 19 Usable by other I/O functions
5 3 RS485 RxTx– (Ch. 5-7)
6 36 RS485 RxTx+ (Ch. 5-7)
7 20 Do no use
8 4 Usable by other I/O functions
9 37 RS485 RxTx– (Ch. 9-11)
10 21 RS485 RxTx+ (Ch. 9-11)
11 22 Do no use
12 6 Usable by other I/O functions
13 39 RS485 RxTx– (Ch. 13-15)
14 23 RS485 RxTx+ (Ch. 13-15)
15 7 Do no use
16 40 Usable by other I/O functions
1) The RS485 RxTx network is a half-duplex network.
The digital I/O functions of the DS6651 Multi-I/O Module framework share the
channels that provide the digital I/O functionality. For more information, refer to
Digital channel dependencies on page 417.

RS485 Rx/Tx settings The following settings on the Parameters page are specific to the RS485 Rx/Tx
I/O function.

High supply Lets you set the differential output voltage to ±3.3 V or ±5 V.

RS485 Termination Lets you enable an internal termination between the

signal lines. The setting can be overwritten by the RS485 termination ports.
§ Open
The signal lines are not terminated.
§ Terminated
An internal 120 Ω/5 nF RC termination terminates the signal lines.
This electrical interface setting can be changed in ConfigurationDesk.

Enable RS485 Termination configuration ports Lets you enable ports to

set the termination of the RS485 input. The following ports are added to the
block:
§ Termination
§ Termination Set
§ Termination Ack

Enable Rx Data simulation port Lets you enable an inport for offline
simulation data. The Sim Rx Data inport is added to the block to connect it
to a Simulink-based I/O environment model.

Enable Tx Data simulation port Lets you enable an outport for offline
simulation data. The Sim Tx Data outport is added to the block to connect it to
a Simulink-based I/O environment model.

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RS485 Tx description Block display If you select an RS485 Tx channel from the channel list,
the block display changes. The simulation and termination ports are displayed
optionally.

Network mode With the RS485 Tx channel you can transmit data to a RS485
network in simplex mode. To connect to a RS485 network in full-duplex mode,
also use the corresponding RS485 Rx I/O function. For details on the RS485 Rx
I/O function, refer to RS485 Rx description on page 410.
To connect to a RS485 network in half-duplex mode, use the RS485 Rx/Tx I/O
function. For details, refer to RS485 Rx/Tx description on page 438.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Outputs the data to the RS485 network if the Enable port is set to 1.
The differential output voltage level depends on the High Supply setting on the
Parameters page.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The output voltage level is low.
§ 1: The output voltage level is high.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Enable Enables the output of data values to the RS485 network.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The output is disabled.
The output voltage level is 0 V. The output does not support an high-impedance
state (tri-state).
§ 1: The output is enabled and transmits the data values of the Data inport.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Termination Specifies whether the signals lines are terminated. A new configuration takes effect
only after the Termination Set port rises from 0 to 1.
Available only if the Enable RS485 Termination configuration ports is set on the
Parameters page.
Data Type: UFix_1_0
Data width: 1

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Port Description
Values:
§ 0: The signal lines are driven directly without a termination.
§ 1: The signal lines are terminated via an internal RC termination with 120 Ω/5 nF.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Termination Lets you set the termination of the RS485 signal lines as specified by
Set the Termination port. A new setting overwrites the settings of the RS485
Termination on the Parameters page.
Available only if the Enable RS485 Termination configuration ports parameter is
set.
Data type: UFix_1_0
Data width: 1
Values:
§ No transition, or a 1 to 0 transition: A new termination setting does not take
effect.
§ 0 to 1 transition: The new settings are sent to the channel. The
Termination Ack port outputs a flag if the channel is up-to-date.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1 bit by
using only the lowest bit.
Output
Termination Outputs a flag that acknowledges a change of the termination setting.
Ack Available only if Enable RS485 Termination configuration ports parameter is set
on the Parameters page.
Data type: UFix_1_0
Data width: 1
The value 1 acknowledges the update. The flag is set high only within one clock
cycle.
Sim Data Simulates an output signal that you can connect to a Simulink-based I/O
environment model.
Available only if the Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Range: ±3.3 V or ±5 V, depends on the High Supply parameter setting.

Note

To set the baud rate for a serial transmission, refer to Using the UART Demo
Model for SCALEXIO Systems (FPGA Programming Blockset Guide ).

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

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I/O mapping The following I/O mapping is relevant if you use the DS6651
Multi-I/O Module framework for RS485 Tx channels. The signals are available
at the female 50-pin Sub-D I/O connector of the respective DS6651 Multi-I/O
Module.

Outport Channel Type Channel Connector Pin Signal

Data Digital In/Out 11 1 18 RS485 Tx– (Ch. 1-2)
2 2 RS485 Tx+ (Ch. 1-2)
3 35 RS485 Tx– (Ch. 3-4)
4 19 RS485 Tx+ (Ch. 3-4)
5 3 RS485 Tx– (Ch. 5-6)
6 36 RS485 Tx+ (Ch. 5-6)
7 20 RS485 Tx– (Ch. 7-8)
8 4 RS485 Tx+ (Ch. 7-8)
9 37 RS485 Tx– (Ch. 9-10)
10 21 RS485 Tx+ (Ch. 9-10)
11 22 RS485 Tx– (Ch. 11-12)
12 6 RS485 Tx+ (Ch. 11-12)
13 39 RS485 Tx– (Ch. 13-14)
14 23 RS485 Tx+ (Ch. 13-14)
15 7 RS485 Tx– (Ch. 15-16)
16 40 RS485 Tx+ (Ch. 15-16)

The digital I/O functions of the DS6651 Multi-I/O Module framework share the
channels that provide the digital I/O functionality. For more information, refer to
Digital channel dependencies on page 417.

RS485 Tx settings The following settings on the Parameters page are specific to the RS485 Tx I/O
function. For common dialog settings, refer to Common settings on page 417.

High supply Lets you set the differential output voltage to ±3.3 V or ±5 V.

RS485 Termination Lets you enable an internal termination between the

signal lines. The setting can be overwritten by the RS485 termination ports.
§ Open
The signal lines are not terminated.
§ Terminated
An internal 120 Ω/5 nF RC termination terminates the signal lines.
This electrical interface setting can be changed in ConfigurationDesk.

Enable RS485 Termination configuration ports Lets you enable ports to

set the termination of the RS485 input. The following ports are added to the
block:
§ Termination
§ Termination Set
§ Termination Ack

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Trigger description Block display If you select a Trigger channel from the channel list, the block
display changes. The simulation and termination ports are displayed optionally.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Enable Lets you trigger the analog measurement of the DS6651 Multi-I/O Module.
Data Type: UFix_1_0
Data width: 1
A transition from 0 to 1 provides a trigger impulse that can be used by the Analog
In/Analog In-L I/O functions. Refer to Analog In description on page 401 and
Analog In‑L description on page 404.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping No external connection.

Trigger settings None

Related topics Basics

Modeling External I/O Access (FPGA Programming Blockset Guide )

Modeling UART Communication (FPGA Programming Blockset Guide )

Scaling Page (FPGA_IO_WRITE_BL)

Purpose To specify the inverting settings for the selected I/O function.

Description You can invert digital I/O signals and UART signals of the selected I/O function
if you select the Enable FPGA test access and scaling parameter on the FPGA

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Access page of the FPGA_SETUP_BL block dialog. The possible modifications

depend on the selected I/O function.

Common settings The following settings on the Scaling page are common to the I/O functions that
you can select on the Unit page.

Enable FPGA test access and scaling for this block Lets you disable FPGA
test access and scaling for the selected I/O function.

Analog Out/Analog Out‑T The following settings on the Scaling page are specific to the Analog Out and
settings Analog Out‑T I/O functions.

Note

Scaling of analog I/O signals also effects the signal path:

§ If you use the parameters of the Scaling page to scale analog signals, the
data type of the Data port is set to the specified data format for scaling.
For more information, refer to How to Change the Data Type of Analog
Signals (FPGA Programming Blockset Guide ).
§ FPGA scaling of analog I/O signals might cause additional latency. If
the latency can be calculated during the modeling, analog I/O functions
display the total latency.

Scaling format Lets you select the data format for scaling and saturation.
§ Signed/Unsigned:
The values of the parameters for scaling and saturation are in fixed‑point
format. The signed fixed-point format reserves one bit for the sign.
You can specify the number of bits and the binary point position with the
Number of bits and Binary point (fraction width) parameters.
§ Single:
The values of the parameters for scaling and saturation are 32-bit values in
the single-precision floating‑point format with a fraction width of 24, which
complies with the IEEE 754 standard (single).
§ Double:
The values of the parameters for scaling and saturation are 64-bit values in
the double-precision floating‑point format with a fraction width of 53, which
complies with the IEEE 754 standard (double).

Number of bits This setting depends on the Scaling format setting.

§ Fixed-point format:
Lets you specify the bit width of the scaling parameters and the Data port in
the range 1 ... 64.
§ Floating-point format:
Displays the bit width of the scaling parameters and the Data port.

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Binary point (fraction width) This setting depends on the Scaling format
setting.
§ Fixed-point format:
Lets you specify the binary point position of the scaling parameters and the
Data port. The position 0 represents the lowest bit position
§ Floating-point format:
Displays the fraction width of the scaling parameters and the Data port.

Scaling factor Lets you specify the scaling factor. The scaling factor gains
the signal of the Data port or the replace value (FPGA test access) before it is
saturated.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Scaling factor parameter
will be saturated to the minimum and maximum values that the scaling format
and the hardware supports.

Scaling offset Lets you add a signal offset after the signal of the Data port is
scaled with the scaling factor.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Scaling offset parameter
will be saturated to the minimum and maximum values that the scaling format
and the hardware supports.

Saturation minimum value Lets you specify the minimum value to which
the scaled Data inport signal is saturated before it is output via an analog output
channel.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation minimum
value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

Saturation maximum value Lets you specify the maximum value to which
the scaled Data inport signal is saturated before it is output via an analog output
channel.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation maximum
value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

Multiplier latency Lets you specify the latency that is caused by the
multiplier for scaling. The multiplier is used to multiply the signal with the value
of the Scaling factor parameter.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The multiplication will be implemented without latency.
§ 1 ... 20: The multiplication will be implemented with the specified latency.
Use this value range in the exceptional case that the optimized latency cause
timing problems during the build process.

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Adder latency Lets you specify the latency that is caused by the offset adder.
The offset adder is used to add the value of the Scaling offset parameter to the
signal.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The adding will be implemented without latency.
§ 1 ... 20: The adding will be implemented with the specified latency.
Use this value range in the exceptional case that the optimized latency causes
timing problems during the build process.

Digital Out/Digital Out‑Z The following settings on the Scaling page are specific to the Digital Out and
settings Digital Out‑Z I/O functions.

Invert polarity Lets you adapt the electrical output signal:

§ Disabled:
If driven with 1, the hardware outputs a high-level signal.
If driven with 0, the hardware outputs a low-level signal.
§ Enabled:
If driven with 1, the hardware outputs a low-level signal.
If driven with 0, the hardware outputs a high-level signal.

Digital In/Out‑Z settings The following settings on the Scaling page are specific to the Digital In/Out‑Z
I/O function.

Invert input polarity Lets you invert the measured values of the electrical
input signal:
§ Disabled:
The Data port outputs the signals as measured: A low-high transition results in
a 1 and vice versa.
§ Enabled:
The output of the Data port is inverted: A low-high transition results in a 0
and vice versa.

Invert output polarity Lets you adapt the electrical output signal:
§ Disabled:
If driven with 1, the hardware outputs a high-level signal.
If driven with 0, the hardware outputs a low-level signal.
§ Enabled:
If driven with 1, the hardware outputs a low-level signal.
If driven with 0, the hardware outputs a high-level signal.

RS485 Rx/Tx settings The following settings on the Scaling page are specific to the RS485 Rx/Tx I/O
function.

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Invert input polarity Lets you adapt the electrical output signal:
§ Disabled:
If the input voltage is negative (<0 V), the Rx Data port outputs a 0.
If the input voltage is positive (≥0 V), the Rx Data port outputs a 1.
§ Enabled:
If the input voltage is negative (<0 V), the Rx Data port outputs a 1.
If the input voltage is positive (≥0 V), the Rx Data port outputs a 0.

Invert output polarity Lets you adapt the electrical output signal:
§ Disabled:
If the Tx Data port is driven with 1, the I/O function sets the output to the
high voltage level.
If the Tx Data port is driven with 0, the I/O function sets the output to the low
voltage level.
§ Enabled:
If the Tx Data port is driven with 1, the I/O function sets the output to the low
voltage level.
If the Tx Data port is driven with 0, the I/O function sets the output to the
high voltage level.

RS485 Tx settings The following settings on the Scaling page are specific to the RS485 Tx I/O
function.

Invert polarity Lets you adapt the electrical output signal:

§ Disabled:
If driven with 1, the I/O function sets the output to the high voltage level.
If driven with 0, the I/O function sets the output to the low voltage level.
§ Enabled:
If driven with 1, the I/O function sets the output to the low voltage level.
If driven with 0, the I/O function sets the output to the high voltage level.

Trigger settings The Scaling page is empty because this I/O function does not support FPGA
scaling.

Related topics Basics

Basics on FPGA Test Access and Scaling (FPGA Programming Blockset Guide )

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Block Settings for the DS660X_MGT Framework

Introduction The block dialogs provide hardware-specific settings after you load one of the
following frameworks together with the DS660X_MGT framework:
§ DS6601 (KU035) FPGA Base Board framework
§ DS6602 (KU15P) FPGA Base Board framework

Where to go from here Information in this section

FPGA_IO_READ_BL (MGT In Settings).................................................... 450

To configure read access to the MGT communication bus when using the
DS660X_MGT framework.

FPGA_IO_WRITE_BL (MGT Out Settings)................................................ 457

To configure write access to the MGT communication bus when using
the DS660X_MGT framework.

FPGA_IO_READ_BL (MGT In Settings)

Purpose To configure read access to the MGT communication bus when using the
DS660X_MGT framework.

Where to go from here Information in this section

Parameters Page (FPGA_IO_READ_BL)................................................... 451

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_READ_BL).......................................................... 457

The Scaling page is empty because the I/O functions of this framework
do not support FPGA scaling.

Information in other sections

Unit Page (FPGA_IO_READ_BL)................................................................ 55

To specify the I/O type and channel to be used for read access.

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Parameters Page (FPGA_IO_READ_BL)

Purpose To specify relevant settings for the selected I/O function.

Description The framework provides the I/O type MGT, which you can select on the Unit
page of the block. The number of the available physical connections determines
the I/O functions that you can select:
§ Aurora 64b66b In 1 … 4
§ Aurora 64b66b 128 Bit In 1 … 4
§ MGT In
§ MGT In Opto Ready

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_IO_READ_BL.

Enable simulation port Lets you enable an inport for offline simulation data.
The Sim Data inport is added to the block to connect it to any Simulink signal
used for simulation.

Aurora 64b66b In description Purpose To read 64-bit data values from an MGT communication channel
using the Aurora 64b66b link-layer protocol.

Used communication protocol setting The I/O function uses the Aurora
64B/66B protocol with the following settings:
§ Transceiver: GTH
§ Line Rate: 10.3125 Gbps
§ Dataflow Mode: Duplex
§ Interface: Framing
§ Flow Control: NFC
§ USER K: off
§ Little Endian Support: off
§ CRC: off
For more information on the protocol, refer to https://docs.xilinx.com/r/en-
US/pg074-aurora-64b66b.

Block display If you select an Aurora 64b66b In channel from the channel
list, the block display changes. The inport Sim Data is displayed optionally.

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I/O characteristics The following table describes the ports of the block for
the MGT module.

Port Description
Input
Ready Specifies that the communication channel is ready to read new data. Use this port
to prevent a data overflow.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The communication channel is not ready.
§ 1: New data can be read.
Sim Data Simulates a data exchange via the MGT communication bus including floating-
point to fixed-point data conversion.
Available only if the Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Output
Data Reads a 64-bit data value from the MGT communication bus.
User data transfer rate: Max. 8 Gbit/s (125 MHz FPGA clock, 64 bits)
MGT latency1):
§ With maximum data rate: 456 ns
§ Single words: Max. 472 ns, typ. 384 ns
If you implement inter-FPGA communication via MGT modules, clock drifts can
result in additional latencies. Refer to Implementing Inter-FPGA Communication
via MGT Modules (FPGA Programming Blockset Guide ).
Data type: UFix_64_0
Data width: 1
Data New Indicates whether a new data value was received by the MGT module.
Data type: UFix_1_0
Data width: 1
If the MGT module contains a new value, the flag changes from 0 to 1 for one
clock cycle:
§ 0: No new data available.
§ 1: New data available.
1) Latency between sender and receiver via an optical loopback.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping The MGT communication bus uses the MPO connector of the
FPGA Base Board.
The order number of the required SCALEXIO MGT adapters are as follows:
§ DS6601_MGT1 for the DS6601 FPGA Base Board.
§ DS6602_MGT1 for the DS6602 FPGA Base Board.

Aurora 64b66b In settings Only common dialog settings. Refer to Common settings on page 451.

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Aurora 64b66b 128 Bit In Purpose To read 128-bit data values from an MGT communication channel
description using the Aurora 64b66b link-layer protocol.

Used communication protocol setting The I/O function uses the Aurora
64B/66B protocol with the following settings:
§ Transceiver: GTH
§ Line Rate: 10.3125 Gbps
§ Dataflow Mode: Duplex
§ Interface: Framing
§ Flow Control: NFC
§ USER K: off
§ Little Endian Support: off
§ CRC: off
For more information on the protocol, refer to https://docs.xilinx.com/r/en-
US/pg074-aurora-64b66b.

Block display If you select an Aurora 64b66b 128 Bit In channel from
the channel list, the block display changes. The inport Sim Data is displayed
optionally.

I/O characteristics The following table describes the ports of the block for
the MGT module.

Port Description
Input
Ready Specifies that the communication channel is ready to read new data. Use this port
to prevent a data overflow.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The communication channel is not ready.
§ 1: New data can be read.
Sim Data Simulates a data exchange via the MGT communication bus including floating-
point to fixed-point data conversion. The converting can lead to inaccuracies.
Available only if the Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Output
Data Reads a 128-bit data value from the MGT communication bus.
User data transfer rate: Max. 10.3125 Gbit/s, limited by the MGT module.

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Port Description
MGT latency1):
§ With maximum data rate: Max. 6.272 µs, typ. 6.192 µs
The latency increases, because the TX-FIFO buffer becomes full when the data
stream fills the buffer with 16 Gbit/s (128 bits at 125 MHz).
§ Single words: Max. 472 ns, typ. 384 ns
If you implement inter-FPGA communication via MGT modules, clock drifts can
result in additional latencies. Refer to Implementing Inter-FPGA Communication
via MGT Modules (FPGA Programming Blockset Guide ).
Data type: UFix_128_0
Data width: 1
Data New Indicates whether a new data value was received by the MGT module.
Data type: UFix_1_0
Data width: 1
If the MGT module contains a new value, the flag changes from 0 to 1 for one
clock cycle:
§ 0: No new data available.
§ 1: New data available.
1) Latency between sender and receiver via an optical loopback.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping The MGT communication bus uses the MPO connector of the
FPGA Base Board.
The order number of the required SCALEXIO MGT adapters are as follows:
§ DS6601_MGT1 for the DS6601 FPGA Base Board.
§ DS6602_MGT1 for the DS6602 FPGA Base Board.

Aurora 64b66b 128 Bit In Only common dialog settings. Refer to Common settings on page 451.
settings

MGT In description Purpose To provide the information about the connection between the GTH
transceivers and the MGT module and to specify the reference clock frequency.
The information is required for customer-specific protocol blocks that configure
the GTH transceivers. A GTH transceiver is a configurable transceiver of the AMD
UltraScale FPGA architecture.

Block display If you select an MGT In channel from the channel list, the block
display changes.

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I/O characteristics The following table describes the ports of the block for
the MGT module.

Port Description
Output
CLK_P Provides the MGT reference clock frequency.
CLK_N The ports represent the differential signal of an internal clock. The ports must be
connected to a block that provides the configuration for the GTH transceivers.
The reference frequency is specified on the Parameters page.
Data type: UFix_1_0
Data width: 1
RX_P Reads the raw data from the MGT module.
RX_N The ports represent the differential output signals of the MGT module. The ports
must be connected to a block that provides the configurations for the GTH
transceiver.
Data type: UFix_4_0
Each bit represents the output of one MGT channel.
Data width: 1
Update rate: Clock frequency of the GTH transceivers.

Multiple clock domain support This block can be used in a user clock
domain to be synchronous to the MGT transceivers, for example. Refer to
Using Multiple Clock Domains for FPGA Modeling (FPGA Programming Blockset
Guide ).

I/O mapping The MGT communication bus uses the MPO connector of the
FPGA Base Board.

Demo model For implementing an MGT communication with a customized

protocol, refer to Modeling MGT Communication Using a Customized Protocol
(FPGA Programming Blockset Guide ).

MGT In settings The Parameters page provides the following dialog setting:

MGT reference clock frequency Lets you specify the reference clock
frequency that is used to generate the MGT clock frequency.
The reference clock frequency depends on the protocol type, transfer rate, and
internal scaling factors. In many cases, the reference clock frequency for the
MGT module of the FPGA base board is 156.25 MHz.
For more information, refer to Modeling MGT Communication Using a
Customized Protocol (FPGA Programming Blockset Guide ).

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MGT In Opto Ready Purpose To provide status information on the connection.

description
Block display If you select an MGT In Opto Ready channel from the channel
list, the block display changes.

I/O characteristics The following table describes the ports of the block for
the MGT module.

Port Description
Output
Opto_Ready Indicates whether the MGT module is ready for data exchange. The port changes
to 1 during the initialization phase, i.e. before the CN APP Status block changes
from stop to running.
Data type: UFix_1_0
Data width: 1
If the MGT module is ready, the flag changes from 0 to 1:
§ 0: The MGT module is not ready.
§ 1: The MGT module is ready.
Update rate: 125 MHz

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping The MGT communication bus uses the MPO connector of the
FPGA Base Board.
The order number of the required SCALEXIO MGT adapters are as follows:
§ DS6601_MGT1 for the DS6601 FPGA Base Board.
§ DS6602_MGT1 for the DS6602 FPGA Base Board.

Demo model For implementing an MGT communication with a customized

protocol, refer to Modeling MGT Communication Using a Customized Protocol
(FPGA Programming Blockset Guide ).

MGT In Opto Ready settings None

Related topics Basics

Modeling Inter-FPGA Communication via MGT Modules (FPGA Programming

Blockset Guide )
Modeling MGT Communication Using a Customized Protocol (FPGA Programming
Blockset Guide )

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Scaling Page (FPGA_IO_READ_BL)

Description The Scaling page is empty because the I/O functions of this framework do not
support FPGA scaling.

Frameworks with scaling The frameworks of the I/O modules support FPGA scaling:
support § DS2655M1 I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 350
§ Scaling Page (FPGA_IO_WRITE_BL) on page 363
§ DS2655M2 Digital I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 377
§ Scaling Page (FPGA_IO_WRITE_BL) on page 397
§ DS6651 Multi-I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 413
§ Scaling Page (FPGA_IO_WRITE_BL) on page 445

Related topics Basics

Basics on FPGA Test Access and Scaling (FPGA Programming Blockset Guide )

FPGA_IO_WRITE_BL (MGT Out Settings)

Purpose To configure write access to the MGT communication bus when using the
DS660X_MGT framework.

Where to go from here Information in this section

Parameters Page (FPGA_IO_WRITE_BL).................................................. 458

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_WRITE_BL)........................................................ 463

The Scaling page is empty because the I/O functions of this framework
do not support FPGA scaling.

Information in other sections

Unit Page (FPGA_IO_WRITE_BL)............................................................... 60

To specify the I/O type and channel to be used for write access.

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Parameters Page (FPGA_IO_WRITE_BL)

Purpose To specify relevant settings for the selected I/O function.

Description The framework provides the I/O type MGT, which you can select on the Unit
page of the block. The number of the available physical connections determines
the I/O functions that you can select:
§ Aurora 64b66b Out 1 … 4
§ Aurora 64b66b 128 Bit Out 1 … 4
§ MGT Out

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_IO_WRITE_BL.

Enable simulation port Lets you enable an outport for offline simulation
data. The Sim Data outport is added to the block to connect it to any Simulink
signal used for simulation.

Aurora 64b66b Out Purpose To write 64-bit data values to an MGT communication channel using
description the Aurora 64b66b link-layer protocol.

Used communication protocol setting The I/O function uses the Aurora
64B/66B protocol with the following settings:
§ Transceiver: GTH
§ Line Rate: 10.3125 Gbps
§ Dataflow Mode: Duplex
§ Interface: Framing
§ Flow Control: NFC
§ USER K: off
§ Little Endian Support: off
§ CRC: off
For more information on the protocol, refer to https://docs.xilinx.com/r/en-
US/pg074-aurora-64b66b.

Block display If you select an Aurora 64b66b Out channel from the channel
list, the block display changes. The outport Sim Data is displayed optionally.

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I/O characteristics The following table describes the ports of the block for
the MGT module:

Port Description
Input
Data Writes a 64-bit data value to the MGT communication bus.
User data transfer rate: Max. 8 Gbit/s (125 MHz FPGA clock, 64 bits)
MGT latency1):
§ With maximum data rate: 456 ns
§ Single words: Max. 472 ns, typ. 384 ns
If you implement inter-FPGA communication via MGT modules, clock drifts can
result in additional latencies. Refer to Implementing Inter-FPGA Communication
via MGT Modules (FPGA Programming Blockset Guide ).
Data type: UFix_64_0
Data width: 1
Enable Enables the write access to the MGT communication bus.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: No write access.
§ 1: The Data port value of the current clock cycle is written on the MGT
communication bus.
Output
Ready Outputs a flag that indicates that the MGT module is ready to write new data on
the MGT communication bus.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The MGT channel is busy.
§ 1: New data values can be written to the MGT communication bus.
Sim Data Simulates a data exchange via the MGT communication bus including fixed-point
to floating-point data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
1)
Latency between sender and receiver via an optical loopback.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping The MGT communication bus uses the MPO connector of the
FPGA Base Board.
The order number of the required SCALEXIO MGT adapters are as follows:
§ DS6601_MGT1 for the DS6601 FPGA Base Board.
§ DS6602_MGT1 for the DS6602 FPGA Base Board.

Aurora 64b66b Out settings Only common dialog settings. Refer to Common settings on page 458.

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Aurora 64b66b 128 Bit Out Purpose To write 128-bit data values to an MGT communication channel
description using the Aurora 64b66b link-layer protocol.

Used communication protocol setting The I/O function uses the Aurora
64B/66B protocol with the following settings:
§ Transceiver: GTH
§ Line Rate: 10.3125 Gbps
§ Dataflow Mode: Duplex
§ Interface: Framing
§ Flow Control: NFC
§ USER K: off
§ Little Endian Support: off
§ CRC: off
For more information on the protocol, refer to https://docs.xilinx.com/r/en-
US/pg074-aurora-64b66b.

Block display If you select an MGT Out channel from the channel list, the
block display changes. The outport Sim Data is displayed optionally.

I/O characteristics The following table describes the ports of the block for
the MGT module:

Port Description
Input
Data Writes a 128-bit data value to the MGT communication bus.
User data transfer rate: Max. 10.3125 Gbit/s, limited by the MGT module.
MGT latency1):
§ With maximum data rate: Max. 6.272 µs, typ. 6.192 µs
The latency increases, because the TX-FIFO buffer becomes full when the data
stream fills the buffer with 16 Gbit/s (128 bits at 125 MHz).
§ Single words: Max. 472 ns, typ. 384 ns
If you implement inter-FPGA communication via MGT modules, clock drifts can
result in additional latencies. Refer to Implementing Inter-FPGA Communication
via MGT Modules (FPGA Programming Blockset Guide ).
Data type: UFix_128_0
Data width: 1

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Port Description
Enable Enables the write access to the MGT communication bus.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: No write access.
§ 1: The Data port value of the current clock cycle is written on the MGT
communication bus.
Output
Ready Outputs a flag that indicates that the MGT module is ready to write new data on
the MGT communication bus.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: The MGT channel is busy.
§ 1: New data values can be written to the MGT communication bus.
Sim Data Simulates a data exchange via the MGT communication bus including fixed-point
to floating-point data conversion. The converting can lead to inaccuracies.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
1) Latency between sender and receiver via an optical loopback.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping The MGT communication bus uses the MPO connector of the
FPGA Base Board.
The order number of the required SCALEXIO MGT adapters are as follows:
§ DS6601_MGT1 for the DS6601 FPGA Base Board.
§ DS6602_MGT1 for the DS6602 FPGA Base Board.

Aurora 64b66b 128 Bit Out Only common dialog settings. Refer to Common settings on page 458.
settings

MGT Out description Purpose To provide the information about the connection between the GTH
transceivers and the MGT module. The information is required for customer-
specific protocol blocks that configure the GTH transceivers. A GTH transceiver is
a configurable transceiver of the AMD UltraScale FPGA architecture.

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Block display If you select an MGT Out channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block for
the MGT module:

Port Description
Input
TX_P Writes data to the MGT module.
TX_N The ports represent the differential signals of the GTH transceivers that are
connected to the MGT module. The ports must be connected to a block that
provides the configuration for the GTH transceivers.
Data type: UFix_4_0
Data width: 1
Each bit represents the input for one MGT channel.
Update rate: MGT reference clock frequency
The MGT reference clock frequency parameter of the MGT In block lets you
specify the reference frequency that is used to generate the MGT clock frequency.
Refer to MGT In description on page 454.

Multiple clock domain support This block can be used in a user clock
domain to be synchronous to the MGT transceivers, for example. Refer to
Using Multiple Clock Domains for FPGA Modeling (FPGA Programming Blockset
Guide ).

I/O mapping The MGT communication bus uses the MPO connector of the
FPGA Base Board.
The order number of the required SCALEXIO MGT adapters are as follows:
§ DS6601_MGT1 for the DS6601 FPGA Base Board.
§ DS6602_MGT1 for the DS6602 FPGA Base Board.

Demo model For implementing an MGT communication with a customized

protocol, refer to Modeling MGT Communication Using a Customized Protocol
(FPGA Programming Blockset Guide ).

MGT Out settings None

Related topics Basics

Modeling Inter-FPGA Communication via MGT Modules (FPGA Programming

Blockset Guide )
Modeling MGT Communication Using a Customized Protocol (FPGA Programming
Blockset Guide )

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Scaling Page (FPGA_IO_WRITE_BL)

Description The Scaling page is empty because the I/O functions of this framework do not
support FPGA scaling.

Frameworks with scaling The frameworks of the I/O modules support FPGA scaling:
support § DS2655M1 I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 350
§ Scaling Page (FPGA_IO_WRITE_BL) on page 363
§ DS2655M2 Digital I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 377
§ Scaling Page (FPGA_IO_WRITE_BL) on page 397
§ DS6651 Multi-I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 413
§ Scaling Page (FPGA_IO_WRITE_BL) on page 445

Related topics Basics

Basics on FPGA Test Access and Scaling (FPGA Programming Blockset Guide )

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Block Settings for the Inter-FPGA Interface Framework

Introduction The block dialogs provide hardware-specific settings after you load one of
the following frameworks together with at least one Inter-FPGA Interface
framework:
§ DS2655 (7K160) FPGA Base Board framework
§ DS2655 (7K410) FPGA Base Board framework
§ DS6601 (KU035) FPGA Base Board framework
§ DS6602 (KU15P) FPGA Base Board framework

Where to go from here Information in this section

FPGA_IO_READ_BL (Inter-FPGA Interface Settings)................................. 464

To configure read access to the inter-FPGA communication bus when
using the Inter-FPGA Interface framework.

FPGA_IO_WRITE_BL (Inter-FPGA Interface Settings)................................ 470

To configure write access to the inter-FPGA communication bus when
using the Inter-FPGA Interface framework.

FPGA_IO_READ_BL (Inter-FPGA Interface Settings)

Purpose To configure read access to the inter-FPGA communication bus when using the
Inter-FPGA Interface framework.

Where to go from here Information in this section

Parameters Page (FPGA_IO_READ_BL)................................................... 465

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_READ_BL).......................................................... 469

The Scaling page is empty because the I/O functions of this framework
do not support FPGA scaling.

Information in other sections

Unit Page (FPGA_IO_READ_BL)................................................................ 55

To specify the I/O type and channel to be used for read access.

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Parameters Page (FPGA_IO_READ_BL)

Purpose To specify relevant settings for the selected I/O function.

NOTICE

The improper assembly of inter-FPGA communication buses will

damage the FPGA boards
For inter-FPGA communication buses, special inter-FPGA communication
cables must be used. Other cables, such as the cables used for connecting
the I/O modules, will damage the FPGA boards. Furthermore, special rules
for attaching the FPGA boards must be observed to ensure proper bus
communication.
§ Use the SCLX_INT_FPGA_CAB1 inter-FPGA cables and observe the
enclosed documentation for assembling.
§ Do not connect FPGA boards via inter-FPGA cables if the FPGA boards are
connected to different processors via IOCNET.

Description The framework provides the I/O type Other_<IO module slot>, which you can
select on the Unit page of the block. The number of the available physical
connections determines the I/O functions that you can select:
§ I‑FPGA In 1 ... 8 [Mod: <1 ... 5>]

Common settings None

I‑FPGA In description Purpose To provide read access to the inter-FPGA communication bus with
bus synchronization.

Block display If you select an I‑FPGA In channel from the channel list, the
block display changes. Except for the outport Data Read, all ports are displayed
optionally.

The module number Mod: <x> depends on the used I/O module slot for inter-
FPGA communication.

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I/O characteristics The following table describes the ports of the block for
the inter‑FPGA communication channels.

Port Description
Input
Errors Reset Resets the Errors output.
The counter of the Errors outport possibly increases until the corresponding
I‑FPGA Out function starts working.
Available only if Bit mode is disabled on the Parameters page.
Data type: UFix_1_0
Data width: 1
Value range: 0 ... 1
Sim Data Read Simulates the data to be read from inter‑FPGA communication bus.
Available only if the Enable simulation Data Read port is set on the Parameters
page.
Data type: Double
Data width: 1
Value range: 0 … 227‑1
Sim Errors Simulates the error counter.
Available only if Bit mode is disabled on the Parameters page.
Output
Data Read Reads data from the inter‑FPGA communication bus. I‑FPGA In supports a
synchronous data exchange. The maximum number of 27 bits is available only
for one bus. If you have specified subbuses (up to 8), the maximum number of
bits depends on their configurations. Bits that exceed the configured bus width
are discarded.
Data type: UFix_27_0
Data width: 1
Value range: 0 … 227‑1
Data New Indicates whether new data was written to the Data Read register.
If the register contains new values, the flag changes from 0 to 1 for one clock
cycle. If the transmission failed, the error counter increases.
Available only if Bit mode is disabled on the Parameters page.
Data type: UFix_1_0
Data width: 1
§ 0: No new data available in the Data Read register. Either the transmission is
not yet finished, or the transmission failed (see Errors outport).
§ 1: New data available in the Data Read register.
Errors Provides the number of transmission errors. The counter is reset only at FPGA
application start or if it reset by the Errors Reset port. If the range is exceeded,
the counter restarts from 0.
Available only if Bit mode is disabled on the Parameters page.
Data type: UFix_32_0
Data width: 1
Value range: 0 … 232‑1

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I/O mapping No external connection to the I/O connector of the board. The
SCALEXIO FPGA base board uses its I/O module slots inside the SCALEXIO system
for inter-FPGA communication.

I‑FPGA In settings The following settings on the Parameters page are specific to the I‑FPGA In I/O
function.

Startbit Lets you specify the bit with which the transmission data starts in the
range 0 … 27.
If you have configured more than one inter‑FPGA bus, you can access a
specific subbus by specifying the related start and end bits. One bit has to be
reserved for synchronization for each configured subbus. The maximum data
width of a subbus is therefore Endbit ‑ Startbit. For more information,
refer to Overview of Inter-FPGA Communication (FPGA Programming Blockset
Guide ).

Note

If you send and receive data with the same inter-FPGA interface, you have
to consider limitations on the bit ranges for the subbuses. Refer to How
to Determine the Bit Ranges for Inter-FPGA Subbuses Between SCALEXIO
FPGA Base Boards (FPGA Programming Blockset Guide ).

Endbit Lets you specify the bit with which the transmission data ends in the
range 0 … 27.
The range of the end bit is automatically adapted to the specified start bit. The
end bit must not be less than the corresponding start bit.
If you have configured more than one inter‑FPGA bus, you can access a
specific subbus by specifying the related start and end bits. One bit has to be
reserved for synchronization for each configured subbus. The maximum data
width of a subbus is therefore Endbit ‑ Startbit. For more information,
refer to Overview of Inter-FPGA Communication (FPGA Programming Blockset
Guide ).

Note

If you send and receive data with the same inter-FPGA interface, you have
to consider limitations on the bit ranges for the subbuses. Refer to How
to Determine the Bit Ranges for Inter-FPGA Subbuses Between SCALEXIO
FPGA Base Boards (FPGA Programming Blockset Guide ).

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Expert mode Lets you enable the expert mode, where you can modify the bit
length, the clock and the filter depth.

Note

You should change these values only if you have enough experience
of configuring buses and knowledge of checking the correctness of the
configured transmission with regard to the observed signal integrity at the
applicable temperature range.
The default values for the bit length, clock, and filter depth have been
tested by dSPACE.

Bit length Displays the default bit length of 6 clock cycles.

If you have enabled Expert mode and disabled Bit mode, you can specify a bit
length in the range 3 … 128 cycles. A reference value for the bit length can
be calculated by 2 + 2 · FilterDepthinport. If FilterDepthinport is 0, the
minimum bit length is 3.

Note

You should change these values only if you have enough experience
of configuring buses and knowledge of checking the correctness of the
configured transmission with regard to the observed signal integrity at the
applicable temperature range.
The default values for the bit length, clock, and filter depth have been
tested by dSPACE.

Clock Displays the default I‑FPGA clock of 125 MHz. This value only affects
the inter‑FPGA communication and not the clock of the FPGA.
If you have enabled Expert mode and disabled Bit mode, you can specify an
I‑FPGA clock of 200 MHz or 250 MHz.

Note

You should change these values only if you have enough experience
of configuring buses and knowledge of checking the correctness of the
configured transmission with regard to the observed signal integrity at the
applicable temperature range.
The default values for the bit length, clock, and filter depth have been
tested by dSPACE.

Filter depth Displays the default filter depth of 2 clock cycles.

At a filter depth > 0, a spike filter with the specified length is applied to the
transmission to reduce transmission errors.

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If you have enabled Expert mode and disabled Bit mode, you can specify a
filter depth in the range 0 … 32 clock cycles.

Note

You should change these values only if you have enough experience
of configuring buses and knowledge of checking the correctness of the
configured transmission with regard to the observed signal integrity at the
applicable temperature range.
The default values for the bit length, clock, and filter depth have been
tested by dSPACE.

Add internal pipeline register to relax timing Lets you enable

an additional internal pipeline to relax timing especially for 250 MHz
communication if otherwise a FPGA build process were not possible.
Configurable only if the Bit mode is disabled.

Bit mode Lets you enable the bit mode to read data with a lower latency
(2 clock cycles), but the bits are not synchronous.
This setting is selectable only if you have enabled Expert mode.

Note

You should enable this mode only if you have enough experience of
configuring buses and knowledge of checking the correctness of the
configured transmission with regard to the observed signal integrity at the
applicable temperature range.

Enable simulation Data Read port Lets you enable an inport for offline
simulation data. The Sim Data Read inport is added to the block to connect it to
simulation data coming from a Simulink-based I/O environment model instead of
the inter‑FPGA communication bus.

Enable simulation Errors port Lets you enable an inport for offline
simulation data. The Sim Errors inport is added to the block to to provide the
number of simulated transmission errors.

Related topics Basics

Modeling Inter-FPGA Communication via I/O Module Slots (FPGA Programming

Blockset Guide )

Scaling Page (FPGA_IO_READ_BL)

Description The Scaling page is empty because the I/O functions of this framework do not
support FPGA scaling.

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Frameworks with scaling The frameworks of the I/O modules support FPGA scaling:
support § DS2655M1 I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 350
§ Scaling Page (FPGA_IO_WRITE_BL) on page 363
§ DS2655M2 Digital I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 377
§ Scaling Page (FPGA_IO_WRITE_BL) on page 397
§ DS6651 Multi-I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 413
§ Scaling Page (FPGA_IO_WRITE_BL) on page 445

Related topics Basics

Basics on FPGA Test Access and Scaling (FPGA Programming Blockset Guide )

FPGA_IO_WRITE_BL (Inter-FPGA Interface Settings)

Purpose To configure write access to the inter-FPGA communication bus when using the
Inter-FPGA Interface framework.

Where to go from here Information in this section

Parameters Page (FPGA_IO_WRITE_BL).................................................. 471

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_WRITE_BL)........................................................ 475

The Scaling page is empty because the I/O functions of this framework
do not support FPGA scaling.

Information in other sections

Unit Page (FPGA_IO_WRITE_BL)............................................................... 60

To specify the I/O type and channel to be used for write access.

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Parameters Page (FPGA_IO_WRITE_BL)

Purpose To specify relevant settings for the selected I/O function.

NOTICE

The improper assembly of inter-FPGA communication buses will

damage the FPGA boards
For inter-FPGA communication buses, special inter-FPGA communication
cables must be used. Other cables, such as the cables used for connecting
the I/O modules, will damage the FPGA boards. Furthermore, special rules
for attaching the FPGA boards must be observed to ensure proper bus
communication.
§ Use the SCLX_INT_FPGA_CAB1 inter-FPGA cables and observe the
enclosed documentation for assembling.
§ Do not connect FPGA boards via inter-FPGA cables if the FPGA boards are
connected to different processors via IOCNET.

Description The framework provides the I/O type Other_<IO module slot>, which you can
select on the Unit page of the block. The number of the available physical
connections determines the I/O functions that you can select:
§ I‑FPGA Out 1 ... 8 [Mod: <1 ... 5>]

Common settings None

I‑FPGA Out description Purpose To provide write access to the inter-FPGA communication bus with
bus synchronization.

Block display If you select an I‑FPGA Out channel from the channel list, the
block display changes. Except for the inport Data Write, all ports are displayed
optionally.

The module number Mod: <x> depends on the used I/O module slot for inter-
FPGA communication.

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I/O characteristics The following table describes the ports of the block for
the inter‑FPGA communication channels:

Port Description
Input
Data Write Outputs data to the inter‑FPGA communication bus. The maximum number of
bits in the data buffer depends on the number of blocks connected to the
bus and the blocks settings. Bits which exceed the configured bus width are
discarded.
Data type: UFix_27_0
Data width: 1
Value range: 0 … 227‑1
Output
Data Sent Provides the last transmitted value.
Available only if Bit mode is disabled on the Parameters page.
Data type: UFix_27_0
Data width: 1
Value range: 0 … 227‑1
Ready Indicates the clock cycle in which the data is sampled for transmission. The port is
high for one clock cycle with the periodicity of the bit length.
Available only if Bit mode is disabled on the Parameters page.
Data width: 1
Sim Data Write Simulates the data to be written to the inter‑FPGA communication bus.
Available only if Enable simulation Data Write port is set on the Parameters
page.
Data type: Double
Data width: 1

I/O mapping No external connection to the I/O connector of the board. The
SCALEXIO FPGA base board uses its I/O module slots inside the SCALEXIO system
for inter-FPGA communication.

I‑FPGA Out settings NOTICE

An incorrect configuration might damage the electrical interface.

If you configure both ends of an inter-FPGA connection bus to write on the
bus, the connection results in a short circuit. This short circuit might damage
the electrical interface of the used I/O module slots. In multiprocessor
applications, an incorrect configuration cannot be detected automatically
to beware hardware damage.
§ Make sure that the counterpart interface on the other FPGA board uses
the same Startbit and Endbit to read the data. Refer to Overview of
Inter-FPGA Communication (FPGA Programming Blockset Guide ).

The following settings on the Parameters page are specific to the I‑FPGA Out
I/O function.

Startbit Lets you specify the bit with which the transmission data starts in the
range 0 … 27.

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If you have configured more than one inter‑FPGA bus, you can access a
specific subbus by specifying the related start and end bits. One bit has to be
reserved for synchronization for each configured subbus. The maximum data
width of a subbus is therefore Endbit ‑ Startbit. For more information,
refer to Overview of Inter-FPGA Communication (FPGA Programming Blockset
Guide ).

Note

If you send and receive data with the same inter-FPGA interface, you have
to consider limitations on the bit ranges for the subbuses. Refer to How
to Determine the Bit Ranges for Inter-FPGA Subbuses Between SCALEXIO
FPGA Base Boards (FPGA Programming Blockset Guide ).

Endbit Lets you specify the bit with which the transmission data ends in the
range 0 … 27.
The range of the end bit is automatically adapted to the specified start bit. The
end bit must not be less than the corresponding start bit.
If you have configured more than one inter‑FPGA bus, you can access a
specific subbus by specifying the related start and end bits. One bit has to be
reserved for synchronization for each configured subbus. The maximum data
width of a subbus is therefore Endbit ‑ Startbit. For more information,
refer to Overview of Inter-FPGA Communication (FPGA Programming Blockset
Guide ).

Note

If you send and receive data with the same inter-FPGA interface, you have
to consider limitations on the bit ranges for the subbuses. Refer to How
to Determine the Bit Ranges for Inter-FPGA Subbuses Between SCALEXIO
FPGA Base Boards (FPGA Programming Blockset Guide ).

Expert mode Lets you enable the expert mode, where you can modify the bit
length, the clock and the filter depth.

Note

You should change these values only if you have enough experience
of configuring buses and knowledge of checking the correctness of the
configured transmission with regard to the observed signal integrity at the
applicable temperature range.
The default values for the bit length, clock, and filter depth have been
tested by dSPACE.

Bit length Displays the default bit length of 6 clock cycles.

If you have enabled Expert mode and disabled Bit mode, you can specify a bit
length in the range 3 … 128 cycles. A reference value for the bit length can
be calculated by 2 + 2 · FilterDepthinport. If FilterDepthinport is 0, the
minimum bit length is 3.

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Note

You should change these values only if you have enough experience
of configuring buses and knowledge of checking the correctness of the
configured transmission with regard to the observed signal integrity at the
applicable temperature range.
The default values for the bit length, clock, and filter depth have been
tested by dSPACE.

Clock Displays the default I‑FPGA clock of 125 MHz. This value only affects
the inter‑FPGA communication and not the clock of the FPGA.
If you have enabled Expert mode and disabled Bit mode, you can specify an
I‑FPGA clock of 200 MHz or 250 MHz.

Note

You should change these values only if you have enough experience
of configuring buses and knowledge of checking the correctness of the
configured transmission with regard to the observed signal integrity at the
applicable temperature range.
The default values for the bit length, clock, and filter depth have been
tested by dSPACE.

Bit mode Lets you enable the bit mode to write data with a lower latency
(2 clock cycles), but the bits are not synchronous.
This setting is selectable only if you have enabled Expert mode.

Note

You should enable this mode only if you have enough experience of
configuring buses and knowledge of checking the correctness of the
configured transmission with regard to the observed signal integrity at the
applicable temperature range.

Enable simulation Data Write port The Sim Data Write simulation port is
available in the block only if you enable it.

Related topics Basics

Modeling Inter-FPGA Communication via I/O Module Slots (FPGA Programming

Blockset Guide )

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Scaling Page (FPGA_IO_WRITE_BL)

Description The Scaling page is empty because the I/O functions of this framework do not
support FPGA scaling.

Frameworks with scaling The frameworks of the I/O modules support FPGA scaling:
support § DS2655M1 I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 350
§ Scaling Page (FPGA_IO_WRITE_BL) on page 363
§ DS2655M2 Digital I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 377
§ Scaling Page (FPGA_IO_WRITE_BL) on page 397
§ DS6651 Multi-I/O Module
§ Scaling Page (FPGA_IO_READ_BL) on page 413
§ Scaling Page (FPGA_IO_WRITE_BL) on page 445

Related topics Basics

Basics on FPGA Test Access and Scaling (FPGA Programming Blockset Guide )

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Block Settings for the MicroAutoBox II Frameworks

Where to go from here Information in this section

Block Settings for the FPGA1401Tp1 with Multi-I/O Module

Frameworks........................................................................................... 478
The block dialogs provide hardware-specific settings after you load a
MicroAutoBox II framework that supports the DS1552 Multi-I/O Module.

Block Settings for the FPGA1401Tp1 with Engine Control I/O

Module Framework............................................................................... 538
The block dialogs provide hardware-specific settings after you load a
MicroAutoBox II framework that supports the DS1554 Engine Control I/O
Module.

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Block Settings for the FPGA1401Tp1 with Multi-I/O Module

Frameworks
Introduction The block dialogs provide hardware-specific settings after you load one of the
following MicroAutoBox II frameworks:
§ FPGA1401Tp1 (7K325) with Multi-I/O Module (DS1552)
§ FPGA1401Tp1 (7K325) with Multi-I/O Module (DS1552B1)

Where to go from here Information in this section

FPGA_XDATA_READ_BL (FPGA1401Tp1 with Multi-I/O Module

Settings)................................................................................................ 478
To configure read access to intermodule bus data in the FPGA model.

FPGA_XDATA_WRITE_BL (FPGA1401Tp1 with Multi-I/O Module

Settings)................................................................................................ 487
To configure write access to intermodule bus data in the FPGA model.

FPGA_IO_READ_BL (FPGA1401Tp1 with Multi-I/O Module

Settings)................................................................................................ 496
To configure read access to analog and digital input signals in the FPGA
model.

FPGA_IO_WRITE_BL (FPGA1401Tp1 with Multi-I/O Module

Settings)................................................................................................ 513
To configure write access to analog and digital output signals in the
FPGA model.

FPGA_INT_BL (FPGA1401Tp1 with Multi-I/O Module Settings)............... 534

To configure the FPGA interrupt channel.

FPGA_XDATA_READ_BL (FPGA1401Tp1 with Multi-I/O

Module Settings)
Purpose To configure read access to intermodule bus data in the FPGA model after you
load one of the following frameworks:
§ FPGA1401Tp1 (7K325) with Multi-I/O Module (DS1552)
§ FPGA1401Tp1 (7K325) with Multi-I/O Module (DS1552B1)

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Where to go from here Information in this section

Parameters Page (FPGA_XDATA_READ_BL)............................................ 479

To specify the data format and specific settings for the selected access
type.

Description Page (FPGA_XDATA_READ_BL)............................................ 486

To provide detailed information about the selected access type.

Information in other sections

Common settings
Block Description (FPGA_XDATA_READ_BL)............................................. 45
To specify read access by the FPGA model to the processor model via
processor bus.

Unit Page (FPGA_XDATA_READ_BL)......................................................... 46

To specify the general configuration for the FPGA board's processor bus
read access.

Related FPGA blocks

PROC_XDATA_WRITE_BL (FPGA Programming Blockset -
Processor Interface Reference )
To write data from the processor model to the FPGA model via the
board-specific bus.

FPGA_XDATA_WRITE_BL......................................................................... 49
To implement write access to processor-bus data in the FPGA model.

FPGA_XDATA_WRITE_BL (FPGA1401Tp1 with Multi-I/O Module

Settings)................................................................................................ 487
To configure write access to intermodule bus data in the FPGA model.

Parameters Page (FPGA_XDATA_READ_BL)

Purpose To specify the data format and specific settings for the selected access type.

Description The FPGA1401Tp1 with Multi-I/O Module frameworks provide the following
access types that you can select on the Unit page of the block's dialog:
§ Register/Register64
If you select Register or Register64 as the access type, the data is read from
an intermodule bus register. 128 registers are available with a data width of
32 bits each and 128 registers with a data width of 64 bits each. The values
are transmitted element by element.

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If you want to access data from several registers simultaneously, you can group
these registers by specifying the same group identifier for them.
Ungrouped registers are automatically combined into one register group with
group ID Ungrouped to optimize data transfer. Since register groups can be
only accessed by one task, you have to explicitly group registers which are
used by different tasks.
§ Buffer/Buffer64
If you select Buffer or Buffer64 as the access type, the data is read from an
intermodule bus buffer. 32 buffers are available that provides elements with a
data width of 32 bits each and 32 buffers that provides elements with a data
width of 64 bits each. Each buffer has a variable buffer size of 1 up to 32768
elements.

There are settings that are common to both access types and settings that are
specific to each access type.

For more information, refer to Details on the access types on page 46.

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_XDATA_READ_BL block.

Binary point position (or fraction width) This setting depends on the
format selected in the Format setting.
§ signed/unsigned
The values of the Data outport are in fixed‑point format.
You can specify the binary point position of the 32‑bit value in the range
0 … 32 and the binary point position of the 64‑bit value in the range 0 … 64.
0 represents the lowest bit position, 32 or 64 the highest bit position.
§ floating‑point
The values of the Data outport are in floating‑point format. The fraction width
is displayed.

Format Lets you select the data format of the Data outport.
§ signed/unsigned
The values of the Data outport are in fixed‑point format with or without one
bit reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
64-bit fixed-point data types are converted to double. Therefore, the fixed-
point resolution of fixed-point data types is restricted to 53 bits.
§ floating‑point
The values of the Data outport are in floating‑point format.
The 32‑bit data value supports the single-precision floating‑point format with a
fraction width of 24, which complies with the IEEE 754 standard (single).
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is displayed in the Binary point position (or fraction
width) setting.

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Enable simulation port Lets you enable an inport for offline simulation data.
The Sim_Data inport is added to the block to connect it to any Simulink signal
used for simulation.

Simulation ports sample time Lets you specify the sample time of the ports
used for simulation, for example, Sim_Data. By default, the sample time is
inherited. You must only specify the sample time explicitly, if the modeling
situation inhibits to inherit the sample time, for example, if the corresponding
PROC block is part of an asynchronous task or is used for multiple access to the
same channel.

Register In description Block display If you specify the register access type, the block display
changes. The simulation ports are optionally displayed.

I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Sim_Data Simulates an intermodule bus data exchange
including floating-point to fixed-point data
conversion.
Available only if Enable simulation port is set on
the Parameters page.
Data type: Double
Data width: 1
Output
Data Outputs a 32-bit data value to be read from a
intermodule bus register. The data format depends
on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary
point position>
§ Floating‑point format
XFloat_8_24
Data New Outputs a flag that indicates the changes of the
register status. If the flag changes from 0 to 1 and
then to 0 again, the requested register contains a
new value. The flag is set to 1 only within one clock
cycle.
Data type: UFix_1_0

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Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register In settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 480.

Register group ID Lets you specify a number in the range 1 … 63 to create

register groups. All registers – 32‑bit and 64‑bit registers – which you specified
with the same group ID are read from the intermodule bus sequentially and then
provided to the FPGA application simultaneously.
Specify 0 for ungrouped read access.

Buffer In description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Sim_Data Simulates an intermodule bus data exchange including floating-point to fixed-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768
Address Specifies an element in the buffer you want to read. The block requires 3 clock
cycles to update the value of the Data outport according to the specified address.
The maximum port range depends on the specified buffer size in the Parameters
page. The valid port range depends on the number of elements currently in the
buffer (see Data Count outport). If you request data from an address that is greater
than the Data Count value, the output of the Data outport is undefined. The first
element of a buffer is addressed by 0.
Data type: UFix_16_0
Output

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Port Description
Data Outputs a 32-bit data value to be read from an intermodule bus buffer. The data
format depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Data New Outputs a flag that indicates the changes of the buffer status. If the flag changes
from 0 to 1 and then to 0 again, the requested buffer contains new values and is
ready to be read. The flag is set to 1 only within one clock cycle.
Data type: UFix_1_0
Data Count Outputs the number of elements in the current buffer.
The maximum range depends on the specified buffer size. You can use the value to
define the valid range for the Address inport of 0 … (Data Count -1).
Data type: UFix_16_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Buffer In settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 480.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.
The maximum range of the Address inport depends on the buffer size.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 32-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Register64 In description Block display If you specify the register access type, the block display
changes. The simulation ports are optionally displayed.

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I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Sim_Data Simulates an intermodule bus data exchange
including floating-point to fixed-point data
conversion.
Available only if Enable simulation port is set on
the Parameters page.
Data type: Double
Data width: 1
Output
Data Outputs a 64-bit data value to be read from an
intermodule bus register. The data format depends
on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary
point position>
64-bit fixed-point data types are converted to
double. Therefore, the fixed-point resolution of
fixed-point data types is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Data New Outputs a flag that indicates the changes of the
register status. If the flag changes from 0 to 1 and
then to 0 again, the requested register contains a
new value. The flag is set to 1 only within one clock
cycle.
Data type: UFix_1_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register64 In settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 480.

Register group ID Lets you specify a number in the range 1 … 63 to create

register groups. All registers – 32‑bit and 64‑bit registers – which you specified
with the same group ID are read from the intermodule bus sequentially and then
provided to the FPGA application simultaneously.
Specify 0 for ungrouped read access.

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Buffer64 In description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Sim_Data Simulates an intermodule bus data exchange including floating-point to fixed-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768
Address Specifies an element in the buffer you want to read. The block requires 3 clock
cycles to update the value of the Data outport according to the specified address.
The maximum port range depends on the specified buffer size in the Parameters
page. The valid port range depends on the number of elements currently in the
buffer (see Data Count outport). If you request data from an address that is greater
than the Data Count value, the output of the Data outport is undefined. The first
element of a buffer is addressed by 0.
Data type: UFix_16_0
Output
Data Outputs a 64-bit data value to be read from an intermodule bus buffer. The data
format depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double. Therefore, the fixed-point
resolution of fixed-point data types is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Data New Outputs a flag that indicates the changes of the buffer status. If the flag changes
from 0 to 1 and then to 0 again, the requested buffer contains new values and is
ready to be read. The flag is set to 1 only within one clock cycle.
Data type: UFix_1_0
Data Count Outputs the number of elements in the current buffer.
The maximum range depends on the specified buffer size. You can use the value to
define the valid range for the Address inport of 0 … (Data Count -1).
Data type: UFix_16_0

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Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Buffer64 In settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 480.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.
The maximum range of the Address inport depends on the buffer size.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Related topics References

Description Page (FPGA_XDATA_READ_BL)............................................................................. 486

FPGA_XDATA_READ_BL........................................................................................................... 44
FPGA_XDATA_READ_BL (FPGA1401Tp1 with Multi-I/O Module Settings)................................ 478

Description Page (FPGA_XDATA_READ_BL)

Purpose To provide detailed information about the selected access type.

Description The Description page provides detailed information about the access type that
you selected on the corresponding Unit page. The information is either in the
text field itself or in an external help document that you can open by clicking the
function-specific Help button on this page.

The description of the access type that is provided by the following standard
frameworks is included in this user documentation:
§ FPGA1401Tp1 (7K325) with Multi-I/O Module (DS1552)
§ FPGA1401Tp1 (7K325) with Multi-I/O Module (DS1552B1)

The descriptions of the access type of customized frameworks, installed I/O

modules, or IP modules are available as a separate documents.

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Related topics References

FPGA_XDATA_READ_BL........................................................................................................... 44
FPGA_XDATA_READ_BL (FPGA1401Tp1 with Multi-I/O Module Settings)................................ 478
Parameters Page (FPGA_XDATA_READ_BL)............................................................................. 479

FPGA_XDATA_WRITE_BL (FPGA1401Tp1 with Multi-I/O

Module Settings)
Purpose To configure write access to intermodule bus data in the FPGA model after you
load one of the following frameworks:
§ FPGA1401Tp1 (7K325) with Multi-I/O Module (DS1552)
§ FPGA1401Tp1 (7K325) with Multi-I/O Module (DS1552B1)

Where to go from here Information in this section

Parameters Page (FPGA_XDATA_WRITE_BL)........................................... 488

To specify the data format and specific settings for the selected access
type.

Description Page (FPGA_XDATA_WRITE_BL)........................................... 495

To provide detailed information about the selected access type.

Information in other sections

Common settings
Block Description (FPGA_XDATA_WRITE_BL)............................................ 50
To specify write access by the FPGA model to the processor model via
processor bus.

Unit Page (FPGA_XDATA_WRITE_BL)............................................. .......... 51

To specify the general configuration for the FPGA board's processor bus
write access.

Related FPGA blocks

PROC_XDATA_READ_BL (FPGA Programming Blockset -
Processor Interface Reference )
To read data in the processor model that comes from the FPGA model via
the board-specific bus.

FPGA_XDATA_READ_BL.......................................................................... 44
To implement read access to processor-bus data in the FPGA model.

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FPGA_XDATA_READ_BL (FPGA1401Tp1 with Multi-I/O Module

Settings)................................................................................................ 478
To configure read access to intermodule bus data in the FPGA model.

Parameters Page (FPGA_XDATA_WRITE_BL)

Purpose To specify the data format and specific settings for the selected access type.

Description The FPGA1401Tp1 with Multi-I/O Module frameworks provide the following
access types that you can select in the Unit page of the block's dialog:
§ Register/Register64
If you select Register or Register64 as the access type, the data is written to
an intermodule bus register. 128 registers are available with a data width of
32 bits each and 128 registers with a data width of 64 bits each. The values
are transmitted element by element. If you want to access data from several
registers simultaneously, you can group these registers by specifying the same
group identifier for them.
§ Buffer/Buffer64
If you select Buffer or Buffer64 as the access type, the data is written to an
intermodule bus buffer. 32 buffers are available that provides elements with a
data width of 32 bits each and 32 buffers that provides elements with a data
width of 64 bits each. Each buffer has a variable buffer size of 1 up to 32768
elements.

There are settings that are common to both access types and settings that are
specific to each access type.

For more information, refer to Details on the access types on page 51.

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_XDATA_WRITE_BL block.

Binary point position (or fraction width) This setting depends on the
format selected in the Format setting.
§ signed/unsigned
The values of the Data inport are in fixed‑point format.
You can specify the binary point position of the 32‑bit value in the range
0 … 32 and the binary point position of the 64‑bit value in the range 0 … 64.
0 represents the lowest bit position, 32 or 64 the highest bit position.
§ floating‑point
The values of the Data inport are in floating‑point format. The fraction width
is displayed.

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Format Lets you select the data format of the Data inport.
§ signed/unsigned
The values of the Data inport are in fixed‑point format with or without one bit
reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
64-bit fixed-point data types are converted to double. Therefore, the fixed-
point resolution of fixed-point data types is restricted to 53 bits.
§ floating‑point
The values of the Data inport are in floating‑point format.
The 32‑bit data value supports the single-precision floating‑point format with a
fraction width of 24, which complies with the IEEE 754 standard (single).
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is displayed in the Binary point position (or fraction
width) setting.

Enable simulation data port Lets you enable an outport for offline
simulation data. The Sim_Data outport is added to the block to connect it to
any Simulink signal used for simulation.

Simulation ports sample time Lets you specify the sample time of the ports
used for simulation, for example, Sim_Data and Sim_Status. By default, the
sample time is inherited. You must only specify the sample time explicitly, if
the modeling situation inhibits to inherit the sample time, for example, if the
corresponding PROC block is part of an asynchronous task or is used for multiple
access to the same channel.

Register Out description Block display If you specify the register access type, the block display
changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Data Specifies a 32-bit data value to be written to an intermodule bus register. The data
format depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24

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Port Description
Output
Sim_Data Simulates an intermodule bus data exchange including fixed-point to floating-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1

Note

The range can be exceeded for the Data inport. The inport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register Out settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 488.

Register group ID Lets you specify a number in the range 1 … 63 to create

register groups. All registers – 32‑bit and 64‑bit registers – which you specified
with the same group ID are sampled simultaneously in the FPGA application. The
values form therefore a consistent data group that is written to the intermodule
bus.

Buffer Out description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a 32-bit data value to be written to an intermodule bus buffer. The data
format depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24

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Port Description
Enable Specifies the current valid Data port value.
Data type: UFix_1_0
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.
Ready Explicitly specifies the buffer state as ready to send immediately, even if the buffer
is not completely filled. The data values are written to a new buffer in the following
clock cycle. While the port value is 1, the buffer switches every clock cycle. You are
therefore recommended to set the value for only one clock cycle. If the buffer is
completely filled, it is automatically switched, and the data values are stored in a
new buffer.
Data type: UFix_1_0
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready to send, even if it is not completely filled. The
buffer is switched and the data values are accessible via intermodule bus in the
following clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.
Output
Sim_Data Simulates an intermodule bus data exchange including fixed-point to floating-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768. The vector width depends on the specified buffer size.
Overflow Outputs a flag that indicates that a buffer overflow occurred. An overflow occurs if
the old buffer is not read completely before a new buffer is ready to be read.
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.
Data type: UFix_1_0
Sim_Status Outputs information about the simulated data exchange on the Sim_Data outport.
Available only if the access type is specified as Buffer and Enable simulation port
is set on the Parameters page.
Data type: UInt32
Data width: 3
§ Sim_Status[0]: Contains the number of valid elements in the Sim_Data vector.
§ Sim_Status[1]: Indicates whether the current buffer contains new or old values. It
is 1, if the buffer contains new values.
§ Sim_Status[2]: Indicates whether a buffer overflow occurred. At least one buffer
was not read and its data is lost before the currently read buffer was filled.

Buffer Out settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 488.

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Buffer size Lets you specify the size of the buffer in the range 1 … 32768.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 32-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation status port Lets you enable an outport to get status
information about the simulation data that is available when you have enabled
the simulation data port. The Sim_Status outport is added to the block.

Register64 Out description Block display If you specify the register access type, the block display
changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Data Specifies a 64-bit data value to be written to an intermodule bus register. The data
format depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double. Therefore, the fixed-point
resolution of fixed-point data types is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Output
Sim_Data Simulates an intermodule bus data exchange including fixed-point to floating-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1

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Note

The range can be exceeded for the Data inport. The inport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register64 Out settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 488.

Register group ID Lets you specify a number in the range 1 … 63 to create

register groups. All registers – 32‑bit and 64‑bit registers – which you specified
with the same group ID are sampled simultaneously in the FPGA application. The
values form therefore a consistent data group that is written to the intermodule
bus.

Buffer64 Out description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a 64-bit data value to be written to an intermodule bus buffer. The data
format depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double. Therefore, the fixed-point
resolution of fixed-point data types is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Enable Specifies the current valid Data port value.
Data type: UFix_1_0
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.
Ready Explicitly specifies the buffer state as ready to send immediately, even if the buffer
is not completely filled. The data values are written to a new buffer in the following

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Port Description
clock cycle. While the port value is 1, the buffer switches every clock cycle. You are
therefore recommended to set the value for only one clock cycle. If the buffer is
completely filled, it is automatically switched, and the data values are stored in a
new buffer.
Data type: UFix_1_0
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready o send, even if it is not completely filled. The
buffer is switched and the data values are accessible via intermodule bus in the
following clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.
Output
Sim_Data Simulates an intermodule bus data exchange including fixed-point to floating-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768. The vector width depends on the specified buffer size.
Overflow Outputs a flag that indicates that a buffer overflow occurred. An overflow occurs if
the old buffer is not read completely before a new buffer is ready to be read.
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.
Data type: UFix_1_0
Sim_Status Outputs information about the simulated data exchange on the Sim_Data outport.
Available only if the access type is specified as Buffer and Enable simulation port
is set on the Parameters page.
Data type: UInt32
Data width: 3
§ Sim_Status[0]: Contains the number of valid elements in the Sim_Data vector.
§ Sim_Status[1]: Indicates whether the current buffer contains new or old values. It
is 1 if the buffer contains new values.
§ Sim_Status[2]: Indicates whether a buffer overflow occurred. At least one buffer
was not read and its data was lost before the currently read buffer was filled.

Buffer64 Out settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 488.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64 bits in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

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Enable simulation status port Lets you enable an outport to get status
information about the simulation data that is available when you have enabled
the simulation data port. The Sim_Status outport is added to the block.

Related topics References

Description Page (FPGA_XDATA_WRITE_BL)............................................................................ 495

FPGA_XDATA_WRITE_BL.......................................................................................................... 49
FPGA_XDATA_WRITE_BL (FPGA1401Tp1 with Multi-I/O Module Settings)............................... 487

Description Page (FPGA_XDATA_WRITE_BL)

Purpose To provide detailed information about the selected access type.

Description The Description page provides detailed information about the access type that
you selected on the corresponding Unit page. The information is either in the
text field itself or in an external help document that you can open by clicking the
function-specific Help button on this page.

The description of the access type that is provided by the following standard
frameworks is included in this user documentation:
§ FPGA1401Tp1 (7K325) with Multi-I/O Module (DS1552)
§ FPGA1401Tp1 (7K325) with Multi-I/O Module (DS1552B1)

The descriptions of the access type of customized frameworks, installed I/O

modules, or IP modules are available as a separate documents.

Related topics References

FPGA_XDATA_WRITE_BL.......................................................................................................... 49
FPGA_XDATA_WRITE_BL (FPGA1401Tp1 with Multi-I/O Module Settings)............................... 487
Parameters Page (FPGA_XDATA_WRITE_BL)............................................................................ 488

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FPGA_IO_READ_BL (FPGA1401Tp1 with Multi-I/O Module

Settings)
Purpose To configure read access to analog and digital input signals in the FPGA model
after you load one of the following frameworks:
§ FPGA1401Tp1 (7K325) with Multi-I/O Module (DS1552)
§ FPGA1401Tp1 (7K325) with Multi-I/O Module (DS1552B1)

Where to go from here Information in this section

Parameters Page (FPGA_IO_READ_BL)................................................... 496

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_READ_BL).......................................................... 509

To specify the inverting, scaling, and saturation settings for the selected
I/O function.

Description Page (FPGA_IO_READ_BL)................................................... 512

To provide detailed information about the selected I/O function.

Information in other sections

Common settings
Block Description (FPGA_IO_READ_BL).................................................... 54
To implement read access to a physical input channel in the FPGA model.

Unit Page (FPGA_IO_READ_BL)................................................................ 55

To specify the I/O type and channel to be used for read access.

Related FPGA blocks

FPGA_IO_WRITE_BL................................................................................. 58
To provide write access to an external device via a physical output
channel.

FPGA_IO_WRITE_BL (FPGA1401Tp1 with Multi-I/O Module

Settings)................................................................................................ 513
To configure write access to analog and digital output signals in the
FPGA model.

Parameters Page (FPGA_IO_READ_BL)

Purpose To specify relevant settings for the selected I/O function.

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Description The framework provides different I/O types, which you can select on the Unit
page of the block. The number of the available physical connections on the
DS1552 or DS1552B1 Multi-I/O Module determines the I/O functions that you
can select:
§ ADC 1 (Type A) … ADC 8 (Type A)
§ ADC 1 (Type B) … ADC 16 (Type B)
§ Digital Crank/Cam Sensor 1 ... Digital Crank/Cam Sensor 3
To provide bit-wise read access to digital camshaft and crankshaft sensors.
Each channel is 1 bit wide.
§ Digital In 1 (Type A) … Digital In 16 (Type A)
§ Digital In 1 (Type B) … Digital In 8 (Type B)
§ Inductive Zero Voltage Detector
To provide read access to an inductive zero voltage detector. If a zero crossing
from positive to negative is detected, the output signal is 1 for 1 clock cycle.
§ Status In
§ Temperature
To provide read access to the FPGA's die temperature.

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_IO_READ_BL block, except
for the Status In and Temperature function.

Enable simulation port Lets you enable an inport for offline simulation data.
The Sim_Data inport is added to the block to connect it to simulation data
coming from a Simulink-based I/O environment model.

ADC (Type A) description Block display If you select an ADC (Type A) channel from the channel list, the
block display changes. The simulation ports are displayed optionally.

I/O characteristics The scaling between the analog input voltage and the
output of the block is:

Multi I/O Module Input Voltage Range Simulink Output

DS1552 0 V ... +5 V The output port range is: 0 … +65535
DS1552B1 -10 V ... +10 V The output port range is: 0 … +65535

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The following table describes the ports of the block for analog input channels:

Port Description
Input
Sim_Data Simulates an input signal in the same range as that specified for the real input
signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Input voltage range (DS1552): 0 V … +5 V
Input voltage range (DS1552B1): -10 V ... +10 V
Data_soc Triggers the sampling of the A/D converter. When the value is set to 1 for at least
one clock cycle, the ADC starts the conversion. The port allows a precise definition
of the starting point of ADC sampling. The Data_eoc outport signals the end of the
conversion process.
Setting this value permanently to 1 results in continuous sampling.
Data type: UFix_1_0
Range: 0 or 1
Output
Data Outputs the current results of the A/D conversions on the current channel.
Data type: UFix_16_0
Range: 0 … +65535
Update rate: 1 Msps
Data_eoc Outputs an end of conversion signal if the conversion result is available. If the flag
changes from 0 to 1, the ADC data contains a new value. The flag is set to 1 for
only one clock cycle.
Data type: UFix_1_0
Range: 0 or 1

If the hardware input signal or the value of the Sim_Data inport exceeds
the specified input voltage range, Data outport is saturated to minimum or
maximum range value.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping The following I/O mapping is relevant if you use one of the
FPGA1401Tp1 with Multi-I/O Module frameworks. The signals are available at
the DS1514 ZIF I/O connector.

Outport Channel Connector Pin Signal

Data 1 X3 AnalogIn+ ch 1
X4 AnalogIn- ch 11)
2 W3 AnalogIn+ ch 2
W4 AnalogIn- ch 21)
3 V3 AnalogIn+ ch 3
V4 AnalogIn- ch 31)
4 U3 AnalogIn+ ch 4
U4 AnalogIn- ch 41)

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Outport Channel Connector Pin Signal

5 H3 AnalogIn+ ch 5
H4 AnalogIn- ch 51)
6 G3 AnalogIn+ ch 6
G4 AnalogIn- ch 61)
7 F3 AnalogIn+ ch 7
F4 AnalogIn- ch 71)
8 E3 AnalogIn+ ch 8
E4 AnalogIn- ch 81)
1) The negative input line of the ADC channel is connected to GND. To get optimum
analog performance, follow the instructions in Connecting Sensor Ground Lines to
MicroAutoBox II (MicroAutoBox II Hardware Installation and Configuration Guide )
for connecting the analog channels to GND.

ADC (Type A) settings Only common dialog settings. Refer to Common settings on page 497.

ADC (Type B) description Block display If you select an ADC (Type B) channel from the channel list, the
block display changes. The simulation ports are displayed optionally.

I/O characteristics The scaling between the analog input voltage and the
output of the block is:

Input Voltage Range Simulink Output

–10 V ... +10 V The output port range is: –32768 … +32767

The following table describes the ports of the block for analog input channels:

Port Description
Input
Sim_Data Simulates an input signal in the same range as that specified for the real input
signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Input voltage range: -10 V ... +10 V
Output
Data Outputs the current results of the A/D conversions on the current channel.
Data type: Fix_16_0
Range: -32768 … +32767
Update rate: 0.2 Msps

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If the hardware input signal or the value of the Sim_Data inport exceeds
the specified input voltage range, Data outport is saturated to minimum or
maximum range value.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping The following I/O mapping is relevant if you use one of the
FPGA1401Tp1 with Multi-I/O Module frameworks. The signals are available at
the DS1514 ZIF I/O connector.

Outport Channel Connector Pin Signal

Data 1 b2 AnalogIn ch 1
2 a2 AnalogIn ch 2
3 Z2 AnalogIn ch 3
4 Y2 AnalogIn ch 4
5 X2 AnalogIn ch 5
6 W2 AnalogIn ch 6
7 V2 AnalogIn ch 7
8 U2 AnalogIn ch 8
9 M2 AnalogIn ch 9
10 L2 AnalogIn ch 10
11 K2 AnalogIn ch 11
12 J2 AnalogIn ch 12
13 H2 AnalogIn ch 13
14 G2 AnalogIn ch 14
15 F2 AnalogIn ch 15
16 E2 AnalogIn ch 16

ADC (Type B) settings Only common dialog settings. Refer to Common settings on page 497.

Digital Crank/Cam Sensor Block display If you select a Digital Crank/Cam Sensor channel from the
description channel list, the block display changes. The simulation ports are displayed
optionally.

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I/O characteristics The following table describes the ports of the block for
crank/cam input channels:

Port Description
Input
Sim_Data Simulates an input signal in the same range as that specified for the real input
signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Input voltage range: -40 V ... +40 V
Output
Data Outputs the status of the crank/cam sensor.
Data type: UFix_1_0
§ 0: The input signal is lower than the Low threshold voltage parameter.
§ 1: The input signal is higher than the High threshold voltage parameter.
Update rate: FPGA clock frequency

If the hardware input signal or the value of the Sim_Data inport exceeds the
specified input range, Data outport is saturated to minimum or maximum range
value.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use one of the
FPGA1401Tp1 with Multi-I/O Module frameworks. The signals are available at
the DS1514 ZIF I/O connector.

Outport Channel Connector Pin Signal

Data 1 R3 CrankCam+ ch 1
R4 CrankCam– ch 1
2 B3 CrankCam+ ch 2
B4 CrankCam– ch 2
3 A3 CrankCam+ ch 3
A4 CrankCam– ch 3

Digital Crank/Cam Sensor The following settings on the Parameters page are specific to the Digital
settings Crank/Cam Sensor I/O function. For common dialog settings, refer to Common
settings on page 497.

Low threshold voltage (-40000 mV ... +40000 mV) Lets you set the low
threshold level for the selected digital input channel. Below this level a logical 0

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is detected, above this level a logical 1 is detected, if the high threshold voltage
was crossed before.

High threshold voltage (-40000 mV ... +40000 mV) Lets you set the high
threshold level for the selected digital input channel. The logical 1 is output, if
this level is crossed and stays 1 until the signal falls below the low threshold level.

Digital In (Type A) description Block display If you select a Digital In (Type A) channel from the channel list,
the block display changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Input
Sim_Data Simulates an input signal in the same range specified for the real input signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Threshold level:
§ 3.6 V for low-high transition
§ 1.2 V for high-low transition
Output
Data Outputs the current results of digital input channel.
Data type: UFix_1_0
§ 0: Input voltage of the channel is below the threshold voltage of a high-low
transition.
§ 1: Input voltage of the channel is higher than or equal to the threshold voltage of
a low-high transition.
Update rate: FPGA clock frequency

Note

The frequency that can be detected is much smaller than the update rate. For
information on the electrical characteristics of the DS1552 Multi-I/O Module,
refer to Digital Inputs (MicroAutoBox II Hardware Reference ).

If the hardware signal or the value of the Sim_Data inport exceeds the minimum
or maximum threshold voltage, it is saturated to the corresponding minimum or
maximum value.

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Note

Asynchronous input data might lead to metastable register states because

input data is synchronized only by a single register stage. Further
synchronization techniques might be necessary.

Note

If you use the same digital channel for the input and the output, the I/O
driver is internally set to InOut mode. As a consequence, the maximum
input voltage for the digital input channel is equal to the specified high
supply, and the applicable threshold voltage is lower than the specified high
supply.
To use the maximum input voltage range, you have to use a digital channel
only as the input.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use one of the
FPGA1401Tp1 with Multi-I/O Module frameworks. The signals are available at
the DS1514 ZIF I/O connector.

Outport Channel Connector Pin Signal

Data 1 V5 DigIn ch 1
2 U5 DigIn ch 2
3 U6 DigIn ch 3
4 T2 DigIn ch 4
5 T3 DigIn ch 5
6 T4 DigIn ch 6
7 T5 DigIn ch 7
8 T6 DigIn ch 8
9 S2 DigIn ch 9
10 S3 DigIn ch 10
11 S5 DigIn ch 11
12 R2 DigIn ch 12
13 R5 DigIn ch 13
14 R6 DigIn ch 14
15 P5 DigIn ch 15
16 P6 DigIn ch 16

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Digital In (Type A) settings Only common dialog settings. Refer to Common settings on page 497.

Digital In (Type B) description Block display If you select a Digital In (Type B) channel from the channel list,
the block display changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Input
Sim_Data Simulates an input signal in the same range specified for the real input signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Threshold level: 1 V ... 7.5 V (in steps of 0.1 V)
Output
Data Outputs the current results of digital input channel.
Data type: UFix_1_0
§ 0: Input voltage of the channel is below the specified threshold voltage.
§ 1: Input voltage of the channel is higher than or equal to the specified threshold
voltage.
Update rate: FPGA clock frequency

Note

The frequency that can be detected is much smaller than the update rate. For
information on the electrical characteristics of the DS1552 Multi-I/O Module,
refer to Digital I/O (Bidirectional) (MicroAutoBox II Hardware Reference ).

If the hardware signal or the value of the Sim_Data inport exceeds the minimum
or maximum threshold voltage, it is saturated to the corresponding minimum or
maximum value.

Note

Asynchronous input data might lead to metastable register states because

input data is synchronized only by a single register stage. Further
synchronization techniques might be necessary.

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Note

If you use the same digital channel for the input and the output, the I/O
driver is internally set to InOut mode. As a consequence, the maximum
input voltage for the digital input channel is equal to the specified high
supply, and the applicable threshold voltage is lower than the specified high
supply.
To use the maximum input voltage range, you have to use a digital channel
only as the input.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use one of the
FPGA1401Tp1 with Multi-I/O Module frameworks. The signals are available at
the DS1514 ZIF I/O connector.

Outport Channel Connector Pin Signal

Data 1 N2 DigIO ch1
2 N3 DigIO ch2
3 N4 DigIO ch3
4 N5 DigIO ch4
5 N6 DigIO ch5
6 M5 DigIO ch6
7 M6 DigIO ch7
8 L4 DigIO ch8

You can use the same digital channel for input and output signals.

Digital In (Type B) settings The following settings on the Parameters page are specific to the Digital In
(Type B) I/O function. For common dialog settings, refer to Common settings on
page 497.

Threshold voltage Lets you specify the threshold level for the current digital
channel in the range 1,000 mV … 7,500 mV in steps of 100 mV. If the input
signal is below this level, a logical 0 is detected, otherwise a logical 1.
The selected threshold voltage is also valid for the enabled simulation data
inport.

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Inductive Zero Voltage Block display If you select a Inductive Zero Voltage Detector channel from
Detector description the channel list, the block display changes. The simulation ports are displayed
optionally.

I/O characteristics The following table describes the ports of the block for
crank/cam input channels:

Port Description
Input
Sim_Data Simulates an input signal in the same range as that specified for the real input
signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Input voltage range: -40 V ... +40 V
Output
Data Detects the zero crossing points of the analog signals. If a zero crossing from
positive to negative is detected, the output signal is 1 for 1 clock cycle.
Data type: UFix_1_0
§ 0: No zero crossing.
§ 1: Zero crossing is detected.
Update rate: FPGA clock frequency

If the hardware input signal or the value of the Sim_Data inport exceeds the
specified input range, Data outport is saturated to minimum or maximum range
value.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use one of the
FPGA1401Tp1 with Multi-I/O Module frameworks. The signals are available at
the DS1514 ZIF I/O connector.

Outport Connector Pin Signal

Data P3 ZeroDetection+
P4 ZeroDetection–

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Inductive Zero Voltage Only common dialog settings. Refer to Common settings on page 497.
Detector settings

Status In description Block display If you select the Status In channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block for
initialization sequence status information:

Port Description
Output
Init Done Outputs the state of the initialization sequence that is started after programming
the FPGA.
Data type: UFix_1_0
§ 0: Initialization sequence is in progress.
§ 1: Initialization sequence has finished.

I/O mapping No external connection.

Status In settings None

Temperature Block display If you select the Temperature channel from the channel list, the
block display changes.

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I/O characteristics The following table describes the ports of the block for
the die temperature input channel:

Port Description
Input
Sim_Temp Simulates the FPGA's die temperature (internal chip temperature).
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Input temperature range: -273.15 °C ... 230.70 °C
The range can be exceeded. The values are then saturated to the minimum or
maximum values.
Output
RAW_temp Outputs the raw value of the FPGA's die temperature measurement. Use the 12
MSB bits to calculate the die temperature.
Equation for calculating the die temperature:
Temperature [°C] = (float)(Temperature[hex] &
0xFFF0) · 503.975 / 65536
- 273.15
Data type: UFix_16_0
Data width: 1
Value range: 0 ... 65536
High Outputs a flag if the FPGA's die temperature exceeds 105 °C.
To reset the flag, the die temperature must fall below 85 °C.
Data type: UFix_1_0
§ 0: Die temperature does not exceed 105 °C.
§ 1: Die temperature exceeds 105 °C.

Note

A high ambient temperature and an FPGA application with a very high

FPGA utilization and/or toggle rate increase the FPGA die temperature
(internal chip temperature). If the die temperature exceeds 105 °C, the
FPGA might work incorrectly.
You can decrease the temperature by reducing the FPGA's toggle rate (e.g.,
by using clock enable) or by reducing the utilization of the FPGA resources.
If the die temperature exceeds 125 °C, the FPGA resets itself. The reset
stays active until the die temperature falls below 85 °C and you restart
MicroAutoBox II or reload the user application.

I/O mapping No external connection.

Temperature settings Only common dialog settings. Refer to Common settings on page 497.

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Related topics References

Description Page (FPGA_IO_READ_BL).................................................................................... 512

FPGA_IO_READ_BL................................................................................................................... 54
FPGA_IO_READ_BL (FPGA1401Tp1 with Multi-I/O Module Settings)....................................... 496
Scaling Page (FPGA_IO_READ_BL)........................................................................................... 509

Scaling Page (FPGA_IO_READ_BL)

Purpose To specify the inverting, scaling, and saturation settings for the selected I/O
function.

Description You can modify the I/O signal of the selected I/O function if you select the
Enable FPGA test access and scaling parameter on the FPGA Access page
of the FPGA_SETUP_BL block dialog. The possible modifications depend on the
selected I/O function.

Common settings The following settings on the Scaling page are common to the I/O functions that
you can select on the Unit page.

Enable FPGA test access and scaling for this block Lets you disable FPGA
test access and scaling for the selected I/O function.

ADC (Type A and Type B) The following settings on the Scaling page are specific to the ADC (Type A) and
settings ADC (Type B) I/O functions.

Note

Scaling of analog I/O signals also effects the signal path:

§ If you use the parameters of the Scaling page to scale analog signals, the
data type of the Data port is set to the specified data format for scaling.
For more information, refer to How to Change the Data Type of Analog
Signals (FPGA Programming Blockset Guide ).
§ FPGA scaling of analog I/O signals might cause additional latency. If
the latency can be calculated during the modeling, analog I/O functions
display the total latency.

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Scaling format Lets you select the data format for scaling and saturation.
§ Signed/Unsigned:
The values of the parameters for scaling and saturation are in fixed‑point
format. The signed fixed-point format reserves one bit for the sign.
You can specify the number of bits and the binary point position with the
Number of bits and Binary point (fraction width) parameters.
§ Single:
The values of the parameters for scaling and saturation are 32-bit values in
the single-precision floating‑point format with a fraction width of 24, which
complies with the IEEE 754 standard (single).
§ Double:
The values of the parameters for scaling and saturation are 64-bit values in
the double-precision floating‑point format with a fraction width of 53, which
complies with the IEEE 754 standard (double).

Number of bits This setting depends on the Scaling format setting.

§ Fixed-point format:
Lets you specify the bit width of the scaling parameters and the Data port in
the range 1 ... 64.
§ Floating-point format:
Displays the bit width of the scaling parameters and the Data port.

Binary point (fraction width) This setting depends on the Scaling format
setting.
§ Fixed-point format:
Lets you specify the binary point position of the scaling parameters and the
Data port. The position 0 represents the lowest bit position
§ Floating-point format:
Displays the fraction width of the scaling parameters and the Data port.

Scaling factor Lets you specify the scaling factor. The scaling factor gains the
signal of the Data port before it is saturated or replaced via FPGA test access.
You must check whether the specified and displayed value is supported by
the specified scaling format. The value of the Scaling factor parameter will
be executed with the maximum accuracy of the specified scaling format
and saturated to the minimum and maximum values that the scaling format
supports.

Scaling offset Lets you add a signal offset after the signal of the Data port is
scaled with the scaling factor.
You must check whether the specified and displayed value is supported by
the specified scaling format. The value of the Scaling offset parameter will
be executed with the maximum accuracy of the specified scaling format
and saturated to the minimum and maximum values that the scaling format
supports.

Saturation minimum value Lets you specify the minimum value to which
the measured and scaled signal is saturated before it is output via the Data port.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation minimum

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value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

Saturation maximum value Lets you specify the maximum value to which
the measured and scaled signal is saturated before it is output via the Data port.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation maximum
value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

Multiplier latency Lets you specify the latency that is caused by the
multiplier for scaling. The multiplier is used to multiply the signal with the value
of the Scaling factor parameter.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The multiplication will be implemented without latency.
§ 1 ... 20: The multiplication will be implemented with the specified latency.
Use this value range in the exceptional case that the optimized latency cause
timing problems during the build process.

Adder latency Lets you specify the latency that is caused by the offset adder.
The offset adder is used to add the value of the Scaling offset parameter to the
signal.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The adding will be implemented without latency.
§ 1 ... 20: The adding will be implemented with the specified latency.
Use this value range in the exceptional case that the optimized latency causes
timing problems during the build process.

Digital In (Type A and Type B) The following settings on the Scaling page are specific to the Digital In
settings (Type A) and Digital In (Type B) I/O functions.

Invert polarity Lets you adapt the measured values to the electrical input
signal:
§ Disabled:
The Data port outputs the signals as measured: A low-high transition results in
a 1 and vice versa.
§ Enabled:
The output of the Data port is inverted: A low-high transition results in a 0
and vice versa.

Digital Crank/Cam Sensor The Scaling page is empty because this I/O function does not support FPGA
settings scaling to scale I/O signals.

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Inductive Zero Voltage The Scaling page is empty because this I/O function does not support FPGA
Detector scaling to scale I/O signals.

Status In The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

Temperature The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

Related topics References

Description Page (FPGA_IO_READ_BL).................................................................................... 512

FPGA_IO_READ_BL................................................................................................................... 54
FPGA_IO_READ_BL (FPGA1401Tp1 with Multi-I/O Module Settings)....................................... 496
Parameters Page (FPGA_IO_READ_BL).................................................................................... 496

Description Page (FPGA_IO_READ_BL)

Purpose To provide detailed information about the selected I/O function.

Description The Description page provides detailed information about the I/O type that you
selected on the corresponding Unit page. The information is either in the text
field itself or in an external help document that you can open by clicking the
function-specific Help button on this page.

The description of the I/O function that is provided by the following standard
frameworks is included in this user documentation:
§ FPGA1401Tp1 (7K325) with Multi-I/O Module (DS1552)
§ FPGA1401Tp1 (7K325) with Multi-I/O Module (DS1552B1)

The description of the access type of customized frameworks or mounted

piggybacks is available as a separate document.

Related topics References

FPGA_IO_READ_BL................................................................................................................... 54
FPGA_IO_READ_BL (FPGA1401Tp1 with Multi-I/O Module Settings)....................................... 496
Parameters Page (FPGA_IO_READ_BL).................................................................................... 496
Scaling Page (FPGA_IO_READ_BL)........................................................................................... 509

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FPGA_IO_WRITE_BL (FPGA1401Tp1 with Multi-I/O Module

Settings)
Purpose To configure write access to analog and digital output signals in the FPGA model
after you load one of the following frameworks:
§ FPGA1401Tp1 (7K325) with Multi-I/O Module (DS1552)
§ FPGA1401Tp1 (7K325) with Multi-I/O Module (DS1552B1)

Where to go from here Information in this section

Parameters Page (FPGA_IO_WRITE_BL).................................................. 513

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_WRITE_BL)........................................................ 531

To specify the inverting, scaling, and saturation settings for the selected
I/O function.

Description Page (FPGA_IO_WRITE_BL).................................................. 534

To provide detailed information about the selected I/O function.

Information in other sections

Common settings
Block Description (FPGA_IO_WRITE_BL)................................................... 59
To implement write access to a physical output channel in the FPGA
model.

Unit Page (FPGA_IO_WRITE_BL)............................................................... 60

To specify the I/O type and channel to be used for write access.

Related FPGA blocks

FPGA_IO_READ_BL.................................................................................. 54
To provide read access to an external device via a physical input channel.

FPGA_IO_READ_BL (FPGA1401Tp1 with Multi-I/O Module

Settings)................................................................................................ 496
To configure read access to analog and digital input signals in the FPGA
model.

Parameters Page (FPGA_IO_WRITE_BL)

Purpose To specify relevant settings for the selected I/O function.

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Description The framework provides the three I/O types Analog, Digital, and Other, which
you can select on the Unit page of the block. The number of the available
physical connections on the DS1552 Multi-I/O Module determines the I/O
functions that you can select:
§ DAC 1 … DAC 4
§ Digital Out 1 (Type A) … Digital Out 16 (Type A)
§ Digital Out 1 (Type B) … Digital Out 8 (Type B)
§ LED Out
§ Sensor Supply
§ UART 1 (RS232) … UART 2 (RS232)
§ UART 1 (RS422/485) … UART 2 (RS422/485)

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_IO_WRITE_BL block, except
for the LED Out and Sensor Supply functions.

Enable simulation port Lets you enable an outport for offline simulation
data. The Sim_Data outport is added to the block to connect it to a Simulink-
based I/O environment model.
If you have selected one of the UART functions, this setting is replaced by
function-specific simulation settings.

DAC description Block display If you have select a DAC channel from the channel list, the
block display changes. The simulation ports are displayed optionally.

I/O characteristics The scaling between the analog output voltage and the
input of the block is:

Output Voltage Range Simulink Input

0 V … +5 V The input port range is: 0 … +65535

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The following table describes the ports of the block:

Port Description
Input
Data Outputs a signal in the specified range.
Data type: UFix_16_0
Output voltage range: 0 … +65535
The range can be exceeded, and saturation is performed to a minimum or maximum
value.
Hardware update rate: 2.1 Msps
If the values are updated at a higher FPGA model rate, intermediate values are not
updated by the DAC.
Output
Sim_Data Simulates an output signal in the same range as that specified for the real output
signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Output voltage range: 0 V … +5 V

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping The following I/O mapping is relevant if you use one of the
FPGA1401Tp1 with Multi-I/O Module frameworks. The signals are available at
the DS1514 ZIF I/O connector.

Inport Channel Connector Pin Signal

Data 1 c2 AnalogOut ch 1
2 c3 AnalogOut ch 2
3 c4 AnalogOut ch 3
4 c5 AnalogOut ch 4

DAC settings Only common dialog settings. Refer to Common settings on page 514.

Digital Out (Type A) Block display If you select a Digital Out (Type A) channel from the channel
description list, the block display changes. The simulation ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Outputs a signal in the specified range.
If driven with 0, the hardware output is 0 V. If driven with 1, the hardware output is
set to the specified high supply voltage (VDRIVE).
The hardware output is only driven if the Enable port is set to 1, otherwise the
output is set to high impedance (High-Z).
Data Type: UFix_1_0
Update rate: FPGA clock frequency

Note

The frequency that can be generated is much smaller than the update rate. For
information on the electrical characteristics of the DS1552 Multi-I/O Module,
refer to Digital Outputs (MicroAutoBox II Hardware Reference ).

Enable Controls the hardware output. If set to 1, the hardware output reacts to the Data
outport, otherwise it is set to High-Z.
Data type: UFix_1_0
Output
Sim_Data Simulates an output signal in the same range as that specified for the real output
signal.
Available only if Enable simulation port is set on the Parameters page.
Output voltage: 0 V ... 45 V
Update rate: FPGA clock frequency

If the value of the Data inport exceeds the specified data width, only the lowest
bit is used.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use one of the
FPGA1401Tp1 with Multi-I/O Module frameworks. The signals are available at
the DS1514 ZIF I/O connector.

Inport Channel Connector Pin Signal

Data 1 F5 DigOut ch 1
2 E5 DigOut ch 2
3 E6 DigOut ch 3
4 D2 DigOut ch 4
5 D3 DigOut ch 5
6 D4 DigOut ch 6

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Inport Channel Connector Pin Signal

7 D5 DigOut ch 7
8 D6 DigOut ch 8
9 C2 DigOut ch 9
10 C3 DigOut ch 10
11 C5 DigOut ch 11
12 B2 DigOut ch 12
13 B5 DigOut ch 13
14 B6 DigOut ch 14
15 A5 DigOut ch 15
16 A6 DigOut ch 16

Digital Out (Type A) settings The following settings on the Parameters page are specific to the Digital Out
(Type A) I/O function. For common dialog settings, refer to Common settings on
page 514.

Simulated VDRIVE pin Lets you select the voltage for the simulated high
side switch for all digital output channels in the range 0 … 45000 mV.

Note

You can specify the simulated voltage value only globally for all digital
output channels.

Digital Out (Type B) Block display If you select a Digital Out (Type B) channel from the channel
description list, the block display changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Outputs a signal in the specified range.
If driven with 0, the hardware output is 0 V. If driven with 1, the hardware output is
3.3 V or 5 V according to the specified high supply voltage.
The hardware output is only driven if the Enable port is set to 1, otherwise the
output is set to high impedance (High-Z).
Data Type: UFix_1_0

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Port Description
Update rate: FPGA clock frequency

Note

The frequency that can be generated is smaller than the update rate. For
information on the electrical characteristics of the DS1552 Multi-I/O Module,
refer to Digital I/O (Bidirectional) (MicroAutoBox II Hardware Reference ).

Enable Controls the hardware output. If set to 1, the hardware output reacts to the Data
outport, otherwise it is set to High-Z.
Data type: UFix_1_0
Output
Sim_Data Simulates an output signal in the same range as that specified for the real output
signal.
Available only if Enable simulation port is set on the Parameters page.
Output voltage: 0 V … 3.3 V or 0 V … 5 V
Update rate: FPGA clock frequency

If the value of the Data inport exceeds the specified data width, only the lowest
bit is used.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use one of the
FPGA1401Tp1 with Multi-I/O Module frameworks. The signals are available at
the DS1514 ZIF I/O connector.

Outport Channel Connector Pin Signal

Data 1 N2 DigIO ch1
2 N3 DigIO ch2
3 N4 DigIO ch3
4 N5 DigIO ch4
5 N6 DigIO ch5
6 M5 DigIO ch6
7 M6 DigIO ch7
8 L4 DigIO ch8

You can use the same digital channel for input and output signals.

Digital Out (Type B) settings The following settings on the Parameters page are specific to the Digital Out
(Type B) I/O function. For common dialog settings, refer to Common settings on
page 514.

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High supply Lets you select the voltage for the high side switch (3.3 V or 5 V)
for all digital output channels.

Note

You can specify the high supply voltage value only globally for all digital
output channels.

LED Out description Block display If you select the LED Out channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Controls the FPGA status LED near the DS1514 ZIF I/O connector.
Data type: UFix_1_0
§ 0: LED lights up green.
§ 1: LED lights up orange.

If the value of the Data inport exceeds the specified data width, only the lowest
bit is used (=1).

I/O mapping No external connection.

LED Out settings None

Sensor Supply description Block display If you select the Sensor Supply channel from the channel list,
the block display changes.

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I/O characteristics The following table describes the ports of the block:

Port Description
Output
Sim_Data Simulates an output signal in the same range as that specified for the real output
signal.
Output voltage: 2 V … 20 V according to the specified supply voltage

I/O mapping The following I/O mapping is relevant if you use one of the
FPGA1401Tp1 with Multi-I/O Module frameworks. The signals are available at
the DS1514 ZIF I/O connector.

Outport Channel Connector Pin Signal

Sim_Data 1 b6 VS-
c6 VS+

Sensor Supply settings The following settings on the Parameters page are specific to the Sensor
Supply I/O function. For common dialog settings, refer to Common settings on
page 514.

Supply voltage Lets you enter the supply voltage a connected sensor is to be
driven with in the range 2000 mV … 20000 mV in steps of 100 mV.

UART (RS232) description Block display If you select an UART (RS232) channel from the channel list,
the block display changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Read_Enable Specifies to start receiving a value.
After three clock cycles, the value is available and can be read from the RX
FIFO buffer. The value remains valid until the next Read_Enable signal.
Before you read data from the RX FIFO buffer, you should check the
Read_Fifo_Empty signal not to be set. The Read_Fifo_Empty signal
switches one clock cycle after the RX FIFO value has been read.

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Port Description
Do not use the Read_Data_Count signal (Read_Data_Count < 0) to check
the RX FIFO buffer, because it requires one additional clock cycle to get the
count value.
You can read one value per clock cycle from the UART.
Data Type: UFix_1_0
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.
Write_Enable Specifies to start sending a value.
The Write_Data value is written to the TX FIFO buffer, from which it is
automatically send to the TX output pin of the I/O connector using the
specified UART communication settings.
Write_Enable must be set to 1 for only one clock cycle.
Before you write data to the TX FIFO buffer, you should check the
Write_Fifo_Full signal not to be set. The Write_Fifo_Full signal switches
one clock cycle after the Write_Enable signal has been set.
Do not use the Write_Data_Count signal (Write_Data_Count < 2047) to
check the TX FIFO buffer, because it requires one additional clock cycle to
get the count value.
Data type: UFix_1_0
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.
The hardware output port is driven with the values from the TX FIFO buffer.
It is synchronously running to the UART clock defined by the UART baud
rate. The hardware port has inverted voltage levels of ‑6 V (logical high)
and +6 V (logical low).
Write_Data Specifies the value to be send.
The Write_Data signal is transferred at each clock cycle with Write_Enable
set to 1.
Data type: UFix_9_0
Data width: 1
Range: 0 … 511
Range exceeding is possible. Then, only the lowest bits 5 … 9 will be used.
Because of the unsigned data type, negative values will be interpreted as
positive values and the saturation will always be towards the maximum
value.
RTS Specifies the Ready‑To‑Send (RTS) signal.
The RTS/CTS handshake is handled by the user, the RTS signal is just passed
through and adapted to the physical layer.
Data type: UFix_1_0
Data width: 1
The hardware port is synchronously running to the UART clock defined by
the UART baud rate. The hardware port has voltage levels of +6 V (active,
logical high) and ‑6 V (inactive).
Sim_RX Simulates an RX value in the RX FIFO buffer.
Available only if Enable simulation RX port is set on the Parameters page.
Data type: Double
Data width: 1

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Port Description
The signal has to be in logical format with 1 as high and 0 as low, and
not in the inverted values of the physical layer (‑12 V high, +12 V low).
The format of this serial bitstream has to correspond to the specified UART
communication settings.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.
Sim_CTS Simulates the Clear‑To‑Send (CTS) hardware signal.
Available only if Enable simulation CTS port is set on the Parameters
page.
The RTS/CTS handshake is handled by the user. The Sim_CTS signal is just
passed through to CTS.
Data type: Double
Data width: 1
Range:
§ 0: CTS inactive
§ 1: CTS active
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.
Output
Read_Data_Count Outputs the number of new entries in the RX FIFO buffer.
Two clock cycles are required to return the number of entries.
If you only want to check whether a value is available in the RX FIFO buffer,
use the Read_Fifo_Empty signal instead of this.
Data type: UFix_11_0
Data width: 1
Range: 0 … 2047
The range can be exceeded, and saturation is performed to a minimum or
maximum value.
Read_Data Outputs the last read data from the RX FIFO buffer.
The read_data is available after three clock cycles after the Read_Enable
signal. The return value is 0, if the data is read before anything has been
received by the RX hardware input.
Data type: UFix_9_0
Data width: 1
Range: 0 … 511
It is not possible to exceed the range.
The hardware input receives serial data for the UART RX FIFO buffer using
inverted voltage levels of ‑6 V (logical high) and +6 V (logical low).
Read_Fifo_Empty Outputs the status of the RX FIFO buffer.
If the status of the buffer is not empty, then you can start reading the data
using the Read_Enable signal.
The Read_Fifo_Empty signal switches one clock cycle after the FIFO value
has been read.
Do not use the Read_Data_Count signal to check the status of the buffer
(Read_Data_Count>0), because this requires one additional clock cycle
before its value is valid.
Data type: UFix_1_0

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Port Description
Data width: 1
Range:
§ 0: The RX FIFO buffer is not empty.
§ 1: The RX FIFO buffer is empty.
It is not possible to exceed the range.
CTS Outputs the state of the Clear‑To‑Send (CTS) hardware port.
RTS/CTS handshake is handled by the user. CTS is just passed through with
conversion to logical 1 and 0.
Data type: UFix_1_0
Data width: 1
Range:
§ 0: CTS inactive
§ 1: CTS active
The CTS hardware port is synchronously running to the UART clock defined
by the UART baud rate. The hardware port has voltage levels of +6 V (active,
logical high) and ‑6 V (inactive).
It is not possible to exceed the range.
Write_Data_Count Outputs the number of values in the TX FIFO buffer.
The values in the TX FIFO buffer has not been sent already.
Do not use the Write_Data_Count signal to check the status of the buffer
(Write_Data_Count<2047), because this requires two clock cycles before its
value is valid, instead of one clock cycle when using the Write_Fifo_Full
signal.
Data type: UFix_11_0
Data width: 1
Range: 0 … 2047
It is not possible to exceed the range.
Write_Fifo_Full Outputs the status of the TX FIFO buffer.
You can use the signal to check the TX FIFO buffer before you start writing
data to the buffer. The Write_Fifo_Full signal switches one clock cycle after
the Write_Enable signal has been set.
Data type: UFix_1_0
Data width: 1
Range:
§ 0: The TX FIFO buffer is not full.
§ 1: The TX FIFO buffer is full.
It is not possible to exceed the range.
Sim_TX Simulates the TX hardware signal.
Available only if Enable simulation TX port is set on the Parameters page.
The signal is in logical format and not in inverted values from the physical
layer (‑6 V high, +6 V low). The format of the serial bitstream corresponds to
the specified UART communication settings.
Data type: Double
Data width: 1

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Port Description
Range:
§ 0: Low
§ 1: High
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.
Sim_RTS Simulates the Ready‑To‑Send (RTS) hardware signal.
Available only if Enable simulation RTS port is set on the Parameters
page.
The signal is in logical format and only passed through to the RTS signal.
Data type: Double
Data width: 1
Range:
§ 0: RTS inactive
§ 1: RTS active
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use one of the
FPGA1401Tp1 with Multi-I/O Module frameworks. The signals are available at
the DS1514 ZIF I/O connector.

Inport Connector Pin Signal

UART 1 (RS232)
Write_Data a5 TX1
RTS a6 RTS1
Read_Data b5 RX1
CTS a4 CTS1
UART 2 (RS232)1)
Write_Data Z5 TX2
RTS Z6 RTS2
Read_Data Z3 RX2
CTS Z4 CTS2
1)
To use UART 2, your DS1552 has to be modified by dSPACE.

UART (RS232) settings The following settings on the Parameters page are specific to the UART
(RS232) I/O function.

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Baud rate Lets you select the baud rate in the range 50 … 1,000,000 baud
(bits per second) from the given list.

Word length Lets you select the word length in the range 5 … 9 bits. The
word length includes the number of data bits and the optional parity bit.
For example, if a message consists of 8 data bits and the parity bit, you have to
set the word length to 9.

Note

The parity bit cannot be controlled via dialog setting. You have to consider
an optional parity bit in your own model implementation.

The Write_Data and Read_Data ports handle raw bits. If you want to use
a parity bit with the Write_Data port, you have to explicitly generate it and
provide it as the last bit of the port. If you want to use a parity bit with the
Read_Data port, you have to explicitly check it and read it as the last bit of the
port.

Stop bits Lets you select the number of stop bits in the range 1, 1.5 and 2.

Enable simulation RX port Lets you enable an inport for offline simulation
data. The Sim_RX inport is added to the block to connect it to simulation data
coming from a Simulink-based I/O environment model.

Enable simulation CTS port Lets you enable an inport for offline simulation
data. The Sim_CTS inport is added to the block to connect it to simulation data
coming from a Simulink-based I/O environment model.

Enable simulation TX port Lets you enable an outport for offline simulation
data. The Sim_TX outport is added to the block to connect it to a Simulink-based
I/O environment model.

Enable simulation RTS port Lets you enable an outport for offline
simulation data. The Sim_RTS outport is added to the block to connect it to
a Simulink-based I/O environment model.

UART (RS422/485) description Block display If you select an UART (RS422/485) channel from the channel
list, the block display changes. The simulation ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block:

Port Description
Input
Read_Enable Specifies to start receiving a value.
After three clock cycles, the value is available and can be read from the RX
FIFO buffer. The value remains valid until the next Read_Enable signal.
Before you read data from the RX FIFO buffer, you should check the
Read_Fifo_Empty signal not to be set. The Read_Fifo_Empty signal
switches one clock cycle after the RX FIFO value has been read.
Do not use the Read_Data_Count signal (Read_Data_Count < 0) to check
the RX FIFO buffer, because it requires one additional clock cycle to get the
count value.
You can read one value per clock cycle from the UART.
Data Type: UFix_1_0
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.
Write_Enable Specifies to start sending a value.
The Write_Data value is written to the TX FIFO buffer, from which it is
automatically send to the TX output pin of the I/O connector using the
specified UART communication settings.
Write_Enable must be set to 1 for only one clock cycle.
Before you write data to the TX FIFO buffer, you should check the
Write_Fifo_Full signal not to be set. The Write_Fifo_Full signal switches
one clock cycle after the Write_Enable signal has been set.
Do not use the Write_Data_Count signal (Write_Data_Count < 2047) to
check the TX FIFO buffer, because it requires one additional clock cycle to get
the count value.
Data type: UFix_1_0
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.
The hardware output port is driven with the values from the TX FIFO buffer. It
is synchronously running to the UART clock defined by the UART baud rate.
The hardware port has inverted voltage levels of ‑6 V (logical high) and +6 V
(logical low).
Write_Data Specifies the value to be send.
The Write_Data signal is transferred at each clock cycle with Write_Enable
set to 1.
Data type: UFix_9_0
Data width: 1
Range: 0 … 511
Range exceeding is possible. Then, only the lowest bits 5 … 9 will be used.
Because of the unsigned data type, negative values will be interpreted as
positive values and the saturation will always be towards the maximum
value.

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Port Description
Driver_Enable Specifies to enable the output driver in the transceiver for data transmission.
If you use the UART (RS485/422) function in half-duplex mode, the output
driver must be disabled while receiving data.
Data type: UFix_1_0
Data width: 1
Sim_RX Simulates an RX value in the RX FIFO buffer.
Available only if Enable simulation RX port is set on the Parameters page.
Data type: Double
Data width: 1
The signal has to be in logical format with 1 as high and 0 as low, and
not in the inverted values of the physical layer (‑12 V high, +12 V low).
The format of this serial bitstream has to correspond to the specified UART
communication settings.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.
Output
Read_Data_Count Outputs the number of new entries in the RX FIFO buffer.
Two clock cycles are required to return the number of entries.
If you only want to check whether a value is available in the RX FIFO buffer,
use the Read_Fifo_Empty signal instead of this.
Data type: UFix_11_0
Data width: 1
Range: 0 … 2047
The range can be exceeded, and saturation is performed to a minimum or
maximum value.
Read_Data Outputs the last read data from the RX FIFO buffer.
The read_data is available after three clock cycles after the Read_Enable
signal. The return value is 0, if the data is read before anything has been
received by the RX hardware input.
Data type: UFix_9_0
Data width: 1
Range: 0 … 511
It is not possible to exceed the range.
The hardware input receives serial data for the UART RX FIFO buffer using
inverted voltage levels of ‑6 V (logical high) and +6 V (logical low).
Read_Fifo_Empty Outputs the status of the RX FIFO buffer.
If the status of the buffer is not empty, then you can start reading the data
using the Read_Enable signal.
The Read_Fifo_Empty signal switches one clock cycle after the FIFO value
has been read.
Do not use the Read_Data_Count signal to check the status of the
buffer (Read_Data_Count>0), because this requires one additional clock cycle
before its value is valid.
Data type: UFix_1_0
Data width: 1

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Port Description
Range:
§ 0: The RX FIFO buffer is not empty.
§ 1: The RX FIFO buffer is empty.
It is not possible to exceed the range.
Write_Data_Count Outputs the number of values in the TX FIFO buffer.
The values in the TX FIFO buffer has not been sent already.
Do not use the Write_Data_Count signal to check the status of the buffer
(Write_Data_Count<2047), because this requires two clock cycles before its
value is valid, instead of one clock cycle when using the Write_Fifo_Full
signal.
Data type: UFix_11_0
Data width: 1
Range: 0 … 2047
It is not possible to exceed the range.
Write_Fifo_Full Outputs the status of the TX FIFO buffer.
You can use the signal to check the RX FIFO buffer before you start writing
data to the buffer. The Write_Fifo_Full signal switches one clock cycle after
the Write_Enable signal has been set.
Data type: UFix_1_0
Data width: 1
Range:
§ 0: The TX FIFO buffer is not full.
§ 1: The TX FIFO buffer is full.
It is not possible to exceed the range.
Sim_TX Simulates the TX hardware signal.
Available only if Enable simulation TX port is set on the Parameters page.
The signal is in logical format and not in inverted values from the physical
layer (‑6 V high, +6 V low). The format of the serial bitstream corresponds to
the specified UART communication settings.
Data type: Double
Data width: 1
Range:
§ 0: Low
§ 1: High
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use one of the
FPGA1401Tp1 with Multi-I/O Module frameworks. The signals are available

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at the DS1514 ZIF I/O connector. The mapping differs when using the UART
(RS422/485) in full-duplex or half-duplex mode.
Full-duplex mode:

Inport Connector Pin Signal

UART 1 (RS422/485)
Write_Data a5 TX‑1
a6 TX+1
Read_Data b5 RX‑1
a4 RX+1
UART 2 (RS422/485)1)
Write_Data Z5 TX‑2
Z6 TX+2
Read_Data Z3 RX‑2
Z4 RX+2
1) To use UART 2, your DS1552 has to be modified by dSPACE.
Half-duplex mode:

Inport Connector Pin Signal

UART 1 (RS422/485)
Write_Data a5 BM1 (RX‑1/TX‑1)
a6 BP1 (RX+1/TX+1)
Read_Data b5 ‑1)
a4 ‑1)
UART 2 (RS422/485)2)
Write_Data Z5 BM2 (RX‑2/TX‑2)
Z6 BP2 (RX+2/TX+2)
Read_Data Z3 ‑1)
Z4 ‑1)
1)
Do not connect, TX signals are available via BM and BP signals.
2) To use UART 2, your DS1552 has to be modified by dSPACE.

UART (RS422/485) settings The following settings on the Parameters page are specific to the UART
(RS422/485) I/O function.

Baud rate Lets you select the baud rate in the range 50 … 10,000,000 baud
(bits per second) from the given list.

Word length Lets you select the word length in the range 5 … 9 bits. The
word length includes the number of data bits and the optional parity bit.

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For example, if a message consists of 8 data bits and the parity bit, you have to
set the word length to 9.

Note

The parity bit cannot be controlled via dialog setting. You have to consider
an optional parity bit in your own model implementation.

The Write_Data and Read_Data ports handle raw bits. If you want to use
a parity bit with the Write_Data port, you have to explicitly generate it and
provide it as the last bit of the port. If you want to use a parity bit with the
Read_Data port, you have to explicitly check it and read it as the last bit of the
port.

Stop bits Lets you select the number of stop bits in the range 1, 1.5 and 2.

Mode Lets you select the mode for receiving messages.

§ Full duplex mode
You can simultaneously send and receive signals on the UART channel.
§ Half duplex mode
You can send or receive signals on the UART channel, but you cannot do both
at the same time.

Termination Lets you enable an internal termination between RX‑ and RX+
and between TX‑ and TX+.

Setting Meaning
Open No termination
Terminated The RX and TX signals are terminated via an
internal 120 Ω resistor.

Enable simulation RX port Lets you enable an inport for offline simulation
data. The Sim_RX inport is added to the block to connect it to simulation data
coming from a Simulink-based I/O environment model.

Enable simulation TX port Lets you enable an outport for offline simulation
data. The Sim_TX outport is added to the block to connect it to a Simulink-based
I/O environment model.

Related topics References

Description Page (FPGA_IO_WRITE_BL)................................................................................... 534

FPGA_IO_WRITE_BL.................................................................................................................. 58
FPGA_IO_WRITE_BL (FPGA1401Tp1 with Multi-I/O Module Settings)...................................... 513
Scaling Page (FPGA_IO_WRITE_BL)......................................................................................... 531

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Scaling Page (FPGA_IO_WRITE_BL)

Purpose To specify the inverting, scaling, and saturation settings for the selected I/O
function.

Description You can modify the I/O signal of the selected I/O function if you select the
Enable FPGA test access and scaling parameter on the FPGA Access page
of the FPGA_SETUP_BL block dialog. The possible modifications depend on the
selected I/O function.

Common settings The following settings on the Scaling page are common to the I/O functions that
you can select on the Unit page.

Enable FPGA test access and scaling for this block Lets you disable FPGA
test access and scaling for the selected I/O function.

DAC settings The following settings on the Scaling page are specific to the DAC I/O function.

Note

Scaling of analog I/O signals also effects the signal path:

§ If you use the parameters of the Scaling page to scale analog signals, the
data type of the Data port is set to the specified data format for scaling.
For more information, refer to How to Change the Data Type of Analog
Signals (FPGA Programming Blockset Guide ).
§ FPGA scaling of analog I/O signals might cause additional latency. If
the latency can be calculated during the modeling, analog I/O functions
display the total latency.

Scaling format Lets you select the data format for scaling and saturation.
§ Signed/Unsigned:
The values of the parameters for scaling and saturation are in fixed‑point
format. The signed fixed-point format reserves one bit for the sign.
You can specify the number of bits and the binary point position with the
Number of bits and Binary point (fraction width) parameters.
§ Single:
The values of the parameters for scaling and saturation are 32-bit values in
the single-precision floating‑point format with a fraction width of 24, which
complies with the IEEE 754 standard (single).

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§ Double:
The values of the parameters for scaling and saturation are 64-bit values in
the double-precision floating‑point format with a fraction width of 53, which
complies with the IEEE 754 standard (double).

Number of bits This setting depends on the Scaling format setting.

§ Fixed-point format:
Lets you specify the bit width of the scaling parameters and the Data port in
the range 1 ... 64.
§ Floating-point format:
Displays the bit width of the scaling parameters and the Data port.

Binary point (fraction width) This setting depends on the Scaling format
setting.
§ Fixed-point format:
Lets you specify the binary point position of the scaling parameters and the
Data port. The position 0 represents the lowest bit position
§ Floating-point format:
Displays the fraction width of the scaling parameters and the Data port.

Scaling factor Lets you specify the scaling factor. The scaling factor gains
the signal of the Data port or the replace value (FPGA test access) before it is
saturated.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Scaling factor parameter
will be saturated to the minimum and maximum values that the scaling format
and the hardware supports.

Scaling offset Lets you add a signal offset after the signal of the Data port is
scaled with the scaling factor.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Scaling offset parameter
will be saturated to the minimum and maximum values that the scaling format
and the hardware supports.

Saturation minimum value Lets you specify the minimum value to which
the scaled Data inport signal is saturated before it is output via an analog output
channel.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation minimum
value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

Saturation maximum value Lets you specify the maximum value to which
the scaled Data inport signal is saturated before it is output via an analog output
channel.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation maximum
value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

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Multiplier latency Lets you specify the latency that is caused by the
multiplier for scaling. The multiplier is used to multiply the signal with the value
of the Scaling factor parameter.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The multiplication will be implemented without latency.
§ 1 ... 20: The multiplication will be implemented with the specified latency.
Use this value range in the exceptional case that the optimized latency cause
timing problems during the build process.

Adder latency Lets you specify the latency that is caused by the offset adder.
The offset adder is used to add the value of the Scaling offset parameter to the
signal.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The adding will be implemented without latency.
§ 1 ... 20: The adding will be implemented with the specified latency.
Use this value range in the exceptional case that the optimized latency causes
timing problems during the build process.

Digital Out (Type A and The following settings on the Scaling page are specific to the Digital Out
Type B) settings (Type A) and Digital Out (Type B) I/O functions.

Invert polarity Lets you adapt the electrical output signal:

§ Disabled:
If driven with 1, the hardware outputs a high-level signal.
If driven with 0, the hardware outputs a low-level signal.
§ Enabled:
If driven with 1, the hardware outputs a low-level signal.
If driven with 0, the hardware outputs a high-level signal.

LED Out settings The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

Sensor Supply settings The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

UART settings The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

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Related topics References

Description Page (FPGA_IO_WRITE_BL)................................................................................... 534

FPGA_IO_WRITE_BL.................................................................................................................. 58
FPGA_IO_WRITE_BL (FPGA1401Tp1 with Multi-I/O Module Settings)...................................... 513
Parameters Page (FPGA_IO_WRITE_BL)................................................................................... 513

Description Page (FPGA_IO_WRITE_BL)

Purpose To provide detailed information about the selected I/O function.

Description The Description page provides detailed information about the I/O type that you
selected on the corresponding Unit page. The information is either in the text
field itself or in an external help document that you can open by clicking the
function-specific Help button on this page.

The description of the I/O function that is provided by the following standard
frameworks is included in this user documentation:
§ FPGA1401Tp1 (7K325) with Multi-I/O Module (DS1552)
§ FPGA1401Tp1 (7K325) with Multi-I/O Module (DS1552B1)

The description of the access type of customized frameworks or mounted

piggybacks is available as a separate document.

Related topics References

FPGA_IO_WRITE_BL.................................................................................................................. 58
FPGA_IO_WRITE_BL (FPGA1401Tp1 with Multi-I/O Module Settings)...................................... 513
Parameters Page (FPGA_IO_WRITE_BL)................................................................................... 513
Scaling Page (FPGA_IO_WRITE_BL)......................................................................................... 531

FPGA_INT_BL (FPGA1401Tp1 with Multi-I/O Module Settings)

Purpose To configure the FPGA interrupt channel after you load one of the following
frameworks:
§ FPGA1401Tp1 (7K325) with Multi-I/O Module (DS1552)
§ FPGA1401Tp1 (7K325) with Multi-I/O Module (DS1552B1)

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Where to go from here Information in this section

Parameters Page (FPGA_INT_BL)............................................................ 535

To enable the simulation port for an interrupt.

Description Page (FPGA_INT_BL)............................................................ 536

To provide detailed information about the selected I/O function.

Information in other sections

Common settings
Unit Page (FPGA_INT_BL)......................................................................... 64
To specify the interrupt channel used to trigger a task in the processor
model.

Other interface blocks

PROC_INT_BL (FPGA Programming Blockset - Processor Interface
Reference )
To receive an interrupt from the FPGA model to trigger an asynchronous
task in the processor model.

Parameters Page (FPGA_INT_BL)

Purpose To enable the simulation port for an interrupt.

Description The FPGA1401Tp1 with Multi-I/O Module frameworks provide 8 interrupt lines.

An interrupt is requested if the Int port is set to 1 for at least one clock cycle. If
you set the Int port to 0, the last interrupt is not released but saved. An interrupt
is edge-triggered.

Int description Block display The figure below shows the block display with the optional
simulation port.

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I/O characteristics The following table describes the ports of the block:

Port Description
Input
Int Provides the interrupt request line.
Data type: UFix_1_0
0 to 1: Interrupt is requested (edge-triggered).
0: No interrupt is requested. Last requested interrupt is saved.
Output
Sim_Int Simulates an interrupt by performing a function-call to enable a function-call
subsystem.
Available only if Enable simulation port is set on the Parameters page.
Data type: Function call

Int settings Enable simulation port Lets you enable an outport for a simulated interrupt.
The Sim_Int outport is added to the block to connect it to a function-call
subsystem in the processor model.

Related topics References

Description Page (FPGA_INT_BL)............................................................................................. 536

FPGA_INT_BL............................................................................................................................ 62
FPGA_INT_BL (FPGA1401Tp1 with Multi-I/O Module Settings)................................................ 534

Description Page (FPGA_INT_BL)

Purpose To provide detailed information about the selected I/O function.

Description The Description page provides detailed information about the I/O type that you
selected on the corresponding Unit page. The information is either in the text
field itself or in an external help document that you can open by clicking the
function-specific Help button on this page.

The description of the I/O function that is provided by the following standard
frameworks is included in this user documentation:
§ FPGA1401Tp1 (7K325) with Multi-I/O Module (DS1552)
§ FPGA1401Tp1 (7K325) with Multi-I/O Module (DS1552B1)

The description of the access type of customized frameworks or mounted

piggybacks is available as a separate document.

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Related topics References

FPGA_INT_BL............................................................................................................................ 62
FPGA_INT_BL (FPGA1401Tp1 with Multi-I/O Module Settings)................................................ 534
Parameters Page (FPGA_INT_BL)............................................................................................. 535

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Block Settings for the FPGA1401Tp1 with Engine Control I/O

Module Framework
Introduction The block dialogs provide hardware-specific settings after you load the
FPGA1401Tp1 (7K325) with Engine Control I/O Module (DS1554) framework
for the MicroAutoBox II.

Where to go from here Information in this section

FPGA_XDATA_READ_BL (FPGA1401Tp1 with Engine Control I/O

Module Settings)................................................................................... 538
To configure read access to intermodule bus data in the FPGA model.

FPGA_XDATA_WRITE_BL (FPGA1401Tp1 with Engine Control I/O

Module Settings)................................................................................... 547
To configure write access to intermodule bus data in the FPGA model.

FPGA_IO_READ_BL (FPGA1401Tp1 with Engine Control I/O

Module Settings)................................................................................... 555
To configure read access to analog and digital input signals in the FPGA
model.

FPGA_IO_WRITE_BL (FPGA1401Tp1 with Engine Control I/O

Module Settings)................................................................................... 570
To configure write access to analog and digital output signals in the
FPGA model.

FPGA_INT_BL (FPGA1401Tp1 with Engine Control I/O Module

Settings)................................................................................................ 579
To configure the FPGA interrupt channel.

FPGA_XDATA_READ_BL (FPGA1401Tp1 with Engine Control

I/O Module Settings)
Purpose To configure read access to the local bus data in the FPGA model when using the
DS1554 Engine Control I/O Module framework.

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Where to go from here Information in this section

Parameters Page (FPGA_XDATA_READ_BL)............................................ 539

To specify the data format and specific settings for the selected access
type.

Description Page (FPGA_XDATA_READ_BL)............................................ 546

To provide detailed information about the selected access type.

Information in other sections

Common settings
Block Description (FPGA_XDATA_READ_BL)............................................. 45
To specify read access by the FPGA model to the processor model via
processor bus.

Unit Page (FPGA_XDATA_READ_BL)......................................................... 46

To specify the general configuration for the FPGA board's processor bus
read access.

Related FPGA blocks

PROC_XDATA_WRITE_BL (FPGA Programming Blockset -
Processor Interface Reference )
To write data from the processor model to the FPGA model via the
board-specific bus.

FPGA_XDATA_WRITE_BL......................................................................... 49
To implement write access to processor-bus data in the FPGA model.

FPGA_XDATA_WRITE_BL (FPGA1401Tp1 with Engine Control I/O

Module Settings)................................................................................... 547
To configure write access to intermodule bus data in the FPGA model.

Parameters Page (FPGA_XDATA_READ_BL)

Purpose To specify the data format and specific settings for the selected access type.

Description The DS1554 Engine Control I/O Module framework provides the following access
types, which you can select on the Unit page of the block's dialog:
§ Fixed-point format:
Signed or unsigned data format with adjustable binary point position
64-bit fixed-point data types are converted to double. Therefore, the fixed-
point resolution of fixed-point data types is restricted to 53 bits.

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§ 32-bit floating-point format:

Single precision (IEEE 754 standard) data format with a fraction width of 24
§ 64-bit floating-point format:
Double precision (IEEE 754 standard) data format with a fraction width of 53

There are settings that are common to both access types and settings that are
specific to each access type.

For more information, refer to Details on the access types on page 46.

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_XDATA_READ_BL block.

Binary point position (or fraction width) This setting depends on the
format selected in the Format setting.
§ signed/unsigned
The values of the Data outport are in fixed‑point format.
You can specify the binary point position of the 32‑bit value in the range
0 … 32 and the binary point position of the 64‑bit value in the range 0 … 64.
0 represents the lowest bit position, 32 or 64 the highest bit position.
§ floating‑point
The values of the Data outport are in floating‑point format. The fraction width
is displayed.

Format Lets you select the data format of the Data outport.
§ signed/unsigned
The values of the Data outport are in fixed‑point format with or without one
bit reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
64-bit fixed-point data types are converted to double. Therefore, the fixed-
point resolution of fixed-point data types is restricted to 53 bits.
§ floating‑point
The values of the Data outport are in floating‑point format.
The 32‑bit data value supports the single-precision floating‑point format with a
fraction width of 24, which complies with the IEEE 754 standard (single).
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is displayed in the Binary point position (or fraction
width) setting.

Enable simulation port Lets you enable an inport for offline simulation data.
The Sim_Data inport is added to the block so you can connect it to any Simulink
signal used for simulation.

Simulation ports sample time Lets you specify the sample time of the
ports used for simulation, for example, Sim_Data. By default, the sample time
is inherited. You must only specify the sample time explicitly if the modeling
situation inhibits to inherit the sample time, for example, if the corresponding
PROC block is part of an asynchronous task or is used for multiple access to the
same channel.

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Register In description Block display If you specify the register access type, the block display
changes. The simulation ports are optionally displayed.

I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Sim_Data Simulates an intermodule bus data exchange
including floating-point to fixed-point data
conversion.
Available only if Enable simulation port is set on
the Parameters page.
Data type: Double
Data width: 1
Output
Data Outputs a 32-bit data value to be read from an
intermodule bus register. The data format depends
on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary
point position>
§ Floating‑point format
XFloat_8_24
Data New Outputs a flag that indicates the changes of the
register status. If the flag changes from 0 to 1 and
then to 0 again, the requested register contains a
new value. The flag is set to 1 only within one clock
cycle.
Data type: UFix_1_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register In settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 540.

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Register group ID Lets you specify a number in the range 1 … 63 to create

register groups. All registers – 32‑bit and 64‑bit registers – which you specified
with the same group ID are read from the intermodule bus sequentially and then
provided to the FPGA application simultaneously.
Specify 0 for ungrouped read access.

Buffer In description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Sim_Data Simulates an intermodule bus data exchange including floating-point to fixed-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768
Address Specifies an element in the buffer you want to read. The block requires 3 clock
cycles to update the value of the Data outport according to the specified address.
The maximum port range depends on the specified buffer size in the Parameters
page. The valid port range depends on the number of elements currently in the
buffer (see Data Count outport). If you request data from an address that is greater
than the Data Count value, the output of the Data outport is undefined. The first
element of a buffer is addressed by 0.
Data type: UFix_16_0
Output
Data Outputs a 32-bit data value to be read from an intermodule bus buffer. The data
format depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Data New Outputs a flag that indicates the changes of the buffer status. If the flag changes
from 0 to 1 and then to 0 again, the requested buffer contains new values and is
ready to be read. The flag is set to 1 only within one clock cycle.
Data type: UFix_1_0

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Port Description
Data Count Outputs the number of elements in the current buffer.
The maximum range depends on the specified buffer size. You can use the value to
define the valid range for the Address inport of 0 … (Data Count -1).
Data type: UFix_16_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Buffer In settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 540.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.
The maximum range of the Address inport depends on the buffer size.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 32-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Register64 In description Block display If you specify the register access type, the block display
changes. The simulation ports are optionally displayed.

I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Sim_Data Simulates an intermodule bus data exchange
including floating-point to fixed-point data
conversion.
Available only if Enable simulation port is set on
the Parameters page.
Data type: Double

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Port Description
Data width: 1
Output
Data Outputs a 64-bit data value to be read from an
intermodule bus register. The data format depends
on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary
point position>
64-bit fixed-point data types are converted to
double. Therefore, the fixed-point resolution of
fixed-point data types is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Data New Outputs a flag that indicates the changes of the
register status. If the flag changes from 0 to 1 and
then to 0 again, the requested register contains a
new value. The flag is set to 1 only within one clock
cycle.
Data type: UFix_1_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register64 In settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 540.

Register group ID Lets you specify a number in the range 1 … 63 to create

register groups. All registers – 32‑bit and 64‑bit registers – which you specified
with the same group ID are read from the intermodule bus sequentially and then
provided to the FPGA application simultaneously.
Specify 0 for ungrouped read access.

Buffer64 In description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Sim_Data Simulates an intermodule bus data exchange including floating-point to fixed-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768
Address Specifies an element in the buffer you want to read. The block requires 3 clock
cycles to update the value of the Data outport according to the specified address.
The maximum port range depends on the specified buffer size in the Parameters
page. The valid port range depends on the number of elements currently in the
buffer (see Data Count outport). If you request data from an address that is greater
than the Data Count value, the output of the Data outport is undefined. The first
element of a buffer is addressed by 0.
Data type: UFix_16_0
Output
Data Outputs a 64-bit data value to be read from an intermodule bus buffer. The data
format depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double. Therefore, the fixed-point
resolution of fixed-point data types is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Data New Outputs a flag that indicates the changes of the buffer status. If the flag changes
from 0 to 1 and then to 0 again, the requested buffer contains new values and is
ready to be read. The flag is set to 1 only within one clock cycle.
Data type: UFix_1_0
Data Count Outputs the number of elements in the current buffer.
The maximum range depends on the specified buffer size. You can use the value to
define the valid range for the Address inport of 0 … (Data Count -1).
Data type: UFix_16_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Buffer64 In settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 540.

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Buffer size Lets you specify the size of the buffer in the range 1 … 32768.
The maximum range of the Address inport depends on the buffer size.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Related topics References

Description Page (FPGA_XDATA_READ_BL)............................................................................. 546

FPGA_XDATA_READ_BL........................................................................................................... 44
FPGA_XDATA_READ_BL (FPGA1401Tp1 with Engine Control I/O Module Settings)................. 538

Description Page (FPGA_XDATA_READ_BL)

Purpose To provide detailed information about the selected access type.

Description The Description page provides detailed information about the access type that
you selected on the corresponding Unit page. The information is either in the
text field itself or in an external help document that you can open by clicking the
function-specific Help button on this page.

The description of the access type that is provided by the standard FPGA1401Tp1
(7K325) with Engine Control I/O Module (DS1554) framework is included in
this user documentation. The descriptions of the access type of customized
frameworks, installed I/O modules, or IP modules are available as a separate
documents.

Related topics References

FPGA_XDATA_READ_BL........................................................................................................... 44
FPGA_XDATA_READ_BL (FPGA1401Tp1 with Engine Control I/O Module Settings)................. 538
Parameters Page (FPGA_XDATA_READ_BL)............................................................................. 539

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FPGA_XDATA_WRITE_BL (FPGA1401Tp1 with Engine Control

I/O Module Settings)
Purpose To configure write access to intermodule bus data in the FPGA model when
using the FPGA1401Tp1 (7K325) with Engine Control I/O Module (DS1554)
framework.

Where to go from here Information in this section

Parameters Page (FPGA_XDATA_WRITE_BL)........................................... 547

To specify the data format and specific settings for the selected access
type.

Description Page (FPGA_XDATA_WRITE_BL)........................................... 554

To provide detailed information about the selected access type.

Information in other sections

Common settings
Block Description (FPGA_XDATA_WRITE_BL)............................................ 50
To specify write access by the FPGA model to the processor model via
processor bus.

Unit Page (FPGA_XDATA_WRITE_BL)............................................. .......... 51

To specify the general configuration for the FPGA board's processor bus
write access.

Related FPGA blocks

PROC_XDATA_READ_BL (FPGA Programming Blockset -
Processor Interface Reference )
To read data in the processor model that comes from the FPGA model via
the board-specific bus.

FPGA_XDATA_READ_BL.......................................................................... 44
To implement read access to processor-bus data in the FPGA model.

FPGA_XDATA_READ_BL (FPGA1401Tp1 with Engine Control I/O

Module Settings)................................................................................... 538
To configure read access to intermodule bus data in the FPGA model.

Parameters Page (FPGA_XDATA_WRITE_BL)

Purpose To specify the data format and specific settings for the selected access type.

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Description The FPGA1401Tp1 (7K325) with Engine Control I/O Module (DS1554)
framework provides the following access types, which you can select on the
Unit page of the block's dialog:
§ Register/Register64
If you select Register or Register64 as the access type, the data is written to
an intermodule bus register. 128 registers are available with a data width of
32 bits each and 128 registers with a data width of 64 bits each. The values
are transmitted element by element. If you want to access data from several
registers simultaneously, you can group these registers by specifying the same
group identifier for them.
§ Buffer/Buffer64
If you select Buffer or Buffer64 as the access type, the data is written to an
intermodule bus buffer. 32 buffers are available that provides elements with a
data width of 32 bits each and 32 buffers that provides elements with a data
width of 64 bits each. Each buffer has a variable buffer size of 1 up to 32768
elements.

There are settings that are common to both access types and settings that are
specific to each access type.

For more information, refer to Details on the access types on page 51.

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_XDATA_WRITE_BL block.

Binary point position (or fraction width) This setting depends on the
format selected in the Format setting.
§ signed/unsigned
The values of the Data inport are in fixed‑point format.
You can specify the binary point position of the 32‑bit value in the range
0 … 32 and the binary point position of the 64‑bit value in the range 0 … 64.
0 represents the lowest bit position, 32 or 64 the highest bit position.
§ floating‑point
The values of the Data inport are in floating‑point format. The fraction width
is displayed.

Format Lets you select the data format of the Data inport.
§ signed/unsigned
The values of the Data inport are in fixed‑point format with or without one bit
reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
64-bit fixed-point data types are converted to double. Therefore, the fixed-
point resolution of fixed-point data types is restricted to 53 bits.
§ floating‑point
The values of the Data inport are in floating‑point format.
The 32‑bit data value supports the single-precision floating‑point format with a
fraction width of 24, which complies with the IEEE 754 standard (single).

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The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is displayed in the Binary point position (or fraction
width) setting.

Enable simulation data port Lets you enable an outport for offline
simulation data. The Sim_Data outport is added to the block so you can connect
it to any Simulink signal used for simulation.

Simulation ports sample time Lets you specify the sample time of the ports
used for simulation, for example, Sim_Data and Sim_Status. By default, the
sample time is inherited. You must only specify the sample time explicitly, if
the modeling situation inhibits to inherit the sample time, for example, if the
corresponding PROC block is part of an asynchronous task or is used for multiple
access to the same channel.

Register Out description Block display If you specify the register access type, the block display
changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Data Specifies a 32-bit data value to be written to an intermodule bus register. The data
format depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Output
Sim_Data Simulates an intermodule bus data exchange including fixed-point to floating-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1

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Note

The range can be exceeded for the Data inport. The inport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register Out settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 548.

Register group ID Lets you specify a number in the range 1 … 63 to create

register groups. All registers – 32‑bit and 64‑bit registers – which you specified
with the same group ID are sampled simultaneously in the FPGA application. The
values therefore form a consistent data group that is written to the intermodule
bus.

Buffer Out description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a 32-bit data value to be written to an intermodule bus buffer. The data
format depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Enable Specifies the current valid Data port value.
Data type: UFix_1_0
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.
Ready Explicitly specifies the buffer state as ready to send immediately, even if the buffer
is not completely filled. The data values are written to a new buffer in the following
clock cycle. While the port value is 1, the buffer switches every clock cycle. You are
therefore recommended to set the value for only one clock cycle. If the buffer is

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Port Description
completely filled, it is automatically switched, and the data values are stored in a
new buffer.
Data type: UFix_1_0
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready to send, even if it is not completely filled. The
buffer is switched and the data values are accessible via the intermodule bus in
the following clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.
Output
Sim_Data Simulates an intermodule bus data exchange including fixed-point to floating-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768. The vector width depends on the specified buffer size.
Overflow Outputs a flag that indicates that a buffer overflow occurred. An overflow occurs if
the old buffer is not read completely before a new buffer is ready to be read.
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.
Data type: UFix_1_0
Sim_Status Outputs information about the simulated data exchange on the Sim_Data outport.
Available only if the access type is specified as Buffer, and Enable simulation port
is set on the Parameters page.
Data type: UInt32
Data width: 3
§ Sim_Status[0]: Contains the number of valid elements in the Sim_Data vector.
§ Sim_Status[1]: Indicates whether the current buffer contains new or old values. It
is 1 if the buffer contains new values.
§ Sim_Status[2]: Indicates whether a buffer overflow occurred. At least one buffer
was not read and its data was lost before the currently read buffer was filled.

Buffer Out settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 548.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 32-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation status port Lets you enable an outport to get status
information about the simulation data that is available when you enable the
simulation data port. The Sim_Status outport is added to the block.

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Register64 Out description Block display If you specify the register access type, the block display
changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Data Specifies a 64-bit data value to be written to an intermodule bus register. The data
format depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double. Therefore, the fixed-point
resolution of fixed-point data types is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Output
Sim_Data Simulates an intermodule bus data exchange including fixed-point to floating-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1

Note

The range can be exceeded for the Data inport. The inport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register64 Out settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 548.

Register group ID Lets you specify a number in the range 1 … 63 to create

register groups. All registers – 32‑bit and 64‑bit registers – which you specified
with the same group ID are sampled simultaneously in the FPGA application. The
values form therefore a consistent data group that is written to the intermodule
bus.

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Buffer64 Out description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a 64-bit data value to be written to an intermodule bus buffer. The data
format depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double. Therefore, the fixed-point
resolution of fixed-point data types is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Enable Specifies the current valid Data port value.
Data type: UFix_1_0
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.
Ready Explicitly specifies the buffer state as ready to send immediately, even if the buffer
is not completely filled. The data values are written to a new buffer in the following
clock cycle. While the port value is 1, the buffer switches every clock cycle. You are
therefore recommended to set the value for only one clock cycle. If the buffer is
completely filled, it is automatically switched, and the data values are stored in a
new buffer.
Data type: UFix_1_0
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready o send, even if it is not completely filled. The
buffer is switched and the data values are accessible via intermodule bus in the
following clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.
Output
Sim_Data Simulates an intermodule bus data exchange including fixed-point to floating-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768. The vector width depends on the specified buffer size.

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Port Description
Overflow Outputs a flag that indicates that a buffer overflow occurred. An overflow occurs if
the old buffer is not read completely before a new buffer is ready to be read.
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.
Data type: UFix_1_0
Sim_Status Outputs information about the simulated data exchange on the Sim_Data outport.
Available only if the access type is specified as Buffer and Enable simulation port
is set on the Parameters page.
Data type: UInt32
Data width: 3
§ Sim_Status[0]: Contains the number of valid elements in the Sim_Data vector.
§ Sim_Status[1]: Indicates whether the current buffer contains new or old values. It
is 1 if the buffer contains new values.
§ Sim_Status[2]: Indicates whether a buffer overflow occurred. At least one buffer
was not read and its data was lost before the currently read buffer was filled.

Buffer64 Out settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 548.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64 bits in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation status port Lets you enable an outport to get status
information about the simulation data that is available when you have enabled
the simulation data port. The Sim_Status outport is added to the block.

Related topics References

Description Page (FPGA_XDATA_WRITE_BL)............................................................................ 554

FPGA_XDATA_WRITE_BL.......................................................................................................... 49
FPGA_XDATA_WRITE_BL (FPGA1401Tp1 with Engine Control I/O Module Settings)................ 547

Description Page (FPGA_XDATA_WRITE_BL)

Purpose To provide detailed information about the selected access type.

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Description The Description page provides detailed information about the access type that
you selected on the corresponding Unit page. The information is either in the
text field itself or in an external help document that you can open by clicking the
function-specific Help button on this page.

The description of the access type that is provided by the standard FPGA1401Tp1
(7K325) with Engine Control I/O Module (DS1554) framework is included in
this user documentation. The descriptions of the access type of customized
frameworks, installed I/O modules, or IP modules are available as a separate
documents.

Related topics References

FPGA_XDATA_WRITE_BL.......................................................................................................... 49
FPGA_XDATA_WRITE_BL (FPGA1401Tp1 with Engine Control I/O Module Settings)................ 547
Parameters Page (FPGA_XDATA_WRITE_BL)............................................................................ 547

FPGA_IO_READ_BL (FPGA1401Tp1 with Engine Control I/O

Module Settings)
Purpose To configure read access to analog and digital input signals in the FPGA
model when using the FPGA1401Tp1 (7K325) with Engine Control I/O Module
(DS1554) framework.

Where to go from here Information in this section

Parameters Page (FPGA_IO_READ_BL)................................................... 556

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_READ_BL).......................................................... 566

To specify the inverting, scaling, and saturation settings for the selected
I/O function.

Description Page (FPGA_IO_READ_BL)................................................... 570

To provide detailed information about the selected I/O function.

Information in other sections

Common settings
Block Description (FPGA_IO_READ_BL).................................................... 54
To implement read access to a physical input channel in the FPGA model.

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Unit Page (FPGA_IO_READ_BL)................................................................ 55

To specify the I/O type and channel to be used for read access.

Related FPGA blocks

FPGA_IO_WRITE_BL................................................................................. 58
To provide write access to an external device via a physical output
channel.

FPGA_IO_WRITE_BL (FPGA1401Tp1 with Engine Control I/O

Module Settings)................................................................................... 570
To configure write access to analog and digital output signals in the
FPGA model.

Parameters Page (FPGA_IO_READ_BL)

Purpose To specify relevant settings for the selected I/O function.

Description The framework provides different I/O types, which you can select on the Unit
page of the block. The number of the available physical connections on the
DS1554 Engine Control I/O Module determines the I/O functions that you can
select:
§ Status In
§ Digital Crank/Cam Sensor 1 ... Digital Crank/Cam Sensor 5
To provide bit-wise read access to digital camshaft and crankshaft sensors.
Each channel is 1 bit wide.
§ Inductive Zero Voltage Detector
To provide read access to an inductive zero voltage detector. If a zero crossing
from positive to negative is detected, the output signal is 1 for 1 clock cycle.
§ Temperature
To provide read access to the FPGA's die temperature.
§ Digital In 1 (Type B) … Digital In 8 (Type B)
§ ADC 1 (Type A) … ADC 14 (Type A)
§ Knock Sensor 1 ... Knock Sensor 4

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_IO_READ_BL block, except
for the Status In and Temperature functions.

Enable simulation port Lets you enable an inport for offline simulation data.
The Sim_Data inport is added to the block so you can connect it to simulation
data coming from a Simulink-based I/O environment model.

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Status In description Block display If you select the Status In channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block for
initialization sequence status information:

Port Description
Output
Init Done Outputs the state of the initialization sequence that is started after programming
the FPGA.
Data type: UFix_1_0
§ 0: Initialization sequence is in progress.
§ 1: Initialization sequence finished.

I/O mapping No external connection.

Status In settings None

Digital Crank/Cam Sensor Block display If you select a Digital Crank/Cam Sensor channel from the
description channel list, the block display changes. The simulation ports are displayed
optionally.

I/O characteristics The following table describes the ports of the block for
crank/cam input channels:

Port Description
Input
Sim_Data Simulates an input signal in the same range as that specified for the real input
signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Input voltage range: -40 V ... +40 V
Output

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Port Description
Data Outputs the status of the crank/cam sensor.
Data type: UFix_1_0
§ 0: The input signal is lower than the Low threshold voltage parameter.
§ 1: The input signal is higher than the High threshold voltage parameter.
Update rate: FPGA clock frequency

If the hardware input signal or the value of the Sim_Data inport exceeds
the specified input range, the Data outport is saturated to the minimum or
maximum value.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use the
FPGA1401Tp1 (7K325) with Engine Control I/O Module (DS1554) framework.
The signals are available at the DS1554 Sub-D I/O connector.

Outport Channel Connector Pin Signal

Data 1 13 CrankCam Ch 1
2 32 CrankCam Ch 2
3 14 CrankCam Ch 3
4 33 CrankCam Ch 4
5 12 CrankCam Ch 5

Digital Crank/Cam Sensor The following settings on the Parameters page are specific to the Digital
settings Crank/Cam Sensor I/O function. For common dialog settings, refer to Common
settings on page 556.

Low threshold voltage (-40000 mV ... +40000 mV) Lets you set the low
threshold level for the selected digital input channel in steps of 100 mV. Below
this level, a logical 0 is detected, above this level, a logical 1 is detected if the
high threshold voltage was crossed before.

High threshold voltage (-40000 mV ... +40000 mV) Lets you set the high
threshold level for the selected digital input channel in steps of 100 mV. The
logical 1 is output if this level is crossed and stays 1 until the signal falls below
the low threshold level.

Inductive Zero Voltage Block display If you select an Inductive Zero Voltage Detector channel from
Detector description the channel list, the block display changes. The simulation ports are displayed
optionally.

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I/O characteristics The following table describes the ports of the block for
Inductive Zero Voltage Detector channels:

Port Description
Input
Sim_Data Simulates an input signal in the same range as that specified for the real input
signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Input voltage range: -40 V ... +40 V
Output
Data Detects the zero crossing points of the analog signals. If a zero crossing from
positive to negative is detected, the output signal is 1 for 1 clock cycle.
Data type: UFix_1_0
§ 0: No zero crossing.
§ 1: Zero crossing is detected.
Update rate: FPGA clock frequency

If the hardware input signal or the value of the Sim_Data inport exceeds
the specified input range, the Data outport is saturated to the minimum or
maximum value.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use the
FPGA1401Tp1 (7K325) with Engine Control I/O Module (DS1554) framework.
The signals are available at the DS1554 Sub-D I/O connector.

Outport Connector Pin Signal

Data 10 ZeroDetection+
29 ZeroDetection–

Inductive Zero Voltage Only common dialog settings. Refer to Common settings on page 556.
Detector settings

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Temperature description Block display If you select the Temperature channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block for
the die temperature input channel:

Port Description
Input
Sim_Temp Simulates the FPGA's die temperature (internal chip temperature).
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Input temperature range: -273.15 °C ... 230.70 °C
The range can be exceeded. The values are then saturated to the minimum or
maximum values.
Output
RAW_temp Outputs the raw value of the FPGA's die temperature measurement. Use the
12 MSB bits to calculate the die temperature.
Equation for calculating the die temperature:
Temperature [°C] = (float)(Temperature[hex] &
0xFFF0) · 503.975 / 65536
- 273.15
Data type: UFix_16_0
Data width: 1
Value range: 0 ... 65536
High Outputs a flag if the FPGA's die temperature exceeds 105 °C.
To reset the flag, the die temperature must fall below 85 °C.
Data type: UFix_1_0
§ 0: Die temperature does not exceed 105 °C.
§ 1: Die temperature exceeds 105 °C.

Note

A high ambient temperature and an FPGA application with a very high

FPGA utilization and/or toggle rate increase the FPGA die temperature
(internal chip temperature). If the die temperature exceeds 105 °C, the
FPGA might work incorrectly.
You can decrease the temperature by reducing the FPGA's toggle rate (e.g.,
by using clock enable) or by reducing the utilization of the FPGA resources.
If the die temperature exceeds 125 °C, the FPGA resets itself. The reset
stays active until the die temperature falls below 85 °C and you restart
MicroAutoBox II or reload the user application.

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I/O mapping No external connection.

Temperature settings Only common dialog settings. Refer to Common settings on page 556.

Digital In (Type B) description Block display If you select a Digital In (Type B) channel from the channel list,
the block display changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Input
Sim_Data Simulates an input signal in the same range specified for the real input signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Threshold level: 1 V ... 7.5 V (in steps of 0.1 V)
Output
Data Outputs the current results of the digital input channel.
Data type: UFix_1_0
§ 0: Input voltage of the channel is below the specified threshold voltage.
§ 1: Input voltage of the channel is higher than or equal to the specified threshold
voltage.
Update rate: FPGA clock frequency

Note

The frequency that can be detected is much smaller than the update
rate. For information on the electrical characteristics of the DS1554 Engine
Control I/O Module, refer to Data Sheet DS1554 Engine Control I/O Module
(MicroAutoBox II Hardware Reference ).

If the hardware signal or the value of the Sim_Data inport exceeds the minimum
or maximum threshold voltage, it is saturated to the appropriate minimum or
maximum value.

Note

Asynchronous input data might lead to metastable register states because

input data is synchronized only by a single register stage. Further
synchronization techniques might be necessary.

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Note

If you use the same digital channel for the input and the output, the I/O
driver is internally set to InOut mode. As a consequence, the maximum
input voltage for the digital input channel is equal to the specified high
supply, and the applicable threshold voltage is lower than the specified high
supply.
To use the maximum input voltage range, you have to use a digital channel
only as the input.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use the
FPGA1401Tp1 (7K325) with Engine Control I/O Module (DS1554) framework.
The signals are available at the DS1514 ZIF I/O connector.

Outport Channel Connector Pin Signal

Data 1 c3 DigIO ch1
2 b5 DigIO ch2
3 b2 DigIO ch3
4 c5 DigIO ch4
5 c4 DigIO ch5
6 c2 DigIO ch6
7 a2 DigIO ch7
8 Z2 DigIO ch8

You can use the same digital channel for input and output signals.

Digital In (Type B) settings The following settings on the Parameters page are specific to the Digital In
(Type B) I/O function. For common dialog settings, refer to Common settings on
page 556.

Threshold voltage Lets you specify the threshold level for the current digital
channel in the range 1,000 mV … 7,500 mV in steps of 100 mV. If the input
signal is below this level, a logical 0 is detected, otherwise a logical 1.
The selected threshold voltage is also valid for the enabled simulation data
inport.

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ADC (Type A) description Block display If you select an ADC (Type A) channel from the channel list, the
block display changes. The simulation ports are displayed optionally.

I/O characteristics The scaling between the analog input voltage and the
output of the block is:

Input Voltage Range Simulink Output

–10 V ... +10 V The outport range is: 0 … +65535

The following table describes the ports of the block for analog input channels:

Port Description
Input
Sim_Data Simulates an input signal in the same range as that specified for the real input
signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Input voltage range: -10 V ... +10 V
Data_soc Triggers the sampling of the A/D converter. When the value is set to 1 for at least
one clock cycle, the ADC starts the conversion. The port allows a precise definition
of the starting point of ADC sampling. The Data_eoc outport signals the end of the
conversion process.
Setting this value permanently to 1 results in continuous sampling.
Data type: UFix_1_0
Range: 0 or 1
Output
Data Outputs the current results of the A/D conversions on the current channel.
Data type: UFix_16_0
Range: 0 … +65535
Update rate: 1 Msps
Data_eoc Outputs an end of conversion signal if the conversion result is available. If the flag
changes from 0 to 1, the ADC data contains a new value. The flag is set to 1 for
only one clock cycle.
Data type: UFix_1_0
Range: 0 or 1

If the hardware input signal or the value of the Sim_Data inport exceeds the
specified input voltage range, Data outport is saturated to the minimum or
maximum value.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

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I/O mapping The following I/O mapping is relevant if you use the
FPGA1401Tp1 (7K325) with Engine Control I/O Module (DS1554) framework.
The signals are available at the DS1514 ZIF I/O connector.

Outport Channel Connector Pin Signal

Data 1 W2 AnalogIn+ ch 1
V2 AnalogIn- ch 11)
2 Y2 AnalogIn+ ch 2
X2 AnalogIn- ch 21)
3 S2 AnalogIn+ ch 3
R2 AnalogIn- ch 31)
4 T2 AnalogIn+ ch 4
U2 AnalogIn- ch 41)
5 V5 AnalogIn+ ch 5
W6 AnalogIn- ch 51)
6 W3 AnalogIn+ ch 6
V3 AnalogIn- ch 61)
7 T3 AnalogIn+ ch 7
U3 AnalogIn- ch 71)
8 U5 AnalogIn+ ch 8
V6 AnalogIn- ch 81)
9 S5 AnalogIn+ ch 9
T6 AnalogIn- ch 91)
10 T5 AnalogIn+ ch 10
U6 AnalogIn- ch 101)
11 R5 AnalogIn+ ch 11
R6 AnalogIn- ch 111)
12 S3 AnalogIn+ ch 12
R3 AnalogIn- ch 121)
13 P5 AnalogIn+ ch 13
P6 AnalogIn- ch 131)
14 P3 AnalogIn+ ch 14
P2 AnalogIn- ch 141)
1)
The negative input line of the ADC channel is connected to GND. For achieving
optimum analog performance, refer to Connecting Sensor Ground Lines to
MicroAutoBox II (MicroAutoBox II Hardware Installation and Configuration Guide ).

ADC (Type A) settings Only common dialog settings. Refer to Common settings on page 556.

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Knock Sensor description Block display If you select the Knock Sensor channel from the channel list,
the block display changes. The simulation ports are displayed optionally.

I/O characteristics The scaling between the analog input voltage and the
output of the block is:

Input Voltage Range Simulink Output

–5 V ... +5 V The outport range is: 0 … +65535

The following table describes the ports of the block for knock sensor input
channels:

Port Description
Input
Sim_Data Simulates an input signal in the same range as that specified for the real input
signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Input voltage range: –5 V ... +5 V
Data_soc Triggers the sampling of the A/D converter. When the value is set to 1 for at least
one clock cycle, the ADC starts the conversion. The port allows a precise definition
of the starting point of ADC sampling. The Data_eoc outport signals the end of the
conversion process.
Setting this value permanently to 1 results in continuous sampling.
Data type: UFix_1_0
Range: 0 or 1
Output
Data Outputs the current results of the A/D conversions on the current channel.
Data type: UFix_16_0
Range: 0 … +65535
Update rate: 1 Msps
Data_eoc Outputs an end of conversion signal if the conversion result is available. If the flag
changes from 0 to 1, the ADC data contains a new value. The flag is set to 1 for
only one clock cycle.
Data type: UFix_1_0
Range: 0 or 1

If the hardware input signal or the value of the Sim_Data inport exceeds the
specified input voltage range, Data outport is saturated to the minimum or
maximum range value.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

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I/O mapping The following I/O mapping is relevant if you use the
FPGA1401Tp1 (7K325) with Engine Control I/O Module (DS1554) framework.
The signals are available at the DS1554 Sub-D I/O connector.

Outport Channel Connector Pin Signal

Data 1 16 KnockIn+ ch 1
34 KnockIn– ch 11)
2 17 KnockIn+ ch 2
35 KnockIn– ch 21)
3 18 KnockIn+ ch 3
36 KnockIn– ch 31)
4 19 KnockIn+ ch 4
37 KnockIn– ch 41)
1) The negative input line of the knock sensor input channel is connected to GND. For
achieving optimum analog performance, refer to Connecting Sensor Ground Lines to
MicroAutoBox II (MicroAutoBox II Hardware Installation and Configuration Guide ).

Knock Sensor settings Only common dialog settings. Refer to Common settings on page 556.

Related topics References

Description Page (FPGA_IO_READ_BL).................................................................................... 570

FPGA_IO_READ_BL................................................................................................................... 54
FPGA_IO_READ_BL (FPGA1401Tp1 with Engine Control I/O Module Settings)........................ 555
Scaling Page (FPGA_IO_READ_BL)........................................................................................... 566

Scaling Page (FPGA_IO_READ_BL)

Purpose To specify the inverting, scaling, and saturation settings for the selected I/O
function.

Description You can modify the I/O signal of the selected I/O function if you select the
Enable FPGA test access and scaling parameter on the FPGA Access page
of the FPGA_SETUP_BL block dialog. The possible modifications depend on the
selected I/O function.

Common settings The following settings on the Scaling page are common to the I/O functions that
you can select on the Unit page.

Enable FPGA test access and scaling for this block Lets you disable FPGA
test access and scaling for the selected I/O function.

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ADC (Type A) settings The following settings on the Scaling page are specific to the ADC (Type A) I/O
function.

Note

Scaling of analog I/O signals also effects the signal path:

§ If you use the parameters of the Scaling page to scale analog signals, the
data type of the Data port is set to the specified data format for scaling.
For more information, refer to How to Change the Data Type of Analog
Signals (FPGA Programming Blockset Guide ).
§ FPGA scaling of analog I/O signals might cause additional latency. If
the latency can be calculated during the modeling, analog I/O functions
display the total latency.

Scaling format Lets you select the data format for scaling and saturation.
§ Signed/Unsigned:
The values of the parameters for scaling and saturation are in fixed‑point
format. The signed fixed-point format reserves one bit for the sign.
You can specify the number of bits and the binary point position with the
Number of bits and Binary point (fraction width) parameters.
§ Single:
The values of the parameters for scaling and saturation are 32-bit values in
the single-precision floating‑point format with a fraction width of 24, which
complies with the IEEE 754 standard (single).
§ Double:
The values of the parameters for scaling and saturation are 64-bit values in
the double-precision floating‑point format with a fraction width of 53, which
complies with the IEEE 754 standard (double).

Number of bits This setting depends on the Scaling format setting.

§ Fixed-point format:
Lets you specify the bit width of the scaling parameters and the Data port in
the range 1 ... 64.
§ Floating-point format:
Displays the bit width of the scaling parameters and the Data port.

Binary point (fraction width) This setting depends on the Scaling format
setting.
§ Fixed-point format:
Lets you specify the binary point position of the scaling parameters and the
Data port. The position 0 represents the lowest bit position
§ Floating-point format:
Displays the fraction width of the scaling parameters and the Data port.

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Scaling factor Lets you specify the scaling factor. The scaling factor gains the
signal of the Data port before it is saturated or replaced via FPGA test access.
You must check whether the specified and displayed value is supported by
the specified scaling format. The value of the Scaling factor parameter will
be executed with the maximum accuracy of the specified scaling format
and saturated to the minimum and maximum values that the scaling format
supports.

Scaling offset Lets you add a signal offset after the signal of the Data port is
scaled with the scaling factor.
You must check whether the specified and displayed value is supported by
the specified scaling format. The value of the Scaling offset parameter will
be executed with the maximum accuracy of the specified scaling format
and saturated to the minimum and maximum values that the scaling format
supports.

Saturation minimum value Lets you specify the minimum value to which
the measured and scaled signal is saturated before it is output via the Data port.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation minimum
value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

Saturation maximum value Lets you specify the maximum value to which
the measured and scaled signal is saturated before it is output via the Data port.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation maximum
value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

Multiplier latency Lets you specify the latency that is caused by the
multiplier for scaling. The multiplier is used to multiply the signal with the value
of the Scaling factor parameter.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The multiplication will be implemented without latency.
§ 1 ... 20: The multiplication will be implemented with the specified latency.
Use this value range in the exceptional case that the optimized latency cause
timing problems during the build process.

Adder latency Lets you specify the latency that is caused by the offset adder.
The offset adder is used to add the value of the Scaling offset parameter to the
signal.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The adding will be implemented without latency.
§ 1 ... 20: The adding will be implemented with the specified latency.

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Use this value range in the exceptional case that the optimized latency causes
timing problems during the build process.

Digital In (Type B) settings The following settings on the Scaling page are specific to the Digital In
(Type B) I/O function.

Invert polarity Lets you adapt the measured values to the electrical input
signal:
§ Disabled:
The Data port outputs the signals as measured: A low-high transition results in
a 1 and vice versa.
§ Enabled:
The output of the Data port is inverted: A low-high transition results in a 0
and vice versa.

Digital Crank/Cam Sensor The Scaling page is empty because this I/O function does not support FPGA
settings scaling to scale I/O signals.

Inductive Zero Voltage The Scaling page is empty because this I/O function does not support FPGA
Detector scaling to scale I/O signals.

Knock Sensor The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

Status In The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

Temperature The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

Related topics References

Description Page (FPGA_IO_READ_BL).................................................................................... 570

FPGA_IO_READ_BL................................................................................................................... 54
FPGA_IO_READ_BL (FPGA1401Tp1 with Engine Control I/O Module Settings)........................ 555
Parameters Page (FPGA_IO_READ_BL).................................................................................... 556

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Description Page (FPGA_IO_READ_BL)

Purpose To provide detailed information about the selected I/O function.

Description The Description page provides detailed information about the access type that
you selected on the corresponding Unit page. The information is either in the
text field itself or in an external help document that you can open by clicking the
function-specific Help button on this page.

The description of the access type that is provided by the standard FPGA1401Tp1
(7K325) with Engine Control I/O Module (DS1554) framework is included in
this user documentation. The descriptions of the access type of customized
frameworks, installed I/O modules, or IP modules are available as a separate
documents.

Related topics References

FPGA_IO_READ_BL................................................................................................................... 54
FPGA_IO_READ_BL (FPGA1401Tp1 with Engine Control I/O Module Settings)........................ 555
Parameters Page (FPGA_IO_READ_BL).................................................................................... 556
Scaling Page (FPGA_IO_READ_BL)........................................................................................... 566

FPGA_IO_WRITE_BL (FPGA1401Tp1 with Engine Control I/O

Module Settings)
Purpose To configure write access to analog and digital output signals in the FPGA
model when using the FPGA1401Tp1 (7K325) with Engine Control I/O Module
(DS1554) framework.

Where to go from here Information in this section

Parameters Page (FPGA_IO_WRITE_BL).................................................. 571

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_WRITE_BL)........................................................ 577

To specify the inverting, scaling, and saturation settings for the selected
I/O function.

Description Page (FPGA_IO_WRITE_BL).................................................. 578

To provide detailed information about the selected I/O function.

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Information in other sections

Common settings
Block Description (FPGA_IO_WRITE_BL)................................................... 59
To implement write access to a physical output channel in the FPGA
model.

Unit Page (FPGA_IO_WRITE_BL)............................................................... 60

To specify the I/O type and channel to be used for write access.

Related FPGA blocks

FPGA_IO_READ_BL.................................................................................. 54
To provide read access to an external device via a physical input channel.

FPGA_IO_READ_BL (FPGA1401Tp1 with Engine Control I/O

Module Settings)................................................................................... 555
To configure read access to analog and digital input signals in the FPGA
model.

Parameters Page (FPGA_IO_WRITE_BL)

Purpose To specify relevant settings for the selected I/O function.

Description The framework provides the three I/O types Analog, Digital, and Other, which
you can select on the Unit page of the block. The number of the available
physical connections on the DS1554 Engine Control I/O Module determines the
I/O functions that you can select:
§ LED Out
§ Sensor Supply
§ Digital Out 1 (Type A) … Digital Out 40 (Type A)
§ Digital Out 1 (Type B) … Digital Out 8 (Type B)

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_IO_WRITE_BL block, except
for the LED Out function.

Enable simulation port Lets you enable an outport for offline simulation
data. The Sim_Data outport is added to the block so you can connect it to a
Simulink-based I/O environment model.

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LED Out description Block display If you select the LED Out channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Controls the FPGA status LED. The LED is located near the
DS1514 ZIF I/O connector.
Data type: UFix_1_0
§ 0: LED lights up green.
§ 1: LED lights up orange.

If the value of the Data inport exceeds the specified data width, only the lowest
bit is used (=1).

I/O mapping No external connection.

LED Out settings None

Sensor Supply description Block display If you select the Sensor Supply channel from the channel list,
the block display changes.

I/O characteristics The following table describes the ports of the block:

Port Description
Output
Sim_Data Simulates an output signal in the same range as that specified
for the real output signal.
Output voltage: 13.14 V

I/O mapping The following I/O mapping is relevant if you use the
FPGA1401Tp1 (7K325) with Engine Control I/O Module (DS1554) framework.
The signals are available at the DS1514 ZIF I/O connector.

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Outport Channel Connector Pin Signal

Sim_Data 1 b6 VSENS+
c6 VSENS–

Sensor Supply settings Only common dialog settings. Refer to Common settings on page 571.

Digital Out (Type A) Block display If you select a Digital Out (Type A) channel from the channel
description list, the block display changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Outputs a signal in the specified range.
If driven with 0, the hardware output is 0 V. If driven with 1, the hardware output is set to the
specified high-supply voltage (VDRIVE).
The hardware output is driven only if the Enable port is set to 1, otherwise the output is set to high
impedance (High-Z).
Data Type: UFix_1_0
Update rate: FPGA clock frequency

Note

The frequency that can be generated is much smaller than the update rate. For information on
the electrical characteristics of the DS1554 Engine Control I/O Module, refer to Digital Outputs
(MicroAutoBox II Hardware Reference ).

Enable Controls the hardware output. If set to 1, the hardware output reacts to the Data outport, otherwise
it is set to High-Z.
Data type: UFix_1_0
Output
Sim_Data Simulates an output signal in the same range as that specified for the real output signal.
Available only if Enable simulation port is set on the Parameters page.
Output voltage: 0 V ... 45 V
Update rate: FPGA clock frequency

If the value of the Data inport exceeds the specified data width, only the lowest
bit is used.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.

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A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use the
FPGA1401Tp1 (7K325) with Engine Control I/O Module (DS1554) framework.
The signals are available at the DS1514 ZIF I/O connector.

Inport Channel Connector Pin Signal

Data 1 L5 DigOut ch 1
2 N2 DigOut ch 2
3 D3 DigOut ch 3
4 N5 DigOut ch 4
5 M6 DigOut ch 5
6 N3 DigOut ch 6
7 D5 DigOut ch 7
8 M2 DigOut ch 8
9 L6 DigOut ch 9
10 K2 DigOut ch 10
11 C3 DigOut ch 11
12 L2 DigOut ch 12
13 G6 DigOut ch 13
14 H2 DigOut ch 14
15 C5 DigOut ch 15
16 J2 DigOut ch 16
17 F6 DigOut ch 17
18 E2 DigOut ch 18
19 B3 DigOut ch 19
20 G2 DigOut ch 20
21 E6 DigOut ch 21
22 C2 DigOut ch 22
23 B5 DigOut ch 23
24 F2 DigOut ch 24
25 D6 DigOut ch 25
26 A6 DigOut ch 26
27 A3 DigOut ch 27
28 D2 DigOut ch 28
29 B6 DigOut ch 29
30 A2 DigOut ch 30
31 A5 DigOut ch 31
32 B2 DigOut ch 32

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Inport Channel Connector Pin Signal

33 F5 DigOut ch 33
34 N6 DigOut ch 34
35 E3 DigOut ch 35
36 E5 DigOut ch 36
37 H3 DigOut ch 37
38 M5 DigOut ch 38
39 G3 DigOut ch 39
40 F3 DigOut ch 40

Digital Out (Type A) settings The following settings on the Parameters page are specific to the Digital Out
(Type A) I/O function. For common dialog settings, refer to Common settings on
page 571.

Simulated VDRIVE pin Lets you select the voltage for the simulated high-
side switch for all digital output channels in the range 0 … 45000 mV in steps of
100 mV.

Note

You can specify the simulated voltage value only globally for all digital
output channels.

Digital Out (Type B) Block display If you select a Digital Out (Type B) channel from the channel
description list, the block display changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Outputs a signal in the specified range.
If driven with 0, the hardware output is 0 V. If driven with 1, the hardware output is 3.3 V or 5 V
according to the specified high-supply voltage.
The hardware output is driven only if the Enable port is set to 1, otherwise the output is set to high
impedance (High-Z).
Data Type: UFix_1_0

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Port Description
Update rate: FPGA clock frequency

Note

The frequency that can be generated is much smaller than the update rate. For information
on the electrical characteristics of the DS1554 Engine Control I/O Module, refer to Digital I/O
(Bidirectional) (MicroAutoBox II Hardware Reference ).

Enable Controls the hardware output. If set to 1, the hardware output reacts to the Data outport, otherwise
it is set to High-Z.
Data type: UFix_1_0
Output
Sim_Data Simulates an output signal in the same range as that specified for the real output signal.
Available only if Enable simulation port is set on the Parameters page.
Output voltage: 0 V … 3.3 V or 0 V … 5 V
Update rate: FPGA clock frequency

If the value of the Data inport exceeds the specified data width, only the lowest
bit is used.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use the
FPGA1401Tp1 (7K325) with Engine Control I/O Module (DS1554) framework.
The signals are available at the DS1514 ZIF I/O connector.
You can use the same digital channel for input and output signals.

Outport Channel Connector Pin Signal

Data 1 c3 DigIO ch1
2 b5 DigIO ch2
3 b2 DigIO ch3
4 c5 DigIO ch4
5 c4 DigIO ch5
6 c2 DigIO ch6
7 a2 DigIO ch7
8 Z2 DigIO ch8

Digital Out (Type B) settings The following settings on the Parameters page are specific to the Digital Out
(Type B) I/O function. For common dialog settings, refer to Common settings on
page 571.

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High supply Lets you select the voltage for the high-side switch (3.3 V or 5 V)
for all digital output channels.

Note

You can specify the high-supply voltage value only globally for all digital
output channels.

Related topics References

Description Page (FPGA_IO_WRITE_BL)................................................................................... 578

FPGA_IO_WRITE_BL.................................................................................................................. 58
FPGA_IO_WRITE_BL (FPGA1401Tp1 with Engine Control I/O Module Settings)....................... 570
Scaling Page (FPGA_IO_WRITE_BL)......................................................................................... 577

Scaling Page (FPGA_IO_WRITE_BL)

Purpose To specify the inverting, scaling, and saturation settings for the selected I/O
function.

Description You can modify the I/O signal of the selected I/O function if you select the
Enable FPGA test access and scaling parameter on the FPGA Access page
of the FPGA_SETUP_BL block dialog. The possible modifications depend on the
selected I/O function.

Common settings The following settings on the Scaling page are common to the I/O functions that
you can select on the Unit page.

Enable FPGA test access and scaling for this block Lets you disable FPGA
test access and scaling for the selected I/O function.

Digital Out (Type A and The following settings on the Scaling page are specific to the Digital Out
Type B) settings (Type A) and Digital Out (Type B) I/O functions.

Invert polarity Lets you adapt the electrical output signal:

§ Disabled:
If driven with 1, the hardware outputs a high-level signal.
If driven with 0, the hardware outputs a low-level signal.
§ Enabled:
If driven with 1, the hardware outputs a low-level signal.
If driven with 0, the hardware outputs a high-level signal.

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LED Out settings The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

Sensor Supply settings The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

Related topics References

Description Page (FPGA_IO_WRITE_BL)................................................................................... 578

FPGA_IO_WRITE_BL.................................................................................................................. 58
FPGA_IO_WRITE_BL (FPGA1401Tp1 with Engine Control I/O Module Settings)....................... 570
Parameters Page (FPGA_IO_WRITE_BL)................................................................................... 571

Description Page (FPGA_IO_WRITE_BL)

Purpose To provide detailed information about the selected I/O function.

Description The Description page provides detailed information about the access type that
you selected on the corresponding Unit page. The information is either in the
text field itself or in an external help document that you can open by clicking the
function-specific Help button on this page.

The description of the access type that is provided by the standard FPGA1401Tp1
(7K325) with Engine Control I/O Module (DS1554) framework is included in
this user documentation. The descriptions of the access type of customized
frameworks, installed I/O modules, or IP modules are available as a separate
documents.

Related topics References

FPGA_IO_WRITE_BL.................................................................................................................. 58
FPGA_IO_WRITE_BL (FPGA1401Tp1 with Engine Control I/O Module Settings)....................... 570
Parameters Page (FPGA_IO_WRITE_BL)................................................................................... 571
Scaling Page (FPGA_IO_WRITE_BL)......................................................................................... 577

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FPGA_INT_BL (FPGA1401Tp1 with Engine Control I/O

Module Settings)
Purpose To configure the FPGA interrupt channel when using the FPGA1401Tp1 (7K325)
with Engine Control I/O Module (DS1554) framework.

Where to go from here Information in this section

Parameters Page (FPGA_INT_BL)............................................................ 579

To enable the simulation port for an interrupt.

Description Page (FPGA_INT_BL)............................................................ 580

To provide detailed information about the selected I/O function.

Information in other sections

Common settings
Unit Page (FPGA_INT_BL)......................................................................... 64
To specify the interrupt channel used to trigger a task in the processor
model.

Other interface blocks

PROC_INT_BL (FPGA Programming Blockset - Processor Interface
Reference )
To receive an interrupt from the FPGA model to trigger an asynchronous
task in the processor model.

Parameters Page (FPGA_INT_BL)

Purpose To enable the simulation port for an interrupt.

Description The FPGA1401Tp1 (7K325) with Engine Control I/O Module (DS1554)
framework provides 8 interrupt lines.

An interrupt is requested if the Int port is set to 1 for at least one clock cycle. If
you set the Int port to 0, the last interrupt is not released but saved. An interrupt
is edge-triggered.

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Int description Block display The following illustration shows the block display with the
optional simulation port:

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Int Provides the interrupt request line.
Data type: UFix_1_0
0 to 1: Interrupt is requested (edge-triggered).
0: No interrupt is requested. Last requested interrupt is saved.
Output
Sim_Int Simulates an interrupt by performing a function-call to enable a function-call
subsystem.
Available only if Enable simulation port is set on the Parameters page.
Data type: Function call

Int settings Enable simulation port Lets you enable an outport for a simulated interrupt.
The Sim_Int outport is added to the block so you can connect it to a function-
call subsystem in the processor model.

Related topics References

Description Page (FPGA_INT_BL)............................................................................................. 580

FPGA_INT_BL............................................................................................................................ 62
FPGA_INT_BL (FPGA1401Tp1 with Engine Control I/O Module Settings)................................. 579

Description Page (FPGA_INT_BL)

Purpose To provide detailed information about the selected I/O function.

Description The Description page provides detailed information about the access type that
you selected on the corresponding Unit page. The information is either in the
text field itself or in an external help document that you can open by clicking the
function-specific Help button on this page.

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The description of the access type that is provided by the standard FPGA1401Tp1
(7K325) with Engine Control I/O Module (DS1554) framework is included in
this user documentation. The descriptions of the access type of customized
frameworks, installed I/O modules, or IP modules are available as a separate
documents.

Related topics References

FPGA_INT_BL............................................................................................................................ 62
FPGA_INT_BL (FPGA1401Tp1 with Engine Control I/O Module Settings)................................. 579
Parameters Page (FPGA_INT_BL)............................................................................................. 579

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Block Settings for the MicroAutoBox III Frameworks

Where to go from here Information in this section

Block Settings for the FPGA1403Tp1 with Multi‑I/O

Module Frameworks.............................................................................. 584
The block dialogs provide hardware-specific settings after you load a
MicroAutoBox III framework that supports the DS1552 Multi-I/O Module.

Block Settings for the FPGA1403Tp1 with Engine Control I/O

Module Framework............................................................................... 647
The block dialogs provide hardware-specific settings after you load
a MicroAutoBox III framework that supports the DS1554 Engine
Control I/O Module.

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Block Settings for the FPGA1403Tp1 with Multi‑I/O Module

Frameworks
Introduction The block dialogs provide hardware-specific settings after you load one of the
following MicroAutoBox III frameworks:
§ FPGA1403Tp1 (7K325) with Multi-I/O Module (DS1552)
§ FPGA1403Tp1 (7K325) with Multi-I/O Module (DS1552B1)

Where to go from here Information in this section

FPGA_XDATA_READ_BL (FPGA1403Tp1 with Multi-I/O Module

Settings)................................................................................................ 584
To configure read access to intermodule bus data in the FPGA model.

FPGA_XDATA_WRITE_BL (FPGA1403Tp1 with Multi-I/O Module

Settings)................................................................................................ 594
To configure write access to intermodule bus data in the FPGA model.

FPGA_IO_READ_BL (FPGA1403Tp1 with Multi-I/O Module

Settings)................................................................................................ 603
To configure read access to analog and digital input signals in the FPGA
model.

FPGA_IO_WRITE_BL (FPGA1403Tp1 with Multi-I/O Module

Settings)................................................................................................ 623
To configure write access to analog and digital output signals in the
FPGA model.

FPGA_INT_BL (FPGA1403Tp1 with Multi-I/O Module Settings)............... 645

To configure the FPGA interrupt channel.

FPGA_XDATA_READ_BL (FPGA1403Tp1 with Multi-I/O

Module Settings)
Purpose To configure read access to intermodule bus data in the FPGA model after you
load one of the following frameworks:
§ FPGA1403Tp1 (7K325) with Multi-I/O Module (DS1552)
§ FPGA1403Tp1 (7K325) with Multi-I/O Module (DS1552B1)

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Where to go from here Information in this section

Parameters Page (FPGA_XDATA_READ_BL)............................................ 585

To specify the data format and specific settings for the selected access
type.

Information in other sections

Unit Page (FPGA_XDATA_READ_BL)......................................................... 46

To specify the general configuration for the FPGA board's processor bus
read access.

Parameters Page (FPGA_XDATA_READ_BL)

Purpose To specify the data format and specific settings for the selected access type.

Description The FPGA1403Tp1 with Multi-I/O Module frameworks provide the following
access types that you can select on the Unit page of the block's dialog:
§ Register/Register64
If you select Register or Register64 as the access type, the data is read from
an intermodule bus register. 128 registers are available with a data width of
32 bits each and 128 registers with a data width of 64 bits each. The values
are transmitted element by element.
If you want to access data from several registers simultaneously, you can group
these registers by specifying the same group identifier for them.
Ungrouped registers are automatically combined into one register group with
group ID Ungrouped to optimize data transfer. Since register groups can be
only accessed by one task, you have to explicitly group registers which are
used by different tasks.
§ Buffer/Buffer64
If you select Buffer or Buffer64 as the access type, the data is read from an
intermodule bus buffer. 32 buffers are available that provides elements with a
data width of 32 bits each and 32 buffers that provides elements with a data
width of 64 bits each. Each buffer has a variable buffer size of 1 up to 32768
elements.
§ Bus
If you select Bus as the access type, the data is read from an intermodule
bus buffer. The bus access type lets you use Simulink buses to model the data
exchange between the processor and the FPGA.

There are settings that are common and settings that are specific to each access
type.

For more information, refer to Details on the access types on page 46.

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Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_XDATA_READ_BL block.

Binary point position (or fraction width) This setting depends on the
format selected in the Format setting.
§ signed/unsigned
The values of the Data outport are in fixed‑point format.
You can specify the binary point position of the 32‑bit value in the range
0 … 32 and the binary point position of the 64‑bit value in the range 0 … 64.
0 represents the lowest bit position, 32 or 64 the highest bit position.
§ floating‑point
The values of the Data outport are in floating‑point format. The fraction width
is displayed.

Format Lets you select the data format of the Data outport.
§ signed/unsigned
The values of the Data outport are in fixed‑point format with or without one
bit reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
64-bit fixed-point data types are converted to double. Therefore, the fixed-
point resolution of fixed-point data types is restricted to 53 bits.
§ floating‑point
The values of the Data outport are in floating‑point format.
The 32‑bit data value supports the single-precision floating‑point format with a
fraction width of 24, which complies with the IEEE 754 standard (single).
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is displayed in the Binary point position (or fraction
width) setting.

Enable simulation port Lets you enable an inport for offline simulation data.
The Sim_Data inport is added to the block to connect it to any Simulink signal
used for simulation.

Simulation ports sample time Lets you specify the sample time of the ports
used for simulation, for example, Sim_Data. By default, the sample time is
inherited. You must only specify the sample time explicitly, if the modeling
situation inhibits to inherit the sample time, for example, if the corresponding
PROC block is part of an asynchronous task or is used for multiple access to the
same channel.

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Register In description Block display If you specify the register access type, the block display
changes. The simulation ports are optionally displayed.

I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Sim_Data Simulates an intermodule bus data exchange including floating-point to fixed-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Output
Data Outputs a 32-bit data value to be read from a intermodule bus register. The data
format depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Data New Outputs a flag that indicates the changes of the register status. If the flag changes
from 0 to 1 and then to 0 again, the requested register contains a new value. The
flag is set to 1 only within one clock cycle.
Data type: UFix_1_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register In settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 586.

Register group ID Lets you specify a number in the range 1 … 63 to create

register groups. All registers – 32‑bit and 64‑bit registers – which you specified
with the same group ID are read from the intermodule bus sequentially and then
provided to the FPGA application simultaneously.
Specify 0 for ungrouped read access.

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Buffer In description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Sim_Data Simulates an intermodule bus data exchange including floating-point to fixed-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768
Address Specifies an element in the buffer you want to read. The block requires 3 clock
cycles to update the value of the Data outport according to the specified address.
The maximum port range depends on the specified buffer size in the Parameters
page. The valid port range depends on the number of elements currently in the
buffer (see Data Count outport). If you request data from an address that is greater
than the Data Count value, the output of the Data outport is undefined. The first
element of a buffer is addressed by 0.
Data type: UFix_16_0
Output
Data Outputs a 32-bit data value to be read from an intermodule bus buffer. The data
format depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Data New Outputs a flag that indicates the changes of the buffer status. If the flag changes
from 0 to 1 and then to 0 again, the requested buffer contains new values and is
ready to be read. The flag is set to 1 only within one clock cycle.
Data type: UFix_1_0
Data Count Outputs the number of elements in the current buffer.
The maximum range depends on the specified buffer size. You can use the value to
define the valid range for the Address inport of 0 … (Data Count -1).
Data type: UFix_16_0

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Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Buffer In settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 586.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.
The maximum range of the Address inport depends on the buffer size.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 32-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Register64 In description Block display If you specify the register access type, the block display
changes. The simulation ports are optionally displayed.

I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Sim_Data Simulates an intermodule bus data exchange including floating-point to fixed-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Output
Data Outputs a 64-bit data value to be read from an intermodule bus register. The data
format depends on the related dialog settings.

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Port Description
Data type:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double. Therefore, the fixed-point
resolution of fixed-point data types is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Data New Outputs a flag that indicates the changes of the register status. If the flag changes
from 0 to 1 and then to 0 again, the requested register contains a new value. The
flag is set to 1 only within one clock cycle.
Data type: UFix_1_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register64 In settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 586.

Register group ID Lets you specify a number in the range 1 … 63 to create

register groups. All registers – 32‑bit and 64‑bit registers – which you specified
with the same group ID are read from the intermodule bus sequentially and then
provided to the FPGA application simultaneously.
Specify 0 for ungrouped read access.

Buffer64 In description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Sim_Data Simulates an intermodule bus data exchange including floating-point to fixed-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768
Address Specifies an element in the buffer you want to read. The block requires 3 clock
cycles to update the value of the Data outport according to the specified address.
The maximum port range depends on the specified buffer size in the Parameters
page. The valid port range depends on the number of elements currently in the
buffer (see Data Count outport). If you request data from an address that is greater
than the Data Count value, the output of the Data outport is undefined. The first
element of a buffer is addressed by 0.
Data type: UFix_16_0
Output
Data Outputs a 64-bit data value to be read from an intermodule bus buffer. The data
format depends on the related dialog settings.
Data type if the bus transfer mode is disabled on the Parameters page:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double. Therefore, the fixed-point
resolution of fixed-point data types is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Data New Outputs a flag that indicates the changes of the buffer status. If the flag changes
from 0 to 1 and then to 0 again, the requested buffer contains new values and is
ready to be read. The flag is set to 1 only within one clock cycle.
Data type: UFix_1_0
Data Count Outputs the number of elements in the current buffer.
The maximum range depends on the specified buffer size. You can use the value to
define the valid range for the Address inport of 0 … (Data Count -1).
Data type: UFix_16_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Buffer64 In settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 586.

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Buffer size Lets you specify the size of the buffer in the range 1 … 32768.
The maximum range of the Address inport depends on the buffer size.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64 bits in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Bus In description Block display If you specify the access type, the block display changes. The
simulation port is optionally displayed.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Sim_Data Simulates a bus data exchange including floating-point to fixed-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768
Output
Data Outputs the signals of the Simulink bus. The data types of the signals depend
on the bus topology that is copied via Copy bus topology from corresponding
processor block or Copy bus topology from gcb on the Parameters page. The
maximum bit wide is 64 bits.
The resolution of the data types is restricted to 53 bits, because the data type of the
received bus signals from the processor application is double and the block converts
the signals to the signal data types.
Data New Outputs a flag that indicates the changes of the buffer status. If the flag changes
from 0 to 1 and then to 0 again, the requested buffer contains new values and is
ready to be read. The flag is set to 1 only within one clock cycle.
Data type: UFix_1_0

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Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Bus In settings The following dialog settings are specific for the Bus access type. For common
dialog settings, refer to Common settings on page 586.

Buffer size Displays the size of the buffer in the range 1 … 32,768. The
buffer size depends on the number of bus signals.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1,024
words. For example, a buffer with a buffer size of 1 allocates a memory
block of 1,024 words with a data width of 64-bit in the FPGA memory. This
applies to any buffer and the related swinging buffer.

Edit bus topology Opens a dialog to display and configure the

bus signals. For more information, refer to Bus Editor Dialog -
FPGA_XDATA_READ_BL/FPGA_XDATA_WRITE_BL on page 66.

Copy bus topology from corresponding processor block Lets you copy an
existing bus topology from the corresponding processor block in the processor
model. For more information, refer to How to Use Simulink Buses of the
Processor Model to Model the Processor Communication (FPGA Programming
Blockset Guide ).

Copy bus topology from gcb Lets you copy an existing FPGA bus topology
from the selected Simulink Bus Creator block, subsystem inport block, or
subsystem outport block to the Data port of the Bus In block.
You cannot copy a bus topology from the processor model, because these
topologies do not include the FPGA data types. For instructions, refer to How
to Use Simulink Buses of the FPGA Model to Model Processor Communication
(FPGA Programming Blockset Guide ).

Reset bus topology Lets you clear the bus topology of the Data port.

Related topics Basics

Modeling Processor Model Access (FPGA Programming Blockset Guide )

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FPGA_XDATA_WRITE_BL (FPGA1403Tp1 with Multi-I/O

Module Settings)
Purpose To configure write access to intermodule bus data in the FPGA model after you
load one of the following frameworks:
§ FPGA1403Tp1 (7K325) with Multi-I/O Module (DS1552)
§ FPGA1403Tp1 (7K325) with Multi-I/O Module (DS1552B1)

Where to go from here Information in this section

Parameters Page (FPGA_XDATA_WRITE_BL)........................................... 594

To specify the data format and specific settings for the selected access
type.

Information in other sections

Unit Page (FPGA_XDATA_WRITE_BL)............................................. .......... 51

To specify the general configuration for the FPGA board's processor bus
write access.

Parameters Page (FPGA_XDATA_WRITE_BL)

Purpose To specify the data format and specific settings for the selected access type.

Description The FPGA1403Tp1 with Multi-I/O Module frameworks provide the following
access types that you can select in the Unit page of the block's dialog:
§ Register/Register64
If you select Register or Register64 as the access type, the data is written to
an intermodule bus register. 128 registers are available with a data width of
32 bits each and 128 registers with a data width of 64 bits each. The values
are transmitted element by element. If you want to access data from several
registers simultaneously, you can group these registers by specifying the same
group identifier for them.
§ Buffer/Buffer64
If you select Buffer or Buffer64 as the access type, the data is written to an
intermodule bus buffer. 32 buffers are available that provides elements with a
data width of 32 bits each and 32 buffers that provides elements with a data
width of 64 bits each. Each buffer has a variable buffer size of 1 up to 32768
elements.

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§ Bus
If you select Bus as the access type, the data is written to an intermodule
bus buffer. The bus access type lets you use Simulink buses to model the data
exchange between the processor and the FPGA.

There are settings that are common and settings that are specific to each access
type.

For more information, refer to Details on the access types on page 51.

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_XDATA_WRITE_BL block.

Binary point position (or fraction width) This setting depends on the
format selected in the Format setting.
§ signed/unsigned
The values of the Data inport are in fixed‑point format.
You can specify the binary point position of the 32‑bit value in the range
0 … 32 and the binary point position of the 64‑bit value in the range 0 … 64.
0 represents the lowest bit position, 32 or 64 the highest bit position.
§ floating‑point
The values of the Data inport are in floating‑point format. The fraction width
is displayed.

Format Lets you select the data format of the Data inport.
§ signed/unsigned
The values of the Data inport are in fixed‑point format with or without one bit
reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
64-bit fixed-point data types are converted to double. Therefore, the fixed-
point resolution of fixed-point data types is restricted to 53 bits.
§ floating‑point
The values of the Data inport are in floating‑point format.
The 32‑bit data value supports the single-precision floating‑point format with a
fraction width of 24, which complies with the IEEE 754 standard (single).
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is displayed in the Binary point position (or fraction
width) setting.

Enable simulation data port Lets you enable an outport for offline
simulation data. The Sim_Data outport is added to the block to connect it to
any Simulink signal used for simulation.

Simulation ports sample time Lets you specify the sample time of the ports
used for simulation, for example, Sim_Data and Sim_Status. By default, the
sample time is inherited. You must only specify the sample time explicitly, if
the modeling situation inhibits to inherit the sample time, for example, if the
corresponding PROC block is part of an asynchronous task or is used for multiple
access to the same channel.

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Register Out description Block display If you specify the register access type, the block display
changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Data Specifies a 32-bit data value to be written to an intermodule bus register. The data
format depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Output
Sim_Data Simulates an intermodule bus data exchange including fixed-point to floating-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1

Note

The range can be exceeded for the Data inport. The inport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register Out settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 595.

Register group ID Lets you specify a number in the range 1 … 63 to create

register groups. All registers – 32‑bit and 64‑bit registers – which you specified
with the same group ID are sampled simultaneously in the FPGA application. The
values form therefore a consistent data group that is written to the intermodule
bus.

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Buffer Out description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a 32-bit data value to be written to an intermodule bus buffer. The data
format depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Enable Specifies the current valid Data port value.
Data type: UFix_1_0
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.
Ready Explicitly specifies the buffer state as ready to send immediately, even if the buffer
is not completely filled. The data values are written to a new buffer in the following
clock cycle. While the port value is 1, the buffer switches every clock cycle. You are
therefore recommended to set the value for only one clock cycle. If the buffer is
completely filled, it is automatically switched, and the data values are stored in a
new buffer.
Data type: UFix_1_0
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready to send, even if it is not completely filled. The
buffer is switched and the data values are accessible via intermodule bus in the
following clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.
Output
Sim_Data Simulates an intermodule bus data exchange including fixed-point to floating-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768. The vector width depends on the specified buffer size.

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Port Description
Overflow Outputs a flag that indicates that a buffer overflow occurred. An overflow occurs if
the old buffer is not read completely before a new buffer is ready to be read.
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.
Data type: UFix_1_0
Sim_Status Outputs information about the simulated data exchange on the Sim_Data outport.
Available only if the access type is specified as Buffer and Enable simulation port
is set on the Parameters page.
Data type: UInt32
Data width: 3
§ Sim_Status[0]: Contains the number of valid elements in the Sim_Data vector.
§ Sim_Status[1]: Indicates whether the current buffer contains new or old values. It
is 1, if the buffer contains new values.
§ Sim_Status[2]: Indicates whether a buffer overflow occurred. At least one buffer
was not read and its data is lost before the currently read buffer was filled.

Buffer Out settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 595.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 32-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation status port Lets you enable an outport to get status
information about the simulation data that is available when you have enabled
the simulation data port. The Sim_Status outport is added to the block.

Register64 Out description Block display If you specify the register access type, the block display
changes. The simulation ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Data Specifies a 64-bit data value to be written to an intermodule bus register. The data
format depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double. Therefore, the fixed-point
resolution of fixed-point data types is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Output
Sim_Data Simulates an intermodule bus data exchange including fixed-point to floating-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1

Note

The range can be exceeded for the Data inport. The inport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register64 Out settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 595.

Register group ID Lets you specify a number in the range 1 … 63 to create

register groups. All registers – 32‑bit and 64‑bit registers – which you specified
with the same group ID are sampled simultaneously in the FPGA application. The
values form therefore a consistent data group that is written to the intermodule
bus.

Buffer64 Out description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a 64-bit data value to be written to an intermodule bus buffer. The data
format depends on the related dialog settings.
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double. Therefore, the fixed-point
resolution of fixed-point data types is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Enable Specifies the current valid Data port value.
Data type: UFix_1_0
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.
Ready Explicitly specifies the buffer state as ready to send immediately, even if the buffer
is not completely filled. The data values are written to a new buffer in the following
clock cycle. While the port value is 1, the buffer switches every clock cycle. You are
therefore recommended to set the value for only one clock cycle. If the buffer is
completely filled, it is automatically switched, and the data values are stored in a
new buffer.
Data type: UFix_1_0
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready o send, even if it is not completely filled. The
buffer is switched and the data values are accessible via intermodule bus in the
following clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.
Output
Sim_Data Simulates an intermodule bus data exchange including fixed-point to floating-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768. The vector width depends on the specified buffer size or
the number of bus signals.
Overflow Outputs a flag that indicates that a buffer overflow occurred. An overflow occurs if
the old buffer is not read completely before a new buffer is ready to be read.
Available only if the bus transfer mode is disabled on the Parameters page.
Data type: UFix_1_0
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.
Sim_Status Outputs information about the simulated data exchange on the Sim_Data outport.
Available only if the access type is specified as Buffer and Enable simulation port
is set on the Parameters page.
Data type: UInt32

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Port Description
Data width: 3
§ Sim_Status[0]: Contains the number of valid elements in the Sim_Data vector.
§ Sim_Status[1]: Indicates whether the current buffer contains new or old values. It
is 1 if the buffer contains new values.
§ Sim_Status[2]: Indicates whether a buffer overflow occurred. At least one buffer
was not read and its data was lost before the currently read buffer was filled.

Buffer64 Out settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 595.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64 bits in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation status port Lets you enable an outport to get status
information about the simulation data that is available when you have enabled
the simulation data port. The Sim_Status outport is added to the block.

Bus Out description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a 64-bit data value to be written to a buffer for data transmission.
The data types of the signals depend on the bus topology that is set via Copy bus
topology from corresponding processor block or Copy bus topology from gcb
on the Parameters page. The maximum bit width is 64 bits.
The resolution of the data type is restricted to 53 bits, because the block converts all
data values to double for transmission.
Output

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Port Description
Sim_Data Simulates a data transmission including fixed-point to floating-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768. The vector width depends on the number of bus signals.

Bus Out settings The following dialog settings are specific for the Bus access type. For common
dialog settings, refer to Common settings on page 595.

Buffer size Displays the size of the buffer in the range 1 … 32,768. The
buffer size depends on the number of bus signals.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1,024
words. For example, a buffer with a buffer size of 1 allocates a memory
block of 1,024 words with a data width of 64 bits in the FPGA memory.
This applies to any buffer and the related swinging buffer.

Edit bus topology Opens a dialog to display and configure the

bus signals. For more information, refer to Bus Editor Dialog -
FPGA_XDATA_READ_BL/FPGA_XDATA_WRITE_BL on page 66.

Copy bus topology from corresponding processor block Lets you copy an
existing bus topology from the corresponding processor block in the processor
model. For more information, refer to How to Use Simulink Buses of the
Processor Model to Model the Processor Communication (FPGA Programming
Blockset Guide ).

Analyze bus topology of input Lets you set the Data inport to the bus
topology of the connected Simulink bus.
If clicked, the FPGA Programming Blockset analyzes the connected Simulink
bus and sets the Data port to a matching bus topology. For instructions,
refer to How to Use Simulink Buses of the FPGA Model to Model Processor
Communication (FPGA Programming Blockset Guide ).

Reset bus topology Lets you clear the bus topology of the Data port.

Related topics Basics

Modeling Processor Model Access (FPGA Programming Blockset Guide )

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FPGA_IO_READ_BL (FPGA1403Tp1 with Multi-I/O Module

Settings)
Purpose To configure read access to analog and digital input signals in the FPGA model
after you load one of the following frameworks:
§ FPGA1403Tp1 (7K325) with Multi-I/O Module (DS1552)
§ FPGA1403Tp1 (7K325) with Multi-I/O Module (DS1552B1)

Where to go from here Information in this section

Parameters Page (FPGA_IO_READ_BL)................................................... 603

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_READ_BL).......................................................... 620

To specify the inverting, scaling, and saturation settings for the selected
I/O function.

Information in other sections

Unit Page (FPGA_IO_READ_BL)................................................................ 55

To specify the I/O type and channel to be used for read access.

Parameters Page (FPGA_IO_READ_BL)

Purpose To specify relevant settings for the selected I/O function.

Description The framework provides different I/O types, which you can select on the Unit
page of the block. The number of the available physical connections on the
DS1552 or DS1552B1 Multi-I/O Module determines the I/O functions that you
can select:
§ Analog In 10 Channel 1 … Analog In 10 Channel 8 (only DS1552)
§ Analog In 11 Channel 1 … Analog In 11 Channel 8 (only DS1552B1)
§ Analog In 12 Channel 1 … Analog In 12 Channel 16
§ Digital Crank/Cam Sensor 1 ... Digital Crank/Cam Sensor 3
To provide bit-wise read access to digital camshaft and crankshaft sensors.
Each channel is 1 bit wide.
§ Digital In 5 Channel 1 … Digital In 5 Channel 16
§ Digital InOut 6 Channel 1 … Digital InOut 6 Channel 8

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§ Inductive Zero Voltage Detector

To provide read access to an inductive zero voltage detector. If a zero crossing
from positive to negative is detected, the output signal is 1 for 1 clock cycle.
§ Status In
§ Subsystem Clock
§ System Clock
§ System Signal Block
§ Temperature
To provide read access to the FPGA's die temperature.

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_IO_READ_BL block, except
for the Status In and Temperature function.

Enable simulation port Lets you enable an inport for offline simulation data.
The Sim_Data inport is added to the block to connect it to simulation data
coming from a Simulink-based I/O environment model.

Analog In 10 description Hardware support Only the DS1552 Multi‑I/O Module provides the
Analog In 10 channels.

Block display If you select an Analog In 10 channel from the channel list, the
block display changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block for
analog input channels:

Port Description
Input
Sim_Data Simulates an input signal in the same range as that specified for the real input
signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Input voltage range: 0 V … +5 V
Data_soc Triggers the sampling of the A/D converter. When the value is set to 1 for at least
one clock cycle, the ADC starts the conversion. The port allows a precise definition
of the starting point of ADC sampling. The Data_eoc outport signals the end of the
conversion process.
Setting this value permanently to 1 results in continuous sampling.
Data type: UFix_1_0
Range: 0 or 1

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Port Description
Output
Data Outputs the current results of the A/D conversions on the current channel.
Data type: UFix_16_0
Range: 0 … +65535
Update rate: 1 Msps
Data_eoc Outputs an end of conversion signal if the conversion result is available. If the flag
changes from 0 to 1, the ADC data contains a new value. The flag is set to 1 for
only one clock cycle.
Data type: UFix_1_0
Range: 0 or 1

If the hardware input signal or the value of the Sim_Data inport exceeds
the specified input voltage range, Data outport is saturated to minimum or
maximum range value.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping The following I/O mapping is relevant if you use one of the
FPGA1403Tp1 with Multi-I/O Module frameworks. The signals are available at
the DS1514 ZIF I/O connector.

Outport Channel Connector Pin Signal

Data 1 X3 Analog In Channel 1 Signal
X4 Analog In Channel 1 Reference
2 W3 Analog In Channel 2 Signal
W4 Analog In Channel 2 Reference
3 V3 Analog In Channel 3 Signal
V4 Analog In Channel 3 Reference
4 U3 Analog In Channel 4 Signal
U4 Analog In Channel 4 Reference
5 H3 Analog In Channel 5 Signal
H4 Analog In Channel 5 Reference
6 G3 Analog In Channel 6 Signal
G4 Analog In Channel 6 Reference
7 F3 Analog In Channel 7 Signal
F4 Analog In Channel 7 Reference
8 E3 Analog In Channel 8 Signal
E4 Analog In Channel 8 Reference

Analog In 10 settings Only common dialog settings. Refer to Common settings on page 604.

Analog In 11 description Hardware support Only the DS1552B1 Multi‑I/O Module provides the
Analog In 11 channels.

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Block display If you select an Analog In 11 channel from the channel list, the
block display changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block for
analog input channels:

Port Description
Input
Sim_Data Simulates an input signal in the same range as that specified for the real input
signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Input voltage range: ‑10 V ... +10 V
Data_soc Triggers the sampling of the A/D converter. When the value is set to 1 for at least
one clock cycle, the ADC starts the conversion. The port allows a precise definition
of the starting point of ADC sampling. The Data_eoc outport signals the end of the
conversion process.
Setting this value permanently to 1 results in continuous sampling.
Data type: UFix_1_0
Range: 0 or 1
Output
Data Outputs the current results of the A/D conversions on the current channel.
Data type: UFix_16_0
Range: 0 … +65535
Update rate: 1 Msps
Data_eoc Outputs an end of conversion signal if the conversion result is available. If the flag
changes from 0 to 1, the ADC data contains a new value. The flag is set to 1 for
only one clock cycle.
Data type: UFix_1_0
Range: 0 or 1

If the hardware input signal or the value of the Sim_Data inport exceeds
the specified input voltage range, Data outport is saturated to minimum or
maximum range value.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping The following I/O mapping is relevant if you use one of the
FPGA1403Tp1 with Multi-I/O Module frameworks. The signals are available at
the DS1514 ZIF I/O connector.

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Outport Channel Connector Pin Signal

Data 1 X3 Analog In Channel 1 Signal
X4 Analog In Channel 1 Reference
2 W3 Analog In Channel 2 Signal
W4 Analog In Channel 2 Reference
3 V3 Analog In Channel 3 Signal
V4 Analog In Channel 3 Reference
4 U3 Analog In Channel 4 Signal
U4 Analog In Channel 4 Reference
5 H3 Analog In Channel 5 Signal
H4 Analog In Channel 5 Reference
6 G3 Analog In Channel 6 Signal
G4 Analog In Channel 6 Reference
7 F3 Analog In Channel 7 Signal
F4 Analog In Channel 7 Reference
8 E3 Analog In Channel 8 Signal
E4 Analog In Channel 8 Reference

Analog In 11 settings Only common dialog settings. Refer to Common settings on page 604.

Analog In 12 description Block display If you select an Analog In 12 channel from the channel list, the
block display changes. The simulation ports are displayed optionally.

I/O characteristics The scaling between the analog input voltage and the
output of the block is:

Input Voltage Range Simulink Output

–10 V ... +10 V The output port range is: –32768 … +32767

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The following table describes the ports of the block for analog input channels:

Port Description
Input
Sim_Data Simulates an input signal in the same range as that specified for the real input
signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Input voltage range: -10 V ... +10 V
Output
Data Outputs the current results of the A/D conversions on the current channel.
Data type: Fix_16_0
Range: -32768 … +32767
Update rate: 0.2 Msps

If the hardware input signal or the value of the Sim_Data inport exceeds
the specified input voltage range, Data outport is saturated to minimum or
maximum range value.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping The following I/O mapping is relevant if you use one of the
FPGA1403Tp1 with Multi-I/O Module frameworks. The signals are available at
the DS1514 ZIF I/O connector.

Outport Channel Connector Pin Signal

Data 1 b2 Analog In 12 Channel 1 Signal
2 a2 Analog In 12 Channel 2 Signal
3 Z2 Analog In 12 Channel 3 Signal
4 Y2 Analog In 12 Channel 4 Signal
5 X2 Analog In 12 Channel 5 Signal
6 W2 Analog In 12 Channel 6 Signal
7 V2 Analog In 12 Channel 7 Signal
8 U2 Analog In 12 Channel 8 Signal
9 M2 Analog In 12 Channel 9 Signal
10 L2 Analog In 12 Channel 10 Signal
11 K2 Analog In 12 Channel 11 Signal
12 J2 Analog In 12 Channel 12 Signal
13 H2 Analog In 12 Channel 13 Signal
14 G2 Analog In 12 Channel 14 Signal
15 F2 Analog In 12 Channel 15 Signal
16 E2 Analog In 12 Channel 16 Signal

Analog In 12 settings Only common dialog settings. Refer to Common settings on page 604.

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Digital Crank/Cam Sensor Block display If you select a Digital Crank/Cam Sensor channel from the
description channel list, the block display changes. The simulation ports are displayed
optionally.

I/O characteristics The following table describes the ports of the block for
crank/cam input channels:

Port Description
Input
Sim_Data Simulates an input signal in the same range as that specified for the real input
signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Input voltage range: -40 V ... +40 V
Output
Data Outputs the status of the crank/cam sensor.
Data type: UFix_1_0
§ 0: The input signal is lower than the Low threshold voltage parameter.
§ 1: The input signal is higher than the High threshold voltage parameter.
Update rate: FPGA clock frequency

If the hardware input signal or the value of the Sim_Data inport exceeds the
specified input range, Data outport is saturated to minimum or maximum range
value.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use one of the
FPGA1403Tp1 with Multi-I/O Module frameworks. The signals are available at
the DS1514 ZIF I/O connector.

Outport Channel Connector Pin Signal

Data 1 R3 Digital In 6 Channel 1 +
R4 Digital In 6 Channel 1 -
2 B3 Digital In 6 Channel 2 +
B4 Digital In 6 Channel 2 -

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Outport Channel Connector Pin Signal

3 A3 Digital In 6 Channel 3 +
A4 Digital In 6 Channel 3 -

Digital Crank/Cam Sensor The following settings on the Parameters page are specific to the Digital
settings Crank/Cam Sensor I/O function. For common dialog settings, refer to Common
settings on page 604.

Low threshold voltage (-40000 mV ... +40000 mV) Lets you set the low
threshold level for the selected digital input channel. Below this level a logical 0
is detected, above this level a logical 1 is detected, if the high threshold voltage
was crossed before.

High threshold voltage (-40000 mV ... +40000 mV) Lets you set the high
threshold level for the selected digital input channel. The logical 1 is output, if
this level is crossed and stays 1 until the signal falls below the low threshold level.

Digital In 5 description Block display If you select a Digital In 5 channel from the channel list, the
block display changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Input
Sim_Data Simulates an input signal in the same range specified for the real input signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Threshold level:
§ 3.6 V for low-high transition
§ 1.2 V for high-low transition
Output
Data Outputs the current results of digital input channel.
Data type: UFix_1_0
§ 0: Input voltage of the channel is below the threshold voltage of a high-low
transition.
§ 1: Input voltage of the channel is higher than or equal to the threshold voltage of
a low-high transition.

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Port Description
Update rate: FPGA clock frequency

Note

The frequency that can be detected is much smaller than the update rate. For
information on the electrical characteristics of the DS1552 Multi-I/O Module,
refer to Digital In 5 Characteristics (MicroAutoBox III Hardware Installation and
Configuration ).

If the hardware signal or the value of the Sim_Data inport exceeds the minimum
or maximum threshold voltage, it is saturated to the corresponding minimum or
maximum value.

Note

Asynchronous input data might lead to metastable register states because

input data is synchronized only by a single register stage. Further
synchronization techniques might be necessary.

Note

If you use the same digital channel for the input and the output, the I/O
driver is internally set to InOut mode. As a consequence, the maximum
input voltage for the digital input channel is equal to the specified high
supply, and the applicable threshold voltage is lower than the specified high
supply.
To use the maximum input voltage range, you have to use a digital channel
only as the input.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use one of the
FPGA1403Tp1 with Multi-I/O Module frameworks. The signals are available at
the DS1514 ZIF I/O connector.

Outport Channel Connector Pin Signal

Data 1 V5 Digital In 5 Channel 1 Signal
2 U5 Digital In 5 Channel 2 Signal
3 U6 Digital In 5 Channel 3 Signal
4 T2 Digital In 5 Channel 4 Signal
5 T3 Digital In 5 Channel 5 Signal
6 T4 Digital In 5 Channel 6 Signal

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Outport Channel Connector Pin Signal

7 T5 Digital In 5 Channel 7 Signal
8 T6 Digital In 5 Channel 8 Signal
9 S2 Digital In 5 Channel 9 Signal
10 S3 Digital In 5 Channel 10
Signal
11 S5 Digital In 5 Channel 11
Signal
12 R2 Digital In 5 Channel 12
Signal
13 R5 Digital In 5 Channel 13
Signal
14 R6 Digital In 5 Channel 14
Signal
15 P5 Digital In 5 Channel 15
Signal
16 P6 Digital In 5 Channel 16
Signal

Digital In 5 settings Only common dialog settings. Refer to Common settings on page 604.

Digital InOut 6 (In) description Block display If you select a Digital InOut 6 (In) channel from the channel list,
the block display changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Input
Sim_Data Simulates an input signal in the same range specified for the real input signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Threshold level: 1 V ... 7.5 V (in steps of 0.1 V)
Output

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Port Description
Data Outputs the current results of digital input channel.
Data type: UFix_1_0
§ 0: Input voltage of the channel is below the specified threshold voltage.
§ 1: Input voltage of the channel is higher than or equal to the specified threshold
voltage.
Update rate: FPGA clock frequency

Note

The frequency that can be detected is much smaller than the update rate. For
information on the electrical characteristics of the DS1552 Multi-I/O Module,
refer to Digital In/Out 6 Characteristics (MicroAutoBox III Hardware Installation
and Configuration ).

If the hardware signal or the value of the Sim_Data inport exceeds the minimum
or maximum threshold voltage, it is saturated to the corresponding minimum or
maximum value.

Note

Asynchronous input data might lead to metastable register states because

input data is synchronized only by a single register stage. Further
synchronization techniques might be necessary.

Note

If you use the same digital channel for the input and the output, the I/O
driver is internally set to InOut mode. As a consequence, the maximum
input voltage for the digital input channel is equal to the specified high
supply, and the applicable threshold voltage is lower than the specified high
supply.
To use the maximum input voltage range, you have to use a digital channel
only as the input.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use one of the
FPGA1403Tp1 with Multi-I/O Module frameworks. The signals are available at
the DS1514 ZIF I/O connector.

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Outport Channel Connector Pin Signal

Data 1 N2 Digital InOut 6 Channel 1
Signal
2 N3 Digital InOut 6 Channel 2
Signal
3 N4 Digital InOut 6 Channel 3
Signal
4 N5 Digital InOut 6 Channel 4
Signal
5 N6 Digital InOut 6 Channel 5
Signal
6 M5 Digital InOut 6 Channel 6
Signal
7 M6 Digital InOut 6 Channel 7
Signal
8 L4 Digital InOut 6 Channel 8
Signal

You can use the same digital channel for input and output signals.

Digital InOut 6 (In) settings The following settings on the Parameters page are specific to the Digital InOut
6 (In) I/O function. For common dialog settings, refer to Common settings on
page 604.

Threshold voltage Lets you specify the threshold level for the current digital
channel in the range 1,000 mV … 7,500 mV in steps of 100 mV. If the input
signal is below this level, a logical 0 is detected, otherwise a logical 1.
The selected threshold voltage is also valid for the enabled simulation data
inport.

Inductive Zero Voltage Block display If you select a Inductive Zero Voltage Detector channel from
Detector description the channel list, the block display changes. The simulation ports are displayed
optionally.

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I/O characteristics The following table describes the ports of the block for
crank/cam input channels:

Port Description
Input
Sim_Data Simulates an input signal in the same range as that specified for the real input
signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Input voltage range: -40 V ... +40 V
Output
Data Detects the zero crossing points of the analog signals. If a zero crossing from
positive to negative is detected, the output signal is 1 for 1 clock cycle.
Data type: UFix_1_0
§ 0: No zero crossing.
§ 1: Zero crossing is detected.
Update rate: FPGA clock frequency

If the hardware input signal or the value of the Sim_Data inport exceeds the
specified input range, Data outport is saturated to minimum or maximum range
value.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use one of the
FPGA1403Tp1 with Multi-I/O Module frameworks. The signals are available at
the DS1514 ZIF I/O connector.

Outport Connector Pin Signal

Data P3 Digital In 7
Channel 1 +
P4 Digital In 7
Channel 1 -

Inductive Zero Voltage Only common dialog settings. Refer to Common settings on page 604.
Detector settings

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Status In description Block display If you select the Status In channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block for
initialization sequence status information:

Port Description
Output
Init Done Outputs the state of the initialization sequence that is started after programming
the FPGA.
Data type: UFix_1_0
§ 0: Initialization sequence is in progress.
§ 1: Initialization sequence has finished.

I/O mapping No external connection.

Status In settings None

Subsystem Clock description Block display If you select the Subsysten Clock channel from the channel list,
the block display changes.

I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Output
Subsystem Outputs the clock signal of the selected subsystem clock domain. You specify the
Clock subsystem clock domain in the FPGA Setup block. Refer to How to Use Multiple
Clock Domains for FPGA Modeling (FPGA Programming Blockset Guide ).
Data type: UFix_1_0
Data width: 1

Multiple clock domain support This block is intended to be used in a user

clock domain with an individual clock period.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

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I/O mapping No external connection.

Subsystem Clock settings None

System Clock description Block display If you select the Systen Clock channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Output
System Clock Outputs the clock signal of the FPGA (base clock rate).
Data type: UFix_1_0
Data width: 1

Multiple clock domain support This block is intended to be used in a user

clock domain with an individual clock period.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping No external connection.

System Clock settings None

System Signal Block Block display If you select the System Signal Block channel from the channel
description list, the block display changes.

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I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Output
System Clock Outputs the clock signal of the FPGA (base clock rate).
Data type: UFix_1_0
Data width: 1
Init Done Outputs the state of the initialization sequence that is started after programming
the FPGA.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Initialization sequence is in progress.
§ 1: Initialization sequence has finished.
CN App Outputs the state of the processor application.
Status Data type: UFix_1_0
Data width: 1
Values:
§ 0: The processor application is stopped.
§ 1: The processor application is running.
Opto_Ready Indicates whether an MGT module is ready for data exchange.
The port value remains 0, because the used dSPACE hardware does not support
MGT modules.

Multiple clock domain support This block is intended to be used in a user

clock domain with an individual clock period.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping No external connection.

System Signal Block settings None

Temperature Block display If you select the Temperature channel from the channel list, the
block display changes.

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I/O characteristics The following table describes the ports of the block for
the die temperature input channel:

Port Description
Input
Sim_Temp Simulates the FPGA's die temperature (internal chip temperature).
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Input temperature range: -273.15 °C ... 230.70 °C
The range can be exceeded. The values are then saturated to the minimum or
maximum values.
Output
RAW_temp Outputs the raw value of the FPGA's die temperature measurement. Use the 12
MSB bits to calculate the die temperature.
Equation for calculating the die temperature:
Temperature [°C] = (float)(Temperature[hex] &
0xFFF0) · 503.975 / 65536
- 273.15
Data type: UFix_16_0
Data width: 1
Value range: 0 ... 65536
High Outputs a flag if the FPGA's die temperature exceeds 105 °C.
To reset the flag, the die temperature must fall below 85 °C.
Data type: UFix_1_0
§ 0: Die temperature does not exceed 105 °C.
§ 1: Die temperature exceeds 105 °C.

Note

A high ambient temperature and an FPGA application with a very high

FPGA utilization and/or toggle rate increase the FPGA die temperature
(internal chip temperature). If the die temperature exceeds 105 °C, the
FPGA might work incorrectly.
You can decrease the temperature by reducing the FPGA's toggle rate (e.g.,
by using clock enable) or by reducing the utilization of the FPGA resources.
If the die temperature exceeds 125 °C, the FPGA resets itself. The reset
stays active until the die temperature falls below 85 °C and you restart
MicroAutoBox III or reload the user application.

I/O mapping No external connection.

Temperature settings Only common dialog settings. Refer to Common settings on page 604.

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Related topics Basics

Modeling External I/O Access (FPGA Programming Blockset Guide )

Scaling Page (FPGA_IO_READ_BL)

Purpose To specify the inverting, scaling, and saturation settings for the selected I/O
function.

Description You can modify the I/O signal of the selected I/O function if you select the
Enable FPGA test access and scaling parameter on the FPGA Access page
of the FPGA_SETUP_BL block dialog. The possible modifications depend on the
selected I/O function.

Common settings The following settings on the Scaling page are common to the I/O functions that
you can select on the Unit page.

Enable FPGA test access and scaling for this block Lets you disable FPGA
test access and scaling for the selected I/O function.

Analog in settings The following settings on the Scaling page are specific to the Analog In 10,
Analog In 11, and Analog In 12 I/O functions.

Note

Scaling of analog I/O signals also effects the signal path:

§ If you use the parameters of the Scaling page to scale analog signals, the
data type of the Data port is set to the specified data format for scaling.
For more information, refer to How to Change the Data Type of Analog
Signals (FPGA Programming Blockset Guide ).
§ FPGA scaling of analog I/O signals might cause additional latency. If
the latency can be calculated during the modeling, analog I/O functions
display the total latency.

Scaling format Lets you select the data format for scaling and saturation.
§ Signed/Unsigned:
The values of the parameters for scaling and saturation are in fixed‑point
format. The signed fixed-point format reserves one bit for the sign.

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You can specify the number of bits and the binary point position with the
Number of bits and Binary point (fraction width) parameters.
§ Single:
The values of the parameters for scaling and saturation are 32-bit values in
the single-precision floating‑point format with a fraction width of 24, which
complies with the IEEE 754 standard (single).
§ Double:
The values of the parameters for scaling and saturation are 64-bit values in
the double-precision floating‑point format with a fraction width of 53, which
complies with the IEEE 754 standard (double).

Number of bits This setting depends on the Scaling format setting.

§ Fixed-point format:
Lets you specify the bit width of the scaling parameters and the Data port in
the range 1 ... 64.
§ Floating-point format:
Displays the bit width of the scaling parameters and the Data port.

Binary point (fraction width) This setting depends on the Scaling format
setting.
§ Fixed-point format:
Lets you specify the binary point position of the scaling parameters and the
Data port. The position 0 represents the lowest bit position
§ Floating-point format:
Displays the fraction width of the scaling parameters and the Data port.

Scaling factor Lets you specify the scaling factor. The scaling factor gains the
signal of the Data port before it is saturated or replaced via FPGA test access.
You must check whether the specified and displayed value is supported by
the specified scaling format. The value of the Scaling factor parameter will
be executed with the maximum accuracy of the specified scaling format
and saturated to the minimum and maximum values that the scaling format
supports.

Scaling offset Lets you add a signal offset after the signal of the Data port is
scaled with the scaling factor.
You must check whether the specified and displayed value is supported by
the specified scaling format. The value of the Scaling offset parameter will
be executed with the maximum accuracy of the specified scaling format
and saturated to the minimum and maximum values that the scaling format
supports.

Saturation minimum value Lets you specify the minimum value to which
the measured and scaled signal is saturated before it is output via the Data port.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation minimum
value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

Saturation maximum value Lets you specify the maximum value to which
the measured and scaled signal is saturated before it is output via the Data port.

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You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation maximum
value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

Multiplier latency Lets you specify the latency that is caused by the
multiplier for scaling. The multiplier is used to multiply the signal with the value
of the Scaling factor parameter.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The multiplication will be implemented without latency.
§ 1 ... 20: The multiplication will be implemented with the specified latency.
Use this value range in the exceptional case that the optimized latency cause
timing problems during the build process.

Adder latency Lets you specify the latency that is caused by the offset adder.
The offset adder is used to add the value of the Scaling offset parameter to the
signal.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The adding will be implemented without latency.
§ 1 ... 20: The adding will be implemented with the specified latency.
Use this value range in the exceptional case that the optimized latency causes
timing problems during the build process.

Digital in settings The following settings on the Scaling page are specific to the Digital In 5 and
Digital InOut 6 (In) I/O functions.

Invert polarity Lets you adapt the measured values to the electrical input
signal:
§ Disabled:
The Data port outputs the signals as measured: A low-high transition results in
a 1 and vice versa.
§ Enabled:
The output of the Data port is inverted: A low-high transition results in a 0
and vice versa.

Digital Crank/Cam Sensor The Scaling page is empty because this I/O function does not support FPGA
settings scaling to scale I/O signals.

Inductive Zero Voltage The Scaling page is empty because this I/O function does not support FPGA
Detector settings scaling to scale I/O signals.

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Status In settings The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

Temperature settings The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

Related topics Basics

Basics on FPGA Test Access and Scaling (FPGA Programming Blockset Guide )

FPGA_IO_WRITE_BL (FPGA1403Tp1 with Multi-I/O Module

Settings)
Purpose To configure write access to analog and digital output signals in the FPGA model
after you load one of the following frameworks:
§ FPGA1403Tp1 (7K325) with Multi-I/O Module (DS1552)
§ FPGA1403Tp1 (7K325) with Multi-I/O Module (DS1552B1)

Where to go from here Information in this section

Parameters Page (FPGA_IO_WRITE_BL).................................................. 623

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_WRITE_BL)........................................................ 642

To specify the inverting, scaling, and saturation settings for the selected
I/O function.

Information in other sections

Unit Page (FPGA_IO_WRITE_BL)............................................................... 60

To specify the I/O type and channel to be used for write access.

Parameters Page (FPGA_IO_WRITE_BL)

Purpose To specify relevant settings for the selected I/O function.

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Description The framework provides the three I/O types Analog, Digital, and Other, which
you can select on the Unit page of the block. The number of the available
physical connections on the DS1552 Multi-I/O Module determines the I/O
functions that you can select:
§ Analog Out 13 Channel 1 … Analog Out 13 Channel 4
§ Digital Out 5 Channel 1 … Digital Out 5 Channel 16
§ Digital InOut 6 Channel 1 … Digital InOut 6 Channel 8
§ LED Out
§ Sensor Supply
§ UART 3 (RS232) Channel 1 … UART 3 (RS232) Channel 2
§ UART 3 (RS422/485) Channel 1 … UART 3 (RS422/485) Channel 2
§ User Clock Out 1 … User Clock Out 32

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_IO_WRITE_BL block, except
for the LED Out and Sensor Supply functions.

Enable simulation port Lets you enable an outport for offline simulation
data. The Sim_Data outport is added to the block to connect it to a Simulink-
based I/O environment model.
If you have selected one of the UART functions, this setting is replaced by
function-specific simulation settings.

Analog Out 13 description Block display If you have selected an Analog Out 13 channel from the
channel list, the block display changes. The simulation ports are displayed
optionally.

I/O characteristics The scaling between the analog output voltage and the
input of the block is:

Output Voltage Range Simulink Input

0 V … +5 V The input port range is: 0 … +65535

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The following table describes the ports of the block:

Port Description
Input
Data Outputs a signal in the specified range.
Data type: UFix_16_0
Output voltage range: 0 … +65535
The range can be exceeded, and saturation is performed to a minimum or maximum
value.
Hardware update rate: 2.1 Msps
If the values are updated at a higher FPGA model rate, intermediate values are not
updated by the DAC.
Output
Sim_Data Simulates an output signal in the same range as that specified for the real output
signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Output voltage range: 0 V … +5 V

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping The following I/O mapping is relevant if you use one of the
FPGA1403Tp1 with Multi-I/O Module frameworks. The signals are available at
the DS1514 ZIF I/O connector.

Inport Channel Connector Pin Signal

Data 1 c2 Analog Out 13
Channel 1 Signal
2 c3 Analog Out 13
Channel 2 Signal
3 c4 Analog Out 13
Channel 3 Signal
4 c5 Analog Out 13
Channel 4 Signal

Analog Out 13 settings Only common dialog settings. Refer to Common settings on page 624.

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Digital Out 5 description Block display If you select a Digital Out 5 channel from the channel list, the
block display changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Outputs a signal in the specified range.
If driven with 0, the hardware output is 0 V. If driven with 1, the hardware output is
set to the specified high supply voltage (VDRIVE).
The hardware output is only driven if the Enable port is set to 1, otherwise the
output is set to high impedance (High-Z).
Data Type: UFix_1_0
Update rate: FPGA clock frequency

Note

The frequency that can be generated is much smaller than the update rate. For
information on the electrical characteristics of the DS1552 Multi-I/O Module,
refer to Digital Out 5 Characteristics (MicroAutoBox III Hardware Installation
and Configuration ).

Enable Controls the hardware output. If set to 1, the hardware output reacts to the Data
outport, otherwise it is set to High-Z.
Data type: UFix_1_0
Output
Sim_Data Simulates an output signal in the same range as that specified for the real output
signal.
Available only if Enable simulation port is set on the Parameters page.
Output voltage: 0 V ... 45 V
Update rate: FPGA clock frequency

If the value of the Data inport exceeds the specified data width, only the lowest
bit is used.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

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I/O mapping The following I/O mapping is relevant if you use one of the
FPGA1403Tp1 with Multi-I/O Module frameworks. The signals are available at
the DS1514 ZIF I/O connector.

Inport Channel Connector Pin Signal

Data 1 F5 Digital Out 5 Channel 1 Signal
2 E5 Digital Out 5 Channel 2 Signal
3 E6 Digital Out 5 Channel 3 Signal
4 D2 Digital Out 5 Channel 4 Signal
5 D3 Digital Out 5 Channel 5 Signal
6 D4 Digital Out 5 Channel 6 Signal
7 D5 Digital Out 5 Channel 7 Signal
8 D6 Digital Out 5 Channel 8 Signal
9 C2 Digital Out 5 Channel 9 Signal
10 C3 Digital Out 5 Channel 10 Signal
11 C5 Digital Out 5 Channel 11 Signal
12 B2 Digital Out 5 Channel 12 Signal
13 B5 Digital Out 5 Channel 13 Signal
14 B6 Digital Out 5 Channel 14 Signal
15 A5 Digital Out 5 Channel 15 Signal
16 A6 Digital Out 5 Channel 16 Signal

Digital Out 5 settings The following settings on the Parameters page are specific to the Digital
Out 5 I/O function. For common dialog settings, refer to Common settings on
page 624.

Simulated VDRIVE pin Lets you select the voltage for the simulated high
side switch for all digital output channels in the range 0 … 45000 mV.

Note

You can specify the simulated voltage value only globally for all digital
output channels.

Digital InOut 6 (Out) Block display If you select a Digital InOut 6 (Out) channel from the channel
description list, the block display changes. The simulation ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Outputs a signal in the specified range.
If driven with 0, the hardware output is 0 V. If driven with 1, the hardware output is
3.3 V or 5 V according to the specified high supply voltage.
The hardware output is only driven if the Enable port is set to 1, otherwise the
output is set to high impedance (High-Z).
Data Type: UFix_1_0
Update rate: FPGA clock frequency

Note

The frequency that can be generated is smaller than the update rate. For
information on the electrical characteristics of the DS1552 Multi-I/O Module,
refer to Digital In/Out 6 Characteristics (MicroAutoBox III Hardware Installation
and Configuration ).

Enable Controls the hardware output. If set to 1, the hardware output reacts to the Data
outport, otherwise it is set to High-Z.
Data type: UFix_1_0
Output
Sim_Data Simulates an output signal in the same range as that specified for the real output
signal.
Available only if Enable simulation port is set on the Parameters page.
Output voltage: 0 V … 3.3 V or 0 V … 5 V
Update rate: FPGA clock frequency

If the value of the Data inport exceeds the specified data width, only the lowest
bit is used.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use one of the
FPGA1403Tp1 with Multi-I/O Module frameworks. The signals are available at
the DS1514 ZIF I/O connector.

Outport Channel Connector Pin Signal

Data 1 N2 Digital InOut 6 Channel 1
Signal
2 N3 Digital InOut 6 Channel 2
Signal
3 N4 Digital InOut 6 Channel 3
Signal

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Outport Channel Connector Pin Signal

4 N5 Digital InOut 6 Channel 4
Signal
5 N6 Digital InOut 6 Channel 5
Signal
6 M5 Digital InOut 6 Channel 6
Signal
7 M6 Digital InOut 6 Channel 7
Signal
8 L4 Digital InOut 6 Channel 8
Signal

You can use the same digital channel for input and output signals.

Digital InOut 6 (Out) settings The following settings on the Parameters page are specific to the Digital InOut
6 (Out) I/O function. For common dialog settings, refer to Common settings on
page 624.

High supply Lets you select the voltage for the high side switch (3.3 V or 5 V)
for all digital output channels.

Note

You can specify the high supply voltage value only globally for all digital
output channels.

LED Out description Block display If you select the LED Out channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Controls the FPGA status LED near the DS1514 ZIF I/O connector.
Data type: UFix_1_0
§ 0: LED lights up green.
§ 1: LED lights up orange.

If the value of the Data inport exceeds the specified data width, only the lowest
bit is used (=1).

I/O mapping No external connection.

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LED Out settings None

Sensor Supply description Block display If you select the Sensor Supply channel from the channel list,
the block display changes.

I/O characteristics The following table describes the ports of the block:

Port Description
Output
Sim_Data Simulates an output signal in the same range as that specified for the real output
signal.
Output voltage: 2 V … 20 V according to the specified supply voltage

I/O mapping The following I/O mapping is relevant if you use one of the
FPGA1403Tp1 with Multi-I/O Module frameworks. The signals are available at
the DS1514 ZIF I/O connector.

Outport Channel Connector Pin Signal

Sim_Data 1 b6 VSENS-
c6 VSENS+

Sensor Supply settings The following settings on the Parameters page are specific to the Sensor
Supply I/O function. For common dialog settings, refer to Common settings on
page 624.

Supply voltage Lets you enter the supply voltage a connected sensor is to be
driven with in the range 2000 mV … 20000 mV in steps of 100 mV.

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UART 3 (RS232) description Block display If you select an UART 3 (RS232) channel from the channel list,
the block display changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Read_Enable Specifies to start receiving a value.
After three clock cycles, the value is available and can be read from the RX
FIFO buffer. The value remains valid until the next Read_Enable signal.
Before you read data from the RX FIFO buffer, you should check the
Read_Fifo_Empty signal not to be set. The Read_Fifo_Empty signal
switches one clock cycle after the RX FIFO value has been read.
Do not use the Read_Data_Count signal (Read_Data_Count < 0) to check
the RX FIFO buffer, because it requires one additional clock cycle to get the
count value.
You can read one value per clock cycle from the UART.
Data Type: UFix_1_0
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.
Write_Enable Specifies to start sending a value.
The Write_Data value is written to the TX FIFO buffer, from which it is
automatically send to the TX output pin of the I/O connector using the
specified UART communication settings.
Write_Enable must be set to 1 for only one clock cycle.
Before you write data to the TX FIFO buffer, you should check the
Write_Fifo_Full signal not to be set. The Write_Fifo_Full signal switches
one clock cycle after the Write_Enable signal has been set.
Do not use the Write_Data_Count signal (Write_Data_Count < 2047) to
check the TX FIFO buffer, because it requires one additional clock cycle to
get the count value.
Data type: UFix_1_0
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.

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Port Description
The hardware output port is driven with the values from the TX FIFO buffer.
It is synchronously running to the UART clock defined by the UART baud
rate. The hardware port has inverted voltage levels of ‑6 V (logical high)
and +6 V (logical low).
Write_Data Specifies the value to be send.
The Write_Data signal is transferred at each clock cycle with Write_Enable
set to 1.
Data type: UFix_9_0
Data width: 1
Range: 0 … 511
Range exceeding is possible. Then, only the lowest bits 5 … 9 will be used.
Because of the unsigned data type, negative values will be interpreted as
positive values and the saturation will always be towards the maximum
value.
RTS Specifies the Ready‑To‑Send (RTS) signal.
The RTS/CTS handshake is handled by the user, the RTS signal is just passed
through and adapted to the physical layer.
Data type: UFix_1_0
Data width: 1
The hardware port is synchronously running to the UART clock defined by
the UART baud rate. The hardware port has voltage levels of +6 V (active,
logical high) and ‑6 V (inactive).
Sim_RX Simulates an RX value in the RX FIFO buffer.
Available only if Enable simulation RX port is set on the Parameters page.
Data type: Double
Data width: 1
The signal has to be in logical format with 1 as high and 0 as low, and
not in the inverted values of the physical layer (‑12 V high, +12 V low).
The format of this serial bitstream has to correspond to the specified UART
communication settings.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.
Sim_CTS Simulates the Clear‑To‑Send (CTS) hardware signal.
Available only if Enable simulation CTS port is set on the Parameters
page.
The RTS/CTS handshake is handled by the user. The Sim_CTS signal is just
passed through to CTS.
Data type: Double
Data width: 1
Range:
§ 0: CTS inactive
§ 1: CTS active
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.
Output
Read_Data_Count Outputs the number of new entries in the RX FIFO buffer.
Two clock cycles are required to return the number of entries.

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Port Description
If you only want to check whether a value is available in the RX FIFO buffer,
use the Read_Fifo_Empty signal instead of this.
Data type: UFix_11_0
Data width: 1
Range: 0 … 2047
The range can be exceeded, and saturation is performed to a minimum or
maximum value.
Read_Data Outputs the last read data from the RX FIFO buffer.
The read_data is available after three clock cycles after the Read_Enable
signal. The return value is 0, if the data is read before anything has been
received by the RX hardware input.
Data type: UFix_9_0
Data width: 1
Range: 0 … 511
It is not possible to exceed the range.
The hardware input receives serial data for the UART RX FIFO buffer using
inverted voltage levels of ‑6 V (logical high) and +6 V (logical low).
Read_Fifo_Empty Outputs the status of the RX FIFO buffer.
If the status of the buffer is not empty, then you can start reading the data
using the Read_Enable signal.
The Read_Fifo_Empty signal switches one clock cycle after the FIFO value
has been read.
Do not use the Read_Data_Count signal to check the status of the buffer
(Read_Data_Count>0), because this requires one additional clock cycle
before its value is valid.
Data type: UFix_1_0
Data width: 1
Range:
§ 0: The RX FIFO buffer is not empty.
§ 1: The RX FIFO buffer is empty.
It is not possible to exceed the range.
CTS Outputs the state of the Clear‑To‑Send (CTS) hardware port.
RTS/CTS handshake is handled by the user. CTS is just passed through with
conversion to logical 1 and 0.
Data type: UFix_1_0
Data width: 1
Range:
§ 0: CTS inactive
§ 1: CTS active
The CTS hardware port is synchronously running to the UART clock defined
by the UART baud rate. The hardware port has voltage levels of +6 V (active,
logical high) and ‑6 V (inactive).
It is not possible to exceed the range.
Write_Data_Count Outputs the number of values in the TX FIFO buffer.
The values in the TX FIFO buffer has not been sent already.
Do not use the Write_Data_Count signal to check the status of the buffer
(Write_Data_Count<2047), because this requires two clock cycles before its

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Port Description
value is valid, instead of one clock cycle when using the Write_Fifo_Full
signal.
Data type: UFix_11_0
Data width: 1
Range: 0 … 2047
It is not possible to exceed the range.
Write_Fifo_Full Outputs the status of the TX FIFO buffer.
You can use the signal to check the TX FIFO buffer before you start writing
data to the buffer. The Write_Fifo_Full signal switches one clock cycle after
the Write_Enable signal has been set.
Data type: UFix_1_0
Data width: 1
Range:
§ 0: The TX FIFO buffer is not full.
§ 1: The TX FIFO buffer is full.
It is not possible to exceed the range.
Sim_TX Simulates the TX hardware signal.
Available only if Enable simulation TX port is set on the Parameters page.
The signal is in logical format and not in inverted values from the physical
layer (‑6 V high, +6 V low). The format of the serial bitstream corresponds to
the specified UART communication settings.
Data type: Double
Data width: 1
Range:
§ 0: Low
§ 1: High
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.
Sim_RTS Simulates the Ready‑To‑Send (RTS) hardware signal.
Available only if Enable simulation RTS port is set on the Parameters
page.
The signal is in logical format and only passed through to the RTS signal.
Data type: Double
Data width: 1
Range:
§ 0: RTS inactive
§ 1: RTS active
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

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I/O mapping The following I/O mapping is relevant if you use one of the
FPGA1403Tp1 with Multi-I/O Module frameworks. The signals are available at
the DS1514 ZIF I/O connector.

Inport Connector Pin Signal

UART 1 (RS232)
Write_Data a5 TX1
RTS a6 RTS1
Read_Data b5 RX1
CTS a4 CTS1
UART 2 (RS232)1)
Write_Data Z5 TX2
RTS Z6 RTS2
Read_Data Z3 RX2
CTS Z4 CTS2
1) To use UART 2, your DS1552 has to be modified by dSPACE.

UART 3 (RS232) settings The following settings on the Parameters page are specific to the UART 3
(RS232) I/O function.

Baud rate Lets you select the baud rate in the range 50 … 1,000,000 baud
(bits per second) from the given list.

Word length Lets you select the word length in the range 5 … 9 bits. The
word length includes the number of data bits and the optional parity bit.
For example, if a message consists of 8 data bits and the parity bit, you have to
set the word length to 9.

Note

The parity bit cannot be controlled via dialog setting. You have to consider
an optional parity bit in your own model implementation.

The Write_Data and Read_Data ports handle raw bits. If you want to use
a parity bit with the Write_Data port, you have to explicitly generate it and
provide it as the last bit of the port. If you want to use a parity bit with the
Read_Data port, you have to explicitly check it and read it as the last bit of the
port.

Stop bits Lets you select the number of stop bits in the range 1, 1.5 and 2.

Enable simulation RX port Lets you enable an inport for offline simulation
data. The Sim_RX inport is added to the block to connect it to simulation data
coming from a Simulink-based I/O environment model.

Enable simulation CTS port Lets you enable an inport for offline simulation
data. The Sim_CTS inport is added to the block to connect it to simulation data
coming from a Simulink-based I/O environment model.

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Enable simulation TX port Lets you enable an outport for offline simulation
data. The Sim_TX outport is added to the block to connect it to a Simulink-based
I/O environment model.

Enable simulation RTS port Lets you enable an outport for offline
simulation data. The Sim_RTS outport is added to the block to connect it to
a Simulink-based I/O environment model.

UART 3 (RS422/485) Block display If you select an UART (RS422/485) channel from the channel
description list, the block display changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Read_Enable Specifies to start receiving a value.
After three clock cycles, the value is available and can be read from the RX
FIFO buffer. The value remains valid until the next Read_Enable signal.
Before you read data from the RX FIFO buffer, you should check the
Read_Fifo_Empty signal not to be set. The Read_Fifo_Empty signal
switches one clock cycle after the RX FIFO value has been read.
Do not use the Read_Data_Count signal (Read_Data_Count < 0) to check
the RX FIFO buffer, because it requires one additional clock cycle to get the
count value.
You can read one value per clock cycle from the UART.
Data Type: UFix_1_0
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.
Write_Enable Specifies to start sending a value.
The Write_Data value is written to the TX FIFO buffer, from which it is
automatically send to the TX output pin of the I/O connector using the
specified UART communication settings.
Write_Enable must be set to 1 for only one clock cycle.

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Port Description
Before you write data to the TX FIFO buffer, you should check the
Write_Fifo_Full signal not to be set. The Write_Fifo_Full signal switches
one clock cycle after the Write_Enable signal has been set.
Do not use the Write_Data_Count signal (Write_Data_Count < 2047) to
check the TX FIFO buffer, because it requires one additional clock cycle to get
the count value.
Data type: UFix_1_0
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.
The hardware output port is driven with the values from the TX FIFO buffer. It
is synchronously running to the UART clock defined by the UART baud rate.
The hardware port has inverted voltage levels of ‑6 V (logical high) and +6 V
(logical low).
Write_Data Specifies the value to be send.
The Write_Data signal is transferred at each clock cycle with Write_Enable
set to 1.
Data type: UFix_9_0
Data width: 1
Range: 0 … 511
Range exceeding is possible. Then, only the lowest bits 5 … 9 will be used.
Because of the unsigned data type, negative values will be interpreted as
positive values and the saturation will always be towards the maximum
value.
Driver_Enable Specifies to enable the output driver in the transceiver for data transmission.
If you use the UART (RS485/422) function in half-duplex mode, the output
driver must be disabled while receiving data.
Data type: UFix_1_0
Data width: 1
Sim_RX Simulates an RX value in the RX FIFO buffer.
Available only if Enable simulation RX port is set on the Parameters page.
Data type: Double
Data width: 1
The signal has to be in logical format with 1 as high and 0 as low, and
not in the inverted values of the physical layer (‑12 V high, +12 V low).
The format of this serial bitstream has to correspond to the specified UART
communication settings.
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.
Output
Read_Data_Count Outputs the number of new entries in the RX FIFO buffer.
Two clock cycles are required to return the number of entries.
If you only want to check whether a value is available in the RX FIFO buffer,
use the Read_Fifo_Empty signal instead of this.
Data type: UFix_11_0
Data width: 1
Range: 0 … 2047

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Port Description
The range can be exceeded, and saturation is performed to a minimum or
maximum value.
Read_Data Outputs the last read data from the RX FIFO buffer.
The read_data is available after three clock cycles after the Read_Enable
signal. The return value is 0, if the data is read before anything has been
received by the RX hardware input.
Data type: UFix_9_0
Data width: 1
Range: 0 … 511
It is not possible to exceed the range.
The hardware input receives serial data for the UART RX FIFO buffer using
inverted voltage levels of ‑6 V (logical high) and +6 V (logical low).
Read_Fifo_Empty Outputs the status of the RX FIFO buffer.
If the status of the buffer is not empty, then you can start reading the data
using the Read_Enable signal.
The Read_Fifo_Empty signal switches one clock cycle after the FIFO value
has been read.
Do not use the Read_Data_Count signal to check the status of the
buffer (Read_Data_Count>0), because this requires one additional clock cycle
before its value is valid.
Data type: UFix_1_0
Data width: 1
Range:
§ 0: The RX FIFO buffer is not empty.
§ 1: The RX FIFO buffer is empty.
It is not possible to exceed the range.
Write_Data_Count Outputs the number of values in the TX FIFO buffer.
The values in the TX FIFO buffer has not been sent already.
Do not use the Write_Data_Count signal to check the status of the buffer
(Write_Data_Count<2047), because this requires two clock cycles before its
value is valid, instead of one clock cycle when using the Write_Fifo_Full
signal.
Data type: UFix_11_0
Data width: 1
Range: 0 … 2047
It is not possible to exceed the range.
Write_Fifo_Full Outputs the status of the TX FIFO buffer.
You can use the signal to check the RX FIFO buffer before you start writing
data to the buffer. The Write_Fifo_Full signal switches one clock cycle after
the Write_Enable signal has been set.
Data type: UFix_1_0
Data width: 1
Range:
§ 0: The TX FIFO buffer is not full.
§ 1: The TX FIFO buffer is full.
It is not possible to exceed the range.

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Port Description
Sim_TX Simulates the TX hardware signal.
Available only if Enable simulation TX port is set on the Parameters page.
The signal is in logical format and not in inverted values from the physical
layer (‑6 V high, +6 V low). The format of the serial bitstream corresponds to
the specified UART communication settings.
Data type: Double
Data width: 1
Range:
§ 0: Low
§ 1: High
Range exceeding is possible (using input bit widths > 1) and will be cast to 1
bit by using only the lowest bit.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use one of the
FPGA1403Tp1 with Multi-I/O Module frameworks. The signals are available
at the DS1514 ZIF I/O connector. The mapping differs when using the UART
(RS422/485) in full-duplex or half-duplex mode.
Full-duplex mode:

Inport Connector Pin Signal

UART 1 (RS422/485)
Write_Data a5 TX‑1
a6 TX+1
Read_Data b5 RX‑1
a4 RX+1
UART 2 (RS422/485)1)
Write_Data Z5 TX‑2
Z6 TX+2
Read_Data Z3 RX‑2
Z4 RX+2
1) To use UART 2, your DS1552 has to be modified by dSPACE.
Half-duplex mode:

Inport Connector Pin Signal

UART 1 (RS422/485)
Write_Data a5 BM1 (RX‑1/TX‑1)
a6 BP1 (RX+1/TX+1)
Read_Data b5 ‑1)

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Inport Connector Pin Signal

a4 ‑1)
UART 2 (RS422/485)2)
Write_Data Z5 BM2 (RX‑2/TX‑2)
Z6 BP2 (RX+2/TX+2)
Read_Data Z3 ‑1)
Z4 ‑1)
1) Do not connect, TX signals are available via BM and BP signals.
2) To use UART 2, your DS1552 has to be modified by dSPACE.

UART 3 (RS422/485) settings The following settings on the Parameters page are specific to the UART 3
(RS422/485) I/O function.

Baud rate Lets you select the baud rate in the range 50 … 10,000,000 baud
(bits per second) from the given list.

Word length Lets you select the word length in the range 5 … 9 bits. The
word length includes the number of data bits and the optional parity bit.
For example, if a message consists of 8 data bits and the parity bit, you have to
set the word length to 9.

Note

The parity bit cannot be controlled via dialog setting. You have to consider
an optional parity bit in your own model implementation.

The Write_Data and Read_Data ports handle raw bits. If you want to use
a parity bit with the Write_Data port, you have to explicitly generate it and
provide it as the last bit of the port. If you want to use a parity bit with the
Read_Data port, you have to explicitly check it and read it as the last bit of the
port.

Stop bits Lets you select the number of stop bits in the range 1, 1.5 and 2.

Mode Lets you select the mode for receiving messages.

§ Full duplex mode
You can simultaneously send and receive signals on the UART channel.
§ Half duplex mode
You can send or receive signals on the UART channel, but you cannot do both
at the same time.

Termination Lets you enable an internal termination between RX‑ and RX+
and between TX‑ and TX+.

Setting Meaning
Open No termination
Terminated The RX and TX signals are terminated via an
internal 120 Ω resistor.

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Enable simulation RX port Lets you enable an inport for offline simulation
data. The Sim_RX inport is added to the block to connect it to simulation data
coming from a Simulink-based I/O environment model.

Enable simulation TX port Lets you enable an outport for offline simulation
data. The Sim_TX outport is added to the block to connect it to a Simulink-based
I/O environment model.

User Clock Out 1 … 32 Block display If you select the User Clock Out channel from the channel list,
description the block display changes.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
User Clock Clock signal for the clock domain used within the subsystem to which the block
belongs. For more information, refer to Using Multiple Clock Domains for FPGA
Modeling (FPGA Programming Blockset Guide ).
Data type: UFix_1_0
Data width: 1

I/O mapping No external connection.

User Clock Out 1 … 32 The Parameters page provides the following dialog setting:
settings
User clock period Lets you specify the expected clock period used within the
subsystem to which the block belongs. A common value for the clock period is in
the range 20 ns ... 4 ns (50 MHz ... 250 MHz).
The value is used during the build process when no user clock is available, for
example, to specify timing constraints.

User clock offline simulation period Lets you specify the clock period to be
used in offline simulation mode. The value must be greater than or equal to the
value of the User clock period parameter.

Related topics Basics

Modeling External I/O Access (FPGA Programming Blockset Guide )

Modeling UART Communication (FPGA Programming Blockset Guide )

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Scaling Page (FPGA_IO_WRITE_BL)

Purpose To specify the inverting, scaling, and saturation settings for the selected I/O
function.

Description You can modify the I/O signal of the selected I/O function if you select the
Enable FPGA test access and scaling parameter on the FPGA Access page
of the FPGA_SETUP_BL block dialog. The possible modifications depend on the
selected I/O function.

Common settings The following settings on the Scaling page are common to the I/O functions that
you can select on the Unit page.

Enable FPGA test access and scaling for this block Lets you disable FPGA
test access and scaling for the selected I/O function.

Analog out settings The following settings on the Scaling page are specific to the Analog Out 13
I/O function.

Note

Scaling of analog I/O signals also effects the signal path:

§ If you use the parameters of the Scaling page to scale analog signals, the
data type of the Data port is set to the specified data format for scaling.
For more information, refer to How to Change the Data Type of Analog
Signals (FPGA Programming Blockset Guide ).
§ FPGA scaling of analog I/O signals might cause additional latency. If
the latency can be calculated during the modeling, analog I/O functions
display the total latency.

Scaling format Lets you select the data format for scaling and saturation.
§ Signed/Unsigned:
The values of the parameters for scaling and saturation are in fixed‑point
format. The signed fixed-point format reserves one bit for the sign.
You can specify the number of bits and the binary point position with the
Number of bits and Binary point (fraction width) parameters.
§ Single:
The values of the parameters for scaling and saturation are 32-bit values in
the single-precision floating‑point format with a fraction width of 24, which
complies with the IEEE 754 standard (single).

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§ Double:
The values of the parameters for scaling and saturation are 64-bit values in
the double-precision floating‑point format with a fraction width of 53, which
complies with the IEEE 754 standard (double).

Number of bits This setting depends on the Scaling format setting.

§ Fixed-point format:
Lets you specify the bit width of the scaling parameters and the Data port in
the range 1 ... 64.
§ Floating-point format:
Displays the bit width of the scaling parameters and the Data port.

Binary point (fraction width) This setting depends on the Scaling format
setting.
§ Fixed-point format:
Lets you specify the binary point position of the scaling parameters and the
Data port. The position 0 represents the lowest bit position
§ Floating-point format:
Displays the fraction width of the scaling parameters and the Data port.

Scaling factor Lets you specify the scaling factor. The scaling factor gains
the signal of the Data port or the replace value (FPGA test access) before it is
saturated.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Scaling factor parameter
will be saturated to the minimum and maximum values that the scaling format
and the hardware supports.

Scaling offset Lets you add a signal offset after the signal of the Data port is
scaled with the scaling factor.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Scaling offset parameter
will be saturated to the minimum and maximum values that the scaling format
and the hardware supports.

Saturation minimum value Lets you specify the minimum value to which
the scaled Data inport signal is saturated before it is output via an analog output
channel.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation minimum
value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

Saturation maximum value Lets you specify the maximum value to which
the scaled Data inport signal is saturated before it is output via an analog output
channel.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation maximum
value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

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Multiplier latency Lets you specify the latency that is caused by the
multiplier for scaling. The multiplier is used to multiply the signal with the value
of the Scaling factor parameter.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The multiplication will be implemented without latency.
§ 1 ... 20: The multiplication will be implemented with the specified latency.
Use this value range in the exceptional case that the optimized latency cause
timing problems during the build process.

Adder latency Lets you specify the latency that is caused by the offset adder.
The offset adder is used to add the value of the Scaling offset parameter to the
signal.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The adding will be implemented without latency.
§ 1 ... 20: The adding will be implemented with the specified latency.
Use this value range in the exceptional case that the optimized latency causes
timing problems during the build process.

Digital outsettings The following settings on the Scaling page are specific to the Digital Out 5 and
Digital InOut 6 (out) I/O functions.

Invert polarity Lets you adapt the electrical output signal:

§ Disabled:
If driven with 1, the hardware outputs a high-level signal.
If driven with 0, the hardware outputs a low-level signal.
§ Enabled:
If driven with 1, the hardware outputs a low-level signal.
If driven with 0, the hardware outputs a high-level signal.

LED Out settings The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

Sensor Supply settings The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

UART settings The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

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Related topics Basics

Basics on FPGA Test Access and Scaling (FPGA Programming Blockset Guide )

FPGA_INT_BL (FPGA1403Tp1 with Multi-I/O Module Settings)

Purpose To configure the FPGA interrupt channel after you load one of the following
frameworks:
§ FPGA1403Tp1 (7K325) with Multi-I/O Module (DS1552)
§ FPGA1403Tp1 (7K325) with Multi-I/O Module (DS1552B1)

Where to go from here Information in this section

Parameters Page (FPGA_INT_BL)............................................................ 645

To enable the simulation port for an interrupt.

Information in other sections

Unit Page (FPGA_INT_BL)......................................................................... 64

To specify the interrupt channel used to trigger a task in the processor
model.

Parameters Page (FPGA_INT_BL)

Purpose To enable the simulation port for an interrupt.

Description The FPGA1403Tp1 with Multi-I/O Module frameworks provide 8 interrupt lines.

An interrupt is requested if the Int port is set to 1 for at least one clock cycle. If
you set the Int port to 0, the last interrupt is not released but saved. An interrupt
is edge-triggered.

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Int description Block display The figure below shows the block display with the optional
simulation port.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Int Provides the interrupt request line.
Data type: UFix_1_0
0 to 1: Interrupt is requested (edge-triggered).
0: No interrupt is requested. Last requested interrupt is saved.
Output
Sim_Int Simulates an interrupt by performing a function-call to enable a function-call
subsystem.
Available only if Enable simulation port is set on the Parameters page.
Data type: Function call

Int settings Enable simulation port Lets you enable an outport for a simulated interrupt.
The Sim_Int outport is added to the block to connect it to a function-call
subsystem in the processor model.

Related topics HowTos

How to Trigger Interrupt-Driven Processor Tasks (FPGA Programming Blockset

Guide )

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Block Settings for the FPGA1403Tp1 with Engine Control I/O

Module Framework
Introduction The block dialogs provide hardware-specific settings after you load the
FPGA1403Tp1 (7K325) with Engine Control Module (DS1554) framework for
the MicroAutoBox III.

Where to go from here Information in this section

FPGA_XDATA_READ_BL (FPGA1403Tp1 with Engine Control I/O

Module Settings)................................................................................... 647
To configure read access to intermodule bus data in the FPGA model.

FPGA_XDATA_WRITE_BL (FPGA1403Tp1 with Engine Control I/O

Module Settings)................................................................................... 657
To configure write access to intermodule bus data in the FPGA model.

FPGA_IO_READ_BL (FPGA1403Tp1 with Engine Control I/O

Module Settings)................................................................................... 666
To configure read access to analog and digital input signals in the FPGA
model.

FPGA_IO_WRITE_BL (FPGA1403Tp1 with Engine Control I/O

Module Settings)................................................................................... 683
To configure write access to analog and digital output signals in the
FPGA model.

FPGA_INT_BL (FPGA1403Tp1 with Engine Control I/O Module

Settings)................................................................................................ 691
To configure the FPGA interrupt channel.

FPGA_XDATA_READ_BL (FPGA1403Tp1 with Engine Control

I/O Module Settings)
Purpose To configure read access to the local bus data in the FPGA model when using the
DS1554 Engine Control I/O Module framework.

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Where to go from here Information in this section

Parameters Page (FPGA_XDATA_READ_BL)............................................ 648

To specify the data format and specific settings for the selected access
type.

Information in other sections

Unit Page (FPGA_XDATA_READ_BL)......................................................... 46

To specify the general configuration for the FPGA board's processor bus
read access.

Parameters Page (FPGA_XDATA_READ_BL)

Purpose To specify the data format and specific settings for the selected access type.

Description The DS1554 Engine Control I/O Module framework provides the following access
types that you can select on the Unit page of the block's dialog:
§ Register/Register64
If you select Register or Register64 as the access type, the data is read from
an intermodule bus register. 128 registers are available with a data width of
32 bits each and 128 registers with a data width of 64 bits each. The values
are transmitted element by element.
If you want to access data from several registers simultaneously, you can group
these registers by specifying the same group identifier for them.
Ungrouped registers are automatically combined into one register group with
group ID Ungrouped to optimize data transfer. Since register groups can be
only accessed by one task, you have to explicitly group registers which are
used by different tasks.
§ Buffer/Buffer64
If you select Buffer or Buffer64 as the access type, the data is read from an
intermodule bus buffer. 32 buffers are available that provides elements with a
data width of 32 bits each and 32 buffers that provides elements with a data
width of 64 bits each. Each buffer has a variable buffer size of 1 up to 32768
elements.
§ Bus
If you select Bus as the access type, the data is read from an intermodule
bus buffer. The bus access type lets you use Simulink buses to model the data
exchange between the processor and the FPGA.

There are settings that are common and settings that are specific to each access
type.

For more information, refer to Details on the access types on page 46.

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Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_XDATA_READ_BL block.

Binary point position (or fraction width) This setting depends on the
format selected in the Format setting.
§ signed/unsigned
The values of the Data outport are in fixed‑point format.
You can specify the binary point position of the 32‑bit value in the range
0 … 32 and the binary point position of the 64‑bit value in the range 0 … 64.
0 represents the lowest bit position, 32 or 64 the highest bit position.
§ floating‑point
The values of the Data outport are in floating‑point format. The fraction width
is displayed.

Format Lets you select the data format of the Data outport.
§ signed/unsigned
The values of the Data outport are in fixed‑point format with or without one
bit reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
64-bit fixed-point data types are converted to double. Therefore, the fixed-
point resolution of fixed-point data types is restricted to 53 bits.
§ floating‑point
The values of the Data outport are in floating‑point format.
The 32‑bit data value supports the single-precision floating‑point format with a
fraction width of 24, which complies with the IEEE 754 standard (single).
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is displayed in the Binary point position (or fraction
width) setting.

Enable simulation port Lets you enable an inport for offline simulation data.
The Sim_Data inport is added to the block so you can connect it to any Simulink
signal used for simulation.

Simulation ports sample time Lets you specify the sample time of the
ports used for simulation, for example, Sim_Data. By default, the sample time
is inherited. You must only specify the sample time explicitly if the modeling
situation inhibits to inherit the sample time, for example, if the corresponding
PROC block is part of an asynchronous task or is used for multiple access to the
same channel.

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Register In description Block display If you specify the register access type, the block display
changes. The simulation ports are optionally displayed.

I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Sim_Data Simulates an intermodule bus data exchange including floating-point to fixed-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Output
Data Outputs a 32-bit data value to be read from an intermodule bus register. The data
format depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Data New Outputs a flag that indicates the changes of the register status. If the flag changes
from 0 to 1 and then to 0 again, the requested register contains a new value. The
flag is set to 1 only within one clock cycle.
Data type: UFix_1_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register In settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 649.

Register group ID Lets you specify a number in the range 1 … 63 to create

register groups. All registers – 32‑bit and 64‑bit registers – which you specified
with the same group ID are read from the intermodule bus sequentially and then
provided to the FPGA application simultaneously.
Specify 0 for ungrouped read access.

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Buffer In description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Sim_Data Simulates an intermodule bus data exchange including floating-point to fixed-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768
Address Specifies an element in the buffer you want to read. The block requires 3 clock
cycles to update the value of the Data outport according to the specified address.
The maximum port range depends on the specified buffer size in the Parameters
page. The valid port range depends on the number of elements currently in the
buffer (see Data Count outport). If you request data from an address that is greater
than the Data Count value, the output of the Data outport is undefined. The first
element of a buffer is addressed by 0.
Data type: UFix_16_0
Output
Data Outputs a 32-bit data value to be read from an intermodule bus buffer. The data
format depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Data New Outputs a flag that indicates the changes of the buffer status. If the flag changes
from 0 to 1 and then to 0 again, the requested buffer contains new values and is
ready to be read. The flag is set to 1 only within one clock cycle.
Data type: UFix_1_0
Data Count Outputs the number of elements in the current buffer.
The maximum range depends on the specified buffer size. You can use the value to
define the valid range for the Address inport of 0 … (Data Count -1).
Data type: UFix_16_0

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Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Buffer In settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 649.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.
The maximum range of the Address inport depends on the buffer size.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 32-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Register64 In description Block display If you specify the register access type, the block display
changes. The simulation ports are optionally displayed.

I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Sim_Data Simulates an intermodule bus data exchange including floating-point to fixed-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Output
Data Outputs a 64-bit data value to be read from an intermodule bus register. The data
format depends on the related dialog settings.

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Port Description
Data type:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double. Therefore, the fixed-point
resolution of fixed-point data types is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Data New Outputs a flag that indicates the changes of the register status. If the flag changes
from 0 to 1 and then to 0 again, the requested register contains a new value. The
flag is set to 1 only within one clock cycle.
Data type: UFix_1_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register64 In settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 649.

Register group ID Lets you specify a number in the range 1 … 63 to create

register groups. All registers – 32‑bit and 64‑bit registers – which you specified
with the same group ID are read from the intermodule bus sequentially and then
provided to the FPGA application simultaneously.
Specify 0 for ungrouped read access.

Buffer64 In description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Sim_Data Simulates an intermodule bus data exchange including floating-point to fixed-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768
Address Specifies an element in the buffer you want to read. The block requires 3 clock
cycles to update the value of the Data outport according to the specified address.
The maximum port range depends on the specified buffer size in the Parameters
page. The valid port range depends on the number of elements currently in the
buffer (see Data Count outport). If you request data from an address that is greater
than the Data Count value, the output of the Data outport is undefined. The first
element of a buffer is addressed by 0.
Data type: UFix_16_0
Output
Data Outputs a 64-bit data value to be read from an intermodule bus buffer. The data
format depends on the related dialog settings.
Data type if the bus transfer mode is disabled on the Parameters page:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double. Therefore, the fixed-point
resolution of fixed-point data types is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Data New Outputs a flag that indicates the changes of the buffer status. If the flag changes
from 0 to 1 and then to 0 again, the requested buffer contains new values and is
ready to be read. The flag is set to 1 only within one clock cycle.
Data type: UFix_1_0
Data Count Outputs the number of elements in the current buffer.
The maximum range depends on the specified buffer size. You can use the value to
define the valid range for the Address inport of 0 … (Data Count -1).
Data type: UFix_16_0

Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Buffer64 In settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 649.

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Buffer size Lets you specify the size of the buffer in the range 1 … 32768.
The maximum range of the Address inport depends on the buffer size.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Bus In description Block display If you specify the access type, the block display changes. The
simulation port is optionally displayed.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Sim_Data Simulates a bus data exchange including floating-point to fixed-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768
Output
Data Outputs the signals of the Simulink bus. The data types of the signals depend
on the bus topology that is copied via Copy bus topology from corresponding
processor block or Copy bus topology from gcb on the Parameters page. The
maximum bit wide is 64 bits.
The resolution of the data types is restricted to 53 bits, because the data type of the
received bus signals from the processor application is double and the block converts
the signals to the signal data types.
Data New Outputs a flag that indicates the changes of the buffer status. If the flag changes
from 0 to 1 and then to 0 again, the requested buffer contains new values and is
ready to be read. The flag is set to 1 only within one clock cycle.
Data type: UFix_1_0

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Note

The range can be exceeded for the Data outport. The outport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Bus In settings The following dialog settings are specific for the Bus access type. For common
dialog settings, refer to Common settings on page 649.

Buffer size Displays the size of the buffer in the range 1 … 32,768. The
buffer size depends on the number of bus signals.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1,024
words. For example, a buffer with a buffer size of 1 allocates a memory
block of 1,024 words with a data width of 64-bit in the FPGA memory. This
applies to any buffer and the related swinging buffer.

Edit bus topology Opens a dialog to display and configure the

bus signals. For more information, refer to Bus Editor Dialog -
FPGA_XDATA_READ_BL/FPGA_XDATA_WRITE_BL on page 66.

Copy bus topology from corresponding processor block Lets you copy an
existing bus topology from the corresponding processor block in the processor
model. For more information, refer to How to Use Simulink Buses of the
Processor Model to Model the Processor Communication (FPGA Programming
Blockset Guide ).

Copy bus topology from gcb Lets you copy an existing FPGA bus topology
from the selected Simulink Bus Creator block, subsystem inport block, or
subsystem outport block to the Data port of the Bus In block.
You cannot copy a bus topology from the processor model, because these
topologies do not include the FPGA data types. For instructions, refer to How
to Use Simulink Buses of the FPGA Model to Model Processor Communication
(FPGA Programming Blockset Guide ).

Reset bus topology Lets you clear the bus topology of the Data port.

Related topics Basics

Modeling Processor Model Access (FPGA Programming Blockset Guide )

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FPGA_XDATA_WRITE_BL (FPGA1403Tp1 with Engine Control

I/O Module Settings)
Purpose To configure write access to intermodule bus data in the FPGA model when
using the FPGA1403Tp1 (7K325) with Engine Control I/O Module (DS1554)
framework.

Where to go from here Information in this section

Parameters Page (FPGA_XDATA_WRITE_BL)........................................... 657

To specify the data format and specific settings for the selected access
type.

Information in other sections

Unit Page (FPGA_XDATA_WRITE_BL)............................................. .......... 51

To specify the general configuration for the FPGA board's processor bus
write access.

Parameters Page (FPGA_XDATA_WRITE_BL)

Purpose To specify the data format and specific settings for the selected access type.

Description The FPGA1403Tp1 (7K325) with Engine Control I/O Module (DS1554)
framework provides the following access types, which you can select on the
Unit page of the block's dialog:
§ Register/Register64
If you select Register or Register64 as the access type, the data is written to
an intermodule bus register. 128 registers are available with a data width of
32 bits each and 128 registers with a data width of 64 bits each. The values
are transmitted element by element. If you want to access data from several
registers simultaneously, you can group these registers by specifying the same
group identifier for them.
§ Buffer/Buffer64
If you select Buffer or Buffer64 as the access type, the data is written to an
intermodule bus buffer. 32 buffers are available that provides elements with a
data width of 32 bits each and 32 buffers that provides elements with a data
width of 64 bits each. Each buffer has a variable buffer size of 1 up to 32768
elements.

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§ Bus
If you select Bus as the access type, the data is written to an intermodule
bus buffer. The bus access type lets you use Simulink buses to model the data
exchange between the processor and the FPGA.

There are settings that are common and settings that are specific to each access
type.

For more information, refer to Details on the access types on page 51.

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_XDATA_WRITE_BL block.

Binary point position (or fraction width) This setting depends on the
format selected in the Format setting.
§ signed/unsigned
The values of the Data inport are in fixed‑point format.
You can specify the binary point position of the 32‑bit value in the range
0 … 32 and the binary point position of the 64‑bit value in the range 0 … 64.
0 represents the lowest bit position, 32 or 64 the highest bit position.
§ floating‑point
The values of the Data inport are in floating‑point format. The fraction width
is displayed.

Format Lets you select the data format of the Data inport.
§ signed/unsigned
The values of the Data inport are in fixed‑point format with or without one bit
reserved for the sign.
You can specify the binary point position in the Binary point position (or
fraction width) setting.
64-bit fixed-point data types are converted to double. Therefore, the fixed-
point resolution of fixed-point data types is restricted to 53 bits.
§ floating‑point
The values of the Data inport are in floating‑point format.
The 32‑bit data value supports the single-precision floating‑point format with a
fraction width of 24, which complies with the IEEE 754 standard (single).
The 64‑bit data value supports the double-precision floating‑point format with
a fraction width of 53, which complies with the IEEE 754 standard (double).
The fraction width is displayed in the Binary point position (or fraction
width) setting.

Enable simulation data port Lets you enable an outport for offline
simulation data. The Sim_Data outport is added to the block so you can connect
it to any Simulink signal used for simulation.

Simulation ports sample time Lets you specify the sample time of the ports
used for simulation, for example, Sim_Data and Sim_Status. By default, the
sample time is inherited. You must only specify the sample time explicitly, if
the modeling situation inhibits to inherit the sample time, for example, if the
corresponding PROC block is part of an asynchronous task or is used for multiple
access to the same channel.

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Register Out description Block display If you specify the register access type, the block display
changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Data Specifies a 32-bit data value to be written to an intermodule bus register. The data
format depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Output
Sim_Data Simulates an intermodule bus data exchange including fixed-point to floating-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1

Note

The range can be exceeded for the Data inport. The inport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register Out settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 658.

Register group ID Lets you specify a number in the range 1 … 63 to create

register groups. All registers – 32‑bit and 64‑bit registers – which you specified
with the same group ID are sampled simultaneously in the FPGA application. The
values therefore form a consistent data group that is written to the intermodule
bus.

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Buffer Out description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a 32-bit data value to be written to an intermodule bus buffer. The data
format depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_32_<Binary point position>/Fix_32_<Binary point position>
§ Floating‑point format
XFloat_8_24
Enable Specifies the current valid Data port value.
Data type: UFix_1_0
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.
Ready Explicitly specifies the buffer state as ready to send immediately, even if the buffer
is not completely filled. The data values are written to a new buffer in the following
clock cycle. While the port value is 1, the buffer switches every clock cycle. You are
therefore recommended to set the value for only one clock cycle. If the buffer is
completely filled, it is automatically switched, and the data values are stored in a
new buffer.
Data type: UFix_1_0
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready to send, even if it is not completely filled. The
buffer is switched and the data values are accessible via the intermodule bus in
the following clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.
Output
Sim_Data Simulates an intermodule bus data exchange including fixed-point to floating-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768. The vector width depends on the specified buffer size.

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Port Description
Overflow Outputs a flag that indicates that a buffer overflow occurred. An overflow occurs if
the old buffer is not read completely before a new buffer is ready to be read.
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.
Data type: UFix_1_0
Sim_Status Outputs information about the simulated data exchange on the Sim_Data outport.
Available only if the access type is specified as Buffer, and Enable simulation port
is set on the Parameters page.
Data type: UInt32
Data width: 3
§ Sim_Status[0]: Contains the number of valid elements in the Sim_Data vector.
§ Sim_Status[1]: Indicates whether the current buffer contains new or old values. It
is 1 if the buffer contains new values.
§ Sim_Status[2]: Indicates whether a buffer overflow occurred. At least one buffer
was not read and its data was lost before the currently read buffer was filled.

Buffer Out settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 658.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 32-bit in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation status port Lets you enable an outport to get status
information about the simulation data that is available when you enable the
simulation data port. The Sim_Status outport is added to the block.

Register64 Out description Block display If you specify the register access type, the block display
changes. The simulation ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block in
register access mode:

Port Description
Input
Data Specifies a 64-bit data value to be written to an intermodule bus register. The data
format depends on the related dialog settings.
Data type:
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double. Therefore, the fixed-point
resolution of fixed-point data types is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Output
Sim_Data Simulates an intermodule bus data exchange including fixed-point to floating-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1

Note

The range can be exceeded for the Data inport. The inport's value is
then cast to the specified data format. This might cause truncation and
bit wrapping if insufficient bits are used before and after the binary point
position to represent the input value.

Register64 Out settings The following dialog settings are specific for the Register access type. For
common dialog settings, refer to Common settings on page 658.

Register group ID Lets you specify a number in the range 1 … 63 to create

register groups. All registers – 32‑bit and 64‑bit registers – which you specified
with the same group ID are sampled simultaneously in the FPGA application. The
values form therefore a consistent data group that is written to the intermodule
bus.

Buffer64 Out description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a 64-bit data value to be written to an intermodule bus buffer. The data
format depends on the related dialog settings.
§ Fixed‑point format
UFix_64_<Binary point position>/Fix_64_<Binary point position>
64-bit fixed-point data types are converted to double. Therefore, the fixed-point
resolution of fixed-point data types is restricted to 53 bits.
§ Floating‑point format
XFloat_11_53
Enable Specifies the current valid Data port value.
Data type: UFix_1_0
§ 0: The Data value to be written is not stored in the buffer.
§ 1: The Data value to be written is stored in the buffer. The value of the current
clock cycle is used.
Ready Explicitly specifies the buffer state as ready to send immediately, even if the buffer
is not completely filled. The data values are written to a new buffer in the following
clock cycle. While the port value is 1, the buffer switches every clock cycle. You are
therefore recommended to set the value for only one clock cycle. If the buffer is
completely filled, it is automatically switched, and the data values are stored in a
new buffer.
Data type: UFix_1_0
§ 0: The buffer is not ready to send.
§ 1: The buffer is marked as ready o send, even if it is not completely filled. The
buffer is switched and the data values are accessible via intermodule bus in the
following clock cycle.
The ready flag must be set no later than the last data value, otherwise the buffer
switches twice.
Output
Sim_Data Simulates an intermodule bus data exchange including fixed-point to floating-point
data conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768. The vector width depends on the specified buffer size or
the number of bus signals.
Overflow Outputs a flag that indicates that a buffer overflow occurred. An overflow occurs if
the old buffer is not read completely before a new buffer is ready to be read.
§ 0: No overflow occurred.
§ 1: An overflow occurred. This value is set for one clock cycle.
Data type: UFix_1_0
Sim_Status Outputs information about the simulated data exchange on the Sim_Data outport.
Available only if the access type is specified as Buffer and Enable simulation port
is set on the Parameters page.
Data type: UInt32

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Port Description
Data width: 3
§ Sim_Status[0]: Contains the number of valid elements in the Sim_Data vector.
§ Sim_Status[1]: Indicates whether the current buffer contains new or old values. It
is 1 if the buffer contains new values.
§ Sim_Status[2]: Indicates whether a buffer overflow occurred. At least one buffer
was not read and its data was lost before the currently read buffer was filled.

Buffer64 Out settings The following dialog settings are specific for the Buffer access type. For common
dialog settings, refer to Common settings on page 658.

Buffer size Lets you specify the size of the buffer in the range 1 … 32768.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1024
words. For example, a buffer with a specified buffer size of 1 allocates a
memory block of 1024 words with a data width of 64 bits in the FPGA
memory. This applies to any specified buffer and its related swinging buffer.

Enable simulation status port Lets you enable an outport to get status
information about the simulation data that is available when you have enabled
the simulation data port. The Sim_Status outport is added to the block.

Bus Out description Block display If you specify the buffer access type, the block display changes.
The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block in
buffer access mode:

Port Description
Input
Data Specifies a 64-bit data value to be written to a buffer for data transmission.
The data types of the signals depend on the bus topology that is set via Copy bus
topology from corresponding processor block or Copy bus topology from gcb
on the Parameters page. The maximum bit width is 64 bits.
The resolution of the data type is restricted to 53 bits, because the block converts all
data values to double for transmission.
Output

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Port Description
Sim_Data Simulates a data transmission including fixed-point to floating-point data
conversion.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1 … 32768. The vector width depends on the number of bus signals.

Bus Out settings The following dialog settings are specific for the Bus access type. For common
dialog settings, refer to Common settings on page 658.

Buffer size Displays the size of the buffer in the range 1 … 32,768. The
buffer size depends on the number of bus signals.

Note

The FPGA memory blocks reserved for buffers have a granularity of 1,024
words. For example, a buffer with a buffer size of 1 allocates a memory
block of 1,024 words with a data width of 64 bits in the FPGA memory.
This applies to any buffer and the related swinging buffer.

Edit bus topology Opens a dialog to display and configure the

bus signals. For more information, refer to Bus Editor Dialog -
FPGA_XDATA_READ_BL/FPGA_XDATA_WRITE_BL on page 66.

Copy bus topology from corresponding processor block Lets you copy an
existing bus topology from the corresponding processor block in the processor
model. For more information, refer to How to Use Simulink Buses of the
Processor Model to Model the Processor Communication (FPGA Programming
Blockset Guide ).

Analyze bus topology of input Lets you set the Data inport to the bus
topology of the connected Simulink bus.
If clicked, the FPGA Programming Blockset analyzes the connected Simulink
bus and sets the Data port to a matching bus topology. For instructions,
refer to How to Use Simulink Buses of the FPGA Model to Model Processor
Communication (FPGA Programming Blockset Guide ).

Reset bus topology Lets you clear the bus topology of the Data port.

Related topics Basics

Modeling Processor Model Access (FPGA Programming Blockset Guide )

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FPGA_IO_READ_BL (FPGA1403Tp1 with Engine Control I/O

Module Settings)
Purpose To configure read access to analog and digital input signals in the FPGA
model when using the FPGA1403Tp1 (7K325) with Engine Control I/O Module
(DS1554) framework.

Where to go from here Information in this section

Parameters Page (FPGA_IO_READ_BL)................................................... 666

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_READ_BL).......................................................... 679

To specify the inverting, scaling, and saturation settings for the selected
I/O function.

Information in other sections

Unit Page (FPGA_IO_READ_BL)................................................................ 55

To specify the I/O type and channel to be used for read access.

Parameters Page (FPGA_IO_READ_BL)

Purpose To specify relevant settings for the selected I/O function.

Description The framework provides different I/O types, which you can select on the Unit
page of the block. The number of the available physical connections on the
DS1554 Engine Control I/O Module determines the I/O functions that you can
select:
§ Status In
§ Digital Crank/Cam Sensor 1 ... Digital Crank/Cam Sensor 5
To provide bit-wise read access to digital camshaft and crankshaft sensors.
Each channel is 1 bit wide.
§ Inductive Zero Voltage Detector
To provide read access to an inductive zero voltage detector. If a zero crossing
from positive to negative is detected, the output signal is 1 for 1 clock cycle.
§ Temperature
To provide read access to the FPGA's die temperature.
§ Digital InOut 8 Channel 1 … Digital InOut 8 Channel 8

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§ Analog In 14 Channel 1 … Analog In 14 Channel 14

§ Knock Sensor 1 ... Knock Sensor 4
§ Subsystem Clock
§ System Clock
§ System Signal Block

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_IO_READ_BL block.

Enable simulation port Lets you enable an inport for offline simulation data.
The Sim_Data inport is added to the block so you can connect it to simulation
data coming from a Simulink-based I/O environment model.

Status In description Block display If you select the Status In channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block for
initialization sequence status information:

Port Description
Output
Init Done Outputs the state of the initialization sequence that is started after programming
the FPGA.
Data type: UFix_1_0
§ 0: Initialization sequence is in progress.
§ 1: Initialization sequence finished.

I/O mapping No external connection.

Status In settings None

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Digital Crank/Cam Sensor Block display If you select a Digital Crank/Cam Sensor channel from the
description channel list, the block display changes. The simulation ports are displayed
optionally.

I/O characteristics The following table describes the ports of the block for
crank/cam input channels:

Port Description
Input
Sim_Data Simulates an input signal in the same range as that specified for the real input
signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Input voltage range: -40 V ... +40 V
Output
Data Outputs the status of the crank/cam sensor.
Data type: UFix_1_0
§ 0: The input signal is lower than the Low threshold voltage parameter.
§ 1: The input signal is higher than the High threshold voltage parameter.
Update rate: FPGA clock frequency

If the hardware input signal or the value of the Sim_Data inport exceeds
the specified input range, the Data outport is saturated to the minimum or
maximum value.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use the
FPGA1403Tp1 (7K325) with Engine Control I/O Module (DS1554) framework.
The signals are available at the DS1554 Sub-D I/O connector.

Outport Channel Connector Pin Signal

Data 1 13 Digital In 9 Channel 1 Signal
2 32 Digital In 9 Channel 2 Signal
3 14 Digital In 9 Channel 3 Signal

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Outport Channel Connector Pin Signal

4 33 Digital In 9 Channel 4 Signal
5 12 Digital In 9 Channel 5 Signal

Digital Crank/Cam Sensor The following settings on the Parameters page are specific to the Digital
settings Crank/Cam Sensor I/O function. For common dialog settings, refer to Common
settings on page 667.

Low threshold voltage (-40000 mV ... +40000 mV) Lets you set the low
threshold level for the selected digital input channel in steps of 100 mV. Below
this level, a logical 0 is detected, above this level, a logical 1 is detected if the
high threshold voltage was crossed before.

High threshold voltage (-40000 mV ... +40000 mV) Lets you set the high
threshold level for the selected digital input channel in steps of 100 mV. The
logical 1 is output if this level is crossed and stays 1 until the signal falls below
the low threshold level.

Inductive Zero Voltage Block display If you select an Inductive Zero Voltage Detector channel from
Detector description the channel list, the block display changes. The simulation ports are displayed
optionally.

I/O characteristics The following table describes the ports of the block for
Inductive Zero Voltage Detector channels:

Port Description
Input
Sim_Data Simulates an input signal in the same range as that specified for the real input
signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Input voltage range: -40 V ... +40 V
Output
Data Detects the zero crossing points of the analog signals. If a zero crossing from
positive to negative is detected, the output signal is 1 for 1 clock cycle.
Data type: UFix_1_0
§ 0: No zero crossing.
§ 1: Zero crossing is detected.
Update rate: FPGA clock frequency

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If the hardware input signal or the value of the Sim_Data inport exceeds
the specified input range, the Data outport is saturated to the minimum or
maximum value.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use the
FPGA1403Tp1 (7K325) with Engine Control I/O Module (DS1554) framework.
The signals are available at the DS1554 Sub-D I/O connector.

Outport Connector Pin Signal

Data 10 Digital In 10 +
29 Digital In 10 -

Inductive Zero Voltage Only common dialog settings. Refer to Common settings on page 667.
Detector settings

Temperature description Block display If you select the Temperature channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block for
the die temperature input channel:

Port Description
Input
Sim_Temp Simulates the FPGA's die temperature (internal chip temperature).
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Input temperature range: -273.15 °C ... 230.70 °C
The range can be exceeded. The values are then saturated to the minimum or
maximum values.
Output
RAW_temp Outputs the raw value of the FPGA's die temperature measurement. Use the
12 MSB bits to calculate the die temperature.
Equation for calculating the die temperature:

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Port Description
Temperature [°C] = (float)(Temperature[hex] &
0xFFF0) · 503.975 / 65536
- 273.15
Data type: UFix_16_0
Data width: 1
Value range: 0 ... 65536
High Outputs a flag if the FPGA's die temperature exceeds 105 °C.
To reset the flag, the die temperature must fall below 85 °C.
Data type: UFix_1_0
§ 0: Die temperature does not exceed 105 °C.
§ 1: Die temperature exceeds 105 °C.

Note

A high ambient temperature and an FPGA application with a very high

FPGA utilization and/or toggle rate increase the FPGA die temperature
(internal chip temperature). If the die temperature exceeds 105 °C, the
FPGA might work incorrectly.
You can decrease the temperature by reducing the FPGA's toggle rate (e.g.,
by using clock enable) or by reducing the utilization of the FPGA resources.
If the die temperature exceeds 125 °C, the FPGA resets itself. The reset
stays active until the die temperature falls below 85 °C and you restart
MicroAutoBox III or reload the user application.

I/O mapping No external connection.

Temperature settings Only common dialog settings. Refer to Common settings on page 667.

Digital InOut 8 (In) description Block display If you select a Digital InOut 8 (In) channel from the channel list,
the block display changes. The simulation ports are displayed optionally.

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I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Input
Sim_Data Simulates an input signal in the same range specified for the real input signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Threshold level: 1 V ... 7.5 V (in steps of 0.1 V)
Output
Data Outputs the current results of the digital input channel.
Data type: UFix_1_0
§ 0: Input voltage of the channel is below the specified threshold voltage.
§ 1: Input voltage of the channel is higher than or equal to the specified threshold
voltage.
Update rate: FPGA clock frequency

Note

The frequency that can be detected is much smaller than the update rate. For
information on the electrical characteristics of the DS1554 Engine Control I/O
Module, refer to Digital In/Out 8 Characteristics (MicroAutoBox III Hardware
Installation and Configuration ).

If the hardware signal or the value of the Sim_Data inport exceeds the minimum
or maximum threshold voltage, it is saturated to the appropriate minimum or
maximum value.

Note

Asynchronous input data might lead to metastable register states because

input data is synchronized only by a single register stage. Further
synchronization techniques might be necessary.

Note

If you use the same digital channel for the input and the output, the I/O
driver is internally set to InOut mode. As a consequence, the maximum
input voltage for the digital input channel is equal to the specified high
supply, and the applicable threshold voltage is lower than the specified high
supply.
To use the maximum input voltage range, you have to use a digital channel
only as the input.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.

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For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use the
FPGA1403Tp1 (7K325) with Engine Control I/O Module (DS1554) framework.
The signals are available at the DS1514 ZIF I/O connector.

Outport Channel Connector Pin Signal

Data 1 c3 Digital InOut 8 Channel 1
Signal
2 b5 Digital InOut 8 Channel 2
Signal
3 b2 Digital InOut 8 Channel 3
Signal
4 c5 Digital InOut 8 Channel 4
Signal
5 c4 Digital InOut 8 Channel 5
Signal
6 c2 Digital InOut 8 Channel 6
Signal
7 a2 Digital InOut 8 Channel 7
Signal
8 Z2 Digital InOut 8 Channel 8
Signal

You can use the same digital channel for input and output signals.

Digital InOut 8 (In) settings The following settings on the Parameters page are specific to the Digital InOut
8 (In) I/O function. For common dialog settings, refer to Common settings on
page 667.

Threshold voltage Lets you specify the threshold level for the current digital
channel in the range 1,000 mV … 7,500 mV in steps of 100 mV. If the input
signal is below this level, a logical 0 is detected, otherwise a logical 1.
The selected threshold voltage is also valid for the enabled simulation data
inport.

Analog In 14 description Block display If you select an Analog In 14 channel from the channel list, the
block display changes. The simulation ports are displayed optionally.

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I/O characteristics The scaling between the analog input voltage and the
output of the block is:

Input Voltage Range Simulink Output

–10 V ... +10 V The outport range is: 0 … +65535

The following table describes the ports of the block for analog input channels:

Port Description
Input
Sim_Data Simulates an input signal in the same range as that specified for the real input
signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Input voltage range: -10 V ... +10 V
Data_soc Triggers the sampling of the A/D converter. When the value is set to 1 for at least
one clock cycle, the ADC starts the conversion. The port allows a precise definition
of the starting point of ADC sampling. The Data_eoc outport signals the end of the
conversion process.
Setting this value permanently to 1 results in continuous sampling.
Data type: UFix_1_0
Range: 0 or 1
Output
Data Outputs the current results of the A/D conversions on the current channel.
Data type: UFix_16_0
Range: 0 … +65535
Update rate: 1 Msps
Data_eoc Outputs an end of conversion signal if the conversion result is available. If the flag
changes from 0 to 1, the ADC data contains a new value. The flag is set to 1 for
only one clock cycle.
Data type: UFix_1_0
Range: 0 or 1

If the hardware input signal or the value of the Sim_Data inport exceeds the
specified input voltage range, Data outport is saturated to the minimum or
maximum value.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping The following I/O mapping is relevant if you use the
FPGA1403Tp1 (7K325) with Engine Control I/O Module (DS1554) framework.
The signals are available at the DS1514 ZIF I/O connector.

Outport Channel Connector Pin Signal

Data 1 W2 Analog In 14 Channel 1 +
V2 Analog In 14 Channel 1 -
2 Y2 Analog In 14 Channel 2 +
X2 Analog In 14 Channel 2 -

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Outport Channel Connector Pin Signal

3 S2 Analog In 14 Channel 3 +
R2 Analog In 14 Channel 3 -
4 T2 Analog In 14 Channel 4 +
U2 Analog In 14 Channel 4 -
5 V5 Analog In 14 Channel 5 +
W6 Analog In 14 Channel 5 -
6 W3 Analog In 14 Channel 6 +
V3 Analog In 14 Channel 6 -
7 T3 Analog In 14 Channel 7 +
U3 Analog In 14 Channel 7 -
8 U5 Analog In 14 Channel 8 +
V6 Analog In 14 Channel 8 -
9 S5 Analog In 14 Channel 9 +
T6 Analog In 14 Channel 9 -
10 T5 Analog In 14 Channel 10 +
U6 Analog In 14 Channel 10 -
11 R5 Analog In 14 Channel 11 +
R6 Analog In 14 Channel 11 -
12 S3 Analog In 14 Channel 12 +
R3 Analog In 14 Channel 12 -
13 P5 Analog In 14 Channel 13 +
P6 Analog In 14 Channel 13 -
14 P3 Analog In 14 Channel 14 +
P2 Analog In 14 Channel 14 -

Analog In 14 settings Only common dialog settings. Refer to Common settings on page 667.

Knock Sensor description Block display If you select the Knock Sensor channel from the channel list,
the block display changes. The simulation ports are displayed optionally.

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I/O characteristics The scaling between the analog input voltage and the
output of the block is:

Input Voltage Range Simulink Output

–5 V ... +5 V The outport range is: 0 … +65535

The following table describes the ports of the block for knock sensor input
channels:

Port Description
Input
Sim_Data Simulates an input signal in the same range as that specified for the real input
signal.
Available only if Enable simulation port is set on the Parameters page.
Data type: Double
Data width: 1
Input voltage range: –5 V ... +5 V
Data_soc Triggers the sampling of the A/D converter. When the value is set to 1 for at least
one clock cycle, the ADC starts the conversion. The port allows a precise definition
of the starting point of ADC sampling. The Data_eoc outport signals the end of the
conversion process.
Setting this value permanently to 1 results in continuous sampling.
Data type: UFix_1_0
Range: 0 or 1
Output
Data Outputs the current results of the A/D conversions on the current channel.
Data type: UFix_16_0
Range: 0 … +65535
Update rate: 1 Msps
Data_eoc Outputs an end of conversion signal if the conversion result is available. If the flag
changes from 0 to 1, the ADC data contains a new value. The flag is set to 1 for
only one clock cycle.
Data type: UFix_1_0
Range: 0 or 1

If the hardware input signal or the value of the Sim_Data inport exceeds the
specified input voltage range, Data outport is saturated to the minimum or
maximum range value.

Multiple clock domain support This block must be used with the FPGA
base rate. The block cannot be used in a user clock domain.

I/O mapping The following I/O mapping is relevant if you use the
FPGA1403Tp1 (7K325) with Engine Control I/O Module (DS1554) framework.
The signals are available at the DS1554 Sub-D I/O connector.

Outport Channel Connector Pin Signal

Data 1 16 Analog In 15 Channel 1 +
34 Analog In 15 Channel 1 -
2 17 Analog In 15 Channel 2 +
35 Analog In 15 Channel 2 -

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Outport Channel Connector Pin Signal

3 18 Analog In 15 Channel 3 +
36 Analog In 15 Channel 3 -
4 19 Analog In 15 Channel 4 +
37 Analog In 15 Channel 4 -

Knock Sensor settings Only common dialog settings. Refer to Common settings on page 667.

Subsystem Clock description Block display If you select the Subsysten Clock channel from the channel list,
the block display changes.

I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Output
Subsystem Outputs the clock signal of the selected subsystem clock domain. You specify the
Clock subsystem clock domain in the FPGA Setup block. Refer to How to Use Multiple
Clock Domains for FPGA Modeling (FPGA Programming Blockset Guide ).
Data type: UFix_1_0
Data width: 1

Multiple clock domain support This block is intended to be used in a user

clock domain with an individual clock period.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping No external connection.

Subsystem Clock settings None

System Clock description Block display If you select the Systen Clock channel from the channel list, the
block display changes.

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I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Output
System Clock Outputs the clock signal of the FPGA (base clock rate).
Data type: UFix_1_0
Data width: 1

Multiple clock domain support This block is intended to be used in a user

clock domain with an individual clock period.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping No external connection.

System Clock settings None

System Signal Block Block display If you select the System Signal Block channel from the channel
description list, the block display changes.

I/O characteristics The following table describes the ports of the block for
digital input channels:

Port Description
Output
System Clock Outputs the clock signal of the FPGA (base clock rate).
Data type: UFix_1_0
Data width: 1
Init Done Outputs the state of the initialization sequence that is started after programming
the FPGA.
Data type: UFix_1_0
Data width: 1
Values:
§ 0: Initialization sequence is in progress.
§ 1: Initialization sequence has finished.

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Port Description
CN App Outputs the state of the processor application.
Status Data type: UFix_1_0
Data width: 1
Values:
§ 0: The processor application is stopped.
§ 1: The processor application is running.
Opto_Ready Indicates whether an MGT module is ready for data exchange.
The port value remains 0, because the used dSPACE hardware does not support
MGT modules.

Multiple clock domain support This block is intended to be used in a user

clock domain with an individual clock period.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping No external connection.

System Signal Block settings None

Related topics Basics

Modeling External I/O Access (FPGA Programming Blockset Guide )

Scaling Page (FPGA_IO_READ_BL)

Purpose To specify the inverting, scaling, and saturation settings for the selected I/O
function.

Description You can modify the I/O signal of the selected I/O function if you select the
Enable FPGA test access and scaling parameter on the FPGA Access page
of the FPGA_SETUP_BL block dialog. The possible modifications depend on the
selected I/O function.

Common settings The following settings on the Scaling page are common to the I/O functions that
you can select on the Unit page.

Enable FPGA test access and scaling for this block Lets you disable FPGA
test access and scaling for the selected I/O function.

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Analog in settings The following settings on the Scaling page are specific to the Analog In 14 I/O
function.

Note

Scaling of analog I/O signals also effects the signal path:

§ If you use the parameters of the Scaling page to scale analog signals, the
data type of the Data port is set to the specified data format for scaling.
For more information, refer to How to Change the Data Type of Analog
Signals (FPGA Programming Blockset Guide ).
§ FPGA scaling of analog I/O signals might cause additional latency. If
the latency can be calculated during the modeling, analog I/O functions
display the total latency.

Scaling format Lets you select the data format for scaling and saturation.
§ Signed/Unsigned:
The values of the parameters for scaling and saturation are in fixed‑point
format. The signed fixed-point format reserves one bit for the sign.
You can specify the number of bits and the binary point position with the
Number of bits and Binary point (fraction width) parameters.
§ Single:
The values of the parameters for scaling and saturation are 32-bit values in
the single-precision floating‑point format with a fraction width of 24, which
complies with the IEEE 754 standard (single).
§ Double:
The values of the parameters for scaling and saturation are 64-bit values in
the double-precision floating‑point format with a fraction width of 53, which
complies with the IEEE 754 standard (double).

Number of bits This setting depends on the Scaling format setting.

§ Fixed-point format:
Lets you specify the bit width of the scaling parameters and the Data port in
the range 1 ... 64.
§ Floating-point format:
Displays the bit width of the scaling parameters and the Data port.

Binary point (fraction width) This setting depends on the Scaling format
setting.
§ Fixed-point format:
Lets you specify the binary point position of the scaling parameters and the
Data port. The position 0 represents the lowest bit position
§ Floating-point format:
Displays the fraction width of the scaling parameters and the Data port.

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Scaling factor Lets you specify the scaling factor. The scaling factor gains the
signal of the Data port before it is saturated or replaced via FPGA test access.
You must check whether the specified and displayed value is supported by
the specified scaling format. The value of the Scaling factor parameter will
be executed with the maximum accuracy of the specified scaling format
and saturated to the minimum and maximum values that the scaling format
supports.

Scaling offset Lets you add a signal offset after the signal of the Data port is
scaled with the scaling factor.
You must check whether the specified and displayed value is supported by
the specified scaling format. The value of the Scaling offset parameter will
be executed with the maximum accuracy of the specified scaling format
and saturated to the minimum and maximum values that the scaling format
supports.

Saturation minimum value Lets you specify the minimum value to which
the measured and scaled signal is saturated before it is output via the Data port.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation minimum
value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

Saturation maximum value Lets you specify the maximum value to which
the measured and scaled signal is saturated before it is output via the Data port.
You must check whether the specified and displayed value is supported by the
specified scaling format or hardware. The value of the Saturation maximum
value parameter will be saturated to the minimum and maximum values that the
scaling format and the hardware supports.

Multiplier latency Lets you specify the latency that is caused by the
multiplier for scaling. The multiplier is used to multiply the signal with the value
of the Scaling factor parameter.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The multiplication will be implemented without latency.
§ 1 ... 20: The multiplication will be implemented with the specified latency.
Use this value range in the exceptional case that the optimized latency cause
timing problems during the build process.

Adder latency Lets you specify the latency that is caused by the offset adder.
The offset adder is used to add the value of the Scaling offset parameter to the
signal.
The following values are possible:
§ -1: The latency is optimized during the build process for speed and FPGA
utilization.
This is the recommended setting.
§ 0: The adding will be implemented without latency.
§ 1 ... 20: The adding will be implemented with the specified latency.

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Use this value range in the exceptional case that the optimized latency causes
timing problems during the build process.

Digital in settings The following settings on the Scaling page are specific to the Digital InOut 8
I/O function.

Invert polarity Lets you adapt the measured values to the electrical input
signal:
§ Disabled:
The Data port outputs the signals as measured: A low-high transition results in
a 1 and vice versa.
§ Enabled:
The output of the Data port is inverted: A low-high transition results in a 0
and vice versa.

Digital Crank/Cam Sensor The Scaling page is empty because this I/O function does not support FPGA
settings scaling to scale I/O signals.

Inductive Zero Voltage The Scaling page is empty because this I/O function does not support FPGA
Detector settings scaling to scale I/O signals.

Knock Sensor settings The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

Status In settings The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

Temperature settings The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

Related topics Basics

Basics on FPGA Test Access and Scaling (FPGA Programming Blockset Guide )

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FPGA_IO_WRITE_BL (FPGA1403Tp1 with Engine Control I/O

Module Settings)
Purpose To configure write access to analog and digital output signals in the FPGA
model when using the FPGA1403Tp1 (7K325) with Engine Control I/O Module
(DS1554) framework.

Where to go from here Information in this section

Parameters Page (FPGA_IO_WRITE_BL).................................................. 683

To specify relevant settings for the selected I/O function.

Scaling Page (FPGA_IO_WRITE_BL)........................................................ 690

To specify the inverting, scaling, and saturation settings for the selected
I/O function.

Information in other sections

Unit Page (FPGA_IO_WRITE_BL)............................................................... 60

To specify the I/O type and channel to be used for write access.

Parameters Page (FPGA_IO_WRITE_BL)

Purpose To specify relevant settings for the selected I/O function.

Description The framework provides the three I/O types Analog, Digital, and Other, which
you can select on the Unit page of the block. The number of the available
physical connections on the DS1554 Engine Control I/O Module determines the
I/O functions that you can select:
§ LED Out
§ Sensor Supply
§ Digital Out 7 Channel 1 … Digital Out 7 Channel 40
§ Digital InOut 8 Channel 1 … Digital InOut 8 Channel 8
§ User Clock Out 1 … User Clock Out 32

Common settings The following settings on the Parameters page are common to the I/O functions
that you can select on the Unit page of the FPGA_IO_WRITE_BL block, except
for the LED Out function.

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Enable simulation port Lets you enable an outport for offline simulation
data. The Sim_Data outport is added to the block so you can connect it to a
Simulink-based I/O environment model.

LED Out description Block display If you select the LED Out channel from the channel list, the
block display changes.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Controls the FPGA status LED. The LED is located near the
DS1514 ZIF I/O connector.
Data type: UFix_1_0
§ 0: LED lights up green.
§ 1: LED lights up orange.

If the value of the Data inport exceeds the specified data width, only the lowest
bit is used (=1).

I/O mapping No external connection.

LED Out settings None

Sensor Supply description Block display If you select the Sensor Supply channel from the channel list,
the block display changes.

I/O characteristics The following table describes the ports of the block:

Port Description
Output
Sim_Data Simulates an output signal in the same range as that specified
for the real output signal.
Output voltage: 13.14 V

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I/O mapping The following I/O mapping is relevant if you use the
FPGA1403Tp1 (7K325) with Engine Control I/O Module (DS1554) framework.
The signals are available at the DS1514 ZIF I/O connector.

Outport Channel Connector Pin Signal

Sim_Data 1 b6 VSENS+
c6 VSENS–

Sensor Supply settings Only common dialog settings. Refer to Common settings on page 683.

Digital Out 7 description Block display If you select a Digital Out 7 channel from the channel list, the
block display changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Outputs a signal in the specified range.
If driven with 0, the hardware output is 0 V. If driven with 1, the hardware output is set to the
specified high-supply voltage (VDRIVE).
The hardware output is driven only if the Enable port is set to 1, otherwise the output is set to high
impedance (High-Z).
Data Type: UFix_1_0
Update rate: FPGA clock frequency

Note

The frequency that can be generated is much smaller than the update rate. For information on
the electrical characteristics of the DS1554 Engine Control I/O Module, refer to Digital Out 7
Characteristics (MicroAutoBox III Hardware Installation and Configuration ).

Enable Controls the hardware output. If set to 1, the hardware output reacts to the Data outport, otherwise
it is set to High-Z.
Data type: UFix_1_0
Output
Sim_Data Simulates an output signal in the same range as that specified for the real output signal.
Available only if Enable simulation port is set on the Parameters page.
Output voltage: 0 V ... 45 V
Update rate: FPGA clock frequency

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If the value of the Data inport exceeds the specified data width, only the lowest
bit is used.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use the
FPGA1403Tp1 (7K325) with Engine Control I/O Module (DS1554) framework.
The signals are available at the DS1514 ZIF I/O connector.

Inport Channel Connector Pin Signal

Data 1 L5 Digital Out 7‑1 Channel 1 Signal
2 N2 Digital Out 7‑1 Channel 2 Signal
3 D3 Digital Out 7‑1 Channel 3 Signal
4 N5 Digital Out 7‑1 Channel 4 Signal
5 M6 Digital Out 7‑1 Channel 5 Signal
6 N3 Digital Out 7‑1 Channel 6 Signal
7 D5 Digital Out 7‑1 Channel 7 Signal
8 M2 Digital Out 7‑1 Channel 8 Signal
9 L6 Digital Out 7‑1 Channel 9 Signal
10 K2 Digital Out 7‑1 Channel 10 Signal
11 C3 Digital Out 7‑1 Channel 11 Signal
12 L2 Digital Out 7‑1 Channel 12 Signal
13 G6 Digital Out 7‑1 Channel 13 Signal
14 H2 Digital Out 7‑1 Channel 14 Signal
15 C5 Digital Out 7‑1 Channel 15 Signal
16 J2 Digital Out 7‑1 Channel 16 Signal
17 F6 Digital Out 7‑2 Channel 17 Signal
18 E2 Digital Out 7‑2 Channel 18 Signal
19 B3 Digital Out 7‑2 Channel 19 Signal
20 G2 Digital Out 7‑2 Channel 20 Signal
21 E6 Digital Out 7‑2 Channel 21 Signal
22 C2 Digital Out 7‑2 Channel 22 Signal
23 B5 Digital Out 7‑2 Channel 23 Signal
24 F2 Digital Out 7‑2 Channel 24 Signal
25 D6 Digital Out 7‑2 Channel 25 Signal
26 A6 Digital Out 7‑2 Channel 26 Signal
27 A3 Digital Out 7‑2 Channel 27 Signal
28 D2 Digital Out 7‑2 Channel 28 Signal
29 B6 Digital Out 7‑2 Channel 29 Signal

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Inport Channel Connector Pin Signal

30 A2 Digital Out 7‑2 Channel 30 Signal
31 A5 Digital Out 7‑2 Channel 31 Signal
32 B2 Digital Out 7‑2 Channel 32 Signal
33 F5 Digital Out 7‑3 Channel 33 Signal
34 N6 Digital Out 7‑3 Channel 34 Signal
35 E3 Digital Out 7‑3 Channel 35 Signal
36 E5 Digital Out 7‑3 Channel 36 Signal
37 H3 Digital Out 7‑3 Channel 37 Signal
38 M5 Digital Out 7‑3 Channel 38 Signal
39 G3 Digital Out 7‑3 Channel 39 Signal
40 F3 Digital Out 7‑3 Channel 40 Signal

Digital Out 7 settings The following settings on the Parameters page are specific to the Digital
Out 7 I/O function. For common dialog settings, refer to Common settings on
page 683.

Simulated VDRIVE pin Lets you select the voltage for the simulated high-
side switch for all digital output channels in the range 0 … 45000 mV in steps of
100 mV.

Note

You can specify the simulated voltage value only globally for all digital
output channels.

Digital InOut 8 (Out) Block display If you select a Digital InOut 8 (Out) channel from the channel
description list, the block display changes. The simulation ports are displayed optionally.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Data Outputs a signal in the specified range.
If driven with 0, the hardware output is 0 V. If driven with 1, the hardware output is 3.3 V or 5 V
according to the specified high-supply voltage.

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Port Description
The hardware output is driven only if the Enable port is set to 1, otherwise the output is set to high
impedance (High-Z).
Data Type: UFix_1_0
Update rate: FPGA clock frequency

Note

The frequency that can be generated is much smaller than the update rate. For information on
the electrical characteristics of the DS1554 Engine Control I/O Module, refer to Digital In/Out 8
Characteristics (MicroAutoBox III Hardware Installation and Configuration ).

Enable Controls the hardware output. If set to 1, the hardware output reacts to the Data outport, otherwise
it is set to High-Z.
Data type: UFix_1_0
Output
Sim_Data Simulates an output signal in the same range as that specified for the real output signal.
Available only if Enable simulation port is set on the Parameters page.
Output voltage: 0 V … 3.3 V or 0 V … 5 V
Update rate: FPGA clock frequency

If the value of the Data inport exceeds the specified data width, only the lowest
bit is used.

Multiple clock domain support This block can be used with an individual
clock period to customize the update rate of digital I/O.
A higher update rate increases the time resolution to generate or sample a digital
signal. A higher update rate does not affect the minimum pulse duration or
frequency of the digital channel.
For instructions on using multiple time domains, refer to Using Multiple Clock
Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

I/O mapping The following I/O mapping is relevant if you use the
FPGA1403Tp1 (7K325) with Engine Control I/O Module (DS1554) framework.
The signals are available at the DS1514 ZIF I/O connector.
You can use the same digital channel for input and output signals.

Outport Channel Connector Pin Signal

Data 1 c3 Digital InOut 8 Channel 1
Signal
2 b5 Digital InOut 8 Channel 2
Signal
3 b2 Digital InOut 8 Channel 3
Signal
4 c5 Digital InOut 8 Channel 4
Signal
5 c4 Digital InOut 8 Channel 5
Signal
6 c2 Digital InOut 8 Channel 6
Signal

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Outport Channel Connector Pin Signal

7 a2 Digital InOut 8 Channel 7
Signal
8 Z2 Digital InOut 8 Channel 8
Signal

Digital InOut 8 (Out) settings The following settings on the Parameters page are specific to the Digital InOut
8 (Out) I/O function. For common dialog settings, refer to Common settings on
page 683.

High supply Lets you select the voltage for the high-side switch (3.3 V or 5 V)
for all digital output channels.

Note

You can specify the high-supply voltage value only globally for all digital
output channels.

User Clock Out 1 … 32 Block display If you select the User Clock Out channel from the channel list,
description the block display changes.

I/O characteristics The following table describes the ports of the block:

Port Description
Input
User Clock Clock signal for the clock domain used within the subsystem to which the block
belongs. For more information, refer to Using Multiple Clock Domains for FPGA
Modeling (FPGA Programming Blockset Guide ).
Data type: UFix_1_0
Data width: 1

I/O mapping No external connection.

User Clock Out 1 … 32 The Parameters page provides the following dialog setting:
settings
User clock period Lets you specify the expected clock period used within the
subsystem to which the block belongs. A common value for the clock period is in
the range 20 ns ... 4 ns (50 MHz ... 250 MHz).
The value is used during the build process when no user clock is available, for
example, to specify timing constraints.

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User clock offline simulation period Lets you specify the clock period to be
used in offline simulation mode. The value must be greater than or equal to the
value of the User clock period parameter.

Related topics Basics

Modeling External I/O Access (FPGA Programming Blockset Guide )

Scaling Page (FPGA_IO_WRITE_BL)

Purpose To specify the inverting, scaling, and saturation settings for the selected I/O
function.

Description You can modify the I/O signal of the selected I/O function if you select the
Enable FPGA test access and scaling parameter on the FPGA Access page
of the FPGA_SETUP_BL block dialog. The possible modifications depend on the
selected I/O function.

Common settings The following settings on the Scaling page are common to the I/O functions that
you can select on the Unit page.

Enable FPGA test access and scaling for this block Lets you disable FPGA
test access and scaling for the selected I/O function.

Digital out settings The following settings on the Scaling page are specific to the Digital Out 7 and
Digital InOut 8 (out) I/O functions.

Invert polarity Lets you adapt the electrical output signal:

§ Disabled:
If driven with 1, the hardware outputs a high-level signal.
If driven with 0, the hardware outputs a low-level signal.
§ Enabled:
If driven with 1, the hardware outputs a low-level signal.
If driven with 0, the hardware outputs a high-level signal.

LED Out settings The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

Sensor Supply settings The Scaling page is empty because this I/O function does not support FPGA
scaling to scale I/O signals.

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Related topics Basics

Basics on FPGA Test Access and Scaling (FPGA Programming Blockset Guide )

FPGA_INT_BL (FPGA1403Tp1 with Engine Control I/O

Module Settings)
Purpose To configure the FPGA interrupt channel when using the FPGA1403Tp1 (7K325)
with Engine Control I/O Module (DS1554) framework.

Where to go from here Information in this section

Parameters Page (FPGA_INT_BL)............................................................ 691

To enable the simulation port for an interrupt.

Information in other sections

Unit Page (FPGA_INT_BL)......................................................................... 64

To specify the interrupt channel used to trigger a task in the processor
model.

Parameters Page (FPGA_INT_BL)

Purpose To enable the simulation port for an interrupt.

Description The FPGA1403Tp1 (7K325) with Engine Control I/O Module (DS1554)
framework provides 8 interrupt lines.

An interrupt is requested if the Int port is set to 1 for at least one clock cycle. If
you set the Int port to 0, the last interrupt is not released but saved. An interrupt
is edge-triggered.

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Int description Block display The following illustration shows the block display with the
optional simulation port:

I/O characteristics The following table describes the ports of the block:

Port Description
Input
Int Provides the interrupt request line.
Data type: UFix_1_0
0 to 1: Interrupt is requested (edge-triggered).
0: No interrupt is requested. Last requested interrupt is saved.
Output
Sim_Int Simulates an interrupt by performing a function-call to enable a function-call
subsystem.
Available only if Enable simulation port is set on the Parameters page.
Data type: Function call

Int settings Enable simulation port Lets you enable an outport for a simulated interrupt.
The Sim_Int outport is added to the block so you can connect it to a function-
call subsystem in the processor model.

Related topics HowTos

How to Trigger Interrupt-Driven Processor Tasks (FPGA Programming Blockset

Guide )

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Enhancements to the Simulink Menus

Introduction The FPGA Programming Blockset provides commands in Simulink menus to

support the modeling and build process of the FPGA application.

Where to go from here Information in this section

Menu Commands for FPGA Programming............................................. 694

Description of the added commands.

Advanced Preferences Dialog................................................................. 699

With the advanced preferences of the FPGA Programming Blockset you
can perform workarounds, for example.

Word Length Calculator........................................................................ 706

The word length calculator lets you calculate an optimal fix-point data
type for a user-defined floating-point value.

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Menu Commands for FPGA Programming

Introduction Description of the added commands.

Where to go from here Information in this section

Advanced Preferences................................................................... ........ 694

To open the Advanced Preferences.

Generate Corresponding Block.............................................................. 695

To generate a processor interface block that corresponds to the selected
block.

Show Corresponding Block.................................................................... 695

To show where the corresponding processor interface block of the
selected block is used in the processor model.

Update All Scaling Subsystems for Last Build.......................................... 696

To update all scaling subsystems of an FPGAC file without rebuilding the
FPGA application.

Update Selected Scaling Subsystems for Last Build................................. 697

To update the selected scaling subsystems of an FPGAC file without
rebuilding the FPGA application.

Word Length Calculator........................................................................ 698

To open the dSPACE Word Length Calculator.

Advanced Preferences

Access Menu bar dSPACE FPGA

Context menu of None
Shortcut key None
Toolbar icon None
MATLAB command None

Purpose To open the Advanced Preferences.

Description The Advanced Preferences dialog lets you change preferences to perform
workarounds or for convenience. For more information, refer to Dialog Settings
of the Advanced Preferences Dialog on page 700.

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Related topics References

Dialog Settings of the Advanced Preferences Dialog................................................................ 700

Generate Corresponding Block

Access Menu bar None

Context menu of XDATA block — dSPACE FPGA
Shortcut key None
Toolbar icon None
MATLAB command None

Purpose To generate a processor interface block that corresponds to the selected block.

Description The generated block is added to the FPGA model. Move the block to the
processor model to use it as a processor interface.

Related topics Basics

Implementing the Processor Interface to the Processor Model (FPGA Programming

Blockset Guide )

References

Show Corresponding Block..................................................................................................... 695

Show Corresponding Block

Access Menu bar None

Context menu of XDATA block — dSPACE FPGA
Shortcut key None
Toolbar icon None
MATLAB command None

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Purpose To show where the corresponding processor interface block of the selected block
is used in the processor model.

Description The subsystem with the corresponding processor interface block opens and
highlights the corresponding block.

Related topics Basics

Implementing the Processor Interface to the Processor Model (FPGA Programming

Blockset Guide )

References

Generate Corresponding Block............................................................................................... 695

Update All Scaling Subsystems for Last Build

Access This command is available only if the following preconditions are fulfilled:
§ A subsystem with the FPGA Setup block is open.
§ The FPGAC file of the last build process is available.
The ConfigurationDesk Interface page of the FPGA Setup block shows the
last build results.

Menu bar dSPACE FPGA

Context menu of None
Shortcut key None
Toolbar icon None
MATLAB command None

Purpose To update all scaling subsystems of an FPGAC file without rebuilding the FPGA
application.

Description The FPGA build process inserts all build result files into an FPGAC file. Building
the FPGA application takes a lot of time. If you have changed only scaling
subsystems, you do not need to rebuild the FPGA subsystem. Updating the
selected scaling subsystem only updates the preprocessing and/or postprocessing
of the processor signals, the FPGA application remains unchanged.

The command updates the FPGAC file without changing the unique ID.

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Related topics Basics

Preprocessing and Postprocessing the Signals Between the FPGA and the Processor
Model (FPGA Programming Blockset Guide )

HowTos

How to Update an FPGAC File with Modified Scaling Subsystems (FPGA

Programming Blockset Guide )

Update Selected Scaling Subsystems for Last Build

Access This command is available only if the following preconditions are fulfilled:
§ At least one scaling subsystem is selected.
§ The FPGAC file of the last build process is available.
The ConfigurationDesk Interface page of the FPGA Setup block shows the
last build results.

Menu bar None

Context menu of § Background of the subsystem - dSPACE
FPGA
§ Selected subsystem - dSPACE FPGA
Shortcut key None
Toolbar icon None
MATLAB command None

Purpose To update the selected scaling subsystems of an FPGAC file without rebuilding
the FPGA application.

Description The FPGA build process inserts all build result files into an FPGAC file. Building
the FPGA application takes a lot of time. If you have changed only scaling
subsystems, you do not need to rebuild the FPGA subsystem. Updating the
selected scaling subsystem only updates the preprocessing and/or postprocessing
of the processor signals, the FPGA application remains unchanged.

The command updates the FPGAC file without changing the unique ID.

Related topics Basics

Preprocessing and Postprocessing the Signals Between the FPGA and the Processor
Model (FPGA Programming Blockset Guide )

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HowTos

How to Update an FPGAC File with Modified Scaling Subsystems (FPGA

Programming Blockset Guide )

Word Length Calculator

Access Menu bar dSPACE FPGA

Context menu of None
Shortcut key None
Toolbar icon None
MATLAB command dsfpga_wordlength_calculator

Purpose To open the dSPACE Word Length Calculator.

Description The word length calculator lets you calculate an optimal fixed-point data type
for a user-defined floating-point value. For more information, refer to Dialog
Settings of the Word Length Calculator on page 707.

Related topics References

Dialog Settings of the Word Length Calculator....................................................................... 707

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Advanced Preferences Dialog

Introduction With the advanced preferences of the FPGA Programming Blockset you can
perform workarounds, for example.

Where to go from here Information in this section

Opening the Advanced Preferences Dialog.................................... ........ 699

Method to open the dialog

Dialog Settings of the Advanced Preferences Dialog............................... 700

To change preferences to perform workarounds or for convenience.

Information in other sections

Script Functions to Manage Advanced Preferences (FPGA

Programming Software Script Interface Reference )
With the advanced preferences of the FPGA Programming Blockset you
can perform workarounds, for example.

Opening the Advanced Preferences Dialog

Opening the dialog In the Simulink model, click dSPACE FPGA - Advanced Preferences.

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Dialog Settings of the Advanced Preferences Dialog

Overview

Refresh button Lets you refresh the table entries.

Set to Default button Lets you reset all preferences to the default setting.

Load from file Lets you set all preferences to a setting that you saved before
to a JSON file.

Save to File Lets you save the current settings to a JSON file.
Changes are effective only for one MATLAB session. To reuse the settings in
several sessions, save the settings to reload them in the next session.

Preferences Changing the preferences lets you change the default behavior of the FPGA
Programming Blockset to perform workarounds or disable features.

Note

§ The changes are effective for one MATLAB session only. When you exit
MATLAB, the preferences are reset to the default values.
§ It is recommended that you use the default settings and change the
preferences only in exceptional cases.

DISABLE_BLOCK_RENAMING

Value range: false, true

Default false
Description: Lets you rename blocks to avoid problems with block names
during the code generation, such as multidriven nets or driverless
pins.
§ False: Blocks are renamed according to the AMD Vitis
Model Composer naming convention, e.g., line feeds (\n) are
removed.

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§ True: The block names remain unchanged.

BUILD_DONT_ASK

Value range: false, true

Default false
Description: Lets you automatically save the entire model before the build
process starts or before you switch the framework.
§ False: A dialog opens and lets you save the model.
§ True: The framework automatically saves the entire model.

DISABLE_BUILD_TIMER

Value range: false, true

Default false
Description: Lets you build the FPGA application in GUI callback to prevent
XSG code generation errors.
§ False: Build runs in timer context. This is the default since
Release 2022-B.
§ True: Build runs in GUI callback. This was the default up to
Release 2022-A.

FLATTEN_MODEL

Value range: 0, 1
Default 0
Description: Lets you flatten the model to avoid errors during the code
generation such as multidriven networks and 0-signals in HIL.
§ 0: No changes to the model.
§ 1: Removes all subsystem and signal hierarchies, sets mask
parameters in the blocks. The model is reduced to blocks
with direct signal lines without buses in the root level. The
functionality of the model does not change.

IGNORE_CLOCK_INTERACTION_PROBLEMS

Value range: false, true

Default false
Description: Lets you ignore problems with the interaction of the clocks if
a model with multiple clock domains exceptionally reaches a
wrong result. However, it is more likely that you have designed
a model with multiple clocks or black boxes, and metastable
crossings of clock domains. The bits in the signals passing
through these crossings might flip randomly. Be sure to design
clock domain crossings with registers (for single-bit signals only),
FIFOs, or DDR RAM decoupling.
§ False: The build process cancels the build if it detects a clock
interaction problem.
§ True: The build process ignores clock interaction problems. You
can use the build results at your own risk.

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For instructions on using multiple clock domains, refer to How to Use Multiple
Clock Domains for FPGA Modeling (FPGA Programming Blockset Guide ).

IGNORE_CRITICAL_WARNINGS

Value range: false, true

Default false
Description: Lets you ignore critical warnings during the build process, e.g., to
avoid multidriven nets if the error code changes again. This lets
you use UART IP cores with the same clock, for example.
§ False: The build process cancels the build if critical warnings
are issued during synthesis and implementation.
§ True: The build process ignores critical warnings. You can use
the build results at your own risk.

IGNORE_WRONG_XILINX_VERSION

Value range: false, true

Default false
Description: Lets you enable the use of the framework even if the active
Vivado version does not support the framework. Using these
Vivado versions can lead to FPGA model problems, build
problems, or incorrect FPGA behavior on the dSPACE platform.
§ False: Version control is enabled. Vivado supports the
framework.
§ True: Version control is disabled. You can use the framework at
your own risk.

DISABLE_OFFLINESIM

Value range: 0, 1, 2
Default 0
Description: Lets you deactivate offline simulation to fix problems when using
different MATLAB versions. Different MATLAB versions can lead
to problems with the offline simulation, for example, when using
the Fixed Point Toolbox and the data type uint64.
§ 0: Offline simulation is activated.
§ 1: Offline simulation is deactivated.
§ 2: Offline simulation is deactivated for blocks with the tag
dsOfflineSimDisable = 1.

PASTE_KEEP_CHANNEL_NUM

Value range: false, true

Default true
Description: Lets you speed up the copy & paste process by deactivating the
automatic reassignment of new hardware resources.
§ False: No new channels are assigned to copied blocks. You
have to reassign the blocks manually.
This setting speeds up the copy & paste process.

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§ True: The blockset automatically analyzes the FPGA model and

reassigns new hardware resources to copied blocks.

XILINX_BRAM_OPTIMIZATION

Value range: false, true

Default false
Description: Lets you activate the BRAM optimization for the AMD Kintex 7
series FPGA. Since Vivado 2019.1, the Vivado coder uses the
Xilinx Parameterized Macro (XPM) memory instead the LogiCore
Block Memory Generator for RAM blocks, but XPM is not
optimized for Kintex 7 from Vivado 2019.1 to Vivado 2021.2
and consumes up to double the amount of resources. Refer to
AMD Answer Records AR76951 and AR76194.
§ False: No optimization for Kintex 7.
§ True: Optimization is enabled.

XILINX_VIVADO_GUI_MODE

Value range: false, true

Default false
Description: Lets you enable the GUI of Vivado when working with the
blockset. If Vivado crashes, it sometimes helps to activate the
GUI during the build process. However, it is more helpful to
reduce the number of threads in the FPGA Setup block to 1
and use a PC with enough RAM. For example: Large models for
the DS6602 FPGA board with a LUT utilization of >75% require
more than 32 GB RAM.
§ False: Vivado is used without GUI.
§ True: Vivado is used with GUI.

XILINX_VIVADO_MONITORING

Value range: false, true

Default false
Description: Lets you disable the dSPACE monitoring of Vivado processes.
Sometimes the Vivado build process takes an unexpectedly long
time. If the CPU utilization is 0% for 30 minutes, dSPACE Vivado
Monitoring stops the Vivado build process. However, Vivado
sometimes stops the build process for extremely large models
for more than 30 minutes, but recovers from this.
§ False: Process monitoring activated.
§ True: Process monitoring deactivated.

XILINX_VIVADO_RLOC_WORKAROUND

Value range: -2 … 127

Default -2
Description: Lets you specify the generation of relative location (RLOC)
constraints to avoid placing errors due to FPGA tracing.
§ -2: The Vivado Coder generates RLOC constraints to achieve
the best FPGA tracing read-out performance.

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§ -1: An RLOC constraint forces 4 Flip-Flops per configurable

logic block (CLB).
§ 0: The Vivado Coder does not generate RLOC constraints.
§ 1 … 127: An RLOC constraint forces the entered number of
Flip-Flops per CLB.

XILINX_VIVADO_SRL32_WORKAROUND

Value range: false, true

Default false
Description: Lets you adapt the timing constraints of multicycle paths to
avoid timing errors. The Vivado Coder uses SRL32E elements for
delays. Delays of less than 17 cycles can lead to timing errors in
multicycle paths.
§ False: No changes to the timing constraints.
§ True: The timing constraints for downsample paths of
multicycle paths are adapted.

XILINX_XSG_FALSE_PATHS_WORKAROUND

Value range: false, true

Default true
Description: Lets you automatically correct the false paths listed in the
false_paths.xdc file.
§ False: No correction
§ True: The false paths are automatically corrected.

XILINX_XSG_MULTICYCLE_CE_FILTER_WORKAROUND

Value range: false, true

Default true
Description: Lets you enable the correction of XSG multicycle constraints for
the application of DSPs whose CE signals are routed through a
LUT, such as floating point cores.
§ False: No correction
§ True: The XSG multicycle constraints are automatically
corrected.

XILINX_XSG_INVALID_MULTICYCLE_WORKAROUND

Value range: false, true

Default false
Description: Lets you enable the conditional instead of mandatory execution
of XSG multicycle constraints. Attention: This can disable
downsample blocks in some scenarios.
§ False: No correction
§ True: The XSG multicycle constraints are executed
conditionally.

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 Advanced Preferences Dialog

Related topics Basics

Script Functions to Manage Advanced Preferences (FPGA Programming Software

Script Interface Reference )

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Word Length Calculator

Introduction The word length calculator lets you calculate an optimal fixed-point data type for
a user-defined floating-point value.

Where to go from here Information in this section

Opening the Word Length Calculator.................................................... 706

Methods to open the tool.

Dialog Settings of the Word Length Calculator...................................... 707

To computate the matching fixed-point data type for a floating-point
value.

Opening the Word Length Calculator

Opening the dialog Possible methods to open the dialog of the word length calculator:
§ In the Simulink® model, click dSPACE FPGA - dSPACE Word Length
Calculator.

§ In the MATLAB Command Window or in an M script, enter

dsfpga_wordlength_calculator.

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Dialog Settings of the Word Length Calculator

Overview The following illustration shows the dialog of the word length calculator.

Input value and fixed-point Lets you enter the maximum value to be represented. The table displays the
representation resulting fixed-point value.

Value Lets you enter the maximum floating-point value that your application
can perform. The calculator supports the following values:
§ Positive or negative value
§ Scalar value
§ Variable defined in the workspace
§ MATLAB constants like pi
Not supported are Inf, Nan, or complex values.

Fixed-point value Displays the resulting fixed-point value that is calculated

with the current settings.

Output type Lets you select the arithmetic type and displays the precision, range, resolution,
and error of the calculated fixed-point data type.

Arithmetic type Lets you select whether the estimated fixed-point data type
is signed or unsigned.

Fixed-point precision Displays the calculated number of bits and the binary
point of the calculated fixed-point data type.

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Range and resolution Displays the calculated value range and the resolution
of the calculated fixed-point data type.
§ If the specified word length is too short, the maximum value is highlighted in
red.
§ If the input value is negative and the arithmetic type is set to unsigned, the
minimum value will be set to zero and highlighted in red.

Error Displays the absolute and relative error between the input value and the
calculated fixed-point data type.

Computation method Lets you select the computation method to calculate the fixed-point data type.
The computation automatically starts when all the necessary input values are
available.

Word length Enables the calculation of the fixed-point data type based on a
specified word length.

Error Enables the calculation of the fixed-point data type based on the
maximum tolerable error.
You specify the relative error between the input value and the resulting fixed-
point data type. The maximum word length is 130 bits.

Resolution Enables the calculation of the fixed-point data type based on the
maximum resolution.
You can specify a positive value smaller than or equal to one. The fixed-point
data type is calculated in a way so that at least the specified resolution can be
represented.

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 Index
Index
Aurora 64b66b In DS6602 FPGA Base Board 296
A MicroLabBox II 155 FPGA1403Tp1 with DS1552 592
SCALEXIO 451 FPGA1403Tp1 with DS1554 655
access type 46, 51
Aurora 64b66b Out MicroLabBox II 131
ADC (Class 1)
MicroLabBox II 175 Bus Out
DS1202 FPGA I/O Type 1 89
SCALEXIO 458 DS2655 FPGA Base Board 215
ADC (Class 2)
DS6601 FPGA Base Board 260
DS1202 FPGA I/O Type 1 91
B DS6602 FPGA Base Board 307
ADC (Type A)
FPGA1403Tp1 with DS1552 601
FPGA1401Tp1 with DS1552 497 buffer
FPGA1403Tp1 with DS1552B1 601
FPGA1401Tp1 with DS1552B1 497 access type 46, 51
FPGA1403Tp1 with DS1554 664
FPGA1401Tp1 with DS1554 563 Buffer In
MicroLabBox II 142
ADC (Type B) DS1202 FPGA I/O Type 1 73
Buzzer
FPGA1401Tp1 with DS1552 499 DS2655 FPGA Base Board 200
DS1202 FPGA I/O Type 1 103
FPGA1401Tp1 with DS1552B1 499 DS6601 FPGA Base Board 245
Analog In DS6602 FPGA Base Board 292
DS2655M1 I/O Module 345 FPGA1401Tp1 with DS1552 482 C
DS6651 Multi-I/O Module 401 FPGA1401Tp1 with DS1552B1 482 CN App Status
Analog In 10 FPGA1401Tp1 with DS1554 542 DS2655 FPGA Base Board 221
FPGA1403Tp1 with DS1552 604 FPGA1403Tp1 with DS1552 588 DS6601 FPGA Base Board 266
Analog In 11 FPGA1403Tp1 with DS1552B1 588 DS6602 FPGA Base Board 313
FPGA1403Tp1 with DS1552B1 605 FPGA1403Tp1 with DS1554 651 MicroLabBox II 159
Analog In 12 MicroLabBox II 128 commands
FPGA1403Tp1 with DS1552 607 Buffer Out Advanced Preferences 694
FPGA1403Tp1 with DS1552B1 607 DS1202 FPGA I/O Type 1 82 Generate Corresponding Block 695
Analog In 14 DS2655 FPGA Base Board 209 Show Corresponding Block 695
FPGA1403Tp1 with DS1554 673 DS6601 FPGA Base Board 254 Show in ConfigurationDesk 698
Analog In 23 DS6602 FPGA Base Board 301 Update All Scaling Subsystems for Last
MicroLabBox II 148 FPGA1401Tp1 with DS1552 490 Build 696
Analog In 24 FPGA1401Tp1 with DS1552B1 490 Update Selected Scaling Subsystems for Last
MicroLabBox II 149 FPGA1401Tp1 with DS1554 550 Build 697
Analog In 25 FPGA1403Tp1 with DS1552 597 Common Program Data folder 13
MicroLabBox II 151 FPGA1403Tp1 with DS1552B1 597
Analog In‑L FPGA1403Tp1 with DS1554 660 D
DS6651 Multi-I/O Module 404 MicroLabBox II 137
DAC
Analog Out Buffer64 In
FPGA1401Tp1 with DS1552 514
DS2655M1 I/O Module 354 DS1202 FPGA I/O Type 1 76
FPGA1401Tp1 with DS1552B1 514
DS6651 Multi-I/O Module 417 DS2655 FPGA Base Board 202
DAC (Class 1)
Analog Out 13 DS6601 FPGA Base Board 247
DS1202 FPGA I/O Type 1 101
FPGA1403Tp1 with DS1552 624 DS6602 FPGA Base Board 294
DDR 4 32 Mode 1
FPGA1403Tp1 with DS1552B1 624 FPGA1401Tp1 with DS1552 485
DS6602 FPGA Base Board 326
Analog Out 19 FPGA1401Tp1 with DS1552B1 485
DDR 4 32 Mode 2
MicroLabBox II 170 FPGA1401Tp1 with DS1554 544
DS6602 FPGA Base Board 330
Analog Out 20 FPGA1403Tp1 with DS1552 590
DDR 4 64 Mode 1
MicroLabBox II 171 FPGA1403Tp1 with DS1552B1 590
DS6602 FPGA Base Board 328
Analog Out-T FPGA1403Tp1 with DS1554 653
DDR 4 64 Mode 2
DS6651 Multi-I/O Module 419 MicroLabBox II 129
DS6602 FPGA Base Board 333
APU Master Buffer64 Out
Description page
DS2655 FPGA Base Board 230 DS1202 FPGA I/O Type 1 84
empty 20
DS6601 FPGA Base Board 277 DS2655 FPGA Base Board 212
Digital Crank/Cam Sensor
DS6602 FPGA Base Board 324 DS6601 FPGA Base Board 257
FPGA1401Tp1 with DS1552 500
MicroLabBox II 173 DS6602 FPGA Base Board 304
FPGA1401Tp1 with DS1554 557
APU Slave FPGA1401Tp1 with DS1552 493
FPGA1403Tp1 with DS1552 609
DS2655 FPGA Base Board 219 FPGA1401Tp1 with DS1552B1 493
FPGA1403Tp1 with DS1554 668
APU Slave 1 ... 6 FPGA1401Tp1 with DS1554 553
Digital In
DS6601 FPGA Base Board 264 FPGA1403Tp1 with DS1552 599
DS2655M1 I/O Module 347
DS6602 FPGA Base Board 311 FPGA1403Tp1 with DS1552B1 599
DS2655M2 I/O Module 369
MicroLabBox II 153 FPGA1403Tp1 with DS1554 662
DS6651 Multi-I/O Module 407
Aurora 64b66b 128 Bit In MicroLabBox II 140
Digital In (Type A)
MicroLabBox II 157 bus
FPGA1401Tp1 with DS1552 502
SCALEXIO 453 access type 46, 51
Digital In (Type B)
Aurora 64b66b 128 Bit Out Bus In
FPGA1401Tp1 with DS1552 504
MicroLabBox II 176 DS2655 FPGA Base Board 204
FPGA1401Tp1 with DS1554 561
SCALEXIO 460 DS6601 FPGA Base Board 249

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 Index

Digital In 5 UART (RS232) 108 Status In 271

FPGA1403Tp1 with DS1552 610 UART (RS422/485) 113 Subsystem Clock 272
Digital In/Out 14 (In) DS2655 FPGA Base Board 196 System Signal Block 273
MicroLabBox II 159 APU Master 230 Temperature 274
Digital In/Out 14 (In/Out‑Z) APU Slave 219 User Clock Out 284
DS6651 Multi-I/O Module 178 Buffer In 200 Watchdog 275
Digital In/Out 15 Buffer Out 209 DS6602 FPGA Base Board 288
MicroLabBox II 183 Buffer64 In 202 APU Master 324
Digital In/Out‑Z Buffer64 Out 212 APU Slave 1 ... 6 311
DS6651 Multi-I/O Module 431 Bus In 204 Buffer In 292
Digital InOut Bus Out 215 Buffer Out 301
DS2655M1 I/O Module 356 CN App Status 221 Buffer64 In 294
Digital InOut (Class 1) I‑FPGA In 465 Buffer64 Out 304
DS1202 FPGA I/O Type 1 104 I-FPGA In (IOCNET) 222 Bus In 296
Digital InOut (Class 2) I‑FPGA Out 471 Bus Out 307
DS1202 FPGA I/O Type 1 106 I-FPGA64 In (IOCNET) 224 CN App Status 313
Digital InOut 6 (In) Int 240 DDR 4 32 Mode 1 326
FPGA1403Tp1 with DS1552 612 IOCNET Global Time 226 DDR 4 32 Mode 2 330
Digital InOut 6 (Out) LED Out 237 DDR 4 64 Mode 1 328
FPGA1403Tp1 with DS1552 627 Register In 198 DDR 4 64 Mode 2 333
Digital InOut 8 (In) Register Out 208 I-FPGA In (IOCNET) 314
FPGA1403Tp1 with DS1554 671 Register64 In 201 I-FPGA Out (IOCNET) 335
Digital InOut 8 (Out) Register64 Out 211 I-FPGA64 In (IOCNET) 316
FPGA1403Tp1 with DS1554 687 Status In 226 I-FPGA64 Out (IOCNET) 338
Digital Out Subsystem Clock 227 Int 343
DS2655M1 I/O Module 361 System Signal Block 228 IOCNET Global Time 318
DS2655M2 I/O Module 379 User Clock Out 238 LED Out 340
DS6651 Multi-I/O Module 421 DS2655M1 I/O Module Register In 290
Digital Out (Type A) Analog In 345 Register Out 300
FPGA1401Tp1 with DS1552 515 Analog Out 354 Register64 In 293
FPGA1401Tp1 with DS1552B1 515 Digital In 347 Register64 Out 303
FPGA1401Tp1 with DS1554 573 Digital InOut 356 Status In 318
Digital Out (Type B) Digital Out 361 Subsystem Clock 319
FPGA1401Tp1 with DS1552 517 DS2655M2 I/O Module System Signal Block 320
FPGA1401Tp1 with DS1554 575 Digital In 369 Temperature 321
Digital Out 5 Digital Out 379 User Clock Out 341
FPGA1403Tp1 with DS1552 626 Digital Out-Z 384 Watchdog 322
FPGA1403Tp1 with DS1552B1 626 RS232 Rx 372 DS6651 Multi-I/O Module
Digital Out 7 RS232 Tx 389 Analog In 401
FPGA1403Tp1 with DS1554 685 RS485 Rx 374 Analog In‑L 404
Digital Out-Z RS485 Rx/Tx 390 Analog Out 417
DS2655M2 I/O Module 384 RS485 Tx 394 Analog Out-T 419
DS6651 Multi-I/O Module 426 DS6601 FPGA Base Board 241 Digital In 407
Documents folder 13 APU Master 277 Digital In/Out‑Z 431
DS1202 FPGA I/O Type 1 APU Slave 1 ... 6 264 Digital Out 421
ADC (Class 1) 89 Buffer In 245 Digital Out-Z 426
ADC (Class 2) 91 Buffer Out 254 RS485 Rx 410
Buffer In 73 Buffer64 In 247 RS485 Rx/Tx 438
Buffer Out 82 Buffer64 Out 257 RS485 Tx 442
Buffer64 In 76 Bus In 249 Trigger 445
Buffer64 Out 84 Bus Out 260
Buzzer 103 CN App Status 266 F
DAC (Class 1) 101 I-FPGA In (IOCNET) 267
FPGA Scope 37
Digital InOut (Class 1) 104 I-FPGA Out (IOCNET) 232, 279
block description 37
Digital InOut (Class 2) 106 I-FPGA64 In (IOCNET) 269
parameters page 39
Int 123 I-FPGA64 Out (IOCNET) 235, 281
FPGA_INT_BL 62
LED Out 107 Int 287
block description 63
Proc App Status 95 IOCNET Global Time 271
description page 64
Register In 72 LED Out 284
DS1202 FPGA I/O Type 1 123
Register Out 81 Register In 243
FPGA1401Tp1 with DS1552 536
Register64 In 75 Register Out 253
FPGA1401Tp1 with DS1552B1 536
Register64 Out 83 Register64 In 246
FPGA1401Tp1 with DS1554 580
Status In 94 Register64 Out 256
parameters page

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 Index

DS1202 FPGA I/O Type 1 122 DS6651 Multi-I/O Module 416 FPGA1401Tp1 with DS1554 547
DS1303 (KU15P) Multi-I/O Board 192 FPGA1401Tp1 with DS1552 513 FPGA1403Tp1 with DS1552 594
DS2655 FPGA Base Board 239 FPGA1401Tp1 with DS1552B1 513 FPGA1403Tp1 with DS1552B1 594
DS6601 FPGA Base Board 286 FPGA1401Tp1 with DS1554 571 FPGA1403Tp1 with DS1554 657
DS6602 FPGA Base Board 343 FPGA1403Tp1 with DS1552 623 unit page 51
FPGA1401Tp1 with DS1552 535 FPGA1403Tp1 with DS1552B1 623 FPGA1401Tp1 with DS1552
FPGA1401Tp1 with DS1552B1 535 FPGA1403Tp1 with DS1554 683 ADC (Type A) 497
FPGA1401Tp1 with DS1554 579 Inter-FPGA Interface 471 ADC (Type B) 499
FPGA1403Tp1 with DS1552 645 MGT module 458 Buffer In 482
FPGA1403Tp1 with DS1552B1 645 scaling page Buffer Out 490
FPGA1403Tp1 with DS1554 691 DS1202 FPGA I/O Type 1 117 Buffer64 In 485
unit page 64 DS1303 (KU15P) Multi-I/O Board 188 Buffer64 Out 493
FPGA_IO_READ_BL 54 DS2655M1 I/O Module 363 DAC 514
block description 54 DS2655M2 I/O Module 397 Digital Crank/Cam Sensor 500
description page 56 DS6651 I/O Module 445 Digital In (Type A) 502
DS1202 FPGA I/O Type 1 98 FPGA1401Tp1 with DS1552 531 Digital In (Type B) 504
FPGA1401Tp1 with DS1552 512 FPGA1401Tp1 with DS1552B1 531 Digital Out (Type A) 515
FPGA1401Tp1 with DS1552B1 512 FPGA1401Tp1 with DS1554 577 Digital Out (Type B) 517
FPGA1401Tp1 with DS1554 570 FPGA1403Tp1 with DS1552 642 Inductive Zero Voltage Detector 506
parameters page FPGA1403Tp1 with DS1552B1 642 Int 535
DS1202 FPGA I/O Type 1 88 FPGA1403Tp1 with DS1554 690 LED Out 519
DS1303 (KU15P) Multi-I/O Board 147 unit page 60 Register In 481
DS2655 FPGA Base Board 218 FPGA_SETUP_BL 24 Register Out 489
DS2655M1 I/O Module 345 block description 24 Register64 In 483
DS2655M2 I/O Module 369 ConfigurationDesk interface page 33 Register64 Out 492
DS6601 FPGA Base Board 263 parameters page 26 Sensor Supply 519
DS6602 FPGA Base Board 310 subsystem clocks page 30 Status In 507
DS6651 Multi-I/O Module 401 tracing page 31 Temperature 507
FPGA1401Tp1 with DS1552 496 unit page 25 UART (RS232) 520
FPGA1401Tp1 with DS1552B1 496 FPGA_XDATA_READ_BL 44 UART (RS422/485) 525
FPGA1401Tp1 with DS1554 556 block description 45 FPGA1401Tp1 with DS1552B1
FPGA1403Tp1 with DS1552 603 description page 48 ADC (Type A) 497
FPGA1403Tp1 with DS1552B1 603 DS1202 FPGA I/O Type 1 77 ADC (Type B) 499
FPGA1403Tp1 with DS1554 666 FPGA1401Tp1 with DS1552 486 Buffer In 482
Inter-FPGA Interface 465 FPGA1401Tp1 with DS1554 546 Buffer Out 490
MGT module 451 parameters page Buffer64 In 485
scaling page DS1202 FPGA I/O Type 1 70 Buffer64 Out 493
DS1202 FPGA I/O Type 1 95 DS1303 (KU15P) Multi-I/O Board 126 DAC 514
DS1303 (KU15P) Multi-I/O Board 165 DS2655 FPGA Base Board 197 Digital Out (Type A) 515
DS2655M1 I/O Module 350 DS6601 FPGA Base Board 242 Int 535
DS2655M2 I/O Module 377, 413 DS6602 FPGA Base Board 289 LED Out 519
FPGA1401Tp1 with DS1552 509 FPGA1401Tp1 with DS1552 479 Register In 481
FPGA1401Tp1 with DS1552B1 509 FPGA1401Tp1 with DS1552B1 479 Register Out 489
FPGA1401Tp1 with DS1554 566 FPGA1401Tp1 with Engine Control 539 Register64 In 483
FPGA1403Tp1 with DS1552 620 FPGA1403Tp1 with DS1552 585 Register64 Out 492
FPGA1403Tp1 with DS1552B1 620 FPGA1403Tp1 with DS1552B1 585 Sensor Supply 519
FPGA1403Tp1 with DS1554 679 FPGA1403Tp1 with Engine Control 648 Temperature 507
unit page 55 unit page 46 UART (RS232) 520
FPGA_IO_WRITE_BL 58 FPGA_XDATA_WRITE_BL 49 UART (RS422/485) 525
block description 59 block description 50 FPGA1401Tp1 with DS1554
description page 60 description page 53 ADC (Type A) 563
DS1202 FPGA I/O Type 1 121 DS1202 FPGA I/O Type 1 86 Buffer In 542
FPGA1401Tp1 with DS1552 534 FPGA1401Tp1 with DS1552 495 Buffer Out 550
FPGA1401Tp1 with DS1552B1 534 FPGA1401Tp1 with DS1552B1 495 Buffer64 In 544
FPGA1401Tp1 with DS1554 578 FPGA1401Tp1 with DS1554 554 Buffer64 Out 553
parameters page parameters page Digital Crank/Cam Sensor 557
DS1202 FPGA I/O Type 1 100 DS1202 FPGA I/O Type 1 79 Digital In (Type B) 561
DS1303 (KU15P) Multi-I/O Board 169 DS1303 (KU15P) Multi-I/O Board 135 Digital Out (Type A) 573
DS2655 FPGA Base Board 230 DS2655 FPGA Base Board 206 Digital Out (Type B) 575
DS2655M1 I/O Module 354 DS6601 FPGA Base Board 251 Inductive Zero Voltage Detector 558
DS2655M2 I/O Module 378 DS6602 FPGA Base Board 298 Int 580
DS6601 FPGA Base Board 276 FPGA1401Tp1 with DS1552 488 Knock Sensor 565
DS6602 FPGA Base Board 323 FPGA1401Tp1 with DS1552B1 488 LED Out 572

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 Index

Register In 541 Buffer64 Out 662 DS6601 FPGA Base Board 271
Register Out 549 Bus In 655 DS6602 FPGA Base Board 318
Register64 In 543 Bus Out 664 MicroLabBox II 161
Register64 Out 552 Digital Crank/Cam Sensor 668
Sensor Supply 572 Digital InOut 8 (In) 671 K
Status In 557 Digital InOut 8 (Out) 687
Knock Sensor
Temperature 560 Digital Out 7 685
FPGA1401Tp1 with DS1554 565
FPGA1403Tp1 with DS1552 Inductive Zero Voltage Detector 669
FPGA1403Tp1 with DS1554 675
Analog In 10 604 Int 692
Analog In 12 607 Knock Sensor 675
Analog Out 13 624 LED Out 684 L
Buffer In 588 Register In 650 LED Out
Buffer Out 597 Register Out 659 DS1202 FPGA I/O Type 1 107
Buffer64 In 590 Register64 In 652 DS2655 FPGA Base Board 237
Buffer64 Out 599 Register64 Out 661 DS6601 FPGA Base Board 284
Bus In 592 Sensor Supply 684 DS6602 FPGA Base Board 340
Bus Out 601 Status In 667 FPGA1401Tp1 with DS1552 519
Digital Crank/Cam Sensor 609 Subsystem Clock 677 FPGA1401Tp1 with DS1552B1 519
Digital In 5 610 System Signal Block 678 FPGA1401Tp1 with DS1554 572
Digital InOut 6 (In) 612 Temperature 670 FPGA1403Tp1 with DS1552 629
Digital InOut 6 (Out) 627 User Clock Out 689 FPGA1403Tp1 with DS1552B1 629
Digital Out 5 626 FPGA1403Tp1 with DS1554 684
Inductive Zero Voltage Detector 614 I MicroLabBox II 186
Int 646 Local Program Data folder 13
I‑FPGA In
LED Out 629
DS2655 FPGA Base Board 465
Register In 587
I-FPGA In (IOCNET) M
Register Out 596
DS2655 FPGA Base Board 222 MGT In
Register64 In 589
DS6601 FPGA Base Board 267 MicroLabBox II 161
Register64 Out 598
DS6602 FPGA Base Board 314 SCALEXIO 454
Sensor Supply 630
I‑FPGA Out MGT In Opto Ready
Status In 616
DS2655 FPGA Base Board 471 MicroLabBox II 163
Subsystem Clock 616, 617
I-FPGA Out (IOCNET) SCALEXIO 456
System Signal Block 617
DS6601 FPGA Base Board 232, 279 MGT Out
Temperature 618
DS6602 FPGA Base Board 335 MicroLabBox II 187
UART 3 (RS232) 631
I-FPGA64 In (IOCNET) SCALEXIO 461
UART 3 (RS422/485) 636
DS2655 FPGA Base Board 224 MicroLabBox II
User Clock Out 641
DS6601 FPGA Base Board 269 Analog In 23 148
FPGA1403Tp1 with DS1552B1
DS6602 FPGA Base Board 316 Analog In 24 149
Analog In 11 605
I-FPGA64 Out (IOCNET) Analog In 25 151
Analog In 12 607
DS6601 FPGA Base Board 235, 281 Analog Out 19 170
Analog Out 13 624
DS6602 FPGA Base Board 338 Analog Out 20 171
Buffer In 588
Inductive Zero Voltage Detector APU Master 173
Buffer Out 597
FPGA1401Tp1 with DS1552 506 APU Slave 1 ... 6 153
Buffer64 In 590
FPGA1401Tp1 with DS1554 558 Aurora 64b66b 128 Bit In 157
Buffer64 Out 599
FPGA1403Tp1 with DS1552 614 Aurora 64b66b 128 Bit Out 176
Bus Out 601
FPGA1403Tp1 with DS1554 669 Aurora 64b66b In 155
Digital Out 5 626
Int Aurora 64b66b Out 175
Int 646
DS1202 FPGA I/O Type 1 123 Buffer In 128
LED Out 629
DS2655 FPGA Base Board 240 Buffer Out 137
Register In 587
DS6601 FPGA Base Board 287 Buffer64 In 129
Register Out 596
DS6602 FPGA Base Board 343 Buffer64 Out 140
Register64 In 589
FPGA1401Tp1 with DS1552 535 Bus In 131
Register64 Out 598
FPGA1401Tp1 with DS1552B1 535 Bus Out 142
Sensor Supply 630
FPGA1401Tp1 with DS1554 580 CN App Status 159
Temperature 618
FPGA1403Tp1 with DS1552 646 Digital In/Out 14 (In) 159
UART 3 (RS232) 631
FPGA1403Tp1 with DS1552B1 646 Digital In/Out 14 (In/Out‑Z) 178
UART 3 (RS422/485) 636
FPGA1403Tp1 with DS1554 692 Digital In/Out 15 183
User Clock Out 641
MicroLabBox II 192 Int 192
FPGA1403Tp1 with DS1554
Inter-FPGA Interface 464 IOCNET Global Time 161
Analog In 14 673
I‑FPGA In 465 LED Out 186
Buffer In 651
I‑FPGA Out 471 MGT In 161
Buffer Out 660
IOCNET Global Time MGT In Opto Ready 163
Buffer64 In 653
DS2655 FPGA Base Board 226 MGT Out 187

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FPGA Programming Blockset - FPGA Interface Reference May 2024
 Index

Register In 132 FPGA1403Tp1 with DS1554 661 FPGA1401Tp1 with DS1554 560
Register Out 144 MicroLabBox II 145 FPGA1403Tp1 with DS1552 618
Register64 In 133 RS232 Rx FPGA1403Tp1 with DS1552B1 618
Register64 Out 145 DS2655M2 I/O Module 372 FPGA1403Tp1 with DS1554 670
Status In 163 RS232 Tx Trigger
Watchdog 164 DS2655M2 I/O Module 389 DS6651 Multi-I/O Module 445
RS485 Rx
P DS2655M2 I/O Module 374 U
DS6651 Multi-I/O Module 410
Parameters page UART (RS232)
RS485 Rx/Tx
empty 20 DS1202 FPGA I/O Type 1 108
DS2655M2 I/O Module 390
Proc App Status FPGA1401Tp1 with DS1552 520
DS6651 Multi-I/O Module 438
DS1202 FPGA I/O Type 1 95 FPGA1401Tp1 with DS1552B1 520
RS485 Tx
UART (RS422/485)
DS2655M2 I/O Module 394
R DS1202 FPGA I/O Type 1 113
DS6651 Multi-I/O Module 442
FPGA1401Tp1 with DS1552 525
register
FPGA1401Tp1 with DS1552B1 525
access type 46, 51 S UART 3 (RS232)
Register In
SCALEXIO FPGA1403Tp1 with DS1552 631
DS1202 FPGA I/O Type 1 72
Aurora 64b66b 128 Bit In 453 FPGA1403Tp1 with DS1552B1 631
DS2655 FPGA Base Board 198
Aurora 64b66b 128 Bit Out 460 UART 3 (RS422/485)
DS6601 FPGA Base Board 243
Aurora 64b66b In 451 FPGA1403Tp1 with DS1552 636
DS6602 FPGA Base Board 290
Aurora 64b66b Out 458 FPGA1403Tp1 with DS1552B1 636
FPGA1401Tp1 with DS1552 481
FPGA blockset 196, 241, 288, 464 User Clock Out
FPGA1401Tp1 with DS1552B1 481
MGT In 454 DS2655 FPGA Base Board 238
FPGA1401Tp1 with DS1554 541
MGT In Opto Ready 456 DS6601 FPGA Base Board 284
FPGA1403Tp1 with DS1552 587
MGT Out 461 DS6602 FPGA Base Board 341
FPGA1403Tp1 with DS1552B1 587
Sensor Supply FPGA1403Tp1 with DS1552 641
FPGA1403Tp1 with DS1554 650
FPGA1401Tp1 with DS1552 519 FPGA1403Tp1 with DS1552B1 641
MicroLabBox II 132
FPGA1401Tp1 with DS1552B1 519 FPGA1403Tp1 with DS1554 689
Register Out
FPGA1401Tp1 with DS1554 572
DS1202 FPGA I/O Type 1 81
FPGA1403Tp1 with DS1552 630 W
DS2655 FPGA Base Board 208
FPGA1403Tp1 with DS1552B1 630
DS6601 FPGA Base Board 253 Watchdog
FPGA1403Tp1 with DS1554 684
DS6602 FPGA Base Board 300 DS6601 FPGA Base Board 275
Status In
FPGA1401Tp1 with DS1552 489 DS6602 FPGA Base Board 322
DS1202 FPGA I/O Type 1 94
FPGA1401Tp1 with DS1552B1 489 MicroLabBox II 164
DS2655 FPGA Base Board 226
FPGA1401Tp1 with DS1554 549
DS6601 FPGA Base Board 271
FPGA1403Tp1 with DS1552 596
DS6602 FPGA Base Board 318
FPGA1403Tp1 with DS1552B1 596
FPGA1401Tp1 with DS1552 507
FPGA1403Tp1 with DS1554 659
FPGA1401Tp1 with DS1554 557
MicroLabBox II 144
FPGA1403Tp1 with DS1552 616
Register64 In
FPGA1403Tp1 with DS1554 667
DS1202 FPGA I/O Type 1 75
MicroLabBox II 163
DS2655 FPGA Base Board 201
Subsystem Clock
DS6601 FPGA Base Board 246
DS2655 FPGA Base Board 227
DS6602 FPGA Base Board 293
DS6601 FPGA Base Board 272
FPGA1401Tp1 with DS1552 483
DS6602 FPGA Base Board 319
FPGA1401Tp1 with DS1552B1 483
FPGA1403Tp1 with DS1552 616, 617
FPGA1401Tp1 with DS1554 543
FPGA1403Tp1 with DS1554 677
FPGA1403Tp1 with DS1552 589
System Signal Block
FPGA1403Tp1 with DS1552B1 589
DS2655 FPGA Base Board 228
FPGA1403Tp1 with DS1554 652
DS6601 FPGA Base Board 273
MicroLabBox II 133
DS6602 FPGA Base Board 320
Register64 Out
FPGA1403Tp1 with DS1552 617
DS1202 FPGA I/O Type 1 83
FPGA1403Tp1 with DS1554 678
DS2655 FPGA Base Board 211
DS6601 FPGA Base Board 256
DS6602 FPGA Base Board 303 T
FPGA1401Tp1 with DS1552 492 Temperature
FPGA1401Tp1 with DS1552B1 492 DS6601 FPGA Base Board 274
FPGA1401Tp1 with DS1554 552 DS6602 FPGA Base Board 321
FPGA1403Tp1 with DS1552 598 FPGA1401Tp1 with DS1552 507
FPGA1403Tp1 with DS1552B1 598 FPGA1401Tp1 with DS1552B1 507

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May 2024 FPGA Programming Blockset - FPGA Interface Reference
 Index

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