Digital Fundamentals: Logic Gates
Digital Fundamentals: Logic Gates
Digital Fundamentals: Logic Gates
CHAPTER 3
Logic Gates
Slide 1
Logic Gates
• Inverter
• AND Gate
• OR Gate
• Exclusive-OR Gate
• NAND Gate
• NOR Gate
• Exclusive-NOR Gate
Slide 2
The Inverter
Slide 3
The Inverter
Slide 4
Figure 3–2 Inverter operation with a pulse input. Open file F03-02 to verify inverter operation.
Slide 5
Figure 3–4
What is the output waveform?
Slide 6
Figure 3–6 The inverter complements an input variable.
Slide 7
Figure 3–7 Example of a 1’s complement circuit using inverters.
Slide 8
The AND Gate
Slide 9
The AND Gate
Boolean expression
Slide 10
The AND Gate
Slide 11
Truth Tables
Slide 12
Figure 3–16 A simple seat belt alarm circuit using an AND gate.
If all three inputs are high, then the output is high and the alarm is activated.
If (Ignition switch = ON) AND (Seat belt = Unbuckled) AND (Timer = ON) then
Activate Alarm
End If
Slide 13
The OR Gate
Slide 14
The OR Gate
Boolean expression
Slide 15
The OR Gate
3-Input OR Gate
4-Input OR Gate
Slide 16
Figure 3–24 A simplified intrusion detection system using an OR gate.
Front
Door
Back
Door
Window
If any of the three inputs are high, then the output is high and the alarm is activated.
If (Front Door = Open) OR (Back Door = Open) OR (Window = Open) then
Activate Alarm
End If Slide 17
The NAND Gate
Slide 18
The NAND Gate
Boolean expression
Truth table
0 = LOW
1 = HIGH
Pulsed waveforms
Slide 19
Figure 3–29
Standard symbols representing the two equivalent operations of a NAND gate.
X = AB = A + B X = A + B = AB
Slide 20
The NAND Gate
Slide 21
The NOR Gate
Slide 22
The NOR Gate
Boolean expression
Truth table
0 = LOW
1 = HIGH
Pulsed waveforms
Slide 23
The NOR Gate
Slide 24
Figure 3–37
Standard symbols representing the two equivalent operations of a NOR gate.
X=A+B=AB X=AB=A+B
Slide 25
Exclusive-OR and Exclusive-NOR Gates
Slide 26
Exclusive-OR Gate
Boolean expression
Truth table
0 = LOW
1 = HIGH
Pulsed waveforms
Slide 27
Exclusive-NOR Gate
Boolean expression
Truth table
0 = LOW
1 = HIGH
Pulsed waveforms
Slide 28
Figure 3–48 An XOR gate used to add two bits.
Slide 29
Review of Basic Logic Gates
• Inverter
• AND Gate
• OR Gate
• Exclusive-OR Gate
• NAND Gate
• NOR Gate
• Exclusive-NOR Gate
Slide 30
Programmable Logic
Slide 31
Programmable Logic
Slide 32
Programmable Logic
Slide 33
Example 3-21
Slide 34
Programmable Logic
Programmable link technology
• Fuse technology
Fuse is permanently open
• Anti-fuse technology
Anti-fuse is permanently closed
• EPROM technology
Electrically Programmable Read-Only Memories
Can be erased and reprogrammed with UV light
• EEPROM technology
Electrically Erasable Programmable Read-Only Memories
In-System Programming (ISP)
Doesn’t need UV light to erase.
• SRAM technology
Static Random Access Memory
Volatile – Doesn’t retain data when power is turned off
Slide 35
Fixed-Function Logic
Slide 36
Fixed-Function Logic
• CMOS
– Complementary Metal-Oxide Semiconductor
• TTL
– Transistor-Transistor Logic
• Logic Functions operate the same in
CMOS and TTL.
• Different voltage, power, speed
Slide 37
CMOS
Slide 38
TTL
• DC Voltage is 5 V
• Not sensitive to electrostatic discharge.
Slide 39
Figure 3–60 Typical dual in-line (DIP) and small-outline (SOIC) packages showing pin
numbers and basic dimensions.
Slide 40
Figure 3–61 Pin configuration diagrams for some common fixed-
function IC gate configurations.
Slide 41
Figure 3–63 Propagation Delay
Slide 42
Power Dissipation
• Power Dissipation, PD
I I CCL
PD VCC CCH
2
Slide 43
Speed Power Product
Slide 44
Figure 3–65 The partial data sheet for a 74LS00.
Slide 45
Figure 3–67
The effect of an open input on a NAND gate.
Slide 46
• Troubleshooting the NAND gate.
Slide 47
• Troubleshooting the NOR gate.
Slide 48
Problem 2.
If a HIGH is applied to point A, what is the logic level at points C, E, and F?
Slide 49
Review
Slide 50