System Verilog Object Oriented Programming and

Classes
 OUTLINE
• Classes
• “this” keyword
• Constructors
• Class Assignment
• Shallow Copy and Deep Copy
• Inheritance
• Polymorphism
• Overriding Class members
• “super” keyword
• Casting
• Data hiding and Encapsulation
• Virtual methods and Extern methods
 Introduction to Classes
• A class is a user-defined data type that includes data (class
properties), functions and tasks that operate on data.
• An object is used by first declaring a variable of that class type
(that holds an object handle) and then creating an object of
that class (using the new function) and assigning it to the
variable.

The class sv_class has one data

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 Class Instance and Object Creation
• Class declaration/Class Instance: - As we know the class is a data
type. Declaring class type variable is similar to declaring other
variables.
• sv_class class_1;
• The above statement shows declaration of variable class_1 with the
type sv_class.
• In other words, variable class_1 can contain a handle to an instance
of the class sv_class.
• Class properties and methods can be accessed only after creating the
object.
Class Example
Class Constructor
Class Constructor
 Class Constructors
• The new function is called as class
constructor.
• On calling the new method it
allocates the memory and returns
the address to the class handle.
• Constructors should be function and
not a task.
• Constructors does not return values.
• Constructors like any other function
take input parameters.
• There can be only one constructor
per class.

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“this” keyword
 “this” keyword
• “this” keyword is used to refer to class properties.
• “this” keyword is used to unambiguously refer to class properties or methods of
the current instance. “this” keyword refers to the object handle in which it is
invoked.

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Static Class members
• Static class members : - Class members can be created with the keyword
static class members with the keyword static are called as static class
members. The class can have static properties and static methods
(functions and tasks).
• Static Properties: - The class can have multiple instances, each instance
of the class will be having its own copy of variables. Sometimes only one
version of a variable is required to be shared by all instances. These class
properties are created using the keyword static.
• A static method can access only static properties of the class and access to
the non-static properties is illegal and lead to a compilation error.
 Static Class Members

Static variable no_of_pkts_created, no_of_pkts_created will get
incremented on every object creation.
Illegal usage of Static Class members
Correct usage of Static class
 Class Assignment
• Object will be created only after doing new to an class handle,
• packet   pkt_1;
pkt_1  = new();
packet   pkt_2;
pkt_2  = pkt_1;
• In the above piece of code, an object is created only for pkt_1, pkt_2 is just
a handle to the packet.
• pkt_1 is assigned to the pkt_2. So only one object has been created, pkt_1
and pkt_2 are two handles both are pointing to the same object
• As both the handles are pointing to the same object any changes made with
respect to pkt_1 will reflect on pkt_2.
Class Assignment
Example: Class Assignment
 Shallow Copy

An object will be created only after doing new to a class handle,

packet pkt_1;

pkt_1 = new();

packet pkt_2;

pkt_2 = new pkt_1;
In the last statement, pkt_2 is created and class properties were copied
from pkt_1 to pkt_2, this is called as “shallow copy”.
Shallow copy allocates the memory, copies the variable values and returns
the memory handle.
In shallow copy, All of the variables are copied across: integers, strings,
instance handles, etc.
Note: Objects will not be copied, only their handles will be copied to
perform the full or deep copy, the custom method can be added.
Shallow Copy
SystemVerilog Shallow Copy Limitation
Difference between assignment and shallow copy
 SystemVerilog deep copy

SystemVerilog deep copy copies all the class members and its nested
class members. unlike in shallow copy, only nested class handles will
be copied.

In shallow copy, Objects will not be copied, only their handles will be
copied. to perform a full or deep copy, the custom method needs to be
added.

In the custom method, a new object is created, all the class properties
will be copied to a new handle and the new handle will be returned.
SystemVerilog deep copy
Example: Deep Copy
Example: Deep Copy
Example: Deep Copy simulator result
 SystemVerilog Parameterized Classes

Parameterized classes are same as the parameterized modules in the
Verilog. parameters are like constants local to that particular class.

The parameter value can be used to define a set of attributes in class.
default values can be overridden by passing a new set of parameters
during instantiation. this is called parameter overriding.
SystemVerilog Parameterized Classes
 SV inheritance

SystemVerilog Inheritance. Inheritance is an OOP concept that allows the
user to create classes that are built upon existing classes. The new class will
be with new properties and methods along with having access to all the
properties and methods of the original class. Inheritance is about inheriting
base class members to the extended class.

New classes can be created based on existing classes, this is referred to
as class inheritance

A derived class by default inherits the properties and methods of its
parent class

An inherited class is called a subclass of its parent class

A derived class may add new properties and methods, or modify the
inherited properties and methods

Inheritance allows re-usability. i.e. derived class by default includes the
properties and methods, which is ready to use

If the class is derived from a derived class, then it is referred to as
Multilevel inheritance
 Polymorphism in SV

Polymorphism means many forms. Polymorphism in SystemVerilog
provides an ability to an object to take on many forms.

Method handle of super-class can be made to refer to the subclass
method, this allows polymorphism or different forms of the same
method.
Polymorphism in SV
Example

Simulator Output: -
 Overriding Class member example

The parent class has the method display().

display() method is re-defined in the child class, which will override
the parent class method.

c is the handle to the child class, because of override calling
c.display will call display method of the child class, not the parent
class.
 System Verilog Inheritance
•

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 Overriding Class members
• Base class or parent class properties and methods can be overridden in the
child class .
• Defining the class properties and methods with the same name as parent
class in the child class will override the class members.

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 Super keyword

The super keyword is used in a derived class to refer to the members
of the parent class.

When class members are overridden in the derived class, It is
necessary to use the super keyword to access members of a parent
class.

With super keyword, it is allowed to access the class members of
parent class which is only one level up.

If the method of the parent class is overridden in the child class, then
using the ‘super’ keyword parent class method can be accessed from
the child class.
“Super” Keyword
 “Super” Keyword
• When class  members are overridden in
the derived class, it is necessary to use
the super keyword to access members
of a parent class.
• With super keyword, it is allowed to
access the class members of parent class
which is only one level up.

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 Data hiding and encapsulation
• Data hiding and Encapsulation:
The technique of hiding the data within the
class and making it available only through
the methods (i.e., by the methods of the
class) is known as encapsulation. 
• Access Control: Access control rules that
restrict the members of a class from being
used outside the class.
• This is achieved by prefixing the class
members with the keywords: local and
keyword.

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 Extern Functions
• The definition of the method
written outside the body of the
class then the method is called an
external method.
• External functions need to declare
the method (Function/Task) with
an extern keyword.
• The extern qualifier indicates that
the body of the method (its
implementation) is to be found
outside the class declaration.

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SV Interface

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SV Interfaces

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