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I/O Resources
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2015.1
 Objectives
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100247**slide

After completing this module, you will be able to:

Describe the I/O features in UltraScale FPGAs

Specify the relationship between banks and

standards Explain each block in the IOB

Describe the SelectIO™ interface logic and SERDES

technology in component mode

Describe the SelectIO interface logic and SERDES technology

in native mode

I/O Resources - 1-2 © Copyright 2015 Xilinx 100245

 Overview
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100248**slide

 Overview
 Electrical Resources
 Logical Resources –
Component Mode
 Logical Resources – Native
Mode
 Summary

I/O Resources - 1-3 © Copyright 2015 Xilinx 100245

 I/O Interface Challenges
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H Source-synchronous operation (clock forwarding)

—
i
— System-synchronous operation (common systems
g
— clock) Terminate transmission lines to avoid signal
h reflections
-Drive and receive data on wide parallel buses
s
— Compensate for bus skew and clock timing errors
p
— Conversion between serial and parallel data

—e Achieve very high bit rate (> 1 Gbps)

e
d
Single data rate (SDR) or double data rate (DDR)
interfaces
o
p
Interface
— Different to many drive
voltages, different standards
strengths and protocols
e
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I/O Resources - 1-4 © Copyright 2015 Xilinx
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 UltraScale FPGA I/O
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Easy interfacing to
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Wide range standard memories

of voltages
— 1.0V to 3.3V operation — Hardware support for
QDRII+ and DDR4
Many different
I/O standards Digitally
— Single ended and controlled
differential impedance
— Referenced inputs
— 3-state support Low
— power
Features to reduce
power
Very high
performance Advanced
— Up to 2400 Mbps signal integrity
single-ended for DDR4 — Transmitter
pre-emphasis
— Receiver
equalization
I/O Resources - 1-5 © Copyright 2015 Xilinx 100245
 I/O Block Diagram
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100258**slide

I/O Resources - 1-6 © Copyright 2015 Xilinx 100245

 I/O Types
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T High Range (HR)

—
w • Supports I/O standards with VCCO voltages up to 3.3V
o
— High Performance (HP)
d•
Supports I/O standards with VCCO voltages up to 1.8V only
i
 Designed for the highest performance
f • Has digitally controlled impedance (DCI), receiver offset control, and receiver V REF scan
f
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I/O Resources - 1-7 © Copyright 2015 Xilinx
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 UltraScale Architecture I/O Columns
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100262**slide

I/O Resources - 1-8 © Copyright 2015 Xilinx 100245

 Electrical Resources
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100249**slide

 Overview
 Electrical Resources
 Logical Resources –
Component Mode
 Logical Resources – Native
Mode
 Summary

I/O Resources - 1-9 © Copyright 2015 Xilinx 100245

 I/O Versatility
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Each pin can be configured as an input, an output (including 3-state),

or bidirectional (input/output)
Most adjacent pairs of pins can be used differential I/O

Each I/O supports 40+ voltage and protocol standards,

including
— Conventional I/O
 LVCMOS (1.2V to 3.3V), LVTTL
 Supports programmable slew rate
o SLOW or FAST for HR banks
o SLOW, MEDIUM or FAST for HP banks
 Supports programmable drive strength (2mA to 16mA)
— Referenced I/O
 HSTL (1.2V, 1.5V, 1.8V), SSTL (1.8V, 1.5V, 1.35V, 1.2V), HSUL (1.2V),
POD (1.0V, 1.2V)
— Differential I/O
 LVDS (1.8V, 2.5V) , LVPECL , TMDS, PPDS, Mini-LVDS, BLVDS, SUB_LVDS,
SLVS_400
I/O Resources - 1-10 © Copyright 2015 Xilinx 100245
 I/O Electrical Resources
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P Individual single-ended signals or

—

— Differential pair
a
n
Receiver can be standard
d
CMOS or voltage comparator
— When standard CMOS
N Logic 0 when “near” ground

p
Logic 1 when “near” VCCO
i Referenced to VREF
—

n•
Logic 0 when below VREF
s
— • Logic 1 when above VREF

c Differential
a • Logic 0 when VP < VN
n • Logic 1 when VP > VN
I/O Resources - 1-11 © Copyright 2015 Xilinx 100245
 VREF Source
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VREF for a bank that uses referenced standards can be supplied externally
via a dedicated VREF pin or can be generated internally
There is one dedicated VREF pin per bank
— Connect to the appropriate voltage when using external VREF

— Tie to ground when using internal VREF or no VREF

Internal VREF is generated from the VCCO power supply

— Voltage is determined by the attribute INTERNAL_VREF attribute

 Legal values are 0.60, 0.675, 0.70, 0.75, 0.84, or 0.90 (in Volts)

Internal VREF can be dynamically tuned in HP banks using the HPIO_VREF

primitive
— Provides a fabric controlled interface, allowing VREF scanning to maximize

data eye
— Each HPIO_VREF tunes the VREF for ¼ of the pins in a bank (one byte

group)
I/O Resources - 1-12 © Copyright 2015 Xilinx 100245
 I/O Bank and Clock Region
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I/O banks are the same height as

the clock region
— 52 I/Os per bank

— 60 CLBs per clock region column

Each I/O bank can have one VCCO

— VCCO determines the drive voltage of most
outputs and is used for conventional inputs
(not differential or referenced inputs)
— Only I/O standards compatible with VCCO
can be placed in the bank

Each I/O bank can have one VREF

I/O Resources - 1-13 © Copyright 2015 Xilinx 100245

 On-Die Termination (ODT)
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C Supported for HSTL, SSTL, HSUL, LVDCI, HSLVDCI,

—
o and POD drivers
n Controlled by OUTPUT_IMPEDANCE attribute
—

t  Programmable to 40Ω, 48Ω, or 60Ω

r
o
Single ended input termination to VCCO
l Supported for POD and HSUL I/O
—

l Controlled by ODT attribute

—

e
d
Split input termination
— Equivalent to termination to VCCO/2 of impedance R
i Supported for HSTL and SSTL I/O
—

mControlled by ODT attribute

—

p Programmable to 40Ω, 48Ω, or 60Ω

e
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I/O Resources - 1-14 © Copyright 2015 Xilinx 100245
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 Termination Calibration
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ODT can be uncalibrated or calibrated using digitally

controlled impedance (DCI)
— DCI is enabled by setting the I/O standard to the corresponding DCI

standard (i.e. HSTL_I_DCI instead of HSTL_I)

— DCI is only available in HP banks

When uncalibrated, impedance can vary from value specified

in ODT/OUTPUT_IMPEDANCE attribute by ±50%

When calibrated with DCI, impedance is calibrated using

a reference resistor
— Calibration reduces impedance variation to ±10% from the specified value
— Reference resistor must be 240Ω for all I/O standards and impedances
— Reference resistor must be connected to VRP pin in a bank using DCI or can
be supplied from another bank in the same column using DCI cascading

I/O Resources - 1-15 © Copyright 2015 Xilinx 100245

 Logical Resources – Component Mode
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100250**slide

 Overview
 Electrical Resources
 Logical Resources –
Component Mode
 Logical Resources – Native Mode
 Summary

I/O Resources - 1-16 © Copyright 2015 Xilinx 100245

 I/O Logical Resources
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T Master and slave

—
w
— Can operate independently or
o concatenated

b
Each block contains
l Input logic
—

o  SDR, DDR, or high-speed serial input logic

c Output logic
—

k  SDR, DDR, or high-speed serial output logic

s IDELAY
—

 Selectable fine-grained input delay

o ODELAY
—

f  Selectable fine-grained output delay

l
o
I/O Resources - 1-17 © Copyright 2015 Xilinx 100245
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 Input Logic
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Data from the IBUF (directly or through

the IDELAY) is routed to the input logic
— Data can pass through the input logic

(combinatorially) directly to the fabric

— Data can be captured with a single data rate

flip-flop
 Any inferred single data rate flip-flop can be
placed in the IOB by setting the IOB attribute of
the port to TRUE

— Data can be captured with a double data

rate flip-flop using the IDDRE1 primitive
 Captured on two clocks 180° out of phase or
on both edges of the same clock

— Data can be captured by the high-speed

input deserializer using the ISERDESE3
I/O Resources - 1-18 © Copyright 2015 Xilinx 100245
 Output Logic
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Data to the OBUF (directly or through the

ODELAY) is routed
— Data can pass from
through the output
the output logic
logic (combinatorially)
directly from the fabric

— Data can may be generated by a single data rate flip-flop

 Any inferred single data rate flip-flop can be placed in the
IOB by setting the IOB attribute of the port to TRUE

— Data can be generated with a double data rate flip-flop

using the ODDRE1 primitive
 Data is generated on both edges of the clock
 Only OPPOSITE_EDGE and SAME_EDGE modes
are supported

— Data can be generated by the high-speed output serializer

using the OSERDESE3
 OSERDESE3 can also generate the 3-state enable
(T_OUT) for 3-state or bidirectional I/O
I/O Resources - 1-19 © Copyright 2015 Xilinx 100245
 ISERDES: Input Serial-to-Parallel Converter
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C
— D is clocked on high-speed clock (CLK)
l— Can be SDR or DDR
o
Sends de-serialized data to fabric
c
— Q is clocked on low-speed clock (CLKDIV or
k FIFO_RD_CLK)
s
CLK and CLKDIV must be in phase
De-serializes data by 2 or 4 (SDR) or 4
i
or 8 (DDR)
n
Optional built-in 8 entry FIFO allows data to be read using
the
— FIFO_RD_CLK
Enabled by setting FIFO_ENABLE attribute to TRUE
d
— FIFO_RD_CLK can be synchronous to CLKDIV (FIFO_SYNC_MODE = TRUE) or
a asynchronous (FIFO_SYNC_MODE = FALSE)
t
a

f
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I/O Resources - 1-20 © Copyright 2015 Xilinx 100245

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 OSERDES: Output Parallel-to-Serial Converter
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S
— OQ and T_OUT are clocked on high-speed clock
e (CLK)
r Can be SDR or DDR
—

i
Parallel
a data comes from fabric
— D is synchronous to low-speed clock (CLKDIV)
l
— Supplies both data and 3-state values
i
CLK
z and CLKDIV must be in phase
Serializes
e data by 2 or 4 (SDR) or 2, 4, or 8 (DDR)
In
s addition to output data, provides 3-state
— 3-state control can be driven combinatorially from T input
control
o (OSERDES_T_BYPASS) or serialized using the same serialization factor as
the OQ
u  3-state and output data share the same D input bus; serialization is limited to 4:1
t

d
I/O Resources - 1-21 © Copyright 2015 Xilinx 100245
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 IDELAYE3 and ODELAYE3
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Each IOB has programmable delay

lines for both
— IDELAYE3 inputs
primitive and inputs
delays outputs
coming from
the IOB
 Output of IDELAYE3 drives the input logic
(direct to fabric, SDR, DDR, or ISERDESE3
capture)
— ODELAYE3 primitive delays outputs going to the
IOB
 Input to ODELAYE3 comes from the
output logic (direct from fabric, SDR, DDR,
or OSERDESE3 generation)

Each delay line has 512 delay elements

— Elements are not calibrated, and will vary over
process, voltage and temperature (PVT)
 2.5 ps to 10 ps per tap

I/O Resources - 1-22 © Copyright 2015 Xilinx 100245

 Tap Count Selection Control
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Tap count selection can be performed manually or can be

automatically controlled to maintain a specified time
delay
Enabling or disabling automatic selection is
dynamically controlled via the EN_VTC pin

When EN_VTC = 1, the tap value is set by a circuit that selects

the correct tap count to obtain the specified delay
— Delay is specified in picoseconds, up to 1250 ps (DELAY_VALUE)

When EN_VTC = 0, the automatic update stops and the value

can be changed manually
— Tap count can be incremented or decremented one at a time
— Tap count can be loaded to a particular value (0 <= count <= 511)

Current tap count value can be observed by the

fabric
I/O Resources - 1-23 © Copyright 2015 Xilinx 100245
 IDELAYCTRL
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When EN_VTC = 1, the tap setting of each

IDELAYE3 and ODELAYE3 is adjusted
based on calibration information generated
by a reference clock using the IDELAYCTRL

REFCLK to the IDELAYCTRL can be a clock

from 200 MHz to 800 MHz in steps of 100
MHz

The REFCLK_FREQUENCY of all

IDELAYE3/ODELAYE3 cells must be set to the
frequency of this clock

I/O Resources - 1-24 © Copyright 2015 Xilinx 100245

 IDELAYE3/ODELAYE3 Cascade
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If 1250 ps of delay is not enough for a given input or output,

the IDELAYE3/ODELAYE3 cells in an IOB pair can be cascaded

I/O Resources - 1-25 © Copyright 2015 Xilinx 100245

 Logical Resources – Native Mode
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100251**slide

 Overview
 Electrical Resources
 Logical Resources –
Component Mode
 Logical Resources –
Native Mode
 Summary

I/O Resources - 1-26 © Copyright 2015 Xilinx 100245

 Summary
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100252**slide

 Overview
 Electrical Resources
 Logical Resources –
Component Mode
 Logical Resources – Native
Mode
 Summary

I/O Resources - 1-27 © Copyright 2015 Xilinx 100245

Apply Your Knowledge

1. What are the two types of I/O in the UltraScale architecture

and what are the differences between them?

2. Can you identify the logical resource of the I/O in the

UltraScale architecture?

I/O Resources - 1-28 © Copyright 2015 Xilinx 100245

 Summary (1)
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T High Range for 3.3V I/O

—
w
— High Performance for the highest throughput at up to1.8V
o
Support for a large range of inputs, outputs and I/O
d
iSupport for many I/O
f
fprotocols Great performance
— e Up to 2400 Mbps single-ended for DDR4
— r Hardware support for QDR2+ and DDR4
e
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t
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I/O Resources - 1-29 © Copyright 2015 Xilinx 100245
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 Summary (2)
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D
iTransmitter pre-emphasis and receiver equalization
g
iSDR, DDR, and high-speed SERDES for
tmanaging high-performance interfaces
a
lCalibrated input and output delays for precise control over
ldata capture
y
Native mode control for implementing high speed
c
parallel interface (like DDR4)
o
n
t
r
o
I/O Resources - 1-30 © Copyright 2015 Xilinx 100245
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