ECE 424 Design of Microprocessor-Based Systems

Intel 8088 (8086) Microprocessor Structure

Haibo Wang
ECE Department
Southern Illinois University
Carbondale, IL 62901

3-1
 Overview
 Intel 8088 facts
 20 bit address bus allow accessing VDD (5V)
1 M memory locations
 16-bit internal data bus and 8-bit
20-bit
external data bus. Thus, it need 8-bit data
address
two read (or write) operations to
read (or write) a 16-bit datum control
8088 control
signals


 Byte addressable and byte-swapping signals


To 8088 from 8088
Word: 5A2F
CLK

18001 5A High byte of word

GND
18000 2F Low byte of word

8088 signal classification

Memory locations
3-2
 Organization of 8088
Address bus (20 bits)
AH AL General purpose
BH BL register 
CH CL
Execution Unit
DH DL
(EU) Data bus
SP CS (16 bits)
Segment
BP register DS
SI SS
DI ALU Data bus ES
(16 bits)
IP

Bus
control
ALU Instruction Queue External bus
EU
control
Flag register
Bus Interface Unit (BIU)
3-3
 General Purpose Registers
15 8 7 0
AX AH AL Accumulator

BX BH BL Base
Data Group
CX CH CL Counter

DX DH DL Data

SP Stack Pointer

BP Base Pointer
Pointer and
Index Group
SI Source Index

DI Destination Index

3-4
 Arithmetic Logic Unit (ALU)
A B F Y
n bits n bits
0 0 0 A+B
0 0 1 A -B
Carry
0 1 0 A -1
Y= 0 ? F 0 1 1 A and B
1 0 0 A or B
A>B?
1 0 1 not A
     
Y
 Signal F control which function will be conducted by ALU.
 Signal F is generated according to the current instruction.

 Basic arithmetic operations: addition, subtraction, 

 Basic logic operations: and, or, xor, shifting,
3-5
 Flag Register
 Flag register contains information reflecting the current status of a
microprocessor. It also contains information which controls the
operation of the microprocessor.
15 0
 NT IOPL OF DF IF TF SF ZF  AF  PF  CF

 Control Flags  Status Flags

IF: Interrupt enable flag CF: Carry flag

DF: Direction flag PF: Parity flag
TF: Trap flag AF: Auxiliary carry flag
ZF: Zero flag
SF: Sign flag
OF: Overflow flag
NT: Nested task flag
IOPL: Input/output privilege level

3-6
 Instruction Machine Codes
 Instruction machine codes are binary numbers
 For Example:

1000100011000011 MOV AL, BL

Register
MOV
mode
 Machine code structure

Opcode Mode Operand1 Operand2

 Some instructions do not have operands, or have only one operand

 Opcode tells what operation is to be performed.
(EU control logic generates ALU control signals according to Opcode)
 Mode indicates the type of a instruction: Register type, or Memory type
 Operands tell what data should be used in the operation. Operands can
be addresses telling where to get data (or where to store results)
3-7
 EU Operation

1. Fetch an instruction from instruction

queue AH AL General purpose
BH BL register
2. According to the instruction, EU control CH CL
logic generates control signals. DH DL
(This process is also referred to as instruction SP
BP
decoding)
SI
DI ALU Data bus
3. Depending on the control signal, (16 bits)
EU performs one of the following
operations:
 An arithmetic operation ALU
EU
 A logic operation control instruction
Flag register 1011000101001010
 Storing a datum into a register
 Moving a datum from a register
 Changing flag register

3-8
 Generating Memory Addresses
 How can a 16-bit microprocessor generate 20-bit memory addresses?

Left shift 4 bits

FFFFF

16-bit register 0000 Addr1 + 0FFFF

Segment
+ 16-bit register Offset
Addr1
Offset
(64K)

20-bit memory address Segment

address
00000

Intel 80x86 memory address generation 1M memory space

3-9
 Memory Segmentation
 A segment is a 64KB block of memory starting from any 16-byte
boundary
 For example: 00000, 00010, 00020, 20000, 8CE90, and E0840 are all valid
segment addresses
 The requirement of starting from 16-byte boundary is due to the 4-bit
left shifting

 Segment registers in BIU

15 0
CS Code Segment

DS Data Segment

SS Stack Segment

ES Extra Segment
3-10
 Memory Address Calculation

 Segment addresses must be stored 0000

Segment address
in segment registers
 Offset is derived from the combination + Offset

of pointer registers, the Instruction Memory address

Pointer (IP), and immediate values

 Examples

CS 3 4 8 A 0 SS 5 0 0 0 0
IP + 4 2 1 4 SP + F F E 0
Instruction address 3 8 A B 4 Stack address 5 F F E 0

DS 1 2 3 4 0
DI + 0 0 2 2
Data address 1 2 3 6 2
3-11
 Fetching Instructions
 Where to fetch the next instruction?
8088 Memory

CS 1234
IP 0012 12352 MOV AL, 0

12352

 Update IP
— After an instruction is fetched, Register IP is updated as follows:

IP = IP + Length of the fetched instruction

— For Example: the length of MOV AL, 0 is 2 bytes. After fetching this instruction,
the IP is updated to 0014

3-12
 Accessing Data Memory
 There is a number of methods to generate the memory address when
accessing data memory. These methods are referred to as
Addressing Modes
 Examples:
— Direct addressing: MOV AL, [0300H]

DS 1 2 3 4 0 (assume DS=1234H)
0 3 0 0
Memory address 1 2 6 4 0

— Register indirect addressing: MOV AL, [SI]

DS 1 2 3 4 0 (assume DS=1234H)
0 3 1 0 (assume SI=0310H)
Memory address 1 2 6 5 0

3-13
 Reserved Memory Locations
 Some memory locations are reserved for special purposes.
Programs should not be loaded in these areas
FFFFF
 Locations from FFFF0H to FFFFFH Reset FFFF0
are used for system reset code instruction
area

 Locations from 00000H to 003FFH

Interrupt
are used for the interrupt pointer table
pointer
 It has 256 table entries table
 Each table entry is 4 bytes
003FF
256  4 = 1024 = memory addressing space
From 00000H to 003FFH 00000

3-14
 Interrupts
 An interrupt is an event that occurs while the processor is executing a program
 The interrupt temporarily suspends execution of the program and switch the
processor to executing a special routine (interrupt service routine)
 When the execution of interrupt service routine is complete, the processor
resumes the execution of the original program
 Interrupt classification

Hardware Interrupts Software Interrupts

 Caused by activating the processor’s  Caused by the execution of an INT
interrupt control signals (NMI, instruction
INTR)  Caused by an event which is
generated
by the execution of a program, such
as division by zero

 8088 can have 256 interrupts

3-15
 Minimum and Maximum Operation modes
 Intel 8088 (8086) has two operation modes:

Minimum Mode Maximum Mode

 8088 generates control signals  It needs 8288 bus controller to generate
for memory and I/O operations control signals for memory and I/O
operations

 Some functions are not available  It allows the use of 8087 coprocessor;
in minimum mode it also provides other functions

 Compatible with 8085-based

systems

3-16