CMOS Transceiver for Nano-Photonic

Links in Data-Centers
Undergraduate Project
Solomon Micheal Serunjogi

Advisor: Dr. xx(xx@yy.ac.ug )

RSC member 1: Dr. yy(xx@yy.ac.ug)
RSC member 1: Mr. zz(xx@yy.ac.ug)

External Member: Dr. yy(xx@yy.ac.ug)

1
Outline

• Introduction
• Motivation
• Background
• Text
• Conclusion
• Future Work

2
Introduction

• High demand for bandwidth over the last ten years.

• IEEE 802.3bm debate/standardization for 100Gb/s and 400Gb/s.
• Silicon Photonic links emerging in data center (DC) applications
3
Modulation Formats in Data Centers

NRZ Duobinary PAM-4

Suffers from Chromatic dispersion(CD) More tolerant to CD than NRZ PAM-4 encodes 3 bits/symbol

Modulation Rate 10 Gb/s 25 Gb/s 40 Gb/s

NRZ 7 GHz 17.5 GHz 28 GHz
Duobinary Not in Scope 7 GHz 11 GHz
PAM-4 Not in Scope 9 GHz 14 GHz
IEEE 802.3 internet working group 4
Outline

• Introduction
• Motivation
• Modulation Techniques
• Linearity of photonic links
• Optical transceiver front end
• Clock and data Recovery
• Conclusion
• Future Work
5
Photonic Link Analysis

We developed a generic model for analysis of nonlinear photonic

systems:

Applications:
• Analyzing link performance based on key figures of merit

• Noise analysis in both photonic and electronic links.

• Link Budget Analysis for both photonic and electronic links
• Benchmarking performance of different systems

8/9/21 6
Linearity Analysis : in Photonic links

Linearity Analysis for Modern Multi-level Modulation formats

• Time domain analysis of Memoryless IMDD links using
Power series expansion (classical)

• Analysis of photonic links with memory effects– PM links

with demodulator at the receiver using Volterra Series/
Bell Polynomials (New)

• Link Analysis of Key Figures of Merit: photocurrent, OIP3,

IMD3. Use of Single tone, 2-tone and 3 tone tests (New)
7
PM Analog Link: Modelling

DATA

DATA

• At A: E( t )  Ps  1  a t   cos0 t    t  

• At B: h( t )  exp i0 t  i  t   a t  

• At C: s(t )   g  h t    du

8
Multi-tone Input

Two Tone Vm (t )  m1 cos1t  m2 cos2t

2l  N 2k M
 m1   m2 
     
2   2 
s  t   exp i  N1  M 2  t     G N l ,l ,M  k ,k  f 1 , f 2 
l 1 k 1  N  l ! l !  M  k ! k !

Three Tone Vm (t )  m1 cos1t  m2 cos2t  m3 cos3t

s t   exp i N1  M 2  L3  t  .
2l  N 2k M 2 pM
 m1   m2   m3 
        
 2   2   2 
    N  l ! l!  M  k ! k!  L  p ! p! G N l ,l ,M k ,k ,L p , p  f 1 , f 2 , f 3 
l 1 k 1 p 1 9
Outline

• Introduction
• Motivation
• Modulation Techniques
• Linearity of photonic links
• Optical transceiver front end
• Clock and data Recovery
• Conclusion
• Future Work
10
Transceiver Front End:
Digital Front En d Analog Front End
M od . Dri ver

MU X
F lip Flo p
R e tim e r Mo d ula to r TX S MF/MMF

P ower
Cont rol
ClockDivider P LL

 Transmitter

DEMUX

Li m it in g a m p. RX SMF
Clock Recovery NRZ TIA P hot odio de

AG C

 Receiver

• The transmitter includes PLL, DAC, CW laser with external modulator

• Receiver includes PIN photodiode, TIA, ADC and CDR 11
 Optical Receiver (45 nm)
Low Power Push Pull TIA

• 2V supply voltage  High power consumption

• Sensitivity 1mA input PD current
J. Kim and J. F. Buckwalter, "A 40-Gb/s optical transceiver front-end in 45nm SOI CMOS technology," Custom
Integrated Circuits Conference (CICC), 2010 IEEE, San Jose, CA, 2010, pp. 1-4.
8/9/21 12
 Matching Network

2
D   1  G1  G out  1  G1    1 
 sL1  sL1   sL1 

Y11 Y12
G in  sC1 0 0 G in 
 I in     Vin 
I   0 Gout  1  G1  1 0  Vout 
sL1 sL1
 1   
 I2   0  1 2  2G1  1   V2 
sL1 sL1 sL1
Node Admittance Matrix   
 I out   G in 0  1 G in  1  V 
 G1   1 
(4.7)  sL1 sL1 
Y21 Y22
 I in   1  1 
2
  Vin 
   G in  sC1  Gin    
Eliminate voltages V1 and V2   2
D  sL1 
 
   1  2  2G1   1  1   G out  1  G1    Gout  1  G1   
 I out   D  sL1  D  sL1   sL1   sL1  Vout 

Iin=-Iout Max Flat transfer Condition 1  2  2G1  G in  sC1 L1

8/9/21
D  sL1  13
Benchmark

Ref Tech. Bitrate BW ZT Gain Input Output Swing DC Power VDD Area (um2) AGC
[Gb/s] GHz [dB-] sensitivity [mVpp] [mW] [V]
(uA)
[1] 65nm 40 35 84 120 800 168 1.2 750 x 1100 No
[2] 65nm 52 50 50 1200 300 49.2 1.2 1200 x 800 No
[3] DHBT 40 49 49 1000 700 200 5.2 780 x 1180 No
[4] 45 nm 40 30 55 1000 300 9 1.2 520 x 540 No
[5] 65 nm 50 40 55 35 ? 107 1.6 ? No
This 65 nm 64 50 70 200 500 80 1 1000 x 2000 yes
work

14
Outline

• Introduction
• Motivation
• Modulation Techniques
• Linearity of photonic links
• Optical transceiver front end
• Clock and data Recovery
• Conclusion
• Future Work
15
CDR in the Rx Chain

• Need to extract clock from NRZ data at the receiver end

• CDR circuits track long sequences without transitions
• Stability for 3rd order CDR
• Jitter generation closed analytical solution 16
3rd Order CDR (Cp)
i n out

1
s

TF: G (s)  2 OD .
 sCR  1
 OD 1  sCR
s (C  C p ) 1  s CC p R s 2C 1  sC p R
C  Cp

JT ( s ) 
G (s)
 OD .
 sCR  1
1  G ( s ) CC p R 2 C  Cp 
3
s s  s OD  OD
CC p R Cp RCC p
o
Where D  /( 2 ) ;O=VCO gain Kvco; n  OD/ C   R / 2 ODC 17
Loop Stability: Bode and Evans
C p2  C p1
C p 3  C p2
C p 0
j
1
r  RC
OD  0

 1 RC2 ,0  1 
RC || Cp RC

 40 d B/de c
OD ( SC R  1)
G 3 ( ) G(s )  ( SC R  1)
p

 20dB/dec

0dB
c  m
Sz  1 
RC
1
1 R C || C p
 m
G3 (  ) RC.
RCC p
C  Cp

-
2 

m
- 3 
4

-
Sz  1 
RC

Phase Margin: m  arctan  cCR   arctan  cC p R  ;

 CR  cC p R
m  arctan c
1  cCRcC p R 18
 Jitter Generation: No input Signal


S out ( )  1  
R ( ) e  j
d
2


R ( )  E  out (t   ) out (t )   
 2 T  12   S out ( )1  cos   d 
0    
 2 T  22  R out (0)  R out ( )   
0  22 2   
  S out ( ) sin  2 d 
0      
 2   

 42   S out ( ) sin  2 d 
0   0    19
Original Contributions of this Thesis

• Nonlinearity analysis in photonic links (Volterra Series with Bell Polynomials)

• CMOS TIA with AGC and offset control
• Frequency domain loop characteristics for both 2nd and 3rd order CDR
• Presented a solution for long term jitter in time domain using the Cauchy
Integral theorem

8/9/21 20
Publications and Patents

• Linearized optical discriminator (IEEE JLT, 2015)

• RAMZI optical discriminator (FTAPS conference, 2017)
• RAMZI optical discriminator (Journal publication underway)
• Low-jitter, Plain Vanilla CMOS CDR with Half-Rate Linear PD and Half Rate
Frequency Detector (submission underway)
• Linearity analysis of photonic links using Volterra series (to be submitted)
• Transceiver Front End (Patent underway).
.

• Broadband design techniques for optical transceivers (to be submitted)

8/9/21 21
Future Work

• Use nonlinear analysis for link budget

• Extend Design circuitry for Duobinary and PAM-4
• Design burst mode CDR
• Integrate the designed Transceiver Architecture operating at
64Gb/s with photonic integrated circuits i.e. PDs, Modulators,
Filters etc.
• Build up measurement capability
• Measure the designed chips .

8/9/21 22
Acknowledgements

Many thanks to
• God Almighty for making all things possible
• Masdar Institute for the scholarship extended to me
• Dr. xx for his mentorship and guidance throughout my PhD and
especially Photonics
• Mrs. xx for his mentorship and guidance throughout my PhD and
especially Photonics
• Mr. yy for his high level support
.

8/9/21 23
 THANK YOU
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