VHDL Lecture 1 Intro To Code Parts

VHDL “Very High Speed Integrated Circuit Hardware Description Language”.
VHDL IS ONE OF TWO MAIN HARDWARE DESCRIPTION

LANGUAGES; THE OTHER IS VERILOG.
WHEN DESIGNING A VHDL MODEL YOU NEED TO INCORPORATE
TWO PARTS (ALONG WITH OTHERS DISCUSSED LATER):
• An Entity
• An Architecture
THESE ARE THE TWO DESIGN UNITS THAT YOU HAVE TO HAVE IN
YOUR VHDL DESIGN DESCRIPTION.
THAT SAID THERE ARE ANOTHER THREE POSSIBLE DESIGN UNITS
THAT COULD BE INCLUDED. (THAT SAID THEY ARE NOT REQUIRED
RIGHT NOW)
PACKAGES, PACKAGE BODIES AND CONFIGURATIONS.
Entity
The entity basically describes the ‘black box’ without describing the function (or process) – ie: it
defines the inputs and outputs.
This is a statement (indicated by the entity key-word) that defines the external circuit (or sub-
circuit).
When writing an entity you need to provide a name (unique to your design) as well as a port list
which defines all the input and output ports of your circuit.
Each Port has to have a name, direction and type.
Entity
Example:
X
Entity fulladder is
port (X: in bit; Y
Y: in bit;
Cin: in bit;
Cout: out bit;
Sum: out bit);
end fulladder;
Architecture:
The architecture describes the function (or process) and/or structure of the ‘black box’.
This is a statement (indicated by the architecture key-word) that describes the function and/or
structure of the circuit.
Each architecture must be coupled (by name) with one entity in your design.
VHDL allows one to have more than one architecture for each entity which is useful for
simulation and for projects team when wanting to experiment with different description
methods.
Architecture:
All architectures consist of zero or more declarations. Declarations define what the circuit actually does.
This declaration is followed by a begin statement, a series of concurrent statements, and an end
statement.
X
Example:
Y
architecture concurrent of fulladder is
begin
Sum <= X xor Y xor Cin;
Cout <= (X and Y) or (X and Cin) or (Y and Cin);
end concurrent;
Other parts that are to be included in your
code.
Apart from the entity and the architecture you will also require the sections mentioned below
to be included in your code:
◦ A Header
◦ A Library Declaration
◦ Comments
◦ Plus more that we may look into at a later date.
For this Module:
For the purpose of this course and module you will need the following sections to appear in you design
code:
1. Header
2. Library declaration
3. Entity declaration
4. Architecture body
Let’s look at a full example and then break it

down into smaller parts for clarity.
Example:
-- VHDL implementation of a
-- 3 input AND gate and a
-- 3 input OR gate

-- Title: Assignment1.vhd Header
-- Designer:Chris Knight
-- Date:29 September 2013
-- Version No: 1
-- Target DE0 board - EP4CE22F17C6

library ieee;
use ieee.std_logic_1164.all;
Library

entity Assignment1 is port (
a,b,c : in std_logic; Entity
x,y : out std_logic);
end Assignment1;

architecture gates of Assignment1 is
begin
x<= a and b and c; Architecture
y<= a or b or c;
end gates;
We will now consider each part in turn.
The Header - Note that all comments are preceded by two hyphens (--).
-- VHDL implementation of a
-- 3 input AND gate and a
-- 3 input OR gate

-- Title: Assignment1.vhd
-- Designer: Chris Knight
-- Date: 29 September 2013
-- Version No: 1
-- Target DE0 board - EP4CE22F17C6
The header is simply a series of comments that gives important information to the user. Note the
elements of the header given in the example – they are; brief description, filename, author/designer,
date, revision number.
Other information can be included such as the name of design units, the limitations of the design,
known errors and the VHDL system that the file was written for.
Library Declaration:
The library declaration is a way of specifying predefined standard design units. The example
below is the one that we will be using as part of this course.
library ieee;
use ieee.std_logic_1164.all;
Note that “library”, “use” and “all” are reserved words, hence why they are in bold type.
The Entity:
The entity defines the inputs to and outputs from the circuit.
entity Assignment1 is port (

a,b,c : in std_logic;
x,y : out std_logic);
end Assignment1;
“entity”, “is port”, “in”, “out” and “end” are all reserved words.
“Assignment1” is the name that has been chosen for this design.
“a”,“b” and “c” are chosen as the labels for inputs – these are defined as inputs and of the type “std_logic”
as defined in the library declaration.
“x” and “y” have been chosen as the labels for two outputs and are also of the type “std_logic”.
Note that semicolons are used to mark the end of statements.
The Port Declaration:
An entity may define ports in various modes (directions):
An entity may define ports in various modes (directions):

in simple dedicated input pin
out simple dedicated output pin
inout bi-directional pin
buffer output that allows for internal feedback

In addition to the port modes the port types must also be specified. In the example above the type is
“std_logic” – this is used to specify individual bits.
A vector may be specified by using “std_logic_vector”.

For example a microprocessor address bus could be specified as:

a: out std_logic_vector(15 downto 0);

In this case “a” is the port name and it has 16 pins - a15 to a0 or a(15) to a(0).

Other port types are “boolean” and “integer”.
The Architecture:
The architecture describes the function and/or the structure of the
system. A particular entity may have more than one architecture.
Architectures in VHDL may be described a wide variety of ways.

The architecture of our example is shown below.

architecture gates of Assignment1 is
begin
x<= a and b and c;
y<= a or b or c;
end gates;

“architecture”, “of”, “is”, “begin”, “and”, “or” and “end” are all reserved words.
“Assignment1” is the name that has been chosen for this design and must be the same as in the entity.
This part of the architecture has been given the name “gates”.
Note that the relationship between inputs and outputs is specified in this case as a Boolean equation where “<=” means ‘is assigned to’.

Generally, architectures are classified in one (or a combination) of three styles or levels. These are:

1. Dataflow (Datapath)
2. Sequential (Behavioural)
3. Structural
Dataflow:
Dataflow descriptions use CONCURRENT statements where no order
of execution is implied. Boolean equations as used in the above
example are dataflow descriptions.
Given below are two alternative dataflow descriptions of an AND gate.

architecture module1_dataflow1 of two_ip_and is
begin
x<= '1' when a ='1' and b='1'
else '0' when a ='1' and b='0'
else '0';
end module1_dataflow1;

architecture module1_dataflow2 of two_ip_and is

begin
x <= ‘1’ when a =’1’ and b=’1’ else ‘0’;
end module1_dataflow2;
Sequential:
Sequential statements resemble a conventional programming language. They can
only be used in processes or in subprograms (procedures and functions).
The examples on this slide and the next are sequential descriptions of the two input AND gate and each use a process.
Each process has a sensitivity list that contains the inputs ‘a’ and ‘b’ in brackets.

Note that sequential statements imply an order but in these examples there is no order applied to the circuit because it
represents only a piece of combinational hardware.

architecture module1_sequential1 of two_ip_and is
begin
process (a, b)
begin
if a='1' and b='1' then x <= '1';
elsif a='1' and b='0' then x <= '0';
else x<='0';
end if;
end process;
end module1_sequential1;
Sequential cont. and Structural
architecture module1_sequential2 of two_ip_and is
begin
process (a, b)
begin
if a='1' and b='1' then x <= '1';
else x<='0';
end if;
end process;
end module1_sequential2;
Structural
Structural descriptions involve describing a set of interconnected components. This type of modelling is dealt
with later on in the course.
Reserved Words:
abs downto library postponed srl
access else linkage procedure subtype
after elsif literal process then
Operators:
alias end loop pure to
all entity map range transport Logical Operators and, or, nand, nor, xor, xnor, not
and exit mod record type Adding Operators +, -, &
architecture file nand register unaffected Multiplying Operators *, /, mod, rem
Miscellaneous Operators abs, **
array for new reject units Assignment Operators <=, :=
assert function next rem until Association Operator =>
attribute generate nor report use Shift Operators sll, srl, sla, sra, rol, ror
begin generic not return variable
block group null rol wait
body guarded of ror when Data Types:
Quartus II supports (along with others) the following pre-
buffer if on select while defined VHDL types:
bus impure open severity with
case in or signal xnor integer character std_logic
component inertial others shared xor boolean string std_logic_vector
bit bit_vector
configuration inout out sla
constant is package sll
disconnect label port sra

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VHDL “Very High Speed Integrated Circuit Hardware Description Language”.

VHDL IS ONE OF TWO MAIN HARDWARE DESCRIPTION

Let’s look at a full example and then break it

entity Assignment1 is port (

A vector may be specified by using “std_logic_vector”.

architecture module1_dataflow2 of two_ip_and is

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