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    CSE 205 Digital Logic Design: MD Hasan Al Kayem

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    Asif Hossain
    This document discusses decoders, encoders, multiplexers and how they are used to implement combinational logic. It explains that decoders convert binary inputs to outputs, encoders perform the inverse, and multiplexers select one input among many. Circuits are presented to realize 3-to-8 decoders using AND gates and 2-to-4 decoders using NAND gates. Truth tables are shown for decoders and encoders. Applications to priority encoders and implementing Boolean functions with multiplexers are also covered.

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    CSE 205 Digital Logic Design: MD Hasan Al Kayem

    Uploaded by

    Asif Hossain
    59 views19 pages
    This document discusses decoders, encoders, multiplexers and how they are used to implement combinational logic. It explains that decoders convert binary inputs to outputs, encoders perform the inverse, and multiplexers select one input among many. Circuits are presented to realize 3-to-8 decoders using AND gates and 2-to-4 decoders using NAND gates. Truth tables are shown for decoders and encoders. Applications to priority encoders and implementing Boolean functions with multiplexers are also covered.

    Original Title

    06 Decoder Encoder

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    This document discusses decoders, encoders, multiplexers and how they are used to implement combinational logic. It explains that decoders convert binary inputs to outputs, encoders perform the inverse, and multiplexers select one input among many. Circuits are presented to realize 3-to-8 decoders using AND gates and 2-to-4 decoders using NAND gates. Truth tables are shown for decoders and encoders. Applications to priority encoders and implementing Boolean functions with multiplexers are also covered.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    59 views19 pages

    CSE 205 Digital Logic Design: MD Hasan Al Kayem

    Uploaded by

    Asif Hossain
    This document discusses decoders, encoders, multiplexers and how they are used to implement combinational logic. It explains that decoders convert binary inputs to outputs, encoders perform the inverse, and multiplexers select one input among many. Circuits are presented to realize 3-to-8 decoders using AND gates and 2-to-4 decoders using NAND gates. Truth tables are shown for decoders and encoders. Applications to priority encoders and implementing Boolean functions with multiplexers are also covered.

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    CSE 205

    Digital Logic Design

    Md Hasan Al Kayem
    Decoders
    • A decoder converts binary information from n
    input lines to a maximum of 2n output lines

    • Also known as n-to-m line decoders where m<


    2n

    • Example 3-to-8 decoders.

    5
    Decoders: Truth Table
    X Y Z D0 D1 D2 D3 D4 D5 D6 D7
    0 0 0 1 0 0 0 0 0 0 0
    0 0 1 0 1 0 0 0 0 0 0
    0 1 0 0 0 1 0 0 0 0 0
    0 1 1 0 0 0 1 0 0 0 0
    1 0 0 0 0 0 0 1 0 0 0
    1 0 1 0 0 0 0 0 1 0 0
    1 1 0 0 0 0 0 0 0 1 0
    1 1 1 0 0 0 0 0 0 0 1

    6
    Decoders: AND implementation

    7
    2-to-4 Decoder: NAND implementation

    Decoder is enabled when E=0

    8
    How to build bigger decoders?

    We can combine two 3-to-8 decoders to build a 4-to-16 decoder.

    Generates from
    0000 to 0111

    Generates from
    1000 to 1111

    9
    Combinational Logic Implementation
    • A decoder provides the 2n minterms of n input variables.

    • Any function is can be expressed in sum of minterms.

    • Use a decoder to make the minterms and an external OR


    gate to make the sum.

    • Example: consider a full adder.


    S(x,y,z) = Σ(1,2,4,7)
    C(x,y,z) = Σ (3,5,6,7)
    10
    Combinational Logic Implementation

    11
    Encoders
    • Encoders perform the inverse operation of a
    decoder:

    • Encoders have 2n input lines and n output line.

    • Output lines generate the binary code


    corresponding to the input value.

    12
    Encoders: Truth Table
    Outputs Inputs

    X Y Z D0 D1 D2 D3 D4 D5 D6 D7
    0 0 0 1 0 0 0 0 0 0 0
    0 0 1 0 1 0 0 0 0 0 0
    0 1 0 0 0 1 0 0 0 0 0
    0 1 1 0 0 0 1 0 0 0 0
    1 0 0 0 0 0 0 1 0 0 0
    1 0 1 0 0 0 0 0 1 0 0
    1 1 0 0 0 0 0 0 0 1 0
    1 1 1 0 0 0 0 0 0 0 1

    • z=D1+D3+D5+D7 y=D2+D3+D6+D7 x=D4+D5+D6+D7

    13
    Priority Encoders
    Encoder limitations:
    • If two inputs are active, the output is undefined.
    Solution: we need to take into account priority.
    • What if all inputs are 0?
    Solution: we need a valid bit

    Input Output
    D0 D1 D2 D3 x y v
    0 0 0 0 X X 0
    1 0 0 0 0 0 1
    X 1 0 0 0 1 1
    X X 1 0 1 0 1
    X X X 1 1 1 1

    14
    Priority Encoders: Map

    15
    Priority Encoders: Circuit

    16
    Multiplexers
    • Multiplexer: selects one binary input from
    many selections
    • example: 2-to-1 MUX

    17
    4-to-1 MUX
    Directs 1 of the 4 inputs to the output

    18
    Multi-bit selection logic
    • Multiplexers can be combined with common
    selection inputs to support multi-bit selection
    logic

    19
    Implementing Boolean functions w/ MUX
    • General rules for implementing any Boolean function with n
    variables:

    • Use a multiplexer with n-1 selection inputs and 2 n-1 data inputs
    • List the truth tabel
    • Apply the first n-1 variables to the selection inputs of
    multiplexer
    • For each combination evaluate the output as a function of the
    last variable.
    • The function can be 0, 1 the variable or the complement of the
    variable.

    20
    Implementing Boolean functions w/ MUX

    21
    Implementing Boolean functions w/ MUX

    22

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