Verilog HDL 18EC56

Module 4(a)
Behavioral Modeling
Dinesh M.A.
dineshma_ece@mitmysore.in
•
/dinesh.ajay
/prof.dineshma
 VISION OF THE DEPARTMENT

• To be recognized by the society at large as

offering Value based Quality Education to
groom the next generation entrepreneurs,
leaders and researchers in the field of
Electronics and Communication to meet the
challenges at global level.

Verilog HDL 03/06/2023 2

 MISSION OF THE DEPARTMENT

• To groom the students with strong foundations of Electronics and

Communication Engineering and to facilitate them to pursue higher
education and research.
• To educate and prepare the students to be competent to face the challenges of
the industry/society and /or to become successful entrepreneurs.
• To provide ethical and value-based education by promoting activities
addressing the societal needs.
• Enable students to develop skills to solve complex technological problems of
current times and also provide a framework for promoting collaborative and
multidisciplinary activities.

Verilog HDL 03/06/2023 3

 Program Educational Objectives (PEOs)

• Be able to have a successful career in dynamic industry

that is global, multidisciplinary, and evolving.
• Solve problems, design and innovate while they work
individually or in teams with sense of  professional ethics
and social responsibility.
• Communicate effectively and manage resources skillfully
as members and leaders of the profession

Verilog HDL 03/06/2023 4

 Program Specific Outcomes (PSOs)

• An ability to apply the basic concepts of engineering

science into various areas of Electronics Communication
Engineering.
• An ability to solve complex Electronics and
Communication Engineering problems, using state of the
art hardware and software tools, along with analytical
skills to arrive at cost effective and efficient solutions.

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 Course Outcomes
CO’s DESCRIPTION OF THE OUTCOMES

Present the comprehension of the IC Design flow, syntax, lexical

18EC56.1 conventions, data types, system tasks compiler directives and logic
synthesis in Verilog HDL.
Develop Verilog modules for digital circuits using gate level and
18EC56.2 data flow modeling, behavioral modeling using different control
structures and related statements and for system tasks as well.
Analyze the behavior of structural, dataflow and behavior modeling
18EC56.3
procedures written in Verilog.
Design digital functional blocks for a given set of specifications
18EC56.4
using hierarchical modeling concepts in Verilog.

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 RBT
Module – 4 Level
Behavioral Modeling: Structured procedures,
initial and always, blocking and non-blocking
statements, delay control, generate statement,
event control, conditional statements, Multiway L1, L2,
branching, loops, sequential and parallel blocks. L3

Tasks and Functions: Differences between tasks

and functions, declaration, invocation, automatic
tasks and functions.

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 Chapter 7
Behavioral Modeling

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 Objectives of this Topic
• Explain the significance of structured procedures always and initial in behavioral modeling.
• Define blocking and nonblocking procedural assignments.
• Understand delay-based timing control mechanism in behavioral modeling.
• Use regular delays, intra-assignment delays, and zero delays.
• Describe event-based timing control mechanism in behavioral modeling.
• Use regular event control, named event control, and event OR control
• Use level-sensitive timing control mechanism in behavioral modeling.
• Explain conditional statements using if and else.
• Describe multiway branching, using case, casex, and casez statements.
• Understand looping statements such as while, for, repeat, and forever.
• Define sequential and parallel blocks.
• Understand naming of blocks and disabling of named blocks.
• Use behavioral modeling statements in practical examples.

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 Introduction

• The move toward higher abstractions

• Gate-level modeling
• Netlist of gates

• Dataflow modeling
• Boolean function assigned to a net

• Now, behavioral modeling

• A sequential algorithm (quite similar to software) that determines the value(s) of signal(s)

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 Structured Procedures

• Two basic structured procedure statements

always
initial
• All behavioral statements can appear only inside these blocks
• Each always or initial block has a separate activity flow (concurrency)
• Start from simulation time 0
• Cannot be nested

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 Structured Procedures:
initial statement

• Starts at time 0
• Executes only once during a simulation
• Multiple initial blocks, execute in parallel
• All start at time 0
• Each finishes independently
• Syntax:
initial
begin
// behavioral statements
end
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 Structured Procedures:
initial statement (cont’d)
• Example:
module stimulus; initial
reg x, y, a, b, m; #50 $finish;
endmodule
initial
m= 1’b0;

initial
begin
#5 a=1’b1;
#25 b=1’b0;
end

initial
begin
#10 x=1’b0;
#25 y=1’b1;
end

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 Structured Procedures:
always statement
• Start at time 0
• Execute the statements in a looping fashion
• Example
module clock_gen;
reg clock;

// Initialize clock at time zero

initial
Can we move this to the
clock = 1’b0;
always block?
// Toggle clock every half-cycle (time period =20)
always
#10 clock = ~clock;

initial
What happens if such a
#1000 $finish;
$finish is not included?
endmodule
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 Procedural Assignments

• Assignments inside initial and always

• Are used to update values of reg, integer, real, or time variables
• The value remains unchanged until another procedural assignment updates it
• In contrast to continuous assignment (Dataflow Modeling, previous chapter)

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 Procedural Assignments (cont’d)

• Syntax
• <lvalue> = <expression>

• <lvalue> can be
• reg, integer, real, time
• A bit-select of the above (e.g., addr[0])
• A part-select of the above (e.g., addr[31:16])
• A concatenation of any of the above
• <expression> is the same as introduced in dataflow modeling
• What happens if the widths do not match?
• LHS wider than RHS => RHS is zero-extended
• RHS wider than LHS => RHS is truncated (Least significant part is kept)

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 Procedural Assignments (cont’d)
• The two types of procedural assignments
• Blocking assignments
• Non-blocking assignments
• Blocking assignments
• are executed in order (sequentially)
• Example:
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count; All executed at time 0
initial begin
x=0; y=1; z=1;
count=0;
reg_a= 16’b0; reg_b = reg_a; executed at time 15
#15 reg_a[2] = 1’b1;
#10 reg_b[15:13] = {x, y, z}; All executed at time 25
count = count + 1;
end
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 Procedural Assignments (cont’d)
• Non-blocking assignments
• The next statements are not blocked for this one
• Syntax:
• <lvalue> <= <expression>
• Example:
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;
initial begin All executed at time 0
x=0; y=1; z=1;
count=0;
reg_a= 16’b0; reg_b = reg_a;
reg_a[2] <= #15 1’b1; Scheduled to run at time 15
reg_b[15:13] <= #10 {x, y, z};
Scheduled to run at time 10
count <= count + 1;
end
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 Procedural Assignments (cont’d)

• Application of non-blocking assignments

• Used to model concurrent data transfers
• Example: Write behavioral statements to swap values of two variables
• Another example
always @(posedge clock)
begin
reg1 <= #1 in1;
reg2 <= @(negedge clock) in2 ^ in3;
reg3 <= #1 reg1; The old value of reg1 is used
end
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 Procedural Assignments (cont’d)

• Race condition
• When the final result of simulating two (or more) concurrent processes depends on their order of execution
• Example:
always @(posedge clock)
b = a;
always @(posedge clock)
a = b;
• Solution: always @(posedge clock)
always @(posedge clock) begin
b <= a; temp_b = b;
always @(posedge clock) temp_a = a;
a <= b; b = temp_a;
a = temp_b;
end

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 Procedural Assignments (cont’d)

• Recommendation
• Concurrent data transfers => race condition
• Use non-blocking assignments wherever concurrent data transfers
• Example: pipeline modeling
• Disadvantage:
• Lower simulation performance
• Higher memory usage in the simulator

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 Timing Controls (Delay-based)

• Delay  Duration between encountering and executing a statement

• Delay symbol: #
• Delay specification syntax:
<delay>
::= #<NUMBER>
||= #<identifier>
||= #<mintypmax_exp> <,<mintypmax_exp>>*)

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 Delay-based
Timing Controls (cont’d)

• Types of delay-based timing controls

1. Regular delay control
2. Intra-assignment delay control
3. Zero-delay control

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 Delay-based
Timing Controls (cont’d)
• Regular Delay Control
• Symbol: non-zero delay before a procedural assignment
• Used in most of our previous examples

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 Delay-based
Timing Controls (cont’d)

• Intra-assignment Delay Control

• Symbol: non-zero delay to the right of the assignment operator
• Operation sequence:
1. Compute the right-hand-side expression at the current time.
2. Defer the assignment of the above computed value to the LHS by the specified
delay.

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 Delay-based
Timing Controls (cont’d)

• Intra-
assignment
delay
examples

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 Delay-based
Timing Controls (cont’d)

• Zero-Delay Control
• Symbol: #0
• Different initial/always blocks in the same simulation time
• Execution order non-deterministic
• Zero-delay ensures execution after all other statements
• Eliminates race conditions
• Multiple zero-delay statements
• Non-deterministic execution order

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 Delay-based
Timing Controls (cont’d)

• Zero-delay control
examples

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 Timing Control (Event-based)

• Event
• Change in the value of a register or net
• Used to trigger execution of a statement or block (reactive behavior/reactivity)
• Types of Event-based timing control
1. Regular event control
2. Named event control
3. Event OR control
4. Level-sensitive timing control (next section)

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 Event-based
Timing Control (cont’d)

• Regular event control

• Symbol: @(<event>)
• Events to specify:
• posedge sig
• Change of sig from any value to 1
• negedge sig
• Change of sig from any value to 0
• sig
• Any change in sig value

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 Event-based
Timing Control (cont’d)
• Regular event control examples

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 Event-based
Timing Control (cont’d)

• Named event control

• You can declare (name) an event, and then trigger and recognize
it.
• Verilog keyword for declaration: event
event calc_finished;
• Verilog symbol for triggering: ->
->calc_finished
• Verilog symbol for recognizing: @()
@(calc_finished)
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 Event-based
Timing Control (cont’d)

• Named
event
control
examples

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 Event-based
Timing Control (cont’d)
• Event OR control
• Used when need to trigger a block upon occurrence of any of a set of events.
• The list of the events: sensitivity list
• Verilog keyword: or

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 Level-sensitive
Timing Control

• Level-sensitive vs. event-based

• event-based: wait for triggering of an event (change in signal value)
• level-sensitive: wait for a certain condition (on values/levels of signals)

• Verilog keyword: wait()

always
wait(count_enable) #20 count=count+1;

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 Behavioral Modeling Statements:
Conditional Statements

• Just the same as if-else in C

• Syntax:
if (<expression>) true_statement;

if (<expression>) true_statement;
else false_statement;

if (<expression>) true_statement1;
else if (<expression>) true_statement2;
else if (<expression>) true_statement3;
else default_statement;

• True is 1 or non-zero
• False is 0 or ambiguous (x or z)
• More than one statement: begin end
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 Conditional Statements (cont’d)

• Examples: • Examples:
if (!lock) buffer = data;
if (alu_control==0)
if (enable) out = in; y = x+z;
else if (alu_control==1)
if (number_queued < MAX_Q_DEPTH) y = x-z;
begin else if (alu_control==2)
data_queue = data; y = x*z;
number_queued = number_queued +1; else
end $display(“Invalid ALU control
signal.”);
else $display(“Queue full! Try
again.”);

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 Behavioral Modeling Statements:
Multiway Branching

• Similar to switch-case statement in C

• Syntax:
case (<expression>)
alternative1: statement1;
alternative2: statement2;
...
default: default_statement; // optional
endcase
• Notes:
• <expression> is compared to the alternatives in the order specified.
• Default statement is optional
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 Multiway Branching (cont’d)

• Examples:
reg [1:0] alu_control;
...
case (alu_control)
2’d0: y = x + z;
2’d1: y = x – z;
2’d2: y = x * z;
default: $display(“Invalid ALU control signal.”);

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 Multiway Branching (cont’d)

• Example 2:
module mux4_to_1(out, i0, i1, i2, i3, s1, s0);
output out;
input i0, i1, i2, i3, s1, s0;
reg out;

always @(s1 or s0 or i0 or i1 or i2 or i3)

case ({s1,s0})
2’d0: out = i0;
2’d1: out = i1;
2’d2: out = i2;
2’d3: out = i3;
endcase
endmodule

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 Multiway Branching (cont’d)
• The case statements compares <expression> and alternatives bit-for-bit
• x and z values should match
module demultiplexer1_to_4(out0, out1, out2, out3, in, s1, s0);
output out0, out1, out2, out3;
input in, s1, s0;
always @(s1 or s0 or in)
case( {s1, s0} )
2’b00: begin ... end
2’b01: begin ... end
2’b10: begin ... end
2’b11: begin ... end
2’bx0, 2’bx1, 2’bxz, 2’bxx, 2’b0x, 2’b1x, 2’bzx:
begin ... end
2’bz0, 2’bz1, 2’bzz, 2’b0z, 2’b1z:
begin ... end
default: $display(“Unspecified control signals”);
endcase
endmodule
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 Multiway Branching (cont’d)

• casex and casez keywords

• casez treats all z values as “don’t care”
• casex treats all x and z values as “don’t care”
• Example:
reg [3:0]
integer state;
casex(encoding)
4’b1xxx: next_state=3;
4’bx1xx: next_state=2;
4’bxx1x: next_state=1;
4’bxxx1: next_state=0;
default: next_state=0;
endcase

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 Behavioral Modeling Statements:
Loops

• Loops in Verilog
• while, for, repeat, forever

• The while loop syntax:

while (<expression>)
statement;

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 Loops (cont’d)

• The for loop

• Similar to C
• Syntax:
for( init_expr; cond_expr; change_expr)
statement;

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 Loops (cont’d)

• The repeat loop

• Syntax:
repeat( number_of_iterations )
statement;

• The number is evaluated only when the loop is first encoutered

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 Loops (cont’d)

• The forever loop

• Syntax:
forever
statement;

• Equivalent to while(1)

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 Sequential and Parallel Blocks

• Blocks: used to group multiple statements

• Sequential blocks
• Keywords: begin end
• Statements are processed in order.
• A statement is executed only after its preceding one completes.
• Exception: non-blocking assignments with intra-assignment delays
• A delay or event is relative to the simulation time when the previous statement
completed execution

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 Sequential and Parallel Blocks (cont’d)

• Parallel Blocks
• Keywords: fork, join
• Statements in the blocks are executed concurrently
• Timing controls specify the order of execution of the statements
• All delays are relative to the time the block was entered
• The written order of statements is not important

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 Sequential and Parallel Blocks (cont’d)

initial
begin
x=1’b0;
#5 y=1’b1;
#10 z={x,y};
#20 w={y,x};
end

initial
fork
x=1’b0;
#5 y=1’b1;
#10 z={x,y};
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#20 w={y,x};
join
 Sequential and Parallel Blocks (cont’d)

• Parallel execution  Race conditions may arise

initial
begin
x=1’b0;
y=1’b1;
z={x,y};
w={y,x};
end

• z, w can take either 2’b01, 2’b10

or 2’bxx, 2’bxx depending on simulator
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 Special Features of Blocks

• Contents
• Nested blocks
• Named blocks
• Disabling named blocks

Verilog HDL 03/06/2023 51

 Special Features of Blocks (cont’d)

• Nested blocks
• Sequential and parallel blocks can be mixed
initial
begin
x=1’b0;
fork
#5 y=1’b1;
#10 z={x,y};
join
#20 w={y,x};
end

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 Special Features of Blocks (cont’d)

• Named blocks
• Syntax:
begin: <the_name> fork: <the_name>
… …
end join
• Advantages:
• Can have local variables
• Are part of the design hierarchy.
• Their local variables can be accessed using hierarchical names
• Can be disabled

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 Special Features of Blocks (cont’d)

module top;
initial
begin : block1
integer i; //hiera. name: top.block1.i
…
end

initial
fork : block2
reg i; //hierarchical name: top.block2.i
…
join
endmodule

Verilog HDL 03/06/2023 54

 Special Features of Blocks (cont’d)

• Disabling named blocks

• Keyword: disable
• Action:
• Similar to break in C/C++, but can disable any named block not just the inner-
most block.

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 Special Features of Blocks (cont’d)
begin: block1
module find_true_bit; while(i < 16)
begin
if (flag[i])
reg [15:0] flag;
begin
integer i;
$display("Encountered a TRUE bit at
element number %d", i);
initial
disable block1;
begin
end
flag =
i = i + 1;
16'b0010_0000_0000_0000;
end
i = 0;
end // block1
end //initial
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endmodule
 Generate Block
• Dynamically generate Verilog code at elaboration time
• Usage:
• Parameterized modules when the parameter value determines the module contents

• Can generate
• Modules
• User defined primitives
• Verilog gate primitives
• Continuous assignments
• initial and always blocks
 Generate Loop
module bitwise_xor (output [N-1:0] out, input [N-1:0] i0, i1);
parameter N = 32; // 32-bit bus by default
genvar j; // This variable does not exist during simulation

generate for (j=0; j<N; j=j+1) begin: xor_loop

//Generate the bit-wise Xor with a single loop
xor g1 (out[j], i0[j], i1[j]);
end
endgenerate //end of the generate block

/* An alternate style using always blocks:

reg [N-1:0] out;
generate for (j=0; j<N; j=j+1) begin: bit
always @(i0[j] or i1[j]) out[j] = i0[j] ^ i1[j];
end
endgenerate
endmodule */
 Example 2: Ripple Carry Adder
module ripple_adder(output co, output [N-1:0] sum, input [N-1:0] a0, a1, input ci);
parameter N = 4; // 4-bit bus by default
wire [N-1:0] carry;
assign carry[0] = ci;

genvar i;
generate for (i=0; i<N; i=i+1) begin: r_loop
wire t1, t2, t3;
xor g1 (t1, a0[i], a1[i]);
xor g2 (sum[i], t1, carry[i]);
and g3 (t2, a0[i], a1[i]);
and g4 (t3, t1, carry[i]);
or g5 (carry[i+1], t2, t3);
end
endgenerate //end of the generate block
assign co = carry[N];
endmodule
 Generate Conditional

module multiplier (output [product_width -1:0] product, input [a0_width-1:0] a0,

input [a1_width-1:0] a1);
parameter a0_width = 8;
parameter a1_width = 8;

localparamproduct_width = a0_width + a1_width;

generate
if (a0_width <8) || (a1_width < 8)
cla_multiplier #(a0_width, a1_width) m0 (product, a0, a1);
else
tree_multiplier #(a0_width, a1_width) m0 (product, a0, a1);
endgenerate

endmodule
 Generate Case
module adder(output co, output [N-1:0] sum,
input [N-1:0] a0, a1, input ci);

parameter N = 4;

// Parameter N that can be redefined at instantiation time.

generate
case (N)
1: adder_1bit adder1(c0, sum, a0, a1, ci);
2: adder_2bit adder2(c0, sum, a0, a1, ci);
default: adder_cla #(N) adder3(c0, sum, a0, a1, ci);
endcase
endgenerate

endmodule
Behavioral Modeling
Examples
 4-to-1 Multiplexer
// 4-to-1 multiplexer. Port list is taken exactly from
// the I/O diagram.
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);

// Port declarations from the I/O diagram

output out;
input i0, i1, i2, i3;
input s1, s0;
reg out; //output declared as register

//recompute the signal out if any input signal changes.

//All input signals that cause a recomputation of out to
//occur must go into the always @(...)
always @(s1 or s0 or i0 or i1 or i2 or i3)
begin
case ({s1, s0})
2'b00: out = i0;
2'b01: out = i1;
2'b10: out = i2;
2'b11: out = i3;
default: out = 1'bx;
endcase
end Verilog HDL 03/06/2023 63
endmodule
 4-bit Up Counter
//Binary counter
module counter(Q , clock, clear);

// I/O ports
output [3:0] Q;
input clock, clear;
//output defined as register
reg [3:0] Q;

always @( posedge clear or negedge clock)

begin
if (clear)
Q = 4'd0;
else
//Q = (Q + 1) % 16;
Q = (Q + 1) ;
end

endmodule
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 4-bit Down Counter
//Binary counter
module counter(Q , clock, clear);

// I/O ports
output [3:0] Q;
input clock, clear;
//output defined as register
reg [3:0] Q;

always @( posedge clear or negedge clock)

begin
if (clear)
Q = 4’d15;
else

Q = (Q - 1) ;
end

endmodule
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 Traffic Signal Controller

Verilog HDL 03/06/2023 66

`define TRUE 1'b1
`define FALSE1'b0
`define RED 2'd0
`define YELLOW 2'd1
`define GREEN2'd2

//State definition HWY CNTRY

`define S0 3'd0 //GREEN RED
`define S1 3'd1 //YELLOW RED
`define S2 3'd2 //RED RED
`define S3 3'd3 //RED GREEN
`define S4 3'd4 //RED YELLOW

//Delays
`define Y2RDELAY 3 //Yellow to red delay
`define R2GDELAY 2 //Red to Green Delay

module sig_control (hwy, cntry, X, clock, clear);

//I/O ports
output [1:0] hwy, cntry; //2 bit output for 3 states of signal GREEN, YELLOW, RED;
reg [1:0] hwy, cntry; //declare output signals are registers

input X; //if TRUE, indicates that there is car on the country road, otherwise FALSE

input clock, clear;

//Internal state variables

reg [2:0] state;
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reg [2:0] next_state;
//Signal controller starts in S0 state
initial begin
state = `S0;
next_state = `S0;
hwy = `GREEN;
cntry = `RED;
end

always @(posedge clock) //state changes only at positive edge of clock

state = next_state;

always @(state) //Compute values of main signal and country signal

begin
case(state)
`S0: begin
hwy = `GREEN;
cntry = `RED;
end
`S1: begin
hwy = `YELLOW;
cntry = `RED;
end
`S2: begin
hwy = `RED;
cntry = `RED;
end
`S3: begin
hwy = `RED;
cntry = `GREEN;
end
`S4: begin
hwy = `RED;
cntry = `YELLOW;
end
endcase
Verilog HDL 03/06/2023 68
end
//State machine using case statements
always @(state or clear or X)
begin
if(clear)
next_state = `S0;
else
case (state)
`S0: if( X)
next_state = `S1;
else
next_state = `S0;
`S1: begin //delay some positive edges of clock
repeat(`Y2RDELAY) @(posedge clock) ;
next_state = `S2;
end
`S2: begin //delay some positive edges of clock
repeat(`R2GDELAY) @(posedge clock)
next_state = `S3;
end
`S3: if( X)
next_state = `S3;
else
next_state = `S4;
`S4: begin //delay some positive edges of clock
repeat(`Y2RDELAY) @(posedge clock) ;
next_state = `S0;
end
default: next_state = `S0;
endcase
end

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endmodule
 Text

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