Verilog HDL 18EC56

Module 3(b)
Dataflow Modeling
Dinesh M.A.
dineshma_ece@mitmysore.in
•
/dinesh.ajay
/prof.dineshma
 VISION OF THE DEPARTMENT

• To be recognized by the society at large as

offering Value based Quality Education to
groom the next generation entrepreneurs,
leaders and researchers in the field of
Electronics and Communication to meet the
challenges at global level.

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 MISSION OF THE DEPARTMENT

• To groom the students with strong foundations of Electronics and

Communication Engineering and to facilitate them to pursue higher
education and research.
• To educate and prepare the students to be competent to face the challenges of
the industry/society and /or to become successful entrepreneurs.
• To provide ethical and value-based education by promoting activities
addressing the societal needs.
• Enable students to develop skills to solve complex technological problems of
current times and also provide a framework for promoting collaborative and
multidisciplinary activities.

Verilog HDL 03/06/2023 3

 Program Educational Objectives (PEOs)

• Be able to have a successful career in dynamic industry

that is global, multidisciplinary, and evolving.
• Solve problems, design and innovate while they work
individually or in teams with sense of  professional ethics
and social responsibility.
• Communicate effectively and manage resources skillfully
as members and leaders of the profession

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 Program Specific Outcomes (PSOs)

• An ability to apply the basic concepts of engineering

science into various areas of Electronics Communication
Engineering.
• An ability to solve complex Electronics and
Communication Engineering problems, using state of the
art hardware and software tools, along with analytical
skills to arrive at cost effective and efficient solutions.

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 Course Outcomes
CO’s DESCRIPTION OF THE OUTCOMES

Present the comprehension of the IC Design flow, syntax, lexical

18EC56.1 conventions, data types, system tasks compiler directives and logic
synthesis in Verilog HDL.
Develop Verilog modules for digital circuits using gate level and
18EC56.2 data flow modeling, behavioral modeling using different control
structures and related statements and for system tasks as well.
Analyze the behavior of structural, dataflow and behavior modeling
18EC56.3
procedures written in Verilog.
Design digital functional blocks for a given set of specifications
18EC56.4
using hierarchical modeling concepts in Verilog.

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 RBT
Module – 3 Level
Gate-Level Modeling: Modeling using basic
Verilog gate primitives, description of and/or
and buf/not type gates, rise, fall and turn-off
delays, min, max, and typical delays. L1, L2,
L3
Dataflow Modeling: Continuous assignments,
delay specification, expressions, operators,
operands,operator types.

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 Chapter 6
Dataflow Modeling

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 Objectives of this Topic

• The assign statement

• Expressions, operators, and operands
• Specifying delays in Dataflow modeling
 Introduction

• Usages of gate-level modeling

• Small designs
• Netlist of gates, Logic Synthesis

• Next level up: Dataflow modeling

• Continuous assignment
• The assign keyword

module my_and(output out, input in1, in2);

assign out = in1 & in2;
endmodule
 Rules for assign statement

• LHS data type: only net (wire)

• RHS data type: any type (register, net) or function
 Implicit continuous assignment

Implicit net declaration

 Gate Level vs. Dataflow Modeling

Gate Level Model

module mux4_to_1 (output out,
input i0, i1, i2, i3, s1, s0);

wire s1n, s0n, y0, y1, y2, y3;

not (s1n, s1);

not (s0n, s0);

and (y0, i0, s1n, s0n);

Dataflow Model
and (y1, i1, s1n, s0); module mux4_to_1 (output out,
input i0, i1, i2, i3, s1, s0);
and (y2, i2, s1, s0n);
and (y3, i3, s1, s0);
assign out = (~s1 & ~s0 & i0)|
(~s1 & s0 & i1)|
or (out, y0, y1, y2, y3); ( s1 & ~s0 & i2)|
( s1 & s0 & i3);
endmodule endmodule
 Another alternative for Mux 4-to-1
• Use conditional operator
4-bit Full-adder Example
 Expression, Operand, Operator
• Dataflow modeling describes the design in terms of expressions instead of
primitive gates.
• Expressions, operators, and operands form the basis of dataflow modeling.
• Expressions are constructs that combine operators and operands to produce a
result.
• Operands can be anyone of the data types.
• Operands can be constants, integers, real numbers, nets, registers, times,
bit-select (one bit of vector net or a vector register), part-select (selected
bits of the vector net or register vector), memories or function calls
(functions are discussed later).
• Operators act on the operands to produce desired results.
 Expression, Operand, Operator

integer count, final_count;

final_count = count + 1; // integer operand

real a, b, c;
c = a - b; // real operands

reg [15:0] reg1, reg2;

reg [3:0] reg_out;
reg_out = reg1[3:0] ^ reg2[3:0]; // part-select operands

reg ret_value;
ret_value = calculate_parity(A, B); // function type oprnd
 Operators
Operator category Operators symbol
Arithmetic * / + - % **
Logical ! && ||
Relational > < <= >=
Equality == != === !===
Bitwise ~ & | ^ ^~ ~^
Reduction & ~& | ~| ^ ~^ ^~
Shift >> << >>> <<<
Concatenation { }
Replication { { } }
Conditional ? :
 Arithmetic Operators
• There are two types of arithmetic operators: binary and unary.
• Binary operators
• Binary arithmetic operators are multiply (*), divide (/), add (+), subtract (-) and
modulus (%).

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 Arithmetic Operators

• Modulus operators produce the remainder from the division of two numbers.

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 Arithmetic Operators
• Unary operators
• The operators + and - can also work as unary operators.
• They are used to specify the positive or negative sign of the operand.
• Unary + or - operators have higher precedence than the binary + or - operators.
• -4 // Negative 4
• +5 //Positive 5
• Negative numbers are represented as 2's complement internally in Verilog.

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 Logical Operators
• Logical operators
are logical-and
(&&), logical-or
(||) and logical-not
(!).
• Operators && and
||are binary
operators.
Operator ! is a
unary operator.
• Outcome: 0,1,x
• ‘x’ value usually
treated as false
 Relational Operators
• Relational operators are greater-than (>) less-than (<), greater-than-or-
equal-to (>=), and less-than-or-equal-to <=).
• If relational operators are used in an expression, the expression returns a
logical value of 1 if the expression is true and 0 if the expression is false.
• If there are any unknown or z bits in the operands, the expression takes a
value x.
 Equality Operators
• Equality operators are logical equality (==), logical inequality (!=), case
equality (===), and case inequality (! ==).
• When used in an expression, equality operators return logical value 1 if
true, 0 if false.
• These operators compare the two operands bit by bit, with zero filling if the
operands are of unequal length.
Equality Operators
 Bitwise Operators
• Bitwise operators are
negation (~), and(&), or
(|), xor (^), xnor (^~, ~^).
• Bitwise operators perform
a bit-by-bit operation on
two operands.
• If one operand is shorter
than the other, it will be bit
extended with zeros to
match the length of the
longer operand.
Bitwise Operators
 Reduction Operators
• Reduction operators are and (&), nand (-&), or (|), nor (~|), xor (^), and
xnor(~^, ^~).
• Reduction operators take only one operand.
• Reduction operators perform a bitwise operation on a single vector operand
and yield a 1-bit result.
• The difference is that bitwise operations are on bits from two different
operands, whereas reduction operations are on the bits of the same operand.
• Reduction operators work bit by bit from right to left.
 Shift Operators
• Shiftoperators are right shift ( >>), left shift (<<), arithmetic right shift
( >>>) and arithmetic left shift (<<<).
• These operators shift a vector operand to the right or the left by a specified
number of bits.
• The operands are the vector and the number of bits to shift.
• When the bits are shifted, the vacant bit positions are filled with zeros.
 Concatenation Operator
• The concatenation operator ( {, } ) provides a mechanism to append multiple
operands.
• Operands can be scalar nets or registers, vector nets or registers, bit-select,
part-select, or sized constants.
 Replication Operator
• Repetitive concatenation of the same number can be expressed by using a
replication constant.
• A replication constant specifies how many times to replicate the number
inside the brackets ( { } ).
 Conditional Operator
• The conditional operator(? :) takes three operands.
• Usage: condition_expr ? true_expr : false_expr ;
• The action is similar to a multiplexer. Alternately, it can be compared to the
if-else expression.
Operators Precedence
 Example: Carry Look ahead Adder
module fulladd4(sum, c_out, assign c1 = g0 | (p0 & c_in),
a, b, c_in); c2 = g1 | (p1 & g0) |
output [3:0] sum; (p1 & p0 & c_in),
output c_out; c3 = g2 | (p2 & g1) |
input [3:0] a,b; (p2 & p1 & g0)
input c_in; |
(p2 & p1 & p0 & c_in),
wire p0,g0, p1,g1, p2,g2, c4 = g3 | (p3 & g2) |
p3,g3, c4, c3, c2, c1; (p3 & p2 & g1) |
assign p0 = a[0] ^ b[0], (p3 & p2 & p1 & g0) |
p1 = a[1] ^ b[1],
p2 = a[2] ^ b[2], (p3 & p2 & p1 & p0 & c_in);
p3 = a[3] ^ b[3]; assign sum[0] = p0 ^ c_in,
assign g0 = a[0] & b[0], sum[1] = p1 ^ c1,
g1 = a[1] & b[1], sum[2] = p2 ^ c2,
g2 = a[2] & b[2], sum[3] = p3 ^ c3;
g3 = a[3] & b[3]; assign c_out = c4;
endmodule
Example: 4-bit Ripple Carry Counter
 Sequential Logic at Dataflow Level

module edge_dff(q, qbar, d, clk,

clear);
output q,qbar;
input d, clk, clear;

•wire s, sbar, r, rbar,cbar;

Negative Edge Triggered D-FF
assign cbar = ~clear;
assign sbar = ~(rbar & s),
s = ~(sbar & cbar & ~clk),
r = ~(rbar & ~clk & s),
rbar = ~(r & cbar & d);
assign q = ~(s & qbar),
qbar = ~(q & r & cbar);
endmodule
 Edge-Triggered T-FF
module edge_dff(q, qbar, d, clk,
clear);
. . .
endmodule

module T_FF(q, clk, clear);

output q;
input clk, clear;
edge_dff ff1(q, ,~q, clk, clear);
endmodule
 Text

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