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    Boundary Scan

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    karthikp207
    The document discusses the IEEE 1149.1 JTAG boundary scan standard. It describes how boundary scan allows testing of ASICs and PCBs by implementing a test access port and scan chains. Key components include a tap controller, instruction register, and boundary scan cells at input and output pins. Standard instructions like EXTEST, INTEST, and IDCODE are used to test off-chip connections, shift test patterns on/off chip, and read device IDs.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd

    Boundary Scan

    Uploaded by

    karthikp207
    33 views31 pages
    The document discusses the IEEE 1149.1 JTAG boundary scan standard. It describes how boundary scan allows testing of ASICs and PCBs by implementing a test access port and scan chains. Key components include a tap controller, instruction register, and boundary scan cells at input and output pins. Standard instructions like EXTEST, INTEST, and IDCODE are used to test off-chip connections, shift test patterns on/off chip, and read device IDs.

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    bscan

    Original Title

    BOUNDARY SCAN

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    The document discusses the IEEE 1149.1 JTAG boundary scan standard. It describes how boundary scan allows testing of ASICs and PCBs by implementing a test access port and scan chains. Key components include a tap controller, instruction register, and boundary scan cells at input and output pins. Standard instructions like EXTEST, INTEST, and IDCODE are used to test off-chip connections, shift test patterns on/off chip, and read device IDs.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    33 views31 pages

    Boundary Scan

    Uploaded by

    karthikp207
    The document discusses the IEEE 1149.1 JTAG boundary scan standard. It describes how boundary scan allows testing of ASICs and PCBs by implementing a test access port and scan chains. Key components include a tap controller, instruction register, and boundary scan cells at input and output pins. Standard instructions like EXTEST, INTEST, and IDCODE are used to test off-chip connections, shift test patterns on/off chip, and read device IDs.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    of 31

    BOUNDARY SCAN

    Diseño ASIC BOUNDARY SCAN


    IEEE 1149.1 JTAG
    Boundary Scan Standard
     Motivation
     Bed-of-nails tester
     System view of boundary scan
    hardware
     Elementary scan cell
     Test Access Port (TAP) controller
     Boundary scan instructions

    Diseño ASIC BOUNDARY SCAN


    Motivation for Standard
     Bed-of-nails printed circuit board tester gone
     We put components on both sides of PCB & replaced
    DIPs with flat packs to reduce inductance
     Nails would hit components

     Reduced spacing between PCB wires


     Nails would short the wires

     PCB Tester must be replaced with built-in test


    delivery system -- JTAG does that
     Need standard System Test Port and Bus
     Integrate components from different vendors
     Test bus identical for various components
     One chip has test hardware for other chips

    Diseño ASIC BOUNDARY SCAN


    Bed-of-Nails Tester Concept

    Diseño ASIC BOUNDARY SCAN


    Purpose of Standard
     Lets test instructions and test data be serially fed into a
    component-under-test (CUT)
     Allows reading out of test results
     Allows RUNBIST command as an instruction
     Too many shifts to shift in external tests
     JTAG can operate at chip, PCB, & system levels
     Allows control of tri-state signals during testing
     Lets other chips collect responses from CUT
     Lets system interconnect be tested separately from
    components
     Lets components be tested separately from wires

    Diseño ASIC BOUNDARY SCAN


    System Test Logic

    Diseño ASIC BOUNDARY SCAN


    Instruction Register Loading with
    JTAG

    Diseño ASIC BOUNDARY SCAN


    System View of Interconnect

    Diseño ASIC BOUNDARY SCAN


    Boundary Scan Chain View

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    Elementary Boundary Scan Cell

    Diseño ASIC BOUNDARY SCAN


    Serial Board / MCM Scan

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    Parallel Board / MCM Scan

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    Independent Path Board / MCM Scan

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    Tap Controller Signals
     Test Access Port (TAP) includes these signals:
     Test Clock Input (TCK) -- Clock for test logic
     Can run at different rate from system clock

     Test Mode Select (TMS) -- Switches system from


    functional to test mode
     Test Data Input (TDI) -- Accepts serial test data and
    instructions -- used to shift in vectors or one of many
    test instructions
     Test Data Output (TDO) -- Serially shifts out test
    results captured in boundary scan chain (or device
    ID or other internal registers)
     Test Reset (TRST) -- Optional asynchronous TAP
    controller reset
    Diseño ASIC BOUNDARY SCAN
    Tap Controller State Diagram

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    Tap Controller Timing

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    TAP Controller Power-Up Reset
    Logic

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    Boundary
    Boundary Scan
    Scan Instructions
    Instructions

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    SAMPLE / PRELOAD Instruction --
    SAMPLE
    Purpose:
    1. Get snapshot of normal chip output signals
    2. Put data on bound. scan chain before next instr.

    Diseño ASIC BOUNDARY SCAN


    SAMPLE / PRELOAD Instruction --
    PRELOAD

    Diseño ASIC BOUNDARY SCAN


    EXTEST Instruction
     Purpose: Test off-chip circuits and board-
    level interconnections

    Diseño ASIC BOUNDARY SCAN


    INTEST Instruction
     Purpose:
    1. Shifts external test patterns onto component
    2. External tester shifts component responses out

    Diseño ASIC BOUNDARY SCAN


    INTEST Instruction Clocks
     Control of applied system clock during INTEST

     Use of TCK for on-chip system logic clock

    Diseño ASIC BOUNDARY SCAN


    RUNBIST Instruction
     Purpose: Allows you to issue BIST command to
    component through JTAG hardware
     Optional instruction
     Lets test logic control state of output pins
    1. Can be determined by pin boundary scan cell
    2. Can be forced into high impedance state
     BIST result (success or failure) can be left in
    boundary scan cell or internal cell
     Shift out through boundary scan chain
     May leave chip pins in an indeterminate state
    (reset required before normal operation
    resumes)
    Diseño ASIC BOUNDARY SCAN
    CLAMP Instruction
     Purpose: Forces component output signals
    to be driven by boundary-scan register
     Bypasses the boundary scan chain by
    using the one-bit Bypass Register
     Optional instruction
     May have to add RESET hardware to
    control on-chip logic so that it does not
    get damaged (by shorting 0’s and 1’s onto
    an internal bus, etc.)

    Diseño ASIC BOUNDARY SCAN


    IDCODE Instruction

     Purpose: Connects the component device


    identification register serially between TDI
    and TDO
     In the Shift-DR TAP controller state
     Allows board-level test controller or
    external tester to read out component ID
     Required whenever a JEDEC identification
    register is included in the design

    Diseño ASIC BOUNDARY SCAN


    Device ID Register --JEDEC Code

    MSB LSB
    31 28 27 12 11 1 0

    Version Part Manufacturer ‘1’


    Number Identity
    (4 bits) (16 bits) (11 bits) (1 bit)

    Diseño ASIC BOUNDARY SCAN


    USERCODE Instruction
     Purpose: Intended for user-programmable components
    (FPGA’s, EEPROMs, etc.)
     Allows external tester to determine user programming of
    component
     Selects the device identification register as serially
    connected between TDI and TDO
     User-programmable ID code loaded into device
    identification register
     On rising TCK edge
     Switches component test hardware to its system function
     Required when Device ID register included on user-
    programmable component

    Diseño ASIC BOUNDARY SCAN


    HIGHZ Instruction
     Purpose: Puts all component output pin signals
    into high-impedance state
     Control chip logic to avoid damage in this mode
     May have to reset component after HIGHZ runs
     Optional instruction

    Diseño ASIC BOUNDARY SCAN


    BYPASS Instruction
     Purpose: Bypasses scan chain with 1-bit register

    Diseño ASIC BOUNDARY SCAN


    Optional / Required Instructions

    Instruction Status
    BYPASS Mandatory
    CLAMP Optional
    EXTEST Mandatory
    HIGHZ Optional
    IDCODE Optional
    INTEST Optional
    RUNBIST Optional
    SAMPLE / PRELOAD Mandatory
    USERCODE Optional

    Diseño ASIC BOUNDARY SCAN

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