Unit-1 / Part-1

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 MOS & Related VLSI Technology
Although CMOS is the dominant technology, some of the examples used to illustrate the design
process will be presented in NMOS form. The reasons for this are as follows:

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Baisc MOS Transistors:

NMOS Enhancement and Depletion mode transistors:

For Enhancement MOSFET,
• NMOS devices are formed in a p-type substrate of moderate doping level.
• Through suitable masks ,the source and drain regions are formed by two n+ type diffusion.
• For connections, metal is deposited on source and drain
• An oxide layer is formed in between source and drain
• Polysilicon is deposited on top of this insulation layer. Later, metal contact is made for the
gate.
• When Vd=Vs=Vgs=0 channel is not conducting.
• When gate is connected to positive voltage w.r.to source, then the electric field established
between the gate and the substrate gives rise to a charge inversion region in the substrate
under the gate insulation and a conducting path or channel is formed between source and
drain.
For Depletion MOSFET, channel will be present by the implant. It can be removed by giving a
proper negative gate voltage. a channel is established during the manufacturing process itself, by
implanting suitable impurities in between source and drain.This transistor is normally ON, even
with Vgs=0.
In both cases, variations of the gate voltage allow control of any current flow between source and
drain.

Fig:MOS transistors (V 0 = 0 V. Source gate and substrate to 0 V) .

Smartworld.asia 11

Sub: Fundamentals of CMOS VLSI Sub code: 10EC56

1.2.4 Enhancement mode Transistor action:-

Figure7. (a)(b)(c) Enhancement mode transistor with different Vds values

To establish the channel between the source and the drain a minimum voltage (Vt) must
be applied between gate and source. This minimum voltage is called as ―Threshold Voltage‖.
The complete working of enhancement mode transistor can be explained with the help of
diagram a, b and c.

Dept of ECE,SJBIT Page 5

a) Vgs > Vt
Vds = 0
Since Vgs > Vt and Vds = 0
the channel is formed but no current flows between drain and source.
b) Vgs > Vt
Vds < Vgs – Vt
This region is called the non-saturation Region or linear region.
Vgs – Vt is called as the “Effective gate voltage”. where the drain current increases linearly withVds. A
corresponding IR drop = Vds along the channel. This results in the voltage between gate and channel
varying with distance along the channel with the voltage being a maximum of Vgs at the source end.
there will be voltage available to invert the channel at the drain end so long as Vgs – Vt >Vds · The
limiting condition comes when Vds =Vgs - Vt .When Vds is increased the drain sidebecomes more
reverse biased (hence more depletion region towards the drain end).
c) Vgs > Vt
Vds > Vgs - Vt
This region is called Saturation Region where the drain current remains almost constant. when Vds is
increased to a level greater than Vgs - Vt. In this case, an IR drop = Vgs - Vt takes place over less than
the whole length of the channel. so that over part of the channel, near the drain, there is insufficient
electric field available to give rise to an inversion layer to create the channel. The channel is, therefore,
“pinched off”. Even if the Vds is increased more and more, the increased voltage gets dropped in the
depletion region leading to a constant current. The typical threshold voltage for an enhancement mode
transistor is given by Vt = 0.2 * Vdd.

Depletion mode Transistor action:-

We can explain the working of depletion mode transistor in the same manner, as that of the enhancement
mode transistor only difference is, channel is established due to the implant even when Vgs = 0 and the
channel can be cut off by applying a –ve voltage between the gate and source. Threshold voltage of
depletion mode transistor is around 0.8*Vdd.
Mos Transistor
Switches:

– But degraded or weak 0

• Thus nMOS are best for pull-down network
NMOS Fabrication:

The following Processing steps are used in fabrication of NMOS.

1.Processing is carried on single crystal silicon of high purity on which required P

impurities are introduced as crystal is grown. Such wafers are about 75 to 150 mm
in diameter and 0.4 mm thick and they are doped with say boron to impurity
concentration of 1015/cm3 to 1016 /cm3.

2. An oxide layer is grown all over the surface. This is called as thick-oxide, having
about 1um thickness. This acts as a protective layer to the for the subsequent
processes.

3. The surface is now covered with the photo resist which is deposited onto the
wafer
 4. The photo resist layer is then exposed to ultraviolet light through masking which
defines those regions into which diffusion is to take place together with transistor
channels.

5.These regions are etched together so that wafer exposed in window defined by

mask.

window in oxide

6. The remaining photo resist is removed and a thin layer of SiO2 (0.1 micro m
typical) is grown over the entire chip surface and then poly silicon is deposited on
the top of this to form the gate structure. The polysilicon layer consists of heavily
doped polysilicon deposited by chemical vapour deposition (CVD).
 7.The thin oxide is removed to expose areas into which n-type impurities are to be
diffused form the source and drain. Diffusion is achieved by heating the wafer to
high temperature and passing gas containing the desired n-type impurity over the
surface.

8. Thick oxide (SiO2) is grown over all again and is then masked with photo resist
and etched to expose selected areas of the poly silicon gate and the drain and
source areas where connections are to be made. (contacts cut)

9. The whole chip then has metal (aluminium) deposited over its surface to a
thickness typically of 1 micro m.

10. This metal layer is then masked and etched to form the required
interconnection pattern.

Note: PMOS Fabrication process is same as NMOS, but instead of p-substrate replace by n-substrate,
instead of n-diffusion replace by p-diffusion.
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Step 5: These regions are etched together so that wafer exposed in window defined by mask.

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Vin

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Note: CMOS Fabrication using n-well process is same as above, but instead of p-well replace n-well,
instead of n-substrate replace p-substrate. n-well place may change.

Thermal aspects of processing:

As evident from the figure, NMOS is a lower temperature process when compared to
CMOS. Hence, NMOS has the advantage of ease of fabrication. Additionally, it has
higher density per unit area. In contrast, CMOS has the advantages of lower power
consumption and ease of circuit design.

Twin tub-CMOS Fabrication Process:

In this process, separate optimization of the n-type and p-type transistors will be provided.
The independent optimization of Vt, body effect and gain of the P-devices, N-devices can
be made possible with this process.The epitaxy layer is utilized here to prevent the short
circuit of the device. The epitaxial layer is lightly doped & hence, it has higher resitivity.
This is used for the prevention of Latch-up.The electrical properties for this layer are
determined by the dopant and its concentration in the silicon.

Different steps of the fabrication of the CMOS using the twintub process are as follows:
Twin well Process Steps

Step1:
N or p type substrate is taken Initially
Step2:
Epitaxial Layer Deposition, Lightly Doped Epitaxial Layer is Deposited
above n+ or p+ Substrate.
Electrical Properties of Layer is Fixed by Dopant and its Concentration.
The Aim of This Step is to Deposite High-Purity Silicon Layer.
Concentration of Dopant Distributed Throught the Layer
Step3:
Tub Formation
n -well-Formation
• Protect certain region in this by using an oxide nitride mask
• Phosphorus implantation
• Form n-well
• Entire substrate to an oxidation process
• The oxide is going to be formed only over the n-well
• The rest of the portions are protected by the oxide nitride mask
• This n-well will also be driven deeper
Step4:
p -well-Formation
• Protect certain region in this by using an oxide nitride mask
• Boron implantation
• Form p-well
• Entire substrate to an oxidation process
• Implant The p-well
Step 5:
Polysilicon Layer is Formed The Overall Surface
Step 6:
Polysilicon gates Are Formed for n-well and p-well by Using Photo-Etching
Process
Step 7:
Using Blanket Implantation(Auto Aligning The Wells)
Step 8:
n+ Diffusion is Formed in n-well
p+ Diffusion is Formed in p-well
These Are Used For VDD and VSS Contacts(Substrate Formation)

Step9:
Contact Cuts Are Defined In Both The Wells
Step10:
Metalization Process (Metal Contacts Are Created)
 After masking and etching process,
formation of the tubs for p-well and n-well

n-well p-well

Apply the CVD Process to form the gate

n-well p-well
After masking and etching, form the gates of pmos and nmos.

n-well p-well

n-well p-well
CMOS TWIN TUB PROCESS,YOU CAN WRITE IN FLOW CHART FORM LIKE FOLLOWING FIG..
collector Emitter Base

p+
p+ n+ p+
n+
n+ n+

fig(a): Arrangement of BICMOS fig(b):BICMOS Technology

fig(b): BICMOS Fabrication
npn Transistor
BICMOS Fabrication In an n-well Process:
The BICMOS fabrication combines the process of fabrication of BJT and CMOS.But merely
variation of the base.The following steps show the BiCMOS fabrication process.

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n+ n+

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 Metal layer

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Silicon On Insulator (SOI):
Rather than using silicon as the substrate, technologies such as SOI have been developed that
use an insulating substrate to improve process characteristics such as latch-up and speed.
Need for SOI Technology:
 Allow continuous miniaturization of MOSFET device.
 Improves bulk technology by Low parasitic capacitance and Resistance to Latch-up.
 Compatible with existing fabrication process without any special equipment or retooling
of an existing factory.
 Capable of higher current densities than obtained in equivalent bulk devices.
Figure shows a CMOS inverter fabricated using the SOI approach.

The steps used in a typical SOI CMOS process are as follows:

• A thin film (7–8 μm) of very lightly doped n-type Si is epitaxially grown over an
insulator. Sapphire or SiO 2 is a commonly used insulator. This process is showed
in Fig a.
• An anisotropic etch is used to etch away the Si except where a diffusion area will be
needed. This process is showed in fig b,c
• Implantation of the p-island where an n-transistor is formed. This process is showed
in Fig d.
• Implantation of the n-island where a p-transistor is formed. This process is showed
in Fig e.
• Growing of a thin gate oxide (500–600 Å) and depositing of phosphorus-doped
poly-silicon film over the oxide. This process is showed in Fig f.
• Patterning of the poly-silicon gate by photo masking and etched. This process is
showed in Fig g.
• Forming of the n-doped source and drain of the n-channel devices in the p-islands.
This process is showed in Fig h.
• Forming of the p-doped source and drain of the p-channel devices in the n-islands.
This process is showed in Fig i
• Depositing of a layer of insulator material such as phosphorus glass or SiO2 over the
entire structure. Etching of the insulator at contact cut locations. The metallization
layer is formed next.Depositing of the passivation layer and etching of the bonding
pad location. As shown in This process is showed in fig j.
Types of SOI Devices:
1. Partially Depleted SOI
2. Fully Depleted SOI

Partially Depleted SOI:

 On the other hand, if the insulated layer of silicon is made thicker, the inversion
region does not extend the full depth of the body.
 A technology designed to operate this way is called a “partially depleted” SOI
technology.
 The undepleted portion of the body is not connected to anything. => Floating
Body.

Fully Depleted SOI:

 In an NMOS transistor, applying a positive voltage to the gate depletes the body
of P-type carriers and induces an N-type inversion channel on the surface of the
body.
 If the insulated layer of silicon is made very thin, the depletion layer fills the full
depth of the body. A technology designed to operate this way is called a “fully
depleted” SOI technology.
 The thin body avoids a floating voltage.

Advantages of SOI
 Due to the absence of wells, transistor structures denser than bulk silicon are
feasible.
 Lower substrate capacitance.
 No field-inversion problems (the existence of a parasitic transistor between two
normal transistors).
 No latch-up is possible because of the isolation of transistors by insulating
substrate.
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IC Fabrication

The following processing steps are used in IC Fabrication

• Wafer Preparation
• Oxidation
• Photolithography
• Etching
• Diffusion
• Ion Implantation
• CVD (Chemical Vapor Deposition)
• Metallization
• Packaging

Wafer Preparation:

The first step is wafer production.

 A wafer is a thin slice of semiconducting material, such as a silicon crystal, upon which
microcircuits are constructed by doping.
 It is the base or substrate for entire chip. Wafers are cut out of silicon boules.
 If large no of impurity atoms are added, then silicon is said to be heavily doped referred
as n+ or p+ material, while a lightly doped referred as n- or p- material.

Oxidation:

 In the oxidation process oxygen (dry oxidation) or H 2O (wet oxidation) molecules

convert silicon layers on top of the wafer to silicon dioxide.

 we use high temperature ultra clean furnace. Silicon dioxide layers are used as high-
quality insulators or masks for ion implantation.

Photolithography:

 Lithography is used to transfer a pattern from a photomask to the surface of the

wafer.
  The photo-resist is hardened by baking and then selectively removed by projection of
light through a reticle containing mask information.he exposed sections are susceptible
to doping, removal, or metallization.

 Specific patterns can be created to form regions of conductors, insulators, or doping.

Putting these patterns onto a wafer is called photolithography.

 The pattern defined by the mask is either removed or remained after development.

Etching:

 Selectively removing unwanted material from the surface of the wafer. The pattern of the
photo-resist is transferred to the wafer by means of etching agents.

 The pattern is defined by the etching mask, because the parts of the material, which
should remain, are protected by the mask.

 The unmasked material can be removed either by wet (chemical) or dry (physical)
etching.

Diffusion:

 The process of junction formation, that is transition from p to n type or vice versa, is
typically accomplished by the process of diffusing the appropriate dopant impurities in a
high temperature furnace.

 Diffusion is the process by which atoms move from high concentration to low
concentration region through the semiconductor crystal.

 Diffusion is used to form the source, drain, and channel regions in a MOS
transistor.

Ion Implantation:

 Ion Implantation is an alternative to a deposition diffusion. In this process the ionized

particles are accelerated through an electrical field and targeted at the semiconductor
wafer.
  The ion become embedded in the crystal lattice.it can be performed at room
temperature.

Chemical Vapour Deposition:

 CVD (Chemical Vapour Deposition) is the deposition of a solid material onto a

heated substrate through decomposition or chemical reaction of compounds contained m
the gas passing over the substrate.

 which causes chemical reactions in gases or vapors, leading to the formation of

solids on a substrate CVD can be used to deposit various materials on silicon
substrate including SiO2,Polysilicon and Si3N4.

 Advantage of CVD layer is that the oxide deposits at a fast rate.

Metallization:

 The purpose of this process is to produce a thin metal film layer that will serve to make
interconnections of the various components on the chip.

 Alluminium is usually used for the metallization of most ICS.

 Metallization involves the initial deposition of a metal over the entire surface of the
silicon.

 The thickness of the metal film can be controlled by the length of time for sputtering.

Packaging:

 A finished silicon wafer may contain several hundred or more finished chips.

 Fine gold wires are normally used to connect the pins of the package to the
metallization pattern on the die.

 Finally the package is selected using plastic or epoxy under vaccum.

Ist unit/2nd part Prepared byby
M.Adiseshaiah
1st unit / 2nd part prepared Adiseshaiah
AssistantProfessor,ece dept

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ASPECTS OF MOS TRANSISTOR THRESHOLD VOLTAGE Vt :

The voltage at which the surface of the semiconductor gets inverted to the opposite polarity is
known as Threshold voltage. In nMOS transistor, the surface will be inverted to n-type and for
pMOS transistor the surface will be inverted to p-type . At the threshold voltage condition, the
concentration of electrons (holes) accumulated near the surface in a nMOS (pMOS) is equal
to the doping concentration of the bulk doping concentration. Threshold voltage for nMOS is
always positive and threshold voltage for pMOS is always negative.

An nMOS (pMOS) transistor has a conducting channel when the gate-source voltage is
greater than threshold voltage, i.e., VGS > Vtn for nmos, and for pmos less than threshod voltage V GS
< Vtp.

The threshold VoltageVt expressed as

Body effects may also taken into account since the substrate may be biased with respect to the
source

fig:Body effect (nmos device)

Body effect : The change in the threshold voltage of a Mos transistor, because of the voltage
difference between body and source is called body effect.

The expression for the threshold voltage is given by the following expression.

Vt  Vt (0)   [ Vsb  2 F  2 F ]

2qN A   si
Where   Cox

Where

Vt = the threshold voltage

Vt(0) = the threshold voltage without body effect

 = the body coefficient factor

ΦF = the Fermi potential

Vsb = the potential difference between source and substrate

If Vsb is zero, then Vt = Vt(0) that means the value of the threshold voltage will not be changed.
Therefore, we short circuit the source and substrate so that, Vsb will be zero.
 Basic Electrical Properties of MOS, BiCMOS Devices  57

 Help Desk

► What is channel length modulation?

When the drain voltage exceeds VDsat the pinch off point (also called as velocity
saturation point) moves from the drain towards the source and a depletion layer exists
between this point and the drain. This movement is referred as channel length modula-
tion. Considering channel length modulation, the drain current is given by the relation
β
ID = (VGS − Vtn )2 (1 + λVDS ) (2.21)
2
where λ is channel length modulation parameter.

► When the channel is pinched off near the drain end, there is no physical
channel between the pinch off point and drain end. But the current remains
constant. How does it happen?
Although there are no inversion charges at the drain end of the channel at the
pinch off point, the drain region is electrically active. Carriers drift from the source
and move under the effect of the horizontal electric field. Once they arrive at the
pinch off point of the channel they travel from that point to the drain driven by the
high electric field of the depletion region. This is drift current in the device which is
almost constant.

► Write down the importance of threshold voltage in a MOSFET and how is it

dependent on oxide thickness, and doping concentration of the substrate.
The threshold voltage of a MOSFET is usually defined as the gate voltage where
an inversion layer forms at the interface between the insulating layer (oxide) and the
substrate (body) of the transistor. It is given by
2qNA ∈si (2φ B + VSB )
Vth = VFB + 2φ B + (2.22)
Cox
Threshold voltage depends on the choice of oxide and on oxide thickness. Using
the formulas above, Vtn is directly proportional to γ, and tox, which is the parameter
for oxide thickness. Thus, the thinner the oxide, the lower the threshold voltage.
The threshold voltage increases with the increase in the NA since the potential
drop across oxide and surface both increase.

► What is subthreshold leakage current?

Subthreshold leakage or subthreshold conduction or subthreshold drain cur-
rent is the current that flows between the source and drain of a MOSFET when the
transistor is in the subthreshold region, i.e., for gate-to-source voltages below the
threshold voltage.
(5)

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NMOS Inverter
The basic inverter circuit has a depletion mode MOSFET (coupled in series with the enhancement mode
MOSFET). The depletion mode MOSFET acts as a pull up transistor as it pulls the output logic from 0
to 1 and enhancement MOSFET acts like a pull down transistor as it pulls the output voltage from logic
1 to logic 0. The gate of the depletion mode MOSFET is shorted to its source, i.e., VGS = 0 to make it
a continuous ON device. The depletion mode MOSFET acts like a resistive load. The output is taken
from the drain and the input applied between the gate and the ground. Figure gives the circuit for nMOS
inverter.

Fig(a): NMOS Inverter

Operation of nMOS Inverter:
 Vin = logic 0, the pull down transistor (enhancement mode) is off and VDD appears near the Vout.
 When Vin = logic 1 and voltage is more than the threshold voltage of the enhancement
mode MOSFET current begins to flow and Vout decreases and output is logic 0.
 To obtain the transfer characteristics of the inverter, we superimpose the Vgs = 0 depletion
mode characteristics curve on the family of curves for enhancement mode device.

Fig(b): Superimposed Characteristic curves of Depletion and enhancement mode transistor

At point A: Vin=0V Pull-down device is OFF
Pull-up device is in linear region
At point B: Vin>Vtn Pull-down device is in Saturation region
Pull-up device is in linear region
At point C: Vin=Vout=0.5VDD Pull-down device is in Saturation region
Pull-up device is in Saturation region
At point D: Vin=VDD Pull-down device is Linear region
Pull-up device is in Saturation region

The points of intersection of the curves gives points on the transfer characteristics and is shown in the
Fig (c).

Fig(c): NMOS Inverter transfer characteristics

 The point at which Vin = Vout is denoted by Vinv or switching threshold.

 The transfer characteristics and Vinv can be shifted by changing the ratio of pull up to pull
down impedances Zp.u / Zp.d. (impedance Z is denoted by ratio of length to width ratio of the
transistor).
 During transition, the slope of the transfer characteristic determines the gain:
Vout
Gain 
Vin
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CMOS INVERTER:
A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain and gate terminals, a supply
voltage VDD at the PMOS source terminal, and a ground connected at the NMOS source terminal, were V in is
connected to the gate terminals and Voutis connected to the drain terminals. As the voltage at the input of the
CMOS device varies between 0 and VDD, the state of the NMOS and PMOS varies accordingly.

Fig(a): CMOS Inverter

By superimposing both characteristics it leads to figure. the actual characteristics may be now determined by
the points of common intersection

Fig(b): Graphical derivation of dc characteristics (superimposing nmos and pmos current characteristics)

Region Condition PMOS-Device NMOS-Device

A 0  Vin  Vtn Linear Cutoff
B Vtn  Vin  0.5V DD Linear Saturation
Vin  0.5V DD
C Saturation Saturation
0.5V DD  Vin  V DD  Vtp
D Saturation Linear
V DD  Vtp  Vin  V DD
E Cutoff Linear
CMOS Inverter DC Characteristics:

The nature and the form of the voltage-transfer characteristic (VTC) can be graphically deduced by
superimposing the current characteristics of the nMOS and the pMOS devices is shown in fig(c)

Fig(c): Transfer characteristics of CMOS inverter Fig(d):CMOS inverter current vs Vin

Region A:
The output in this region is high because the Pmos device is OFF and n device is ON. In region A,NMOS is
cutoff region and PMOS is on, therefore output is logic high (VDD).

Region B:
The input voltage has increased to a level which just exceeds the threshold voltage of the nmos
transistor. In this PMOS Transistor is in linear and NMOS Transistor is in saturation. The output voltage is in
between 0.5VDD and VDD.

Region D:
It is is similar to region B but with the roles of the p- and n-transistors reversed. In this PMOS Transistor
is in saturation and NMOS Transistor is in linear. The output voltages is in between 0.5V DD and gnd.

Region E:
Vin = logic 1, the n-transistor is fully on while the p-transistor is fully off. No current flows and a good
logic ‘0’ appears at the output. In this . In this PMOS Transistor is in cut-off and NMOS Transistor is in linear.

Region C:
Both n and p transistors are in saturation region, at this region Vin=Vout=0.5VDD. and both currents are equal
 I dsn   I dsp  (1)

we can equate both the currents and we can obtain the expression for the midpoint voltage or switching
point voltage of a inverter. In saturation region the current equation is

I ds  V gs  Vt   ( 2)
2

2
PMOS NMOS

Vgs  Vin  VDD Vgs  Vin

Vt  Vtp Vt  Vt n

Substitute these values in eq(2)

I dsp 
p
2
V in 2
 VDD  Vt p  (3) I dsn 
n
2
V in  Vt n 
2
 (4)

Substituting eq(3) and (4) in Eq (1) we get

p
2
V in  VDD  Vtp 2
 
n
2
V in  Vtn 
2
 (5)

If n  p and Vtn  Vtp then substitute these in eq(5) we get

Vin  0.5VDD  (6)

Influence of βn / βp on the VTC characteristics:

Fig: Transfer characteristics with β ratio

n
 For cmos inverter  1 will only hold good around the point of symmetry when Vin=Vout=0.5VDD.
p
n
 When  1 , the transition region shifts to left. This indicates that when . the dimensions of the nmos
p
must be larger than that of pmos transistor . The inverter threshold voltage(V inv) <0.5VDD.
n
 When  1 , the transition region shifts to left. This indicates that when . the dimensions of the pmos
p
must be larger than that of nmos transistor . The inverter threshold voltage(V inv) >0.5VDD
BiCMOS Inverters:
When designing .with BiCMOS in mind, the logical approach is to use MOS switches to perform the
logic function and bipolar transistors to drive the output loads.

It consists of two bipolar transistors T1 and T2 with one nMOS transistor T3, and one pMOS
transistor T4, both being enhancement mode devices.

Fig(a): A simple BICMOS inverter

The action of the circuit is straightforward and may be described as follows:

 With Vin = 0 volts (GND) T3 is off so that T1 will be non-conducting. But T4 is on and
supplies current to the base of T2 which will conduct and act as a current source to charge the load
CL toward +5 volts(VDD). The output of the inverter will rise to +5 volts less the · base to
emitter voltage VBE of T2. i.e VDD-vBE=logic ‘1’.
 With Vin = +5 volts· CVDD) T4 is off so that T2 will be non-conducting. But T3 will now be
on and will supply current to the base of T1 which will conduct and act as a current sink to the'
load CL discharging it toward 0 volts (GND). The output of the inverter will fall to 0 volts plus
the saturation voltage VCEsat from the collector to the emitter of T1. i.e 0V+VCE sat= logic ‘0’.
 T1and T2 will present low impedances when turned on into saturation and the load C L will be
charged or discharged rapidly.
 The output logic levels will be good and will be close to the rail voltages since V CEsat quite small
and VBE is approximately + 0.7 volts.
 Due to presence of DC path from VDD to gnd through T3 & T1, this is not a good arrangement to
implement since there will be significant static current flow whenever V in=logic ‘1’.

Drawback: There is no discharge path for current from the base of either bipolar transistor when it is
being turned off. This will slow down the action of this circuit.
To avoid this improved version of the circuit is used.

Fig(b): An alternative BICMOS Inverter with no static current flow.

 In which the DC path through T3 and T1 is eliminated.

 But the output voltage swing is now reduced, since the output cannot fall below the base to
emitter voltage VBE of T1 .

An improved inverter arrangement is shown in fig(c).Two additional enhancement-type nMOS devices have
been added (T5 and T6) to the existing design. These transistors provide discharge paths for transistor base
currents during turn-off. Without T5, the output low voltage cannot fall below the base to emitter voltage V BE
of T3.

Fig(c): An Improved BICMOS Inverter using MOS transistors for base current dlschange.

1. When Vin = 0
T3 is OFF, therefore T1 is non-conducting. T4 is ON and supplies current to base of T2. T2 base
voltage is set to VDD. T6 is turned ON and clamps base of T1 to GND. T1 is turned OFF. T2
conducts and acts as current source to charge load CL towards VDD. Vout rises to VDD – VBE (of T2).
2. Vin = VDD
T4 is OFF. T3 is ON and supplies current to the base of T1. T5 is turned ON and clamps the base of
T2 to GND. T2 is turned off. T1 conducts acts as a current sink to discharge load C L towards 0V.
Vout falls to 0 V + VCEsat (of T1)
Latch-up in CMOS Circuits:
The basic limitation with CMOS process is that, during the fabrication of n-well & p-well,
there is a formation of parasitic bipolar transistors. These transistors give rise to a condition
called “Latch-up”, A by-product of the Bulk CMOS structure is a pair of parasitic bipolar
transistors. The collector of each BJT is connected to the base of the other transistor in a
positive feedback structure . A phenomenon called latch-up can occur when

a) Both BJT’s conduct, in which VDD & VSS get shorted (i.e creating a low resistance
path between VDD and GND) and
b) The product of the gains of the two transistors in the feedback loop
β1 × β2, is >1.

The result of latch-up is at the minimum a circuit malfunction, and in the worst case,
the destruction of the device.

Fig(a): Latch-up effect in CMOS-n-well process.

If sufficient substrate current flows to generate enough voltage across R-sub to turn on
transistor Q2(voltage drop across R-sub >0.7V(VBE of transistor Q2). This will then draw
current through R-well and, if the voltage drop across R-well is high enough, Q1 will also
turn on, establishing a self-sustaining low-resistance path between the supply rails. If the
current gains of the two transistors are such that β1 x β2 > 1, latch-up may occur.
Fig(b): Equivalent circuit of latch-up. Fig(c): Latch-up current vs Voltage

Once latched-up, this condition will be maintained until the latch-up current drops
below Il. Once latch-up has begun, the only way to stop it is to reduce the current below a
critical level, usually by removing power from the circuit.

Preventing latch-up Problems:

• Higher substrate doping level reduces R-sub .

• Reducing R-well by control of fabrication parameters and by ensuring a low
contact resistance to ground.
• By Placing guard rings around each transistor.
• By the proper layout techniques through for n-channel & p-channel transistors.

BICMOS LATCH-UP SUSCEPTIBILITY:

One benefit of the BiCMOS process is that it produces circuits which are less likely to
suffer from latch-up problems. This is due to several factors :
• A reduction of substrate resistance R-sub
• A reduction of n-well resistance R-well.
• A reduction of R-sub and R-well means that a larger lateral current is necessary
to invite latch-up and a higher value of holding current is also required.
• The parasitic (vertical) pnp transistor which is part of the n-well latch-up circuit
has its reduce the gain product β1 x β2 by presence of the buried n+ layer. This
has the effect of reducing carrier lifetime in the n-base region and this
contributes the reduction in beta.