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TOPIC :INSTRUCTION CYCLE

(CONTINUOUS ASSESSMENT -1)

NAME : BISWAJIT MANDI

ROLL : 11000223012
STREAM : INFORMATION TECHNOLOGY
SEMSTER : 3TH
SUBJECT: COMPUTER ORGANISATION
PAPER CODE : PCC – CS302

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# The instruction cycle is defined as the

basic cycle in which a computer system
fetches an instruction from memory,
decodes it, and then executes it. Fetch-
Execute-Cycle is another name for it. All
instructions in a computer system are
executed in the RAM of the computer
system. The CPU is in charge of carrying out
the instruction

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During this phase, the

computer system boots up
and the Operating System
loads into the central
processing unit's main
memory. It begins when the
computer system starts.

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Here ‘I’ is the instruction length. The

notations (t1, t2, t3) represents successive
time units. We assume that a clock is
• At the beginning •Step 1: The •Step 2: The address in MAR is available for timing purposes and it emits
of the fetch cycle, address in the placed on the address bus, now regularly spaced clock pulses. Each clock
the address of the program counter the control unit issues a READ pulse defines a time unit. Thus, all time
next instruction to is moved to the command on the control bus, units are of equal duration. Each micro-
be executed is in memory address and the result appears on the operation can be performed within the time
the Program register(MAR), as data bus and is then copied into of a single time unit.
Counter(PC). this is the only the memory buffer First time unit: Move the contents of the PC
register which is register(MBR). Program counter to MAR.
connected to is incremented by one, to get Second time unit: Move contents of
address lines of ready for the next instruction. memory location specified by MAR to MBR.
the system bus. (These two action can be Increment content of PC by I.
performed simultaneously to Third time unit: Move contents of MBR to
save time ) IR.
•Step 3: The content of the MBR Note: Second and third micro-operations
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is moved to the instruction both take place during the second time
register(IR). unit.
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The Indirect
Cycles –  Step 1: The address field
of the instruction is
transferred to the MAR.
This is used to fetch the
address of the operand.
 Step 2: The address field
of the IR is updated from
Once an instruction is fetched, the next the MBR.(So that it now
step is to fetch source operands. Source contains a direct
Operand is being fetched by indirect addressing rather than
addressing( it can be fetched by any indirect addressing)
addressing mode, here its done by  Step 3: The IR is now in
indirect addressing). Register-based the state, as if indirect
operands need not be fetched. Once the addressing has not been
opcode is executed, a similar process occurred.
may be needed to store the result in  Note: Now IR is ready for
main memory. Following micro- the execute cycle, but it
operations takes place skips that cycle for a TUHINPAL_11000223053

moment to consider the

 Here, this instruction adds Here, the content of location X is
The Execute the content of location X to incremented by 1. If the result is 0, 10
register R. Corresponding the next instruction will be
Cycle : micro-operation will be:- skipped. Corresponding sequence
of micro-operation will be :-

The Execute Cycle

The other three cycles(Fetch,
Indirect and Interrupt) are
simple and predictable. Each of
them requires simple, small
and fixed sequence of micro- We begin with the IR
operation. In each case same containing the ADD
micro-operation are repeated instruction.
each time around. Step 1: The address portion
of IR is loaded into the MAR.
Execute Cycle is different from Here, the PC is incremented if (MBR)
Step 2: The address field of
them. Like, for a machine with the IR is updated from the
= 0. This test (is MBR equal to zero or
N different opcodes there are N not) and action (PC is incremented by
MBR, so the reference
different sequence of micro- 1) can be implemented as one micro-
memory location is read.
operation.
operations that can occur. Step 3: Now, the contents of
Note : This test and action micro-
Lets take an hypothetical R and MBR are added by the
operation can be performed during
example :- ALU.
the same time unit during which the
consider an add Lets take a complex
updated value MBR is stored back to
example :- TUHINPAL_11000223053
instruction: memory.
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The Interrupt Cycle:
At the completion of the
Execute Cycle, a test is made
to determine whether any
enabled interrupt has
occurred or not. If an enabled Step 1: Contents of the PC is transferred to the MBR, so that
interrupt has occurred then they can be saved for return.
Interrupt Cycle occurs. The Step 2: MAR is loaded with the address at which the contents
nature of this cycle varies of the PC are to be saved.
greatly from one machine to PC is loaded with the address of the start of the interrupt-
another. processing routine.
Lets take a sequence of micro- Step 3: MBR, containing the old value of PC, is stored in
operation:- memory.
Note: In step 2, two actions are implemented as one micro-
operation. However, most processor provide multiple types
of interrupts, it may take one or more micro-operation to
obtain the save_address and the routine_address before they
are transferred to the MAR and PC respectively.

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• It is responsible for the complete

flow of instructions from the start of
• The instruction cycle of a computer
the computer system through its
system is necessary for understanding shutdown. The instruction cycle
the flow of instructions and the helps to understand the internal flow
execution of an instruction in a computer of the central processing unit,
processor. allowing any faults to be
immediately resolved.

• All instructions for the

• It deals with a computer computer processor system
processor's basic operations follow the fetch-decode-
and demands a detailed execute cycle.Also read,
understanding of the many microprogrammed control unit
steps involved.
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The fetch-decode-execute cycle,

consisting of instruction cycles, The instruction cycle controls the
allows CPUs to execute flow of program execution,
instructions sequentially and advancing to the next instruction
efficiently, ensuring that each after each cycle, allowing for precise
instruction is processed in a well- execution and program control.
defined manner.

CPUs can handle a wide range of CPUs can quickly respond to external
instructions, from arithmetic events and handle interrupts or
operations to data transfers, by exceptions using the interrupt cycle,
following the execution cycle for making them versatile and suitable for
each instruction type. various tasks.
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Clock Speed: Pipeline Complexity: Instruction Set

Stalls:: Limitations:

In pipelined architectures, The fetch-decode-execute cycle

The speed of instruction CPUs are limited by their
where multiple instructions is an intricate process, and the
execution is often constrained by instruction set architectures
are processed simultaneously, complexity of instruction
the system's clock speed, limiting (ISAs), which may not include
issues like pipeline stalls can execution can lead to design
the number of instructions that certain specialized instructions
lead to inefficiencies if challenges and potential errors
can be executed in a given time or features required for
instructions depend on one in the processor's
period. specific applications.
another. microarchitecture.

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https://media.geeksforgeeks.org/wp-content/uploads/Screenshot-from-2018-03-29-09-49-05.png

The instruction cycle is crucial in

CPU operations, encompassing
fetching, decoding, and executing
instructions. Understanding this
cycle is essential for optimizing
computer performance and
troubleshooting issues. Mastery
of these steps ensures efficient
processing and is fundamental to
advancements in computing
technology.

Reference :
• Geeks for geeks
• Code ninja
• Byjus

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