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Chapter – IV The Control Unit

 Control unit operations, Micro operations, Control

of the processor.

 Hardwired Implementation, Basic Concepts, Micro

Instruction Sequencing, Micro Instruction
Execution

4.1 Control Unit Micro Operation

The execution of an instruction involves the execution of a sequence of sub steps,

generally called cycles. For example, an execution may consist of fetch, indirect, execute,
and interrupt cycles. Each cycle is in turn made up of a sequence of more fundamental
operations, called micro-operations. A single micro-operation generally involves a
transfer between registers, a transfer between a register and an external bus, or a simple
ALU operation.

The control unit of a processor performs two tasks: (1) It causes the processor to step
through a series of micro-operations in the proper sequence, based on the program being
executed, and (2) it generates the control signals that cause each micro-operation to be
executed.

The control signals generated by the control unit cause the opening and closing of logic
gates, resulting in the transfer of data to and from registers and the operation of the ALU.
One technique for implementing a control unit is referred to as hardwired implementation,
in which the control unit is a combinatorial circuit. Its input logic signals, governed by the
current machine instruction, are transferred into a set of output control signals.

The operation of a computer, in executing a program, consists of a sequence of instruction

cycles, with one machine instruction per cycle. Of course, we must remember that this
sequence of instruction cycles is not necessarily the same as the written sequence of
instructions that make up the program, because of the existence of branching instructions.
What we are referring to here is the execution time sequence of instructions.

The prefix micro refers to the fact that each step is very simple and accomplishes very
little. Below figure depicts the relationship among the various concepts we have been
discussing. To summarize, the execution of a program consists of the sequential execution

Lecture Notes by: Dr. Leonard T Das (Dept of Electrical & Comp. Engineering)
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of instructions. Each instruction is executed during an instruction cycle made up of shorter

sub cycles (e.g., fetch, indirect, execute, interrupt). The execution of each sub cycle
involves one or more shorter operations, that is, micro-operations.

Elements of Program Execution

Fetch Cycle

We begin by looking at the fetch cycle, which occurs at the beginning of each instruction
cycle and causes an instruction to be fetched from memory.
Four registers are involved:
 Memory address register (MAR): Is connected to the address
lines of the system bus. It specifies the address in memory for a
read or write operation.
 Memory buffer register (MBR): Is connected to the data lines
of the system bus. It contains the value to be stored in memory
or the last value read from memory.
 Program counter (PC): Holds the address of the next instruction to be
fetched.
 Instruction register (IR): Holds the last instruction fetched.

An example appears in below Figure. At the beginning of the fetch cycle, the address of the
next instruction to be executed is in the program counter (PC); in this case, the address is
1100100. The first step is to move that address to the memory address register (MAR)
because this is the only register connected to the address lines of the system bus. The second
step is to bring in the instruction. The desired address (in the MAR) is placed on the address
bus, the control unit issues a READ command on the control bus, and the result appears on
the data bus and is copied into the memory buffer register (MBR). We also need to
increment the PC by the instruction length to get ready for the next instruction.

Lecture Notes by: Dr. Leonard T Das (Dept of Electrical & Comp. Engineering)
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Sequence of Events, Fetch Cycle

The third step is to move the contents of the MBR to the instruction register (IR). This
frees up the MBR for use. Symbolically, we can write this sequence of events as follows:

t1: MAR  (PC)

t2: MBR  Memory
PC  (PC) + I
t3: IR  (MBR)

The notation (t1, t2, t3) represents successive time units. In words, we have
 First time unit: Move contents of PC to MAR.
 Second time unit: Move contents of memory location
specified by MAR to MBR. Increment by I the contents of the
PC.
 Third time unit: Move contents of MBR to IR

Note that the second and third micro-operations both take place during the second time
unit.

The Indirect Cycle

Once an instruction is fetched, the next step is to fetch source operands. It includes the
following micro-operations:

Lecture Notes by: Dr. Leonard T Das (Dept of Electrical & Comp. Engineering)
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t1: MAR  (IR (Address))

t2: MBR  Memory
t3: IR (Address)  (MBR (Address))

The address field of the instruction is transferred to the MAR. This is then used to fetch
the address of the operand. Finally, the address field of the IR is updated from the MBR.

The Interrupt Cycle

At the completion of the execute cycle, a test is made to determine whether any enabled
interrupts have occurred. If so, the interrupt cycle occurs. The nature of this cycle varies
greatly from one machine to another.

The Execute Cycle

The fetch, indirect, and interrupt cycles are simple and predictable. Each
involves a small, fixed sequence of micro-operations and, in each case, the
same micro-operations are repeated each time around.

This is not true of the execute cycle. Because of the variety opcodes, there are
a number of different sequences of micro-operations that can occur. Let us
consider several hypothetical examples.

First, consider an add instruction:

ADD R1, X

which adds the contents of the location X to register R1. The following sequence of
micro-operations might occur:

t1: MAR  (IR (address))

t2: MBR  Memory
t3: R1  (R1) + (MBR)

Instruction cycle code (ICC) designates the state of the processor in terms of which
portion of the cycle it is in:
00: Fetch
01: Indirect
10: Execute
11: Interrupt

4.2 Control of the Processor

By reducing the operation of the processor to its most fundamental level, we
are able to define exactly what it is that the control unit must cause to happen.

Lecture Notes by: Dr. Leonard T Das (Dept of Electrical & Comp. Engineering)
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Thus, we can define the functional requirements for the control unit: those
functions that the control unit must perform. A definition of these functional
requirements is the basis for the design and implementation of the control unit.

With the information at hand, the following three-step process leads to a char-
acterization of the control unit:
a) Define the basic elements of the processor.
b) Describe the micro-operations that the processor performs.
c) Determine the functions that the control unit must perform to
cause the micro-operations to be performed.

The ALU is the functional essence of the computer. Registers are used to store data
internal to the processor. Some registers contain status information needed to manage
instruction sequencing (e.g., a program status word). Others contain data that go to or
come from the ALU, memory, and I/O modules. Internal data paths are used to move
data between registers and between register and ALU. External data paths link registers
to memory and I/O modules, often by means of a system bus. The control unit causes
operations to happen within the processor. The control unit performs two basic tasks:
 Sequencing: The control unit causes the processor to step
through a series of micro-operations in the proper sequence,
based on the program being executed.
 Execution: The control unit causes each micro-operation to be
performed.

Internal processor bus connects the ALU & all processor registers.

Lecture Notes by: Dr. Leonard T Das (Dept of Electrical & Comp. Engineering)
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4.3 Hardwired Implementation

To execute an instruction, the control unit of the CPU must generate the required control signal
in the proper sequence. There are two approaches used for generating the control signals in
proper sequence as Hardwired Control unit and Micro-programmed control unit.

The control hardware can be viewed as a state machine that changes from one state to another
in every clock cycle, depending on the contents of the instruction register, the condition codes
and the external inputs. The outputs of the state machine are the control signals. The sequence
of the operation carried out by this machine is determined by the wiring of the logic elements
and hence named as “hardwired”.
 Fixed logic circuits that correspond directly to the Boolean expressions are used to
generate the control signals.
 Hardwired control is faster than micro-programmed control.
 A controller that uses this approach can operate at high speed.
 RISC architecture is based on hardwired control unit.

It is implemented with the help of gates, flip flops, decoders etc. in the hardware. The inputs to
control unit are the instruction register, flags, timing signals etc. This organization can be very
complicated if we have to make the control unit large.
If the design has to be modified or changed, all the combinational circuits have to be modified
which is a very difficult task.

Lecture Notes by: Dr. Leonard T Das (Dept of Electrical & Comp. Engineering)
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4.4 Basics of Micro-programmed Control

It is implemented by using programming approach. A sequence of micro operations is carried out

by executing a program consisting of micro-instructions. In this organization any modifications
or changes can be done by updating the micro program in the control memory by the
programmer.
Some Important Terms: –
 Control Word: A control word is a word whose individual bits represent various
control signals.
 Micro-routine: A sequence of control words corresponding to the control sequence of
a machine instruction constitutes the micro-routine for that instruction.
 Micro-instruction: Individual control words in this micro-routine are referred to as
microinstructions.
 Micro-program: A sequence of micro-instructions is called a micro-program, which is
stored in a ROM or RAM called a Control Memory (CM).
 Control Store: the micro-routines for all instructions in the instruction set of a
computer are stored in a special memory called the Control Store.

Types of Micro-programmed Control Unit – Based on the type of Control Word stored in the
Control Memory (CM), it is classified into two types:

a) Horizontal Micro-programmed control unit:

The control signals are represented in the decoded binary format that is 1 bit/CS.
Example: If 53 Control signals are present in the processor than 53 bits are required.
More than one control signal can be enabled at a time.

 It supports longer control word.

 It is used in parallel processing applications.
 It allows higher degree of parallelism. If degree is n, n CS are enabled at a time.
 It requires no additional hardware (decoders). It means it is faster than Vertical Micro
programmed.
 It is more flexible than vertical micro programmed.

Lecture Notes by: Dr. Leonard T Das (Dept of Electrical & Comp. Engineering)
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b) Vertical Micro-programmed control Unit :

The control signals are represented in the encoded binary format. For N control signals-
Log2 (N) bits are required.

 It supports shorter control words.

 It supports easy implementation of new control signals therefore it is more flexible.
 It allows low degree of parallelism i.e., degree of parallelism is either 0 or 1.
 Requires an additional hardware (decoders) to generate control signals, it implies it
is slower than horizontal micro-programmed.
 It is less flexible than horizontal but more flexible than that of hardwired control
unit.

The below figure shows how these control words or microinstructions could be arranged in a
control memory. The microinstructions in each routine are to be executed sequentially. Each
routine ends with a branch or jump instruction indicating where to go next. There is a special
execute cycle routine whose only purpose is to signify that one of the machine instruction routines
(AND, ADD, and so on) is to be executed next, depending on the current opcode.

The control memory in below figure (Organization of Control Memory) is a concise description of the
complete operation of the control unit. It defines the sequence of micro-operations to be performed
during each cycle (fetch, indirect, execute, interrupt), and it specifies the sequencing of these
cycles. If nothing else, this notation would be a useful device for documenting the functioning of a
control unit for a particular computer. But it is more than that. It is also a way of implementing the
control unit.

The below figure (Control Unit Micro Architecture) shows the key elements of such an implementation.
The set of microinstructions is stored in the control memory. The control address register contains
the address of the next microinstruction to be read. When a microinstruction is read from the
control memory, it is transferred to a control buffer register.

The control unit functions as follows: - 1. To execute an instruction, the sequencing logic unit
issues a READ command to the control memory. 2. The word whose address is specified in the
control address register is read into the control buffer register. 3. The content of the control
buffer register generates control signals and next-address information for the sequencing logic

Lecture Notes by: Dr. Leonard T Das (Dept of Electrical & Comp. Engineering)
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unit. 4. The sequencing logic unit loads a new address into the control address register based on
the next-address information from the control buffer register and the ALU flags. All this happens
during once clock pulse.
Organization of Control Memory

Control Unit Micro Architecture

Lecture Notes by: Dr. Leonard T Das (Dept of Electrical & Comp. Engineering)
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4.4.1 Microinstruction Sequencing & Execution

The two basic tasks performed by a micro-programmed control unit are as follows:

 Microinstruction sequencing:- Get the next microinstruction from the control memory.
 Microinstruction execution: - Generate the control signals needed to execute the
microinstruction.

In designing a control unit, these tasks must be considered together, because both affect the
format of the microinstruction and the timing of the control unit. Two concerns are involved in
the design of a microinstruction sequencing technique: the size of the microinstruction and the
address generation time. The first concern is obvious; minimizing the size of the control
memory reduces the cost of that component. The second concern is simply a desire to execute
microinstructions as fast as possible. In executing a micro program, the address of the next
microinstruction to be executed is in one of these categories: -

 Determined by instruction register

 Next sequential address
 Branch

The first category occurs only once per instruction cycle, just after an instruction is fetched. The
second category is the most common in most designs. However, the design cannot be optimized
just for sequential access. Branches, both conditional and unconditional, are a necessary part of a
micro-program. Furthermore, microinstruction sequences tend to be short; one out of every three or
four microinstructions could be a branch. Based on the current microinstruction, condition flags,
and the contents of the instruction register, a control memory address must be generated for the
next microinstruction.

A wide variety of techniques have been used. We can group them into three general categories:-

a) Two Address Fields b) Single Address Field c) Variable Format

The microinstruction cycle is the basic event on a micro-programmed processor. Each cycle is
made up of two parts: fetch and execute. The fetch portion is determined by the generation of a
microinstruction address and execution of a micro instruction.

The effect of the execution of a microinstruction is to generate control signals. Some of these
signals control points internal to the processor. The remaining signals go to the external control bus
or other external interface. As an incidental function, the address of the next microinstruction is
determined. The below figure suggests the organization of a control unit. The sequencing logic
module contains the logic to perform the functions discussed in the preceding section. It generates
the address of the next microinstruction, using as inputs the instruction register, ALU flags, the
control address register (for incrementing), and the control buffer register. The last may provide an
actual address, control bits, or both.

Lecture Notes by: Dr. Leonard T Das (Dept of Electrical & Comp. Engineering)
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The module is driven by a clock that determines the timing of the microinstruction cycle.
The control logic module generates control signals as a function of some of the bits in the
microinstruction. It should be clear that the format and content of the microinstruction will
determine the complexity of the control logic module.

Control Unit Organization

End of Chapter- IV

Lecture Notes by: Dr. Leonard T Das (Dept of Electrical & Comp. Engineering)